US7107425B2 - SDRAM controller that improves performance for imaging applications - Google Patents
SDRAM controller that improves performance for imaging applications Download PDFInfo
- Publication number
- US7107425B2 US7107425B2 US10/656,609 US65660903A US7107425B2 US 7107425 B2 US7107425 B2 US 7107425B2 US 65660903 A US65660903 A US 65660903A US 7107425 B2 US7107425 B2 US 7107425B2
- Authority
- US
- United States
- Prior art keywords
- memory
- row
- current row
- image data
- bank
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related, expires
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
- G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
- G06F13/1631—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests through address comparison
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
- Image Input (AREA)
Abstract
Description
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/656,609 US7107425B2 (en) | 2003-09-06 | 2003-09-06 | SDRAM controller that improves performance for imaging applications |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/656,609 US7107425B2 (en) | 2003-09-06 | 2003-09-06 | SDRAM controller that improves performance for imaging applications |
Publications (2)
Publication Number | Publication Date |
---|---|
US20050055349A1 US20050055349A1 (en) | 2005-03-10 |
US7107425B2 true US7107425B2 (en) | 2006-09-12 |
Family
ID=34226378
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/656,609 Expired - Fee Related US7107425B2 (en) | 2003-09-06 | 2003-09-06 | SDRAM controller that improves performance for imaging applications |
Country Status (1)
Country | Link |
---|---|
US (1) | US7107425B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070188503A1 (en) * | 2006-02-14 | 2007-08-16 | Taiyi Cheng | Method and system for programmable breakpoints in an integrated embedded image and video accelerator |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106302374B (en) | 2015-06-26 | 2019-08-16 | 深圳市中兴微电子技术有限公司 | It is a kind of for improve list item access bandwidth and atomicity operation device and method |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4937791A (en) * | 1988-06-02 | 1990-06-26 | The California Institute Of Technology | High performance dynamic ram interface |
US5889714A (en) * | 1997-11-03 | 1999-03-30 | Digital Equipment Corporation | Adaptive precharge management for synchronous DRAM |
US6052134A (en) * | 1997-12-22 | 2000-04-18 | Compaq Computer Corp. | Memory controller and method for dynamic page management |
US6286075B1 (en) * | 1998-11-16 | 2001-09-04 | Infineon Technologies Ag | Method of speeding up access to a memory page using a number of M page tag registers to track a state of physical pages in a memory device having N memory banks where N is greater than M |
US6442645B1 (en) * | 1998-12-04 | 2002-08-27 | Intel Corporation | Pre-decode conditional command generation for reduced SDRAM cycle latency |
US6535966B1 (en) * | 2000-05-17 | 2003-03-18 | Sun Microsystems, Inc. | System and method for using a page tracking buffer to reduce main memory latency in a computer system |
US20040236889A1 (en) * | 2003-05-24 | 2004-11-25 | Samsung Electronics Co., Ltd. | Bus arbiter and bus arbitrating method |
-
2003
- 2003-09-06 US US10/656,609 patent/US7107425B2/en not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4937791A (en) * | 1988-06-02 | 1990-06-26 | The California Institute Of Technology | High performance dynamic ram interface |
US5889714A (en) * | 1997-11-03 | 1999-03-30 | Digital Equipment Corporation | Adaptive precharge management for synchronous DRAM |
US6052134A (en) * | 1997-12-22 | 2000-04-18 | Compaq Computer Corp. | Memory controller and method for dynamic page management |
US6286075B1 (en) * | 1998-11-16 | 2001-09-04 | Infineon Technologies Ag | Method of speeding up access to a memory page using a number of M page tag registers to track a state of physical pages in a memory device having N memory banks where N is greater than M |
US6442645B1 (en) * | 1998-12-04 | 2002-08-27 | Intel Corporation | Pre-decode conditional command generation for reduced SDRAM cycle latency |
US6535966B1 (en) * | 2000-05-17 | 2003-03-18 | Sun Microsystems, Inc. | System and method for using a page tracking buffer to reduce main memory latency in a computer system |
US20040236889A1 (en) * | 2003-05-24 | 2004-11-25 | Samsung Electronics Co., Ltd. | Bus arbiter and bus arbitrating method |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070188503A1 (en) * | 2006-02-14 | 2007-08-16 | Taiyi Cheng | Method and system for programmable breakpoints in an integrated embedded image and video accelerator |
US8238415B2 (en) * | 2006-02-14 | 2012-08-07 | Broadcom Corporation | Method and system for programmable breakpoints in an integrated embedded image and video accelerator |
Also Published As
Publication number | Publication date |
---|---|
US20050055349A1 (en) | 2005-03-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5390308A (en) | Method and apparatus for address mapping of dynamic random access memory | |
US7246215B2 (en) | Systolic memory arrays | |
US7089369B2 (en) | Method for optimizing utilization of a double-data-rate-SDRAM memory system | |
US8482573B2 (en) | Apparatus and method for processing data | |
US8595459B2 (en) | Micro-threaded memory | |
US5561777A (en) | Process for sequentially reading a page from an image memory in either of two directions | |
EP1894112B1 (en) | Memory micro-tiling speculative returns | |
US8332598B2 (en) | Memory micro-tiling request reordering | |
KR100817057B1 (en) | Mapping method and video system for mapping pixel data included same pixel data group to same bank address of memory | |
US7765366B2 (en) | Memory micro-tiling | |
US20060047886A1 (en) | Memory controller | |
WO2003007303A2 (en) | Memory device having different burst order addressing for read and write operations | |
JP2005501300A (en) | Array and method for accessing data in a virtual memory array | |
US10691608B2 (en) | Memory device accessed in consideration of data locality and electronic system including the same | |
KR20180006645A (en) | Semiconductor device including a memory buffer | |
US5761714A (en) | Single-cycle multi-accessible interleaved cache | |
US6282604B1 (en) | Memory controller and method for meory devices with mutliple banks of memory cells | |
US6535966B1 (en) | System and method for using a page tracking buffer to reduce main memory latency in a computer system | |
JP2010507868A (en) | System for interleaved storage of video data | |
US6008823A (en) | Method and apparatus for enhancing access to a shared memory | |
US7107425B2 (en) | SDRAM controller that improves performance for imaging applications | |
US5703810A (en) | DRAM for texture mapping | |
JP4318422B2 (en) | System including integrated circuit memory | |
US6622203B2 (en) | Embedded memory access method and system for application specific integrated circuits | |
EP1523712B1 (en) | A system, apparatus, and method for a flexible dram architecture |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: MATCH LAB, INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FRAZER, DAVID A.;REEL/FRAME:014481/0034 Effective date: 20030905 |
|
AS | Assignment |
Owner name: GOOD NEWS ENTERPRISES LIMITED, TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MATCH LAB, INC.;REEL/FRAME:017759/0894 Effective date: 20060611 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FEPP | Fee payment procedure |
Free format text: PAT HOLDER NO LONGER CLAIMS SMALL ENTITY STATUS, ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: STOL); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: LIBRE HOLDINGS, INC., MASSACHUSETTS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GOOD NEWS ENTERPRISES LIMITED;REEL/FRAME:032684/0568 Effective date: 20140318 |
|
FEPP | Fee payment procedure |
Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.) |
|
LAPS | Lapse for failure to pay maintenance fees |
Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20180912 |