US7132740B2 - Semiconductor package with conductor impedance selected during assembly - Google Patents
Semiconductor package with conductor impedance selected during assembly Download PDFInfo
- Publication number
- US7132740B2 US7132740B2 US10/411,531 US41153103A US7132740B2 US 7132740 B2 US7132740 B2 US 7132740B2 US 41153103 A US41153103 A US 41153103A US 7132740 B2 US7132740 B2 US 7132740B2
- Authority
- US
- United States
- Prior art keywords
- conductors
- array
- auxiliary
- conductor
- ground
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6627—Waveguides, e.g. microstrip line, strip line, coplanar line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/1016—Shape being a cuboid
- H01L2924/10161—Shape being a cuboid with a rectangular active surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1903—Structure including wave guides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30105—Capacitance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
- H01L2924/30111—Impedance matching
Definitions
- This invention relates generally to a semiconductor package, and more particularly to the impedance of conductors in a semiconductor package.
- IC integrated circuit
- clock circuit drivers of many high frequency circuits are designed for 50 ohm matched impedance, and this in turn necessitates a specific geometric conductor design, and a predetermined output location for the conductor system in a package or substrate to match the circuit design.
- the conductor system within a substrate or package used for both single ended and differential signal transmission has different impedance levels for each mode, and thus a specific conductor design for individual devices.
- Arrays of conductors provide transmission lines in semiconductor packages or substrates; these arrays or systems include signal layer(s), and a ground conductor(s) which may be within the substrate, the printed wiring board or the semiconductor chip itself.
- the conductive layers are interspaced with dielectric materials. Characteristic impedance of the conductors is a function of conductor spacing, dielectric thickness, conductor width, the electrical properties of the materials, and the velocity of signal propagation on the line.
- Differential impedance between a pair of conductors is either odd mode or even mode depending upon the direction of signal propagation, and for some circuits the need for both modes exists within the same device. This is particularly true of higher frequency and microwave devices designed for even mode impedance, often at 100 ohms.
- the primary object of the invention is to provide a multiple use conductor system for interconnecting an integrated circuit chip to an external circuit wherein the impedance level of the conductors serving as transmission lines can be arbitrarily selected.
- Yet another objective is to provide a flexible conductor system which is usable with different types of packages or substrates.
- the invention is a microelectronic device, and a method of fabricating the device, wherein the impedance of single ended or differential signal transmission lines is determined by the choice of which conductors are connected to ground during the assembly of the semiconductor device. Moreover, the device is applicable to pairs of conductors having odd or even mode impedance within the same conductor system.
- the device is a semiconductor package having a plurality of conductors arrayed in two (or more) parallel planes, and a ground conductor.
- Each of the primary conductors has the same dimensions and spacing between conductors, and each of the auxiliary conductors has the same dimensions and spacing.
- Conductors in the auxiliary or second plane substantially overlay the primary signal conductors in the first plane, and the impedance of any lead or lead pair is arbitrarily set by connecting the auxiliary conductors to ground or by leaving them floating. Differential pairs of signal conductors, either odd or even mode are set by connecting the auxiliary conductors to a ground contact.
- a conductor system wherein single ended and differential impedance modes are mixed within the same package or substrate.
- Conductors are arrayed in two (or more) parallel planes, with an available ground conductor, and the auxiliary conductors substantially overlay the primary conductors. Conductor dimensions and spacing are set to provide alternating impedance modes.
- FIG. 1 is a cross sectional design of conductors of the current invention.
- FIG. 2 shows the overlaying conductors from a top view.
- FIG. 3 illustrates bond selection of the primary conductors for differential mode transmission
- FIG. 4 illustrates bond selection of the primary and ground conductors for single ended signal transmission.
- FIG. 5 is a cross sectional diagram of a conductor system applicable to mixed mode, to single ended, or to a differential pair of transmission lines.
- FIG. 6 illustrates a mixed transmission mode conductor system in the same device.
- FIG. 7 is a Ball Grid Array package with single ended transmission lines.
- FIG. 8 is a flip chip bonded BGA package of the current invention.
- FIG. 9 is a cross section of a device of the current invention using a flex circuit substrate.
- FIG. 1 provides a cross section of the conductors of the current invention, wherein a ground plane 105 exists either in the package, the chip, or the next level of interconnection, typically a printed wiring board.
- a first level or primary conductors 101 are positioned at a distance “h 1 ” above the ground plane 105 and have a defined width “w 1 ”, and a separation “d” from the adjacent primary conductor.
- An auxiliary or second level 102 of conductors having width “w 2 ” is positioned above the primary conductors 101 at a distance “h 2 ” above the ground plane, and substantially follow the path of the primary conductors throughout the conductor system.
- the conductors 101 and 102 are of the same material and have thickness “t”. The conductors are interspaced with a dielectric material.
- FIG. 2 provides a top view of the conductors 102 and 101 showing the position furthermost from the ground source. From this view it can be seen that an auxiliary conductor 102 lies directly above each of the primary conductors 101 . Contact pads 104 and 107 are located on the substrate 106 .
- impedance of a conductor or lead is a function of inductance and capacitance of the conductors, and is determined by the height above the ground plane, and the conductor width, and that for single ended transmission lines, impedance is a function of the spacing between the conductors. It is further recognized that the ratio of “h” and “w” is the same for each conductor in a given signal layer if the impedance of the conductors is to be substantially the same.
- the general equation for a impedance “Z” of a conductor is given by:
- FIG. 1 all primary conductors 101 in the system are designed for a selected impedance level, taking into account the known geometric constraints discussed previously, the dielectric constant of the materials of construction and the resistivity of the conductors.
- FIG. 3 shows the primary conductors 101 electrically connected to an output signal pin 104 of the package or substrate 106 . In this embodiment, the electrical connections are made by way of a wire bond.
- the auxiliary conductors 102 are “floating” or unattached to any other conductor, and the impedance values of the auxiliary conductors are of no concern to the device performance.
- a dielectric layer 134 separates the two conductor layers and the dielectric thickness is equal to the difference between “h 1 ” and “h 2 ” in FIG. 1 .
- This transmission configuration provides impedance results of the primary conductors which are have only slightly different from a device with a single level of conductors; i.e., the auxiliary conductors cause a minor change in the capacitance values which results in only minor changes in the impedance values.
- the bonding configuration, shown in FIG. 3 is used with differential mode transmission lines.
- each of the primary conductors 401 is connected to a signal output pin 404 , and each of the overlying auxiliary conductors 402 is electrically connected to a ground contact 407 .
- a dielectric layer 434 separates the primary and auxiliary conductor levels. This configuration provides a connection for single ended transmission by the primary conductors. Connection of the auxiliary conductors 402 to ground essentially sandwiches the primary conductors between two ground levels; i.e., the ground plane within the package or board, and a second isolated ground plane formed by the auxiliary conductors when attached to a ground contact.
- the impedance of the conductors of the current invention are arbitrarily selected as single ended or differential mode transmission lines depending on connection to ground.
- modes can be mixed within a conductor system having an array of primary conductors 51 , 52 , 53 , and 54 , and a parallel array of auxiliary conductors 521 , 522 , 523 , and 524 substantially overlaying the primary conductors, and separated by a dielectric layer 534 .
- spacing of the primary and auxiliary conductors are not uniform throughout the respective conductor planes, but are spaced at predetermined distances to allow mixed mode impedance, single ended impedance or differential impedance depending upon the connection of the auxiliary conductors to ground.
- the primary conductors 51 , 52 , 53 , 54 are connected to signal output pins or pads.
- all auxiliary conductors 521 , 522 , 523 and 524 are connected to ground 507 .
- the auxiliary conductors are floating or not connected, and the center pair 52 and 53 are spaced and dimensioned to provide a differential pair of specified impedance.
- the conductors 52 and 53 are made the differential transmission lines, and leads 51 and 54 are made single ended transmission lines by attaching auxiliary conductors 521 and 524 to ground 507 .
- Each primary conductor is electrically connected to an output pad 504 , and auxiliary conductors 521 and 524 are connected to ground contact 507 , thereby a device having a pair of differential transmission lines, 52 and 53 , and two single ended lines 51 and 54 .
- the single ended conductors of FIG. 4 were designed for 50 ohm impedance, and the model data shows the values to be within 5%. By connecting the specific auxiliary conductors to ground, differential impedance of the odd and even modes are within 3%.
- FIG. 7 illustrates a preferred embodiment of the invention as a BGA (Ball Grid Array) semiconductor package.
- the package substrate 706 is comprised of a composite material, such as BT resin having a dielectric constant of 4.
- the device includes a primary level of conductors 701 overlaid by a second level of auxiliary conductors 702 , and the conductors separated by a layer of dielectric 734 .
- Plated vias 711 connect each primary conductor 701 to an external solder ball contact 721 .
- Plated vias 712 connect each second level conductor 702 to a ground plane 732 embedded within the package substrate, to an array of external solder ball contacts 722 .
- An integrated circuit chip 700 is adhered to a chip pad 715 on the package substrate 706 , and the chip 700 is connected by wire bonds 716 to selected conductors.
- the chip and conductor system are encapsulated in a plastic material (not shown).
- an embodiment of the invention includes a flip chip interconnected integrated circuit chip 800 electrically connected by solder bumps 820 to a pattern of primary conductors 801 and auxiliary conductors 802 on the substrate 806 .
- the primary conductors 801 on the surface of the substrate interconnect the solder bumps on the IC chip to the external signal leads or solder balls 821
- the auxiliary conductors 802 interconnect the chip ground contacts to the ground plane 832 .
- External ground contacts are made through solder balls 822 by way of vias to the ground plane 832 . Ground contacts to be excluded, as in the case of differential mode transmission lines, are avoided by removing designated solder balls prior to assembly onto the substrate.
- Conductive vias provide electrical connection between the primary 801 and secondary 802 conductors to external solder ball contacts 821 and 822 .
- the preferred embodiments, as demonstrated in FIGS. 7 and 8 include a ground plane 732 , 832 within the package substrate.
- the ground plane often exists within the printed circuit board, rather than in the package itself and the configuration is usable with the current invention. Ground contacts are made directly to the printed wiring board ground plane, avoiding the need for an additional layer within the package.
- the conductor system of the current invention is applicable not only to rigid substrates, as illustrated in FIGS. 6 , 7 and 8 wherein the conductors are supported on a rigid material and separated by a dielectric layer, but the system is also applicable to thin flex circuits.
- a cross section of a Flex Circuit device of the current invention is provided having a level of primary conductors 901 on one surface and an overlaying array of auxiliary conductors 902 on the alternate surface on a thin film dielectric 903 , such as a polyimide film.
- the IC chip 900 has solder bump connections 905 to said conductors on the film substrate. External contacts to conductors 901 and 902 are made a perimeter contact pads 910 .
- the invention has been illustrated and described as a single chip package, but the overlying conductor system of this invention is equally applicable to multichip devices require controlled impedance transmission lines.
- packages or substrates having a conductor system of this invention include leaded devices, rather than those having solder ball connectors.
Abstract
A semiconductor package having a plurality of conductors arrayed in two (or more) parallel planes, and an available ground conductor. Conductors in the auxiliary or second plane substantially overlay the primary signal conductors in the first plane, and the impedance of any lead or lead pair is arbitrarily set at the assembly process by connecting the auxiliary conductors to ground or by leaving them floating. Differential pairs of signal conductors, either odd or even mode are set by connecting the auxiliary conductors to a ground contact.
Description
This application is a continuation of application Ser. No. 09/750,393 filed Dec. 28, 2000, now U.S. Pat. No. 6,563,208, which claims priority from provisional application Ser. No. 60/173,450 filed Dec. 29, 1999.
This invention relates generally to a semiconductor package, and more particularly to the impedance of conductors in a semiconductor package.
In order to maintain signal integrity, the design of high speed integrated circuit (IC) devices requires specific characteristic impedance of conductors which interconnect an IC chip to a printed wiring board or the next level of interconnection. For example, clock circuit drivers of many high frequency circuits are designed for 50 ohm matched impedance, and this in turn necessitates a specific geometric conductor design, and a predetermined output location for the conductor system in a package or substrate to match the circuit design. Moreover, the conductor system within a substrate or package used for both single ended and differential signal transmission has different impedance levels for each mode, and thus a specific conductor design for individual devices.
Arrays of conductors provide transmission lines in semiconductor packages or substrates; these arrays or systems include signal layer(s), and a ground conductor(s) which may be within the substrate, the printed wiring board or the semiconductor chip itself. The conductive layers are interspaced with dielectric materials. Characteristic impedance of the conductors is a function of conductor spacing, dielectric thickness, conductor width, the electrical properties of the materials, and the velocity of signal propagation on the line.
Differential impedance between a pair of conductors is either odd mode or even mode depending upon the direction of signal propagation, and for some circuits the need for both modes exists within the same device. This is particularly true of higher frequency and microwave devices designed for even mode impedance, often at 100 ohms.
The ongoing proliferation of high speed circuits with specific conductor requirements places a difficult and costly demand for as many package or substrate designs. A need exists for more flexible conductor systems which accommodate a number of different circuit design requirements.
The primary object of the invention is to provide a multiple use conductor system for interconnecting an integrated circuit chip to an external circuit wherein the impedance level of the conductors serving as transmission lines can be arbitrarily selected.
It is an object of the invention to provide a semiconductor package having conductors wherein the impedance can be selected for individual leads or lead pairs.
It is an object of the invention to provide a semiconductor package wherein the characteristic impedance of the conductors can be selected for single ended or differential pairs of transmission lines, as well as for odd and even mode differential transmission lines within the same package.
It is an object of the invention to provide a semiconductor package wherein the impedance level of the conductors is established during the assembly of the circuit.
It is an object of the invention to provide a semiconductor package which is usable for many chip designs, and thus reduces the costs associated with tooling, inventory, and package design.
It is further an object that the interconnection of the conductors is compatible with either wire bond or flip chip interconnection.
Yet another objective is to provide a flexible conductor system which is usable with different types of packages or substrates.
It is an object of one embodiment of the invention to provide a conductor system wherein single ended and differential mode transmission can be mixed within the same conductor system.
The invention is a microelectronic device, and a method of fabricating the device, wherein the impedance of single ended or differential signal transmission lines is determined by the choice of which conductors are connected to ground during the assembly of the semiconductor device. Moreover, the device is applicable to pairs of conductors having odd or even mode impedance within the same conductor system.
In one embodiment, the device is a semiconductor package having a plurality of conductors arrayed in two (or more) parallel planes, and a ground conductor. Each of the primary conductors has the same dimensions and spacing between conductors, and each of the auxiliary conductors has the same dimensions and spacing. Conductors in the auxiliary or second plane substantially overlay the primary signal conductors in the first plane, and the impedance of any lead or lead pair is arbitrarily set by connecting the auxiliary conductors to ground or by leaving them floating. Differential pairs of signal conductors, either odd or even mode are set by connecting the auxiliary conductors to a ground contact.
In an alternate embodiment, a conductor system is provided wherein single ended and differential impedance modes are mixed within the same package or substrate. Conductors are arrayed in two (or more) parallel planes, with an available ground conductor, and the auxiliary conductors substantially overlay the primary conductors. Conductor dimensions and spacing are set to provide alternating impedance modes.
It is known by those skilled in the art that the impedance of a conductor or lead is a function of inductance and capacitance of the conductors, and is determined by the height above the ground plane, and the conductor width, and that for single ended transmission lines, impedance is a function of the spacing between the conductors. It is further recognized that the ratio of “h” and “w” is the same for each conductor in a given signal layer if the impedance of the conductors is to be substantially the same. The general equation for a impedance “Z” of a conductor is given by:
In FIG. 1 all primary conductors 101 in the system are designed for a selected impedance level, taking into account the known geometric constraints discussed previously, the dielectric constant of the materials of construction and the resistivity of the conductors. FIG. 3 shows the primary conductors 101 electrically connected to an output signal pin 104 of the package or substrate 106. In this embodiment, the electrical connections are made by way of a wire bond. The auxiliary conductors 102 are “floating” or unattached to any other conductor, and the impedance values of the auxiliary conductors are of no concern to the device performance. A dielectric layer 134 separates the two conductor layers and the dielectric thickness is equal to the difference between “h1” and “h2” in FIG. 1 .
This transmission configuration provides impedance results of the primary conductors which are have only slightly different from a device with a single level of conductors; i.e., the auxiliary conductors cause a minor change in the capacitance values which results in only minor changes in the impedance values. The bonding configuration, shown in FIG. 3 is used with differential mode transmission lines.
Turning now to FIG. 4 , each of the primary conductors 401 is connected to a signal output pin 404, and each of the overlying auxiliary conductors 402 is electrically connected to a ground contact 407. A dielectric layer 434 separates the primary and auxiliary conductor levels. This configuration provides a connection for single ended transmission by the primary conductors. Connection of the auxiliary conductors 402 to ground essentially sandwiches the primary conductors between two ground levels; i.e., the ground plane within the package or board, and a second isolated ground plane formed by the auxiliary conductors when attached to a ground contact.
From FIGS. 3 and 4 , it is apparent that the impedance of the conductors of the current invention are arbitrarily selected as single ended or differential mode transmission lines depending on connection to ground.
In an alternate embodiment, illustrated in FIGS. 5 and 6 , it can be seen that modes can be mixed within a conductor system having an array of primary conductors 51, 52, 53, and 54, and a parallel array of auxiliary conductors 521, 522, 523, and 524 substantially overlaying the primary conductors, and separated by a dielectric layer 534. In this embodiment, spacing of the primary and auxiliary conductors are not uniform throughout the respective conductor planes, but are spaced at predetermined distances to allow mixed mode impedance, single ended impedance or differential impedance depending upon the connection of the auxiliary conductors to ground.
In each application, the primary conductors 51,52,53,54 are connected to signal output pins or pads. In an application requiring single ended transmission lines, all auxiliary conductors 521,522, 523 and 524 are connected to ground 507. In an application requiring a differential pair, the auxiliary conductors are floating or not connected, and the center pair 52 and 53 are spaced and dimensioned to provide a differential pair of specified impedance.
For the application of mixed modes, the conductors 52 and 53 are made the differential transmission lines, and leads 51 and 54 are made single ended transmission lines by attaching auxiliary conductors 521 and 524 to ground 507.
The configuration of mixed mode is further illustrated in FIG. 6 . Each primary conductor is electrically connected to an output pad 504, and auxiliary conductors 521 and 524 are connected to ground contact 507, thereby a device having a pair of differential transmission lines, 52 and 53, and two single ended lines 51 and 54.
In order to insure proper signal transmission and timing, prediction and control of electrical parameters of a packaging system is analyzed using computer modeling and simulation program. Such electrical modeling programs are both commercially available, and have been developed by a number of university programs. The geometry and material properties of a series of conductors and insulators are input to the program, and the output includes capacitance, inductance of the conductors and the resulting impedance of the lead in question, and of the surrounding leads. The results of such analyses are then input to a simulation model to predict a circuit performance.
Validity of the current invention is illustrated by results of an electrical model of the device in FIGS. 3 and 4 are given in Tables 1 and 2 respectively.
Conductor material: Copper (resistivity=1.67 ohm cm) permeability (μr=1)
Substrate material: BT resin (dielectric constant=4) (dielectric loss tangent δ=0
Conductor design in mm
w2 = 0.0625 | w1 = 0.125 | ||
t = 0.02 | d1 = 0.125 | ||
h1 = 0.251 | h2 = 0.3615 | ||
TABLE 1 |
First Level Conductors With |
Differential Transmission Lines |
(Auxiliary Conductors Floating) |
Conductor # |
1 | 2 | 3 | 4 | ||
CAPACITANCE MATRIX | 1.32 | 1.39 | 1.39 | 1.32 |
(pf/cm) pico farads | ||||
per centimeter | ||||
INDUCTANCE MATRIX | 5.00 | 5.00 | 5.07 | 5.07 |
(nh/cm) nanohenries/cm | ||||
IMPEDANCE MATRIX (ohm) | 76.22 | 75.19 | 75.19 | 76.22 |
adjacent lead | 25 | 25 | 25 | 25 |
Differential mode | ||||
Impedance | 51.22 | 50.19 | 50.19 | 51.22 |
TABLE 2 |
First Level Conductors With Single |
Ended Transmission Lines |
(Auxiliary Conductors Grounded) |
Conductor # |
1 | 2 | 3 | 4 | ||
CAPACITANCE MATRIX | 1.32 | 1.39 | 1.39 | 1.32 |
(pf/cm) pico farads | ||||
per centimeter | ||||
INDUCTANCE MATRIX | 3.44 | 3.33 | 3.35 | 3.44 |
(nh/cm) nanohenries/cm | ||||
IMPEDANCE MATRIX (ohm) | 51.59 | 50.02 | 50.02 | 51.59 |
The single ended conductors of FIG. 4 were designed for 50 ohm impedance, and the model data shows the values to be within 5%. By connecting the specific auxiliary conductors to ground, differential impedance of the odd and even modes are within 3%.
An analysis of the mixed mode device in FIGS. 5 and 6 , provides the results given in Table 3.
Conductor material: Copper (resistivity=1.67 ohm cm) (permeability μr=1)
Substrate material: BT resin (dielectric constant=4) (dielectric loss tangent δ=0)
Conductor design in mm
t = 0.02 | ||
w2 0.02 | ||
d3 = 0.52 | ||
d3 = 0.1 | ||
h1 = 0.192 | ||
w1 = 0.1 | ||
d2 = 0.18 | ||
d4 = 0.45 | ||
h2 = 0.264 | ||
TABLE 3 |
|
(Auxiliary Conductors Floating) |
|
51 | 52 | 53 | 54 | ||
CAPACITANCE MATRIX | 1.33 | 1.42 | 1.42 | 1.33 |
(pf/cm) pico farads | ||||
per centimeter | ||||
INDUCTANCE MATRIX | 5.00 | 4.93 | 4.93 | 5.00 |
(nh/cm) nanohenries/cm | ||||
IMPEDANCE MATRIX (ohm) | 75.27 | 74.21 | 74.22 | 75.26 |
adjacent lead | 24.79 | 24.79 | ||
Differential mode | ||||
Impedance | 49.42 | 49.43 | ||
Conductors With Single Transmission Lines |
(All Auxiliary Conductors Grounded) |
|
51 | 52 | 53 | 54 | ||
CAPACITANCE MATRIX | 1.33 | 1.42 | 1.42 | 1.33 |
(pf/cm) picofarads | ||||
per centimeter | ||||
INDUCTANCE MATRIX | 3.33 | 3.22 | 3.21 | 3.33 |
(nh/cn) nanohenries/cm | ||||
IMPEDANCE MATRIX (ohm) | 50.02 | 48.27 | 48.22 | 50.01 |
Mixed Mode Transmission |
Differential Pair |
52, 53, Single Ended 51, 54 |
|
51 | 52 | 53 | 54 | ||
CAPACITANCE MATRIX | 1.33 | 1.42 | 1.42 | 1.33 |
(pf/cm) picofarads | ||||
per centimeter | ||||
INDUCTANCE MATRIX | 3.34 | 4.88 | 4.88 | 3.34 |
(nh/cm) nanohenries/cm | ||||
IMPEDANCE MATRIX (ohm) | 50.13 | 73.44 | 73.44 | 50.13 |
adjacent lead | 24.12 | 24.12 | ||
Differential mode | ||||
Impedance | 49.32 | 49.32 | ||
Thus, in the preferred embodiment illustrated in FIGS. 3 and 4 , and the analysis in Tables 1 and 2, a conductor system having overlaying conductors in a single device design is provided, and said design is compatible with various chip transmission requirements, thereby eliminating a need for specific package designs for various impedance matching conductors.
In the alternate embodiment, given in FIGS. 5 and 6 and the analysis in Table 3, a conductor system is shown which allows both single ended and differential mode impedance transmission lines within the same package, or allows either single ended or for differential transmission modes to be selected arbitrarily by the bonding configuration.
In FIG. 8 , an embodiment of the invention includes a flip chip interconnected integrated circuit chip 800 electrically connected by solder bumps 820 to a pattern of primary conductors 801 and auxiliary conductors 802 on the substrate 806. The primary conductors 801 on the surface of the substrate interconnect the solder bumps on the IC chip to the external signal leads or solder balls 821, and the auxiliary conductors 802 interconnect the chip ground contacts to the ground plane 832. External ground contacts are made through solder balls 822 by way of vias to the ground plane 832. Ground contacts to be excluded, as in the case of differential mode transmission lines, are avoided by removing designated solder balls prior to assembly onto the substrate. Conductive vias provide electrical connection between the primary 801 and secondary 802 conductors to external solder ball contacts 821 and 822.
The preferred embodiments, as demonstrated in FIGS. 7 and 8 include a ground plane 732, 832 within the package substrate. However, the ground plane often exists within the printed circuit board, rather than in the package itself and the configuration is usable with the current invention. Ground contacts are made directly to the printed wiring board ground plane, avoiding the need for an additional layer within the package.
The conductor system of the current invention is applicable not only to rigid substrates, as illustrated in FIGS. 6 , 7 and 8 wherein the conductors are supported on a rigid material and separated by a dielectric layer, but the system is also applicable to thin flex circuits. In FIG. 9 , a cross section of a Flex Circuit device of the current invention is provided having a level of primary conductors 901 on one surface and an overlaying array of auxiliary conductors 902 on the alternate surface on a thin film dielectric 903, such as a polyimide film. The IC chip 900 has solder bump connections 905 to said conductors on the film substrate. External contacts to conductors 901 and 902 are made a perimeter contact pads 910.
The invention has been illustrated and described as a single chip package, but the overlying conductor system of this invention is equally applicable to multichip devices require controlled impedance transmission lines.
Further, packages or substrates having a conductor system of this invention include leaded devices, rather than those having solder ball connectors.
While preferred embodiments and some alternative applications of the invention have been described above, they are not intended to be limited, but instead it should be understood that various modifications may be made from the specific details described herein without departing from the spirit and scope of the invention as set forth in the appended claims.
Claims (16)
1. A microelectronic device, comprising:
a substrate comprising:
an array of primary conductors in a first plane in said substrate;
an array of auxiliary conductors in a second plane in said substrate, each auxiliary conductor in said array substantially overlying a corresponding primary conductor;
a selectable connection between said array of auxiliary conductors and electrical ground;
a semiconductor chip mounted on said substrate, said chip including a contact pad;
an interconnect between said contact pad and a primary conductor in said array.
2. The device of claim 1 , wherein said selectable connection between said array of auxiliary conductors and electrical ground comprises no connection between said array of auxiliary conductors and electrical ground.
3. The device of claim 1 , wherein said selectable connection between said array of auxiliary conductors and electrical ground comprises an interconnect between every auxiliary conductor and a ground contact.
4. The device of claim 1 , wherein said selectable connection between said array of auxiliary conductors and electrical ground comprises an interconnect between selected ones of said array of auxiliary conductors and a ground contact.
5. The device of claim 1 , wherein said selectable connection between said array of auxiliary conductors and electrical ground comprises solder between every auxiliary conductor and a ground contact.
6. The device of claim 1 , wherein said selectable connection between said array of auxiliary conductors and electrical ground comprises solder between selected ones of said array of auxiliary conductors and a ground contact.
7. A microelectronic device, comprising:
a substrate comprising:
a ground plane;
an array of primary conductors in a first plane in said substrate above said ground plane;
an array of auxiliary conductors in a second plane in said substrate, each auxiliary conductor in said array substantially overlying a corresponding primary conductor;
a selectable connection between said array of auxiliary conductors and said ground plane;
a semiconductor chip mounted on said substrate, said chip including a contact pad;
an interconnect between said contact pad and a primary conductor in said array.
8. The device of claim 7 , wherein said selectable connection between said array of auxiliary conductors and electrical ground comprises no connection between said array of auxiliary conductors and said ground plane.
9. The device of claim 7 , wherein said selectable connection between said array of auxiliary conductors and said ground plane comprises an interconnect between every auxiliary conductor and said ground plane.
10. The device of claim 7 , wherein said selectable connection between said array of auxiliary conductors and said ground plane comprises an interconnect between selected ones of said array of auxiliary conductors and said ground plane.
11. The device of claim 7 , wherein said selectable connection between said array of auxiliary conductors and said ground plane comprises solder between every auxiliary conductor and said ground plane.
12. The device of claim 7 , wherein said selectable connection between said array of auxiliary conductors and said ground plane comprises solder between selected ones of said array of auxiliary conductors and said ground plane.
13. A microelectronic device, comprising:
a substrate having first and second surfaces;
an array of primary conductors on said first surface;
an array of auxiliary conductors on said second surface electrically insulated from said primary conductors, wherein each auxiliary conductor in said array substantially only overlies a corresponding different primary conductor;
a semiconductor chip mounted over said second surface, said chip including a contact pad;
an interconnect between said contact pad on said chip and a primary conductor in said array.
14. The device of claim 13 , wherein said substrate is flexible.
15. The device of claim 14 , wherein said substrate is polyimide film.
16. The device of claim 13 , wherein said interconnect between said contact pad on said chip and said primary conductor comprises solder.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/411,531 US7132740B2 (en) | 1999-12-29 | 2003-04-10 | Semiconductor package with conductor impedance selected during assembly |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US17345099P | 1999-12-29 | 1999-12-29 | |
US09/750,393 US6563208B2 (en) | 1999-12-29 | 2000-12-28 | Semiconductor package with conductor impedance selected during assembly |
US10/411,531 US7132740B2 (en) | 1999-12-29 | 2003-04-10 | Semiconductor package with conductor impedance selected during assembly |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/750,393 Continuation US6563208B2 (en) | 1999-12-29 | 2000-12-28 | Semiconductor package with conductor impedance selected during assembly |
Publications (2)
Publication Number | Publication Date |
---|---|
US20030201519A1 US20030201519A1 (en) | 2003-10-30 |
US7132740B2 true US7132740B2 (en) | 2006-11-07 |
Family
ID=22632093
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/750,393 Expired - Lifetime US6563208B2 (en) | 1999-12-29 | 2000-12-28 | Semiconductor package with conductor impedance selected during assembly |
US10/411,531 Expired - Lifetime US7132740B2 (en) | 1999-12-29 | 2003-04-10 | Semiconductor package with conductor impedance selected during assembly |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/750,393 Expired - Lifetime US6563208B2 (en) | 1999-12-29 | 2000-12-28 | Semiconductor package with conductor impedance selected during assembly |
Country Status (4)
Country | Link |
---|---|
US (2) | US6563208B2 (en) |
EP (1) | EP1113497A3 (en) |
JP (1) | JP2001196499A (en) |
KR (1) | KR100686671B1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070251720A1 (en) * | 2003-05-14 | 2007-11-01 | Wright Mitchel E | Tailoring impedances of conductive traces in a circuit board |
US20090195325A1 (en) * | 2008-02-01 | 2009-08-06 | Viasat, Inc. | Differential internally matched wire-bond interface |
US11728283B2 (en) | 2020-08-10 | 2023-08-15 | Samsung Electronics Co., Ltd. | Package substrate and semiconductor package including the same |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1113497A3 (en) * | 1999-12-29 | 2006-01-25 | Texas Instruments Incorporated | Semiconductor package with conductor impedance selected during assembly |
DE10031843A1 (en) * | 2000-06-30 | 2002-01-10 | Alcatel Sa | Electrical or opto-electrical component with a plastic packaging and method for varying the impedance of a connection line of such a component |
US7149666B2 (en) * | 2001-05-30 | 2006-12-12 | University Of Washington | Methods for modeling interactions between massively coupled multiple vias in multilayered electronic packaging structures |
JP3674780B2 (en) * | 2001-11-29 | 2005-07-20 | ユーディナデバイス株式会社 | High frequency semiconductor device |
US20040012935A1 (en) * | 2002-07-16 | 2004-01-22 | Matsushita Electric Industrial Co., Ltd. | Printed wiring board |
US7265443B2 (en) * | 2005-04-29 | 2007-09-04 | Texas Instruments Incorporated | Wire bonded semiconductor device having low inductance and noise |
US7605477B2 (en) * | 2007-01-25 | 2009-10-20 | Raytheon Company | Stacked integrated circuit assembly |
MY191544A (en) | 2016-12-27 | 2022-06-30 | Intel Corp | Multi-conductor interconnect structure for a microelectronic device |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4626889A (en) | 1983-12-23 | 1986-12-02 | Hitachi, Ltd. | Stacked differentially driven transmission line on integrated circuit |
US5925925A (en) | 1996-04-03 | 1999-07-20 | Bull, S.A. | Three-dimensional integrated circuit package having conductors at different fixed potentials |
US6137168A (en) | 1998-01-13 | 2000-10-24 | Lsi Logic Corporation | Semiconductor package with traces routed underneath a die |
US6172305B1 (en) | 1997-07-31 | 2001-01-09 | Kyocera Corporation | Multilayer circuit board |
US6201308B1 (en) | 1997-09-16 | 2001-03-13 | Nec Corporation | Semiconductor chip having a low-noise ground line |
US6229209B1 (en) * | 1995-02-23 | 2001-05-08 | Matsushita Electric Industrial Co., Ltd. | Chip carrier |
US6563208B2 (en) * | 1999-12-29 | 2003-05-13 | Texas Instruments Incorporated | Semiconductor package with conductor impedance selected during assembly |
Family Cites Families (82)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4498122A (en) * | 1982-12-29 | 1985-02-05 | At&T Bell Laboratories | High-speed, high pin-out LSI chip package |
KR920005701B1 (en) * | 1989-07-20 | 1992-07-13 | 현대전자산업 주식회사 | Metal barrier layer for semiconductor integrated circuit |
EP0459179B1 (en) * | 1990-05-28 | 1995-04-05 | Siemens Aktiengesellschaft | IC-housing made of three coated dielectric plates |
US5228911A (en) * | 1991-04-18 | 1993-07-20 | Merck Patent Gesellschaft Mit Beschrankter Haftung | Oxidized graphite flaky particles and pigments based thereon |
JPH05109924A (en) * | 1991-10-17 | 1993-04-30 | Ngk Spark Plug Co Ltd | Integrated circuit package |
US5261916A (en) * | 1991-12-12 | 1993-11-16 | Target Therapeutics | Detachable pusher-vasoocclusive coil assembly with interlocking ball and keyway coupling |
US5234437A (en) * | 1991-12-12 | 1993-08-10 | Target Therapeutics, Inc. | Detachable pusher-vasoocclusion coil assembly with threaded coupling |
US5266912A (en) * | 1992-08-19 | 1993-11-30 | Micron Technology, Inc. | Inherently impedance matched multiple integrated circuit module |
US5350397A (en) * | 1992-11-13 | 1994-09-27 | Target Therapeutics, Inc. | Axially detachable embolic coil assembly |
US5312415A (en) * | 1992-09-22 | 1994-05-17 | Target Therapeutics, Inc. | Assembly for placement of embolic coils using frictional placement |
US5250071A (en) * | 1992-09-22 | 1993-10-05 | Target Therapeutics, Inc. | Detachable embolic coil assembly using interlocking clasps and method of use |
US5690671A (en) * | 1994-12-13 | 1997-11-25 | Micro Interventional Systems, Inc. | Embolic elements and methods and apparatus for their delivery |
JP2963037B2 (en) * | 1995-11-30 | 1999-10-12 | 三洋電機株式会社 | Disk recording and playback device |
US6406420B1 (en) * | 1997-01-02 | 2002-06-18 | Myocor, Inc. | Methods and devices for improving cardiac function in hearts |
US6077214A (en) * | 1998-07-29 | 2000-06-20 | Myocor, Inc. | Stress reduction apparatus and method |
US6050936A (en) * | 1997-01-02 | 2000-04-18 | Myocor, Inc. | Heart wall tension reduction apparatus |
FR2768324B1 (en) * | 1997-09-12 | 1999-12-10 | Jacques Seguin | SURGICAL INSTRUMENT FOR PERCUTANEOUSLY FIXING TWO AREAS OF SOFT TISSUE, NORMALLY MUTUALLY REMOTE, TO ONE ANOTHER |
US6332893B1 (en) * | 1997-12-17 | 2001-12-25 | Myocor, Inc. | Valve to myocardium tension members device and method |
US6190408B1 (en) * | 1998-03-05 | 2001-02-20 | The University Of Cincinnati | Device and method for restructuring the heart chamber geometry |
US6143024A (en) * | 1998-06-04 | 2000-11-07 | Sulzer Carbomedics Inc. | Annuloplasty ring having flexible anterior portion |
US6250308B1 (en) * | 1998-06-16 | 2001-06-26 | Cardiac Concepts, Inc. | Mitral valve annuloplasty ring and method of implanting |
US6701929B2 (en) * | 1999-03-03 | 2004-03-09 | Hany Hussein | Device and method for treatment of congestive heart failure |
US6752813B2 (en) * | 1999-04-09 | 2004-06-22 | Evalve, Inc. | Methods and devices for capturing and fixing leaflets in valve repair |
CA2620783C (en) * | 1999-04-09 | 2011-04-05 | Evalve, Inc. | Methods and apparatus for cardiac valve repair |
US20040044350A1 (en) * | 1999-04-09 | 2004-03-04 | Evalve, Inc. | Steerable access sheath and methods of use |
US6709382B1 (en) * | 1999-05-04 | 2004-03-23 | Simon Marcus Horner | Cardiac assist method and apparatus |
US6626899B2 (en) * | 1999-06-25 | 2003-09-30 | Nidus Medical, Llc | Apparatus and methods for treating tissue |
US6997951B2 (en) * | 1999-06-30 | 2006-02-14 | Edwards Lifesciences Ag | Method and device for treatment of mitral insufficiency |
SE521337C2 (en) * | 1999-08-09 | 2003-10-21 | Electrolux Ab | Textile washing machine with steam drying |
US6299637B1 (en) * | 1999-08-20 | 2001-10-09 | Samuel M. Shaolian | Transluminally implantable venous valve |
US20030069570A1 (en) * | 1999-10-02 | 2003-04-10 | Witzel Thomas H. | Methods for repairing mitral valve annulus percutaneously |
FR2799364B1 (en) * | 1999-10-12 | 2001-11-23 | Jacques Seguin | MINIMALLY INVASIVE CANCELING DEVICE |
US6626930B1 (en) * | 1999-10-21 | 2003-09-30 | Edwards Lifesciences Corporation | Minimally invasive mitral valve repair method and apparatus |
US7507252B2 (en) * | 2000-01-31 | 2009-03-24 | Edwards Lifesciences Ag | Adjustable transluminal annuloplasty system |
US6402781B1 (en) * | 2000-01-31 | 2002-06-11 | Mitralife | Percutaneous mitral annuloplasty and cardiac reinforcement |
US6797002B2 (en) * | 2000-02-02 | 2004-09-28 | Paul A. Spence | Heart valve repair apparatus and methods |
KR20010087130A (en) * | 2000-03-06 | 2001-09-15 | 0 | System and method for providing advertisement and technical skill premium by using network |
JP4257485B2 (en) * | 2000-06-21 | 2009-04-22 | セイコーエプソン株式会社 | Ceramic film, manufacturing method thereof, semiconductor device, and piezoelectric element |
EP1330189B1 (en) * | 2000-06-23 | 2007-12-19 | Viacor Incorporated | Automated annular plication for mitral valve repair |
US7527646B2 (en) * | 2000-09-20 | 2009-05-05 | Ample Medical, Inc. | Devices, systems, and methods for retaining a native heart valve leaflet |
US6723038B1 (en) * | 2000-10-06 | 2004-04-20 | Myocor, Inc. | Methods and devices for improving mitral valve function |
US6918917B1 (en) * | 2000-10-10 | 2005-07-19 | Medtronic, Inc. | Minimally invasive annuloplasty procedure and apparatus |
JP4184794B2 (en) * | 2001-02-05 | 2008-11-19 | ビアカー・インコーポレーテッド | Method and apparatus for improving mitral valve function |
NZ528076A (en) * | 2001-03-02 | 2005-09-30 | Medimmune Inc | Methods of preventing or treating inflammatory or autoimmune disorders by administering integrin alphav beta3 antagonists with an immunomodulatory agents, anti-inflammatory agents, TNF-alpha antagonists or CD2 binding molecules |
US6619291B2 (en) * | 2001-04-24 | 2003-09-16 | Edwin J. Hlavka | Method and apparatus for catheter-based annuloplasty |
US20030069635A1 (en) * | 2001-05-29 | 2003-04-10 | Cartledge Richard G. | Prosthetic heart valve |
US6726716B2 (en) * | 2001-08-24 | 2004-04-27 | Edwards Lifesciences Corporation | Self-molding annuloplasty ring |
DE10142232B4 (en) * | 2001-08-29 | 2021-04-29 | Roche Diabetes Care Gmbh | Process for the production of an analytical aid with a lancet and test element |
US7125421B2 (en) * | 2001-08-31 | 2006-10-24 | Mitral Interventions, Inc. | Method and apparatus for valve repair |
US20030050693A1 (en) * | 2001-09-10 | 2003-03-13 | Quijano Rodolfo C. | Minimally invasive delivery system for annuloplasty rings |
JP4458845B2 (en) * | 2001-10-01 | 2010-04-28 | アンプル メディカル,インコーポレイテッド | Medical device |
JP2003122402A (en) * | 2001-10-09 | 2003-04-25 | Yaskawa Electric Corp | Method for controlling servo controller |
US7144363B2 (en) * | 2001-10-16 | 2006-12-05 | Extensia Medical, Inc. | Systems for heart treatment |
US7052487B2 (en) * | 2001-10-26 | 2006-05-30 | Cohn William E | Method and apparatus for reducing mitral regurgitation |
US6949122B2 (en) * | 2001-11-01 | 2005-09-27 | Cardiac Dimensions, Inc. | Focused compression mitral valve device and method |
US6575971B2 (en) * | 2001-11-15 | 2003-06-10 | Quantum Cor, Inc. | Cardiac valve leaflet stapler device and methods thereof |
US6740107B2 (en) * | 2001-12-19 | 2004-05-25 | Trimedyne, Inc. | Device for treatment of atrioventricular valve regurgitation |
US6764510B2 (en) * | 2002-01-09 | 2004-07-20 | Myocor, Inc. | Devices and methods for heart valve treatment |
US7125420B2 (en) * | 2002-02-05 | 2006-10-24 | Viacor, Inc. | Method and apparatus for improving mitral valve function |
US7048754B2 (en) * | 2002-03-01 | 2006-05-23 | Evalve, Inc. | Suture fasteners and methods of use |
US6797001B2 (en) * | 2002-03-11 | 2004-09-28 | Cardiac Dimensions, Inc. | Device, assembly and method for mitral valve repair |
US6770063B2 (en) * | 2002-04-23 | 2004-08-03 | Uresil, L.P. | Thoracic vent kit |
US7101395B2 (en) * | 2002-06-12 | 2006-09-05 | Mitral Interventions, Inc. | Method and apparatus for tissue connection |
US8287555B2 (en) * | 2003-02-06 | 2012-10-16 | Guided Delivery Systems, Inc. | Devices and methods for heart valve repair |
US6723036B2 (en) * | 2002-06-19 | 2004-04-20 | Contour Fabricators, Inc. | Methods and apparatus for folding sheet material |
DE60318861T2 (en) * | 2002-08-13 | 2009-01-08 | The General Hospital Corp., Boston | HEART DEVICES FOR THE PERCUTANEOUS REPAIR OF ATRIOVENTRICULAR FLAPS |
US7297150B2 (en) * | 2002-08-29 | 2007-11-20 | Mitralsolutions, Inc. | Implantable devices for controlling the internal circumference of an anatomic orifice or lumen |
AU2003277116A1 (en) * | 2002-10-01 | 2004-04-23 | Ample Medical, Inc. | Devices, systems, and methods for reshaping a heart valve annulus |
US20040133062A1 (en) * | 2002-10-11 | 2004-07-08 | Suresh Pai | Minimally invasive cardiac force transfer structures |
EP1553897A1 (en) * | 2002-10-24 | 2005-07-20 | Boston Scientific Limited | Venous valve apparatus and method |
US20040097979A1 (en) * | 2002-11-14 | 2004-05-20 | Oleg Svanidze | Aortic valve implantation device |
US6878331B2 (en) * | 2002-12-03 | 2005-04-12 | Ucar Carbon Company Inc. | Manufacture of carbon composites by hot pressing |
US20040133279A1 (en) * | 2003-01-06 | 2004-07-08 | Krueger David J. | Surgical implants for use as spinal spacers |
US20040133240A1 (en) * | 2003-01-07 | 2004-07-08 | Cardiac Dimensions, Inc. | Electrotherapy system, device, and method for treatment of cardiac valve dysfunction |
US6956705B2 (en) * | 2003-02-05 | 2005-10-18 | Pentax Corporation | Structure of a lens barrel |
US20040162510A1 (en) * | 2003-02-14 | 2004-08-19 | Medtronic Physio-Control Corp | Integrated external chest compression and defibrillation devices and methods of operation |
US6871523B2 (en) * | 2003-03-31 | 2005-03-29 | Matsushita Electric Industrial Co., Ltd. | Method and apparatus for forming microchannels in a filament wire |
US6784510B1 (en) * | 2003-04-16 | 2004-08-31 | Freescale Semiconductor, Inc. | Magnetoresistive random access memory device structures |
US20040220657A1 (en) * | 2003-05-02 | 2004-11-04 | Cardiac Dimensions, Inc., A Washington Corporation | Tissue shaping device with conformable anchors |
US7383148B2 (en) * | 2004-03-25 | 2008-06-03 | Siemens Building Technologies, Inc. | Method and apparatus for graphically displaying a building system |
US7641686B2 (en) * | 2004-04-23 | 2010-01-05 | Direct Flow Medical, Inc. | Percutaneous heart valve with stentless support |
US7704277B2 (en) * | 2004-09-14 | 2010-04-27 | Edwards Lifesciences Ag | Device and method for treatment of heart valve regurgitation |
-
2000
- 2000-12-20 EP EP00127906A patent/EP1113497A3/en not_active Withdrawn
- 2000-12-26 JP JP2000394486A patent/JP2001196499A/en not_active Abandoned
- 2000-12-28 KR KR1020000083615A patent/KR100686671B1/en active IP Right Grant
- 2000-12-28 US US09/750,393 patent/US6563208B2/en not_active Expired - Lifetime
-
2003
- 2003-04-10 US US10/411,531 patent/US7132740B2/en not_active Expired - Lifetime
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4626889A (en) | 1983-12-23 | 1986-12-02 | Hitachi, Ltd. | Stacked differentially driven transmission line on integrated circuit |
US6229209B1 (en) * | 1995-02-23 | 2001-05-08 | Matsushita Electric Industrial Co., Ltd. | Chip carrier |
US5925925A (en) | 1996-04-03 | 1999-07-20 | Bull, S.A. | Three-dimensional integrated circuit package having conductors at different fixed potentials |
US6172305B1 (en) | 1997-07-31 | 2001-01-09 | Kyocera Corporation | Multilayer circuit board |
US6201308B1 (en) | 1997-09-16 | 2001-03-13 | Nec Corporation | Semiconductor chip having a low-noise ground line |
US6137168A (en) | 1998-01-13 | 2000-10-24 | Lsi Logic Corporation | Semiconductor package with traces routed underneath a die |
US6563208B2 (en) * | 1999-12-29 | 2003-05-13 | Texas Instruments Incorporated | Semiconductor package with conductor impedance selected during assembly |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070251720A1 (en) * | 2003-05-14 | 2007-11-01 | Wright Mitchel E | Tailoring impedances of conductive traces in a circuit board |
US7518884B2 (en) * | 2003-05-14 | 2009-04-14 | Hewlett-Packard Development Company, L.P. | Tailoring impedances of conductive traces in a circuit board |
US20090195325A1 (en) * | 2008-02-01 | 2009-08-06 | Viasat, Inc. | Differential internally matched wire-bond interface |
WO2009099912A2 (en) * | 2008-02-01 | 2009-08-13 | Viasat, Inc. | Differential internally matched wire-bond interface |
WO2009099912A3 (en) * | 2008-02-01 | 2013-03-28 | Viasat, Inc. | Differential internally matched wire-bond interface |
US8436450B2 (en) * | 2008-02-01 | 2013-05-07 | Viasat, Inc. | Differential internally matched wire-bond interface |
US11728283B2 (en) | 2020-08-10 | 2023-08-15 | Samsung Electronics Co., Ltd. | Package substrate and semiconductor package including the same |
Also Published As
Publication number | Publication date |
---|---|
US6563208B2 (en) | 2003-05-13 |
US20030201519A1 (en) | 2003-10-30 |
US20020003291A1 (en) | 2002-01-10 |
EP1113497A3 (en) | 2006-01-25 |
EP1113497A2 (en) | 2001-07-04 |
KR20010062801A (en) | 2001-07-07 |
KR100686671B1 (en) | 2007-02-26 |
JP2001196499A (en) | 2001-07-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7247932B1 (en) | Chip package with capacitor | |
US7550842B2 (en) | Integrated circuit assembly | |
US6501157B1 (en) | Substrate for accepting wire bonded or flip-chip components | |
US4926241A (en) | Flip substrate for chip mount | |
USRE42332E1 (en) | Integrated circuit package, ball-grid array integrated circuit package | |
US5475264A (en) | Arrangement having multilevel wiring structure used for electronic component module | |
US5841191A (en) | Ball grid array package employing raised metal contact rings | |
US5093708A (en) | Multilayer integrated circuit module | |
EP0782191A2 (en) | Multi-level stacked integrated-circuit-chip assembly | |
US5029325A (en) | TAB tape translator for use with semiconductor devices | |
US7611981B1 (en) | Optimized circuit design layout for high performance ball grid array packages | |
US7132740B2 (en) | Semiconductor package with conductor impedance selected during assembly | |
US20090091019A1 (en) | Memory Packages Having Stair Step Interconnection Layers | |
US6642137B2 (en) | Method for manufacturing a package structure of integrated circuits | |
US20040058477A1 (en) | Integrated circuit package and manufacturing method therefor | |
US6586825B1 (en) | Dual chip in package with a wire bonded die mounted to a substrate | |
US20080136011A1 (en) | Semiconductor device | |
US7948093B2 (en) | Memory IC package assembly having stair step metal layer and apertures | |
US5434450A (en) | PGA package type semiconductor device having leads to be supplied with power source potential | |
KR100219473B1 (en) | Semiconductor device the use for tab lead and method of mount of the same | |
WO2003065440A1 (en) | Method to arrange silicon structures on top of each other and arrangement herefor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553) Year of fee payment: 12 |