Búsqueda Imágenes Maps Play YouTube Noticias Gmail Drive Más »
Iniciar sesión
Usuarios de lectores de pantalla: deben hacer clic en este enlace para utilizar el modo de accesibilidad. Este modo tiene las mismas funciones esenciales pero funciona mejor con el lector.

Patentes

  1. Búsqueda avanzada de patentes
Número de publicaciónUS7323364 B2
Tipo de publicaciónConcesión
Número de solicitudUS 11/411,185
Fecha de publicación29 Ene 2008
Fecha de presentación25 Abr 2006
Fecha de prioridad18 May 2005
TarifaPagadas
También publicado comoUS7033861, US20060263938
Número de publicación11411185, 411185, US 7323364 B2, US 7323364B2, US-B2-7323364, US7323364 B2, US7323364B2
InventoresJulian Partridge, James Douglas Wehrly, Jr., David Roper
Cesionario originalStaktek Group L.P.
Exportar citaBiBTeX, EndNote, RefMan
Enlaces externos: USPTO, Cesión de USPTO, Espacenet
Stacked module systems and method
US 7323364 B2
Resumen
A combination composed from a form standard and a CSP is attached to flex circuitry. Solder paste is applied to first selected locations on the flex circuitry and adhesive is applied to second selected locations on the flex circuitry. The flex circuitry and the combination of the form standard and CSP are brought into proximity with each other. During solder reflow operation, a force is applied that tends to bring the combination and flex circuitry closer together. As the heat of solder reflow melts the contacts of the CSP, the combination collapses toward the flex circuitry displacing the adhesive as the solder paste and contacts merge into solder joints. In a preferred embodiment, the form standard will be devised of heat transference material, a metal, for example, such as copper would be preferred, to improve thermal performance. In other embodiments, the methods of the invention may be used to attach a CSP without a form standard to flex circuitry.
Imágenes(4)
Previous page
Next page
Reclamaciones(21)
1. A method for devising a high-density circuit module, the method comprising the steps of:
providing a first CSP having contacts;
providing flex circuitry;
disposing the first CSP and the flex circuitry in proximity to each other; and
applying a force to move the first CSP toward the flex circuitry during a solder reflow operation.
2. The method of claim 1 in which the step of applying force to move the first CSP toward the flex circuitry comprises placing a weight on the first CSP.
3. The method of claim 1 in which the step of applying force to move the first CSP toward the flex circuitry comprises applying a downward force on the first CSP with a fixture while the flex circuitry is supported from beneath.
4. The method of claim 1 in which the flex circuitry comprises at least two conductive layers.
5. The method of claim 1 further comprising the steps of:
providing a second CSP;
disposing the second CSP above the first CSP; and
connecting the first and second CSPs with the flex circuitry.
6. The method of claim 5 in which the flex circuitry comprises at least two conductive layers.
7. A high-density circuit module devised in accordance with the method of claim 1.
8. A method for devising a high-density circuit module, the method comprising the steps of:
providing a first CSP having a planar surface rising above which are contacts;
providing a flex circuit upon which is located solder paste at first selected sites and adhesive at second selected sites;
disposing the first CSP adjacent to the flex circuit to realize areas of contact between the contacts and the first selected sites;
applying a force to the first CSP during a solder reflow operation to move the first CSP and flex circuit closer together while displacing the adhesive.
9. The method of claim 8 in which the flex circuit comprises two conductive layers.
10. The method of claim 9 in which the displaced adhesive cures after the solder reflow operation.
11. The method of claim 8 further comprising the step of disposing a second CSP above the first CSP and connecting the flex circuit to the second CSP.
12. The method of claim 11 in which the flex circuit comprises two conductive layers.
13. The method of claim 12 in which the displaced adhesive cures after the solder reflow operation.
14. A method for devising a high-density circuit module, the method comprising the steps of:
providing a first CSP having a first major surface and a second major surface along which are disposed contacts;
providing a flex circuit having a first end portion;
disposing the first CSP and the flex circuit in proximity to each other;
applying a force to move the first CSP toward the flex circuitry;
performing a solder reflow operation to connect the contacts of the first CSP to the flex circuit; and
disposing the first end portion of the flex circuit along at least a first portion of the first major surface of the first CSP.
15. The method of claim 14 further comprising the step of attaching the first end portion of the flex circuit to at least part of the first portion of the first major surface of the first CSP with adhesive.
16. The method of claim 14 in which the flex circuit further comprises a second end portion, and the method further comprises the step of disposing the second end portion of the flex circuit along at least a second portion of the first major surface of the first CSP.
17. The method of claim 16 further comprising the steps of:
attaching the first end portion of the flex circuit to at least part of the first portion of the first major surface of the first CSP with adhesive; and
attaching the second end portion of the flex circuit to at least part of the second portion of the first major surface of the first CSP with adhesive.
18. The method of claim 14 further comprising the steps of:
disposing a second CSP in a stacked configuration with the first CSP; and
connecting the second CSP to the first end portion of the flex circuit.
19. The method of claim 15 further comprising the steps of:
disposing a second CSP in a stacked configuration with the first CSP; and
connecting the second CSP to the first end portion of the flex circuit.
20. The method of claim 16 further comprising the steps of:
disposing a second CSP in a stacked configuration with the first CSP;
connecting the second CSP to the first end portion of the flex circuit; and
connecting the second CSP to the second end portion of the flex circuit.
21. The method of claim 17 further comprising the steps of:
disposing a second CSP in a stacked configuration with the first CSP;
connecting the second CSP to the first end portion of the flex circuit; and
connecting the second CSP to the second end portion of the flex circuit.
Descripción
RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 11/131,812 filed May 18, 2005, now U.S. Pat. No. 7,033,861 B1, which is incorporated herein for all purposes.

U.S. patent application Ser. No. 10/453,398, filed Jun. 3, 2003, is incorporated herein by reference for all purposes.

TECHNICAL FIELD

The present invention relates to aggregating integrated circuits and, in particular, to methods for creating high density modules from chip-scale type devices.

BACKGROUND OF THE INVENTION

A variety of techniques are used to stack packaged integrated circuits. Some methods require special packages, while other techniques stack conventional packages.

The predominant package configuration employed during the past decade has encapsulated an integrated circuit (IC) in a plastic surround typically having a rectangular configuration. The enveloped integrated circuit is connected to the application environment through leads emergent from the edge periphery of the plastic encapsulation. Such “leaded packages” have been the constituent elements most commonly employed by techniques for stacking packaged integrated circuits.

Leaded packages play an important role in electronics, but efforts to miniaturize electronic components and assemblies have driven development of technologies that preserve circuit board surface area. Because leaded packages have leads emergent from peripheral sides of the package, leaded packages occupy more than a minimal amount of circuit board surface area. Consequently, alternatives to leaded packages known as chip scale packaging or “CSP” have recently gained market share.

CSP refers generally to packages that provide connection to an integrated circuit through a set of contacts (often embodied as “bumps” or “balls”) arrayed across a major surface of the package. Instead of leads emergent from a peripheral side of the package, contacts are placed on a major surface and typically emerge from the planar bottom surface of the package. The absence of “leads” on package sides renders most stacking techniques devised for leaded packages inapplicable for CSP stacking.

A variety of previous techniques for stacking CSPs may present complex assembly problems. What is needed, therefore, is a technique and system for stacking CSPs that provides a thermally-efficient, reliable structure that performs well at higher frequencies but does not add excessive height to the stack yet allows efficient production at reasonable cost with readily understood and managed materials and methods.

SUMMARY OF THE INVENTION

The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. Although the present invention is applied most frequently to chip scale packages that contain one die, it may be employed with chip scale packages that include more than one integrated circuit die. Multiple numbers of CSPs may be stacked in accordance with the present invention. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry. That flex circuitry may exhibit one or two or more conductive layers.

A combination composed from a form standard and a CSP is attached to flex circuitry. Solder paste is applied to first selected locations on the flex circuitry and adhesive is applied to second selected locations on the flex circuitry. The flex circuitry and the combination of the form standard and CSP are brought into proximity with each other. During solder reflow operation, a force is applied that tends to bring the combination and flex circuitry closer together. As the heat of solder reflow melts the contacts of the CSP, the combination collapses toward the flex circuitry displacing the adhesive as the solder paste and contacts merge into solder joints. In a preferred embodiment, the form standard will be devised of heat transference material, a metal, for example, such as copper would be preferred, to improve thermal performance. In other embodiments, the methods of the invention may be used to attach a CSP without a form standard to flex circuitry.

SUMMARY OF THE DRAWINGS

FIG. 1 illustrates a step in a prior art method for constructing a high-density circuit module.

FIG. 2 depicts a step in a prior art method for constructing a high-density circuit module.

FIG. 3 depicts a step in a prior art method for constructing a high-density circuit module.

FIG. 4 depicts a step in a method for constructing a high-density circuit module in accordance with a preferred embodiment of the present invention.

FIG. 5 depicts a step in a method for construction of a high-density circuit module in accordance with a preferred embodiment of the present invention.

FIG. 6 depicts a step in a method for construction of a high-density circuit module in accordance with a preferred embodiment of the present invention.

FIG. 7 depicts a high-density circuit module in accordance with a preferred embodiment of the present invention.

DESCRIPTION OF PREFERRED EMBODIMENTS

FIGS. 1-3 depict steps in a prior art method for constructing a high-density circuit module. FIG. 1 depicts a CSP 18 attached with adhesive 36 to form standard 34. In the configurations depicted, form standard 34 is devised to be employed with a CSP to provide a standard form for flex circuitry connector(s). Contacts 28 of CSP 18 have been compressed in a solid or semi-solid state and solder paste 41 and adhesive 43 have been applied to flex circuitry 30 and 32. FIG. 2 depicts a step in a prior art method for construction of a high-density module. Contacts 28 and solder paste sites 41 have come into contact as have form standard 34 and adhesive sites 43. FIG. 3 illustrates how solder paste sites 41 and compressed contacts 28 have merged to form solder joints and flex circuitry 30 and 32 has been wrapped about CSP 18.

FIG. 4 depicts a method in accordance with a preferred embodiment of the present invention. CSP 18 and form standard 34 are attached with adhesive 36 to form a primary combination 50. The depicted configuration of form standard 34 is one of many that can provide a standard form about which flex circuitry may be disposed. This allows a connective design implemented in flex circuitry to be used with CSPs of a variety of designs and configurations. Form standard 34 may also provide thermal advantages particularly when devised from metallic materials such as copper and copper alloys for example. Other configurations of form standard 34 may be employed with the present invention including but not limited to those that extend across the bottom surface 19 of CSP 18. Further, some form standards may not extend beyond the perimeter of CSP 18. Still other embodiments may not employ a form standard and may use the methods of the present invention to affix flex circuitry to CSP bodies.

Flex circuitry in this embodiment is comprised of flex circuits 30 and 32. Other embodiments may use one contiguous flex circuit or several and the flex circuitry may be flexible throughout or flexible in some areas and rigid in other areas. Flex circuitry has solder paste applied at selected sites as represented by reference 41 and an adhesive at selected sites identified by reference 44. The adhesive is, preferably, a thermoset adhesive or epoxy that will not soften during subsequent reflow operations such as exposure to 200-250 degrees Centigrade, for example.

In FIG. 5, the primary combination and the flex circuitry have been disposed in proximity to each other. Typically, there will be contact between contacts 28 and solder paste sites 41 but a large gap “G” between flex circuitry and form standard 34 will be exhibited because primary combination 50 is suspended above flex circuits 30 and 32 by the adhesive 44 and the uncompressed height of contacts 28 and solder paste 41. Weight 52 is disposed above CSP 18 on primary combination 50 while flex circuits 30 and 32 are supported from beneath by work support 54. Work support 54 is preferably a carrier that is in motion through an assembly process or may be stationary. Primary combination 50 and the flex circuitry are subjected to a solder reflow operation examples of which are well known to those of skill in the art.

With primary combination 50 and flex circuits 30 and 32 under force F which tends to move them closer together, primary combination 50 collapses toward the flex circuitry as contacts 28 melt in the solder reflow operation and merge with the solder paste on flex circuits 30 and 32 to form solder joints 56 as adhesive 44 is compressed as well. In preferred modes, adhesive 44 cures after the solder has melted. Unit 58 is formed by such a process and comprises CSP 18, form standard 34 and flex circuitry 30 and 32. A unit 58 devised in accordance with the preferred methods described is shown in FIG. 7. After appreciating this specification those of skill will recognize that force F may be applied by several methods and apparatus including weights and fixtures that apply force F during the reflow operation that melts contacts 28. An alternate system using a fixture 38 to apply force F is shown in FIG. 6. These processes are amenable to implementation in a standard pick and place operation. Once devised, unit 58 may then be employed as a unit in a stacked module such as that shown in FIG. 8.

FIG. 8 depicts a high-density circuit module 60 comprised of unit 58 in combination with upper CSP 16 which has its own attached form standard 34. To form module 60, one or more upper CSPs 16 may be combined with unit 58. When aggregating more than two CSPs in a module 60, further iterations of flex circuitry will typically be employed as those of skill will understand. Each of the upper CSPs may optionally include an upper form standard 34 such as the one illustrated in FIG. 8 associated with upper CSP 16. Module 60 is shown with module contacts 38.

Although the present invention has been described in detail, it will be apparent to those skilled in the art that the invention may be embodied in a variety of specific forms and that various changes, substitutions and alterations can be made without departing from the spirit and scope of the invention. The described embodiments are only illustrative and not restrictive and the scope of the invention is, therefore, indicated by the following claims.

Citas de patentes
Patente citada Fecha de presentación Fecha de publicación Solicitante Título
US341112213 Ene 196612 Nov 1968IbmElectrical resistance element and method of fabricating
US343660425 Abr 19661 Abr 1969Texas Instruments IncComplex integrated circuit array and method for fabricating same
US36543948 Jul 19694 Abr 1972Gordon Eng CoField effect transistor switch, particularly for multiplexing
US37469346 May 197117 Jul 1973Siemens AgStack arrangement of semiconductor chips
US376643912 Ene 197216 Oct 1973Gen ElectricElectronic module using flexible printed circuit board with heat sink means
US37727763 Dic 196920 Nov 1973Thomas & Betts CorpMethod of interconnecting memory plane boards
US380676715 Mar 197323 Abr 1974Tek Wave IncInterboard connector
US398354727 Jun 197428 Sep 1976International Business Machines - IbmThree-dimensional bubble device
US407951130 Jul 197621 Mar 1978Amp IncorporatedMethod for packaging hermetically sealed integrated circuit chips on lead frames
US428884120 Sep 19798 Sep 1981Bell Telephone Laboratories, IncorporatedDouble cavity semiconductor chip carrier
US43814211 Jul 198026 Abr 1983Tektronix, Inc.Electromagnetic shield for electronic equipment
US44065082 Jul 198127 Sep 1983Thomas & Betts CorporationDual-in-line package assembly
US442079410 Sep 198113 Dic 1983Research, IncorporatedIntegrated circuit switch
US443723523 Ago 198220 Mar 1984Honeywell Information Systems Inc.Integrated circuit package
US451336822 May 198123 Abr 1985Data General CorporationDigital data processing system having object-based logical memory addressing and self-structuring modular memory
US45875969 Abr 19846 May 1986Amp IncorporatedHigh density mother/daughter circuit board connector
US46459444 Sep 198424 Feb 1987Matsushita Electric Industrial Co., Ltd.MOS register for selecting among various data inputs
US469652513 Dic 198529 Sep 1987Amp IncorporatedSocket for stacking integrated circuit packages
US471212930 Sep 19858 Dic 1987Texas Instruments IncorporatedIntegrated circuit device with textured bar cover
US47226913 Feb 19862 Feb 1988General Motors CorporationHeader assembly for a printed circuit board
US473346124 Dic 198529 Mar 1988Micro Co., Ltd.Method of stacking printed circuit boards
US475887522 May 198119 Jul 1988Hitachi, Ltd.Resin encapsulated semiconductor device
US47631884 Nov 19879 Ago 1988Thomas JohnsonPackaging system for multiple semiconductor devices
US48210076 Feb 198711 Abr 1989Tektronix, Inc.Strip line circuit component and method of manufacture
US48232341 Jul 198618 Abr 1989Dai-Ichi Seiko Co., Ltd.Semiconductor device and its manufacture
US483356829 Ene 198823 May 1989Berhold G MarkThree-dimensional circuit component assembly and method corresponding thereto
US48397177 Jun 198813 Jun 1989Fairchild Semiconductor CorporationCeramic package for high frequency semiconductor devices
US486224917 Abr 198729 Ago 1989Xoc Devices, Inc.Packaging system for stacking integrated circuits
US488423717 Mar 198928 Nov 1989International Business Machines CorporationStacked double density memory module using industry standard memory chips
US48917893 Mar 19882 Ene 1990Bull Hn Information Systems, Inc.Surface mounted multilayer memory printed circuit board
US490316919 Sep 198820 Feb 1990Matsushita Electric Industrial Co., Ltd.Shielded high frequency apparatus having partitioned shield case, and method of manufacture thereof
US49116433 Ago 198927 Mar 1990Beta Phase, Inc.High density and high signal integrity connector
US49530605 May 198928 Ago 1990Ncr CorporationStackable integrated circuit chip package with improved heat removal
US49566944 Nov 198811 Sep 1990Dense-Pac Microsystems, Inc.Integrated circuit chip stacking
US498353328 Oct 19878 Ene 1991Irvine Sensors CorporationHigh-density electronic modules - process and product
US49857032 Feb 198915 Ene 1991Nec CorporationAnalog multiplexer
US501232320 Nov 198930 Abr 1991Micron Technology, Inc.Double-die semiconductor package having a back-bonded die and a face-bonded die interconnected on a single leadframe
US501613818 Sep 198914 May 1991Woodman John KThree dimensional integrated circuit package
US503435014 Mar 199023 Jul 1991Sgs Thomson Microelectronics S.R.L.Semiconductor device package with dies mounted on both sides of the central pad of a metal frame
US504101530 Mar 199020 Ago 1991Cal Flex, Inc.Electrical jumper assembly
US504190214 Dic 198920 Ago 1991Motorola, Inc.Molded electronic package with compression structures
US505003926 Jun 199017 Sep 1991Digital Equipment CorporationMultiple circuit chip mounting and cooling arrangement
US50579038 Nov 199015 Oct 1991Microelectronics And Computer Technology CorporationThermal heat sink encapsulated integrated circuit
US50647826 Abr 199012 Nov 1991Sumitomo Electric Industries, Ltd.Method of adhesively and hermetically sealing a semiconductor package lid by scrubbing
US50687082 Oct 198926 Nov 1991Advanced Micro Devices, Inc.Ground plane for plastic encapsulated integrated circuit die packages
US508106710 May 199114 Ene 1992Fujitsu LimitedHermetic sealing ceramic packages on a support, wires, solders and caps
US509939325 Mar 199124 Mar 1992International Business Machines CorporationElectronic package for high density applications
US510482024 Jun 199114 Abr 1992Irvine Sensors CorporationMethod of fabricating electronic circuitry unit containing stacked IC layers having lead rerouting
US511728229 Oct 199026 May 1992Harris CorporationStacked configuration for integrated circuit devices
US512286214 Mar 199016 Jun 1992Ngk Insulators, Ltd.Ceramic lid for sealing semiconductor element and method of manufacturing the same
US51384306 Jun 199111 Ago 1992International Business Machines CorporationHigh performance versatile thermally enhanced IC chip mounting
US513843422 Ene 199111 Ago 1992Micron Technology, Inc.Packaging for semiconductor logic devices
US51589129 Abr 199127 Oct 1992Digital Equipment CorporationIntegral heatsink semiconductor package
US51594341 Feb 199127 Oct 1992Hitachi, Ltd.Semiconductor device having a particular chip pad structure
US515953513 Jun 198927 Oct 1992International Business Machines CorporationMethod and apparatus for mounting a flexible film semiconductor chip carrier on a circuitized substrate
US516892625 Sep 19918 Dic 1992Intel CorporationHeat sink design integrating interface material
US519888820 Dic 199030 Mar 1993Hitachi, Ltd.Semiconductor stacked device
US519896518 Dic 199130 Mar 1993International Business Machines CorporationFree form packaging of specific functions within a computer system
US52143078 Jul 199125 May 1993Micron Technology, Inc.Lead frame for semiconductor devices having improved adhesive bond line control
US521979413 Mar 199215 Jun 1993Hitachi, Ltd.Semiconductor integrated circuit device and method of fabricating same
US52220142 Mar 199222 Jun 1993Motorola, Inc.Three-dimensional multi-chip pad array carrier
US522402310 Feb 199229 Jun 1993Smith Gary WFoldable electronic assembly module
US522964126 Ago 199220 Jul 1993Hitachi Maxell, Ltd.Semiconductor card and manufacturing method therefor
US52299164 Mar 199220 Jul 1993International Business Machines CorporationChip edge interconnect overlay element
US52391982 Jul 199224 Ago 1993Motorola, Inc.Overmolded semiconductor device having solder ball and edge lead connective structure
US524058827 Ago 199231 Ago 1993Nec CorporationMethod for electroplating the lead pins of a semiconductor device pin grid array package
US524145422 Ene 199231 Ago 1993International Business Machines CorporationMutlilayered flexible circuit package
US524313318 Feb 19927 Sep 1993International Business Machines, Inc.Ceramic chip carrier with lead frame or edge clip
US524742326 May 199221 Sep 1993Motorola, Inc.Stacking three dimensional leadless multi-chip module and method for making the same
US525285515 Oct 199112 Oct 1993Mitsubishi Denki Kabushiki KaishaLead frame having an anodic oxide film coating
US52528575 Ago 199112 Oct 1993International Business Machines CorporationStacked DCA memory chips
US525977019 Mar 19929 Nov 1993Amp IncorporatedImpedance controlled elastomeric connector
US526106825 May 19909 Nov 1993Dell Usa L.P.Dual path memory retrieval system for an interleaved dynamic RAM memory unit
US52629277 Feb 199216 Nov 1993Lsi Logic CorporationPartially-molded, PCB chip carrier package
US527641825 Mar 19914 Ene 1994Motorola, Inc.Flexible substrate electronic assembly
US528185210 Dic 199125 Ene 1994Normington Peter J CSemiconductor device including stacked die
US528906223 Mar 199322 Feb 1994Quality Semiconductor, Inc.Fast transmission gate switch
US528934616 Feb 199322 Feb 1994Microelectronics And Computer Technology CorporationPeripheral to area adapter with protective bumper for an integrated circuit chip
US531309716 Nov 199217 May 1994International Business Machines, Corp.High density memory module
US53373883 Ago 19939 Ago 1994International Business Machines CorporationMatrix of pluggable connectors for connecting large numbers of clustered electrical and/or opticcal cables to a module
US534336624 Jun 199230 Ago 1994International Business Machines CorporationPackages for stacked integrated circuit chip cubes
US53452055 Abr 19906 Sep 1994General Electric CompanyCompact high density interconnected microwave system
US534715924 Sep 199113 Sep 1994Tessera, Inc.Semiconductor chip assemblies with face-up mounting and rear-surface connection to substrate
US53474283 Dic 199213 Sep 1994Irvine Sensors CorporationModule comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip
US535747830 Sep 199118 Oct 1994Mitsubishi Denki Kabushiki KaishaSemiconductor integrated circuit device including a plurality of cell array blocks
US536122830 Abr 19931 Nov 1994Fuji Photo Film Co., Ltd.IC memory card system having a common data and address bus
US536265615 Abr 19948 Nov 1994Intel CorporationMethod of making an electronic assembly having a flexible circuit wrapped around a substrate
US53750412 Dic 199220 Dic 1994Intel CorporationElectronic assembly
US538469027 Jul 199324 Ene 1995International Business Machines CorporationFlex laminate package for a parallel processor
US53863411 Nov 199331 Ene 1995Motorola, Inc.Flexible substrate folded in a U-shape with a rigidizer plate located in the notch of the U-shape
US53943039 Sep 199328 Feb 1995Kabushiki Kaisha ToshibaSemiconductor device
US53965733 Ago 19937 Mar 1995International Business Machines CorporationPluggable connectors for connecting large numbers of electrical and/or optical cables to a module through a seal
US539791626 Jul 199314 Mar 1995Normington; Peter J. C.Semiconductor device including stacked die
US54281902 Jul 199327 Jun 1995Sheldahl, Inc.Rigid-flex board with anisotropic interconnect and method of manufacture
US543263011 Sep 199211 Jul 1995Motorola, Inc.Optical bus with optical transceiver modules and method of manufacture
US54382241 Dic 19931 Ago 1995Motorola, Inc.Integrated circuit package having a face-to-face IC chip arrangement
US54485111 Jun 19945 Sep 1995Storage Technology CorporationMemory stack with an integrated interconnect and mounting structure
US547708211 Ene 199419 Dic 1995Exponential Technology, Inc.Bi-planar multi-chip module
US548495911 Dic 199216 Ene 1996Staktek CorporationHigh density lead-on-package fabrication method and apparatus
US6323060 *5 May 199927 Nov 2001Dense-Pac Microsystems, Inc.Stackable flex circuit IC package and method of making same
US6444490 *28 Jun 20013 Sep 2002International Business Machines CorporationThin film semiconductors formed with stamping and metals
US6576992 *26 Oct 200110 Jun 2003Staktek Group L.P.Stacks chip scale-packaged integrated circuits into modules that conserve board surface area
Otras citas
Referencia
11992 Proceedings, 42nd Electronic Components & Technology Conference. May 18-20, 1992.
23D Interconnection for Ultra-Dense Multichip Modules; Christian Vai. Thomson-CSF DCS Computer Division, Thierry Lemoine, Thomson-CSF RCM Radar Countermeasures Division.
3Chip Scale Packaging and Redistribution, Paul A. Magill, Glenn A. Rinne, J. Daniel Mis, Wayne C. Machon, Joseph W Baggs. Unitive Electronics Inc.
4Chip Scale Review Online-An Independent Journal Dedicated to the Advancement of Chip-Scale Electronics. (Website 9 pages) Fjelstad, Joseph. Pacific Consultants L.L.C., Published Jan. 2001 on Internet.
5Dense-Pac Microsystems. 16 Megabit High Speed CMOS SRAM DPS1MX16MKn3.
6Dense-Pac Microsystems. 256 Megabyte CMOS DRAM DP3ED32MS72RW5.
7Dense-Pac Microsystems. Breaking Space Barriers. 3-D Technology 1993.
8Dense-Pac Microsystems. DPS512X16A3. Ceramic 512Kx16 CMOS SRAM Module.
9Design Requirements for Outlines of Solid State and Related Products, Ball Grid Array Package (BGA), Sep. 2005, Jedec Publication 95.
10Die Products: Ideal IC Packaging for Demanding Applications-Advanced packaging that's no bigger than the die itself brings together high performance and high reliability with small size and low cost. (Website 3 pages with 2 figures) Larry Gilg and Chris Windsor. Dec. 23, 2002. Published on Internet.
11Flexible Printed Circuit Technology-A Versatile Interconnection Option. (Website 2 pages) Fjelstad, Joseph. Dec. 3, 2002.
12Flexible Thinking: Examining the Flexible Circuit Tapes. (Website 2 pages) Fjelstad, Joseph., Published Apr. 20, 2000 on Internet.
13High Density Memory Packaging Technology High Speed Imaging Applications, Dean Frew. Texas Instruments Incorporated.
14Howard W. Markstein, Western Editor, Rigid-Flex: A Maturing Technology dated Feb. 1996, Electronic Packaging & Production.
15IBM Preliminary 168 Pin SDRAM Registered DIMM Functional Description & Timing Diagrams.
16IBM Technical Disclosure Bulletin, vol. 20, No. 11A, Apr. 1976.
17IBM Technical Disclosure Bulletin, vol. 23, No. 12, May 1981.
18IBM Technical Disclosure Bulletin, vol. 32, NO. 3B, Aug. 1989.
19Orthogonal Chip Mount - A 3D Hybrid Wafer Scale Integration Technology, International Electron Device Meeting, IEDM Technical Digest, Washington, D.C., Dec. 6-9, 1987.
20PCT/US2005/010756, International Preliminary Report on Patentability dated Apr. 12, 2007.
21PCT/US2005/010756, International Search Report and Written Opinion dated Oct. 12, 2006.
22PCT/US2005/013336, International Preliminary Report on Patentability dated Nov. 9, 2006.
23PCT/US2005/013345, International Preliminary Report on Patentability dated Nov. 2, 2006.
24PCT/US2005/016764; International Preliminary Report on Patentability dated Nov. 23, 2006.
25PCT/US2005/039307, International Search Report and Written Opinion dated Sep. 26, 2006.
26PCT/US2006/017015, International Search Report and Written Opinion dated Oct. 17, 2006.
27Research Disclosure. Organic Card Device Carrier, 31318. May 1990, No. 313.
28Ron Bauer, Intel, "Stacked-CSP Delivers Flexiblity, Reliability, and Space-Saving Capabilities". vol. 3, Spring 2002. Published on Internet.
29Tessera Introduces uZ a -Ball Stacked Memory Package for Computing and Portable Electronic Products Joyce Smeragdis. Tessera Public Relations. Sandy Skees, MCA PR (www.tessera.com/news<SUB>-</SUB>events/press<SUB>-</SUB>coverage.cfm): 2 figures that purport to be directed to the uZ #-Ball Stacked Memory Package. Published Jul. 17, 2002 in San Jose, CA.
30Tessera Technologies, Inc.-Semiconductor Intellectual Property. Chip Scale Packaging-Website pages (3). Internet.
31Tessera uZ Ball Stack Package. 4 figures that purport to be directed to the uZ-Ball Stacked Memory, Published on the internet.
32Verticany-Intergrated Package. Alvin Weinberg. Pacesetter, Inc. and W. Kinzy Jones. Florida International University.
33William R. Newberry, Design Techniques for Ball Grid Arrays, Xynelix Design Systems, Inc., Portland, Maine, Published on the Internet.
34William R. Newberry, Xynetic Design Systems, Inc., Design Techniques for Ball Grid Arrays, 1997 published on the Internet.
Clasificaciones
Clasificación de EE.UU.438/109, 257/E23.069, 257/E21.705, 257/E23.101, 257/E25.023, 257/E23.065, 257/E23.034
Clasificación internacionalH01L21/44
Clasificación cooperativaH01L2225/1041, H01L2225/1058, H01L2225/107, H01L23/4985, H01L25/105, H01L23/36, H05K3/3436, H05K3/305, H05K2203/0278, H05K1/189, H01L25/50, H01L23/49816, H01L2224/16, H01L2224/16225, H01L2224/73253, H01L2224/32225
Clasificación europeaH01L25/50, H01L25/10J, H05K3/34C4B
Eventos legales
FechaCódigoEventoDescripción
2 Dic 2012ASAssignment
Owner name: OVID DATA CO. LLC, DELAWARE
Effective date: 20121031
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ENTORIAN TECHNOLOGIES INC.;REEL/FRAME:029389/0672
25 Oct 2012ASAssignment
Effective date: 20100714
Free format text: MERGER;ASSIGNOR:ENTORIAN GP LLC;REEL/FRAME:029195/0114
Owner name: ENTORIAN TECHNOLOGIES INC., TEXAS
Free format text: MERGER;ASSIGNOR:ENTORIAN TECHNOLOGIES L.P.;REEL/FRAME:029195/0048
Owner name: ENTORIAN GP LLC, TEXAS
29 Jul 2011FPAYFee payment
Year of fee payment: 4
26 Ene 2010ASAssignment
Owner name: ENTORIAN TECHNOLOGIES L.P., TEXAS
Free format text: CHANGE OF NAME;ASSIGNOR:STAKTEK GROUP, L.P.;REEL/FRAME:023848/0062
Effective date: 20080229
15 Ene 2008ASAssignment
Owner name: STAKTEK GROUP L.P., TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:PARTRIDGE, JULIAN;WEHRLY, JAMES DOUGLAS;ROPER, DAVID L.;REEL/FRAME:020368/0028;SIGNING DATES FROM 20050329 TO 20050407