US7335531B2 - Semiconductor device package and method of production and semiconductor device of same - Google Patents
Semiconductor device package and method of production and semiconductor device of same Download PDFInfo
- Publication number
- US7335531B2 US7335531B2 US11/130,845 US13084505A US7335531B2 US 7335531 B2 US7335531 B2 US 7335531B2 US 13084505 A US13084505 A US 13084505A US 7335531 B2 US7335531 B2 US 7335531B2
- Authority
- US
- United States
- Prior art keywords
- capacitor
- circuit board
- semiconductor chip
- external connection
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related, expires
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 169
- 238000000034 method Methods 0.000 title claims description 27
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 239000003990 capacitor Substances 0.000 claims abstract description 124
- 239000004020 conductor Substances 0.000 claims abstract description 77
- 239000002184 metal Substances 0.000 claims description 83
- 229910052751 metal Inorganic materials 0.000 claims description 83
- 238000005530 etching Methods 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 14
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 230000003014 reinforcing effect Effects 0.000 claims description 2
- 238000003475 lamination Methods 0.000 claims 20
- 238000009413 insulation Methods 0.000 claims 3
- 239000010410 layer Substances 0.000 description 69
- 229920005989 resin Polymers 0.000 description 34
- 239000011347 resin Substances 0.000 description 34
- 229910000679 solder Inorganic materials 0.000 description 24
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 12
- 229910052802 copper Inorganic materials 0.000 description 12
- 239000010949 copper Substances 0.000 description 12
- 239000010409 thin film Substances 0.000 description 10
- 238000009713 electroplating Methods 0.000 description 9
- 239000010408 film Substances 0.000 description 9
- 238000000206 photolithography Methods 0.000 description 7
- 239000004642 Polyimide Substances 0.000 description 4
- 239000011162 core material Substances 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 238000007772 electroless plating Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910004353 Ti-Cu Inorganic materials 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229910002370 SrTiO3 Inorganic materials 0.000 description 1
- 229910003086 Ti–Pt Inorganic materials 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010329 laser etching Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920001955 polyphenylene ether Polymers 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/33—Thin- or thick-film capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
- H05K1/187—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding the patterned circuits being prefabricated circuits, which are not yet attached to a permanent insulating substrate, e.g. on a temporary carrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05005—Structure
- H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05024—Disposition the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
- H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Definitions
- the present invention relates to a semiconductor device package and a method of production and semiconductor device of the same, more particularly relates to a semiconductor device package providing a capacitor in a circuit board on which a semiconductor chip is mounted and a method of production and semiconductor device of the same.
- the semiconductor device 100 shown in FIG. 10 is comprised of a multilayer circuit board, that is, a semiconductor device package 104 (hereinafter referred to simply as “the package 104 ”) and a semiconductor chip 102 mounted on the same.
- the semiconductor device package 104 is formed with multiple layers of conductor patterns 108 , 108 . . . on the two surfaces of a plate-shaped core material 106 comprised of a glass epoxy board etc.
- the conductor patterns 108 , 108 . . . are formed in multiple layers.
- the conductor patterns 108 , 108 . . . formed in the multiple layers are electrically connected by through holes 110 , 110 passing through the core material 106 and vias 112 , 112 , etc. passing through insulating layers 114 , 114 . . . .
- the package 104 has a capacitor 118 inserted into a recess 116 formed by a router etc. in the core material 106 .
- the capacitor 118 is comprised of a silicon substrate 118 a , a film 118 b comprised of a dielectric material formed on one surface of the same, and a conductive film 118 c formed on the surface of that film.
- the capacitor 118 is bonded by a conductor binder 122 on to a metal plating film 120 formed along the inside wall of the recess 116 .
- the capacitor 118 is inserted into the recess 116 formed in the core 106 formed at the substantial center of the package 104 .
- the conductor circuit extending from the electrode terminals of the mounted semiconductor chip 102 to the capacitor 118 is formed bent.
- the conductor circuit extending from the electrode terminals of the semiconductor chip 102 to the capacitor 118 is long and has many connection locations, and the inductance of the conductor circuit extending from the external connection terminals of the semiconductor device 100 to the semiconductor chip 102 becomes large. Due to this, it was learned that the power supplied to the semiconductor chip 102 easily became unstable.
- An object of the present invention is to provide a semiconductor device package able to shorten as much as possible the conductor circuit extending from the electrode terminals of the mounted semiconductor chip to the capacitor and a method of production and semiconductor device for the same.
- the inventors engaged in studies to achieve this object believing it effective to provide a capacitor 118 in a package 104 so as to directly connect external connection terminals of the capacitor 118 to connection pads to be connected with electrode terminals of the semiconductor chip 102 formed on the surface of the package 104 for mounting the semiconductor chip 102 and as a result perfected the present invention.
- a semiconductor device package providing a capacitor in a circuit board for mounting a semiconductor chip, wherein the capacitor is provided directly beneath a semiconductor chip mounting surface of the circuit board to which the semiconductor chip is to be mounted, the semiconductor chip mounting surface of the circuit board is formed with connection pads exposed at one surface so that electrode terminals of the semiconductor chip may be directly connected, and the other surface of the connection pads to which the electrode terminals of the semiconductor chip are to be connected corresponding to the external connection terminals of the capacitor among the connection pads have the external connection terminals of the capacitor directly connected to them.
- a method of production of a semiconductor device package for producing a semiconductor device package providing a capacitor in a circuit board comprising directly connecting external connection terminals of the capacitor to one surface of capacitor connection terminals to which the capacitor is to be connected among the connection pads formed in a state with the other surface to which electrode terminals of the semiconductor chip to be mounted are to be directly connected in close contact with one surface of a metal plate, forming a circuit board provided with a conductor circuit electrically connecting the connection pads and external connection terminals of the capacitor at one surface of the metal plate, or mounting the capacitor so as to make one surface of the connection surfaces of the external connection terminals to which the electrode terminals of the semiconductor chip to be mounted are to be directly connected closely contact one surface of the metal plate, then forming a circuit board provided with a conductor circuit electrically connected with other external connection terminals of the capacitor at that surface of the metal plate, and etching the other surface of the metal plate to expose the semiconductor mounting surface of the circuit board including at least the connection pads or the
- a semiconductor device comprised of such a semiconductor device package and a semiconductor chip mounted on a semiconductor chip mounting surface of that package, wherein electrode terminals of the semiconductor chip are directly connected to one surface of connection pads to the other surface of which the external connection terminals of the capacitor provided at the semiconductor device package are directly connected or the connection surfaces of the external connection terminals of the capacitor provided in the semiconductor device package.
- the capacitor a two-sided wiring type capacitor comprised of a silicon substrate and external connection terminals formed at the two surfaces and thereby further shorten the length of the conductor circuit electrically connecting the electrode terminals of the semiconductor chip and external connection terminals of the package through the capacitor.
- the conductor circuit electrically connecting the capacitor connection pads formed on the semiconductor chip mounting surface on one surface of the circuit board and directly connected to the external connection terminals of the capacitor and the board external connection terminals formed at the other surface of the circuit board through the capacitor the shortest distance
- the circuit board As a multilayer circuit board, by forming a conductor circuit electrically connecting the capacitor connection pads formed on the semiconductor chip mounting surface on one surface of the multilayer circuit board and the board external connection terminals formed at the other surface of the multilayer circuit board through the capacitor by stacking in straight lines the vias formed by filling metal into through holes passing through the layers, it is possible to make the conductor circuit electrically connecting with the board external connection terminals formed at the other surface of the circuit board through the capacitor the shortest distance possible.
- the electrode terminals of the semiconductor chip corresponding to the external connection terminals of the capacitor are directly connected to one surface of connection pads to the other surface of which the external connection terminals of the capacitor are directly connected among the connection pads formed exposed at one surface at the semiconductor chip mounting circuit.
- the electrode terminals of the semiconductor chip corresponding to the external connection terminals of the capacitor are directly connected to the connection surfaces of the external connection terminals of the capacitor exposed at the semiconductor chip mounting surface.
- the electrode terminals of the semiconductor chip and the electrode terminals of the capacitor are connected through the connection pads or directly, it is possible to shorten the distance of the conductor circuit between terminals as much as possible and reduce the connection locations and possible to reduce the inductance of the conductor circuit electrically connecting the electrode terminals of the semiconductor chip and electrode terminals of the capacitor.
- FIG. 1 is a sectional view for explaining an example of a semiconductor device according to the present invention
- FIG. 2 is a sectional view for explaining an example of a capacitor provided at a semiconductor device package forming the semiconductor device shown in FIG. 1 ;
- FIG. 3 is a partially enlarged sectional view of the semiconductor device shown in FIG. 1 ;
- FIGS. 4A to 4K are sectional views for explaining steps of production of a semiconductor device package forming the semiconductor device shown in FIG. 1 ;
- FIGS. 5A to 5G are sectional views for explaining steps of production of the capacitor shown in FIG. 2 ;
- FIG. 6 is a sectional view for explaining another example of a semiconductor device according to the present invention.
- FIG. 7 is a sectional view for explaining another example of a capacitor provided at a semiconductor device package forming the semiconductor device shown in FIG. 6 ;
- FIG. 8 is a partially enlarged sectional view of the semiconductor device shown in FIG. 6 ;
- FIGS. 9A to 9C are sectional views for explaining steps of production of a semiconductor device package forming the semiconductor device shown in FIG. 8 ;
- FIG. 10 is a sectional view for explaining a semiconductor device of the related art.
- FIG. 1 A semiconductor device according to the present invention is shown in FIG. 1 .
- the semiconductor device 10 shown in FIG. 1 is comprised of a semiconductor device package 14 (hereinafter sometimes simply referred to as a “package”) provided inside it with a capacitor 18 , a frame-shaped metal plate 11 serving as a reinforcing member bonded to one surface of the same by a thin resin layer 13 , and a semiconductor chip 12 mounted by flip-chip bonding to a semiconductor chip mounting surface formed in a frame-shaped opening of the metal plate 11 .
- a semiconductor device package 14 hereinafter sometimes simply referred to as a “package”
- a capacitor 18 a capacitor 18
- a frame-shaped metal plate 11 serving as a reinforcing member bonded to one surface of the same by a thin resin layer 13
- a semiconductor chip 12 mounted by flip-chip bonding to a semiconductor chip mounting surface formed in a frame-shaped opening of the metal plate 11 .
- the package 14 is a multilayer circuit board comprised of a stack of resin layers 14 a , 14 b , and 14 c serving as insulating layers formed with conductor patterns 16 , 16 . . . .
- the conductor patterns 16 , 16 . . . formed on the layers are electrically connected by vias 20 , 20 . . . formed through the layers.
- the other surface of the package 14 has solder balls attached to it serving as board external connector terminals.
- the solder balls 24 , 24 . . . are electrically connected to electrode terminals of the semiconductor chip 12 by a conductor circuit comprised of the conductor patterns 16 , vias 20 , etc.
- the other surface of the package 14 is covered by a solder resist 23 other than at the portions of the solder balls 24 , 24 . . . .
- the capacitor 18 provided in the package 14 is a two-sided wiring-type capacitor comprised of a silicon substrate 22 formed with external connection terminals 18 a , 18 a , 18 b , 18 b at the two surfaces.
- the silicon substrate 22 is formed with through holes 42 .
- One surface of the silicon substrate 22 and the inside walls of the through holes 42 are formed with an oxide film layer 26 .
- the oxide film layer 26 has formed on it a conductor pattern 46 a and conductor pattern 52 a adjoining each other via a dielectric layer 48 in a conductor circuit comprised of the conductor patterns 46 a and 52 b and a conductor circuit comprised of the conductor pattern 52 a .
- a conductor circuit comprised of the conductor patterns 46 a and 52 b and the conductor circuit comprised of the conductor pattern 52 a are formed bump-shaped external connection terminals 18 a , 18 a.
- connection terminals 18 b , 18 b extending to the other surface of the silicon substrate 22 through vias formed by filling the through holes 42 , 42 passing through the silicon substrate 22 with metal by plating etc. and formed with flat connection surfaces.
- the bump-shaped external connection terminals 18 a , 18 a formed on one surface of the capacitor 18 are directly connected to one surface of the capacitor connection pads 32 c , 32 c among the connection pads 32 , 32 . . . formed on the semiconductor chip mounting surface of the package 14 and directly connected at the other surface to the electrode terminals of the semiconductor chip 12 .
- the electrode terminals (solder bumps) 12 a , 12 a of the semiconductor chip 12 and the external connection terminals 18 a , 18 a formed on one surface of the capacitor 18 are connected through the connection pads 32 c , 32 c .
- the distance is shortened and the number of connection locations is smaller.
- the external connection terminals 18 b , 18 b formed on the other surface of the capacitor 18 are electrically connected with the solder balls 24 , 24 serving as the board external connection terminals attached to the other surface of the package 14 by the conductor circuit formed by the stack of vias 20 , 20 . . . formed in the layers.
- the inductance of the conductor circuit can be further reduced by forming to the shortest distance the conductor circuit, formed by stacking of the vias 20 , 20 . . . , electrically connecting the capacitor connection pads 32 c , 32 c and the solder balls 24 , 24 through the capacitor 18 .
- the “shortest distance” means the solder balls 24 , 24 are formed in the direction of the verticals descending from the capacitor connection pads 32 c , 32 c to the other surface of the package 14 and the conductor circuit connecting the capacitor connector pads 32 c , 32 c and solder balls 24 , 24 is formed substantially straight.
- the conductor circuit connecting the connection pads 32 , 32 . . . and solder balls 24 , 24 . . . is formed by stacking the vias 20 , 20 . . . formed in the layers, making the vias 20 , 20 . . . filled vias formed by filling through holes with copper or another metal makes it easier to flatten the end face of the formed vias 20 and makes it easier to stack the vias 20 , 20 . . . straight.
- the package 14 forming the semiconductor device 10 shown in FIG. 1 to FIG. 3 can be produced by the method shown in FIGS. 4A to 4K .
- one surface of the metal plate 11 a comprised of copper or another metal is coated with a polyimide or other resin to form a thin resin layer 13 ( FIG. 4A ).
- the surface of the thin resin layer 13 is formed with a thin film metal layer of copper etc. by electroless plating etc.
- This thin film metal layer is used as a power feed layer to form a metal layer by electroplating.
- This metal layer is patterned by photolithography or another known method to form connection pads 32 , 32 . . . ( FIG. 4B ).
- the connection pads 32 , 32 . . . are formed in a state with one surface to which the electrode terminals of the semiconductor chip 12 are to be directly connected in close contact with the thin resin layer 13 formed on the metal plate 11 a.
- the other surfaces of the capacitor connection pads 32 c , 32 c among the connection pads 32 , 32 . . . are joined with the external connection terminals 18 a , 18 a formed on one surface of the capacitor 18 using solder or another brazing material so as to mount the capacitor 18 ( FIG. 4C ).
- This resin layer 14 a can be formed by coating a resin such as an epoxy, polyimide, or polyphenylene ether or stacking resin sheets comprised of these resins.
- the resin layer 14 a is formed with recesses 34 , 34 . . . for forming vias by etching or a laser ( FIG. 4E ). At the bottoms of these recesses 34 , 34 . . . , the connection pads 32 or external connection terminals 18 b of the capacitor 18 are exposed.
- the entire surface of the resin layer 14 a including the bottoms and inside walls of the recesses 34 , 34 . . . is formed with a copper or other metal thin film formed by electroless plating etc. This is used as a power feed layer for electroplating to fill the recesses 34 , 34 . . . by copper or another metal and form the metal layer 36 ( FIG. 4F ).
- this electroplating use of PR electroplating where the anode and cathode are reversed at a predetermined period is preferred.
- the anode and cathode carrying the forward current for filling copper or another metal in the recesses 34 , 34 . . . at a predetermined period to apply PR electroplating carrying reverse current in the opposite direction to the direction of flow of the forward current so as to form a metal film on the metal thin films in the recesses 34 , 34 . . . , then electroplate the remaining portions of the recesses 34 , 34 . . . by direct current to fill them with copper or another metal and form the vias 20 , 20 . . . in that it is possible to sufficiently fill even small diameter recesses with a metal in a predetermined time to form vias.
- the surface of the metal layer 36 may be polished to make the surface of the metal layer 36 flat.
- the metal layer 36 is patterned by photolithography or another known method to form conductor patterns 16 , 16 . . . ( FIG. 4G ).
- the formed conductor patterns 16 , 16 . . . are laminated with a resin layer 14 b to cover them by a resin.
- the resin layer 14 b formed is then formed with recesses 34 , 34 . . . for forming vias by etching or laser. At the bottoms of the recesses 34 , 34 . . . are exposed the conductor pattern 16 and vias 20 ( FIG. 4H ).
- the recesses 34 , 34 . . . formed in the resin layer 14 b are formed with vias 20 and the conductor pattern 16 in the same way as with the step of FIG. 4F .
- the resin layer 14 c formed so as to cover the conductor pattern 16 etc. formed at the resin layer 14 b is also formed with vias 20 etc. ( FIG. 4I ), then the surface of the resin layer 14 c is coated with a solder resist 23 other than at the pad portions where the solder balls 24 serving as the board external connection terminals are to be attached ( FIG. 4J ).
- the metal plate 11 a is etched so as to expose the semiconductor chip mounting surface including the surfaces of the connection pads 32 , 32 . . . to be connected to the electrode terminals 12 a , 12 a . . . of the semiconductor chip 12 .
- the metal plate 11 a may be etched to remove all of the metal plate 11 a , but it is preferable to expose only the semiconductor chip mounting surface where the semiconductor chip 12 is to be mounted by etching away only the part covering the semiconductor chip mounting surface of the metal plate 11 a and forming a package 14 reinforced by a frame-shaped metal plate 11 shown in FIG. 4K .
- the thin resin layer 13 between the metal plate 11 a and the resin layer 14 a is normally not etched by the etching solution etching the metal plate 11 a.
- the etching solution etching the metal plate 11 a.
- a thin resin layer 13 comprised of a resin of a different color from the metal plate 11 a
- the color of that portion will change and therefore it will be possible to directly judge that the etching had finished.
- the exposed portion of the thin resin layer 13 is etched by an etching solution for etching the thin resin layer 13 without etching the metal plate 11 a and the surfaces of the connection pads 32 , 32 . . . are exposed.
- the semiconductor chip 12 is mounted on the semiconductor chip mounting surface of the resin layer 14 a exposed at the opening of the metal plate 11 formed into the frame shape.
- the electrode terminals (solder bumps) 12 a , 12 a . . . of the semiconductor chip 12 are brought into contact with surfaces of the corresponding connection pads 32 and joined with them by reflowing so as to form the semiconductor device 10 shown in FIG. 1 .
- the semiconductor device 10 shown in FIG. 1 by using one of the electrode terminals for power and the other of the electrode terminals for grounding among the electrode terminals 12 a , 12 a of the semiconductor chip 12 connected with the external connection terminals 18 a , 18 b of the capacitor 18 through the capacitor connection pads 32 c , 32 c , it is possible to stabilize the power supplied to the semiconductor chip 12 etc. Therefore, even if mounting a semiconductor chip 12 increased in operating frequency, erroneous operation due to instability of the power etc. can be prevented.
- recesses 42 a , 42 a for forming vias opening at one surface of the silicon substrate 40 are formed, then the entire area of that surface of the silicon substrate 40 including the inside walls of the recesses 42 a , 42 a is formed with an oxide film 44 ( FIG. 5A ).
- the recesses 42 a , 42 a can be formed by laser or reactive ion etching (RIE).
- the entire surface of the oxide film 44 is formed with a thin film metal layer comprised of Ti—Cu by sputtering etc., then the thin film metal layer is used as a power feed layer for electroplating to fill the recesses 42 a , 42 a with copper or another metal and form a predetermined thickness of the metal layer on the thin film metal layer.
- the formed metal layer is patterned by photolithography or another known method to form a conductor pattern 46 a etc. ( FIG. 5B ).
- the entire area of one surface of the silicon substrate 40 formed with the conductor pattern 46 a etc. is formed with a bonding layer comprised of Ti—Pt by sputtering etc., then is formed with a dielectric layer 48 a of SrTiO 3 , BaTiO 3 , Ta 2 O 5 , etc. ( FIG. 5C ).
- This dielectric layer 48 a is patterned by photolithography or another known method to leave only the dielectric layer 48 covering the conductor pattern 46 a and form a via hole 50 a in the dielectric layer 48 ( FIG. 5D ).
- the entire area of one surface of the silicon substrate 40 formed with the dielectric layer 48 etc. is formed with a thin film metal layer comprised of Ti—Cu by sputtering etc., then the thin film metal layer is used as a power feed layer for electroplating to fill the via hole 50 a with copper or another metal to form the via 50 and form a metal layer 52 comprised of copper etc. to a predetermined thickness ( FIG. 5E ).
- the metal layer 52 formed is patterned by photolithography or another known method to form a conductor pattern 52 a and a conductor pattern 52 b electrically connected to the conductor pattern 46 a by the via 50 ( FIG. 5F ).
- the conductor patterns 52 a , 52 b are formed with solder bumps serving as external connection terminals 18 a , 18 a.
- the other surface of the silicon substrate 40 is polished to remove the bottoms of the recesses 42 a , 42 a and form the through holes 42 .
- the end faces of the metal filled in the through holes 42 are exposed to form the vias 52 , 52 ( FIG. 5G ).
- the conductor circuit comprised of the conductor patterns 46 a and 52 b and the conductor circuit comprised of the conductor pattern 52 a are formed with the conductor pattern 46 a and the conductor pattern 52 a adjoining each other via the dielectric layer 48 to exhibit the capacitor function.
- the external connection terminals 18 a , 18 a of the capacitor 18 and the electrode terminals 12 a , 12 a of the semiconductor chip 12 are electrically connected through capacitor connection pads 32 c.
- the electrode terminals 12 a , 12 a of the semiconductor chip 12 are directly connected to the flat connection surfaces of the external connection terminals 18 c , 18 c formed on one surface of the capacitor 18 . It is therefore possible to shorten the distance of the conductor circuit between the capacitor 18 and semiconductor chip 12 from the semiconductor device 10 shown in FIG. 1 .
- the capacitor 18 using the semiconductor device 10 shown in FIG. 6 has the connection surfaces of the external connection terminals 18 b , 18 c to be connected to the terminals of other electronic components formed flat. Therefore, in the package 14 with the capacitor 18 , as shown in FIG. 8 , the flat surfaces of the external connection terminals 18 c , 18 c are exposed at the semiconductor chip mounting surface and are directly connected to the corresponding electrode terminals 12 a , 12 a of the semiconductor chip 12 .
- the external connection terminals 18 b , 18 b formed on the other surface of the capacitor 18 shown in FIG. 7 , as shown in FIG. 6 and FIG. 8 , are electrically connected with the solder balls 24 , 24 serving as the board external connection terminals attached to the other surface of the package 14 by the conductor circuit formed by the stack of vias 20 , 20 . . . formed in the layers.
- the inductance of the conductor circuit can be further reduced by forming to the shortest distance the conductor circuit, formed by stacking of the vias 20 , 20 . . . , electrically connecting the external connection terminals 18 c , 18 c of the capacitor to which the electrode terminals 12 a , 12 a of the semiconductor chip 12 are to be directly connected and the solder balls 24 , 24 through the body of the capacitor 18 .
- the “shortest distance” means the solder balls 24 , 24 are formed in the direction of the verticals descending from the external connection terminals 18 c , 18 c to which the electrode terminals 12 a , 12 a of the semiconductor chip 12 are to be connected to the other surface of the package 14 and the conductor circuit connecting the external connection terminals 18 c , 18 c of the capacitor 18 and solder balls 24 , 24 is formed substantially straight.
- the capacitor 18 shown in FIG. 7 can be obtained by substantially the same steps as the steps for production of the capacitor 18 shown in FIGS. 5A to 5G except for the step of FIG. 5F .
- one surface of the metal plate 11 a comprised of copper or another metal is formed with a thin resin layer 13 comprised of a polyimide or other resin ( FIG. 9A ), then the surface of the thin resin layer 13 is formed with a thin film of copper or other metal by electroless plating.
- This is used as a power feed layer for electroplating to form a metal layer which is then patterned by photolithography or another known method to form connection pads 32 , 32 . . . ( FIG. 9B ).
- the capacitor connection pads 32 c , 32 c are not formed. Therefore, the connection pads 32 , 32 . . . formed are connected with vias 20 connected to conductor patterns etc. other than of the capacitor 18 forming the package 14 .
- the capacitor 18 shown in FIG. 7 is mounted at the exposed portion of the thin resin layer 13 ( FIG. 9C ). At this time, the capacitor 18 is mounted so that the flat connection surfaces of the external connection terminals 18 c , 18 c of the capacitor 18 contact the exposed surface of the thin resin layer 13 .
- the package 14 forming the semiconductor device 10 explained here was a three-layer circuit board, but it may also be made a more than three layer board or may be a single-layer package.
- the semiconductor device 10 is left with the frame-shaped metal plate 11 on the semiconductor chip mounting surface, but if the package 14 is sufficiently rigid, it is also possible to etch away all of the metal plate 11 a . Further, solder balls 24 are attached as board external connection terminals, but it is also possible to use pins.
Abstract
Description
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/130,845 US7335531B2 (en) | 2001-12-26 | 2005-05-17 | Semiconductor device package and method of production and semiconductor device of same |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001394694A JP3492348B2 (en) | 2001-12-26 | 2001-12-26 | Method of manufacturing package for semiconductor device |
JP2001-394694 | 2001-12-26 | ||
US10/315,468 US6914322B2 (en) | 2001-12-26 | 2002-12-10 | Semiconductor device package and method of production and semiconductor device of same |
US11/130,845 US7335531B2 (en) | 2001-12-26 | 2005-05-17 | Semiconductor device package and method of production and semiconductor device of same |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/315,468 Division US6914322B2 (en) | 2001-12-26 | 2002-12-10 | Semiconductor device package and method of production and semiconductor device of same |
Publications (2)
Publication Number | Publication Date |
---|---|
US20050208705A1 US20050208705A1 (en) | 2005-09-22 |
US7335531B2 true US7335531B2 (en) | 2008-02-26 |
Family
ID=19188896
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/315,468 Expired - Lifetime US6914322B2 (en) | 2001-12-26 | 2002-12-10 | Semiconductor device package and method of production and semiconductor device of same |
US11/130,845 Expired - Fee Related US7335531B2 (en) | 2001-12-26 | 2005-05-17 | Semiconductor device package and method of production and semiconductor device of same |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/315,468 Expired - Lifetime US6914322B2 (en) | 2001-12-26 | 2002-12-10 | Semiconductor device package and method of production and semiconductor device of same |
Country Status (5)
Country | Link |
---|---|
US (2) | US6914322B2 (en) |
JP (1) | JP3492348B2 (en) |
KR (1) | KR100919797B1 (en) |
CN (1) | CN100492637C (en) |
TW (1) | TWI273612B (en) |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060130301A1 (en) * | 2004-02-20 | 2006-06-22 | Nec Tokin Corporation | Solid electrolytic capacitor, transmission-line device, method of producing the same, and composite electronic component using the same |
US20080029297A1 (en) * | 2006-08-01 | 2008-02-07 | Shinko Electric Industries Co., Ltd. | Wiring substrate and manufacturing method thereof, and semiconductor device |
US20080030968A1 (en) * | 2006-08-07 | 2008-02-07 | Shinko Electric Industries Co., Ltd. | Capacitor built-in interposer and method of manufacturing the same and electronic component device |
US20080291649A1 (en) * | 2006-08-10 | 2008-11-27 | Shinko Electric Industries Co., Ltd. | Capacitor built-in substrate and method of manufacturing the same and electronic component device |
US20090290317A1 (en) * | 2008-05-23 | 2009-11-26 | Shinko Electric Industries Co., Ltd. | Printed circuit board, method of fabricating printed circuit board, and semiconductor device |
US20110057273A1 (en) * | 2009-09-04 | 2011-03-10 | Analog Devices, Inc. | System with Recessed Sensing or Processing Elements |
US20110317381A1 (en) * | 2010-06-29 | 2011-12-29 | Samsung Electronics Co., Ltd. | Embedded chip-on-chip package and package-on-package comprising same |
US20120119358A1 (en) * | 2010-11-11 | 2012-05-17 | Samsung Electro-Mechanics Co., Ltd. | Semicondiuctor package substrate and method for manufacturing the same |
US20150245481A1 (en) * | 2012-08-21 | 2015-08-27 | Epcos Ag | Electric Component Assembly |
US9407997B2 (en) | 2010-10-12 | 2016-08-02 | Invensense, Inc. | Microphone package with embedded ASIC |
US9666558B2 (en) | 2015-06-29 | 2017-05-30 | Point Engineering Co., Ltd. | Substrate for mounting a chip and chip package using the substrate |
US9847462B2 (en) | 2013-10-29 | 2017-12-19 | Point Engineering Co., Ltd. | Array substrate for mounting chip and method for manufacturing the same |
Families Citing this family (55)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004311768A (en) | 2003-04-08 | 2004-11-04 | Shinko Electric Ind Co Ltd | Manufacturing method of substrate, substrate for semiconductor devices and semiconductor device |
KR100546359B1 (en) * | 2003-07-31 | 2006-01-26 | 삼성전자주식회사 | Semiconductor chip package and stacked module thereof having functional part and packaging part arranged sideways on one plane |
JP4298559B2 (en) * | 2004-03-29 | 2009-07-22 | 新光電気工業株式会社 | Electronic component mounting structure and manufacturing method thereof |
JP4387231B2 (en) * | 2004-03-31 | 2009-12-16 | 新光電気工業株式会社 | Capacitor-mounted wiring board and manufacturing method thereof |
JP4628008B2 (en) * | 2004-03-31 | 2011-02-09 | セイコーインスツル株式会社 | Electronic circuit device having a silicon substrate |
JP4063240B2 (en) * | 2004-04-21 | 2008-03-19 | 日本電気株式会社 | Semiconductor device mounting substrate, manufacturing method thereof, and semiconductor package |
US20050258533A1 (en) * | 2004-05-21 | 2005-11-24 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device mounting structure |
JP2006019441A (en) | 2004-06-30 | 2006-01-19 | Shinko Electric Ind Co Ltd | Method of manufacturing substrate with built-in electronic substrate |
JP4575071B2 (en) * | 2004-08-02 | 2010-11-04 | 新光電気工業株式会社 | Manufacturing method of electronic component built-in substrate |
JP2006059992A (en) * | 2004-08-19 | 2006-03-02 | Shinko Electric Ind Co Ltd | Method for manufacturing electronic component built-in board |
JP4800606B2 (en) * | 2004-11-19 | 2011-10-26 | Okiセミコンダクタ株式会社 | Method for manufacturing element-embedded substrate |
JP2006210852A (en) * | 2005-01-31 | 2006-08-10 | Toshiba Corp | Circuit board with surface-mounting circuit component, and its manufacture |
JP2006310783A (en) * | 2005-03-30 | 2006-11-09 | Sanyo Electric Co Ltd | Circuit device |
JP4016039B2 (en) * | 2005-06-02 | 2007-12-05 | 新光電気工業株式会社 | Wiring board and method for manufacturing wiring board |
JP2006344631A (en) * | 2005-06-07 | 2006-12-21 | Murata Mfg Co Ltd | Component built-in substrate |
KR100914552B1 (en) | 2005-07-25 | 2009-09-02 | 삼성전자주식회사 | semiconductor memory device and memory module including it |
JP2007059821A (en) | 2005-08-26 | 2007-03-08 | Shinko Electric Ind Co Ltd | Method for manufacturing wiring board |
DE112005003671B4 (en) * | 2005-08-31 | 2010-11-25 | Intel Corporation, Santa Clara | A microprocessor with a L4 level cache and method of manufacturing the assembly and system comprising the assembly |
US8101868B2 (en) * | 2005-10-14 | 2012-01-24 | Ibiden Co., Ltd. | Multilayered printed circuit board and method for manufacturing the same |
US7906850B2 (en) * | 2005-12-20 | 2011-03-15 | Unimicron Technology Corp. | Structure of circuit board and method for fabricating same |
JP4714049B2 (en) * | 2006-03-15 | 2011-06-29 | Okiセミコンダクタ株式会社 | Semiconductor device and manufacturing method of semiconductor device |
US8064211B2 (en) * | 2006-08-31 | 2011-11-22 | Tdk Corporation | Passive component and electronic component module |
JP4965989B2 (en) * | 2006-12-19 | 2012-07-04 | 新光電気工業株式会社 | Electronic component built-in substrate and method for manufacturing electronic component built-in substrate |
JP5280014B2 (en) * | 2007-04-27 | 2013-09-04 | ラピスセミコンダクタ株式会社 | Semiconductor device and manufacturing method thereof |
JP5025399B2 (en) * | 2007-09-27 | 2012-09-12 | 新光電気工業株式会社 | Wiring board and manufacturing method thereof |
KR101489798B1 (en) * | 2007-10-12 | 2015-02-04 | 신꼬오덴기 고교 가부시키가이샤 | Wiring board |
JP5144222B2 (en) * | 2007-11-14 | 2013-02-13 | 新光電気工業株式会社 | Wiring board and manufacturing method thereof |
JP2009231635A (en) * | 2008-03-24 | 2009-10-08 | Shinko Electric Ind Co Ltd | Wiring board and its manufacturing method, semiconductor device, and its manufacturing method |
EP2286446A1 (en) * | 2008-06-02 | 2011-02-23 | Nxp B.V. | Electronic device and method of manufacturing an electronic device |
US8186042B2 (en) * | 2009-05-06 | 2012-05-29 | Bae Systems Information And Electronic Systems Integration Inc. | Manufacturing method of a printed board assembly |
JP2011165741A (en) * | 2010-02-05 | 2011-08-25 | Renesas Electronics Corp | Semiconductor device, and method of manufacturing the same |
US9048233B2 (en) * | 2010-05-26 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package systems having interposers |
FR2963478B1 (en) * | 2010-07-27 | 2013-06-28 | St Microelectronics Grenoble 2 | SEMICONDUCTOR DEVICE COMPRISING A PASSIVE COMPONENT OF CAPACITORS AND METHOD FOR MANUFACTURING SAME |
CN102148222B (en) * | 2010-12-18 | 2012-07-18 | 日月光半导体制造股份有限公司 | Semiconductor structure and semiconductor packaging structure having proximity communication signal input ends |
US20120286416A1 (en) * | 2011-05-11 | 2012-11-15 | Tessera Research Llc | Semiconductor chip package assembly and method for making same |
JP2013004866A (en) * | 2011-06-20 | 2013-01-07 | Dainippon Printing Co Ltd | Component built-in substrate |
KR102011840B1 (en) * | 2012-10-19 | 2019-08-19 | 해성디에스 주식회사 | Method of manufacturing circuit board and chip package and circuit board prepared by the same |
US9035194B2 (en) * | 2012-10-30 | 2015-05-19 | Intel Corporation | Circuit board with integrated passive devices |
KR101420526B1 (en) * | 2012-11-29 | 2014-07-17 | 삼성전기주식회사 | Substrate embedding electronic component and manufacturing mehtod thereof |
US20140158414A1 (en) * | 2012-12-11 | 2014-06-12 | Chris Baldwin | Recessed discrete component mounting on organic substrate |
US20140167900A1 (en) | 2012-12-14 | 2014-06-19 | Gregorio R. Murtagian | Surface-mount inductor structures for forming one or more inductors with substrate traces |
US9461025B2 (en) | 2013-03-12 | 2016-10-04 | Taiwan Semiconductor Manfacturing Company, Ltd. | Electric magnetic shielding structure in packages |
US8901748B2 (en) * | 2013-03-14 | 2014-12-02 | Intel Corporation | Direct external interconnect for embedded interconnect bridge package |
US9704735B2 (en) | 2014-08-19 | 2017-07-11 | Intel Corporation | Dual side solder resist layers for coreless packages and packages with an embedded interconnect bridge and their methods of fabrication |
US9721799B2 (en) | 2014-11-07 | 2017-08-01 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with reduced via hole width and reduced pad patch and manufacturing method thereof |
US10079156B2 (en) | 2014-11-07 | 2018-09-18 | Advanced Semiconductor Engineering, Inc. | Semiconductor package including dielectric layers defining via holes extending to component pads |
US9420695B2 (en) | 2014-11-19 | 2016-08-16 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and semiconductor process |
US9426891B2 (en) | 2014-11-21 | 2016-08-23 | Advanced Semiconductor Engineering, Inc. | Circuit board with embedded passive component and manufacturing method thereof |
KR101672641B1 (en) | 2015-07-01 | 2016-11-03 | 앰코 테크놀로지 코리아 주식회사 | Manufacturing method of semiconductor device and semiconductor device thereof |
KR101706470B1 (en) | 2015-09-08 | 2017-02-14 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor device with surface finish layer and manufacturing method thereof |
JP6693228B2 (en) | 2016-03-30 | 2020-05-13 | Tdk株式会社 | Electronic component mounting board |
CN106132085B (en) * | 2016-06-28 | 2019-06-07 | Oppo广东移动通信有限公司 | Pcb board component and mobile terminal with it |
US10242964B1 (en) | 2018-01-16 | 2019-03-26 | Bridge Semiconductor Corp. | Wiring substrate for stackable semiconductor assembly and stackable semiconductor assembly using the same |
US20200161206A1 (en) * | 2018-11-20 | 2020-05-21 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and semiconductor manufacturing process |
KR102513087B1 (en) * | 2018-11-20 | 2023-03-23 | 삼성전자주식회사 | Fan-out semiconductor package |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6108212A (en) * | 1998-06-05 | 2000-08-22 | Motorola, Inc. | Surface-mount device package having an integral passive component |
JP2000349225A (en) | 1999-03-30 | 2000-12-15 | Ngk Spark Plug Co Ltd | Capacitor-attached wiring board, the wiring board, and capacitor |
JP2001274034A (en) | 2000-01-20 | 2001-10-05 | Shinko Electric Ind Co Ltd | Electronic parts package |
US6370013B1 (en) * | 1999-11-30 | 2002-04-09 | Kyocera Corporation | Electric element incorporating wiring board |
US20020185303A1 (en) * | 2001-03-12 | 2002-12-12 | Ngk Spark Plug Co., Ltd. | Wiring circuit board and method for producing same |
US6764931B2 (en) * | 2001-08-24 | 2004-07-20 | Shinko Electric Industries Co., Ltd. | Semiconductor package, method of manufacturing the same, and semiconductor device |
US7176556B2 (en) * | 2001-10-26 | 2007-02-13 | Fujitsu Limited | Semiconductor system-in-package |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3013831B2 (en) * | 1998-01-26 | 2000-02-28 | 日本電気株式会社 | MMIC package |
JP3635219B2 (en) * | 1999-03-11 | 2005-04-06 | 新光電気工業株式会社 | Multilayer substrate for semiconductor device and manufacturing method thereof |
JP4211210B2 (en) * | 2000-09-08 | 2009-01-21 | 日本電気株式会社 | Capacitor, mounting structure thereof, manufacturing method thereof, semiconductor device and manufacturing method thereof |
JP2003031719A (en) * | 2001-07-16 | 2003-01-31 | Shinko Electric Ind Co Ltd | Semiconductor package, production method therefor and semiconductor device |
-
2001
- 2001-12-26 JP JP2001394694A patent/JP3492348B2/en not_active Expired - Fee Related
-
2002
- 2002-12-10 US US10/315,468 patent/US6914322B2/en not_active Expired - Lifetime
- 2002-12-20 KR KR1020020081634A patent/KR100919797B1/en active IP Right Grant
- 2002-12-25 TW TW091137353A patent/TWI273612B/en not_active IP Right Cessation
- 2002-12-26 CN CNB021593213A patent/CN100492637C/en not_active Expired - Fee Related
-
2005
- 2005-05-17 US US11/130,845 patent/US7335531B2/en not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6108212A (en) * | 1998-06-05 | 2000-08-22 | Motorola, Inc. | Surface-mount device package having an integral passive component |
JP2000349225A (en) | 1999-03-30 | 2000-12-15 | Ngk Spark Plug Co Ltd | Capacitor-attached wiring board, the wiring board, and capacitor |
US6370013B1 (en) * | 1999-11-30 | 2002-04-09 | Kyocera Corporation | Electric element incorporating wiring board |
JP2001274034A (en) | 2000-01-20 | 2001-10-05 | Shinko Electric Ind Co Ltd | Electronic parts package |
US20020185303A1 (en) * | 2001-03-12 | 2002-12-12 | Ngk Spark Plug Co., Ltd. | Wiring circuit board and method for producing same |
US6764931B2 (en) * | 2001-08-24 | 2004-07-20 | Shinko Electric Industries Co., Ltd. | Semiconductor package, method of manufacturing the same, and semiconductor device |
US7176556B2 (en) * | 2001-10-26 | 2007-02-13 | Fujitsu Limited | Semiconductor system-in-package |
Cited By (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7595235B2 (en) | 2004-02-20 | 2009-09-29 | Nec Tokin Corporation | Solid electrolytic capacitor, transmission-line device, method of producing the same, and composite electronic component using the same |
US20060130301A1 (en) * | 2004-02-20 | 2006-06-22 | Nec Tokin Corporation | Solid electrolytic capacitor, transmission-line device, method of producing the same, and composite electronic component using the same |
US20080029297A1 (en) * | 2006-08-01 | 2008-02-07 | Shinko Electric Industries Co., Ltd. | Wiring substrate and manufacturing method thereof, and semiconductor device |
US7943863B2 (en) * | 2006-08-01 | 2011-05-17 | Shinko Electric Industries Co., Ltd. | Wiring substrate and manufacturing method thereof, and semiconductor device |
US7755910B2 (en) * | 2006-08-07 | 2010-07-13 | Shinko Electric Industries Co., Ltd. | Capacitor built-in interposer and method of manufacturing the same and electronic component device |
US20080030968A1 (en) * | 2006-08-07 | 2008-02-07 | Shinko Electric Industries Co., Ltd. | Capacitor built-in interposer and method of manufacturing the same and electronic component device |
US7936568B2 (en) * | 2006-08-10 | 2011-05-03 | Shinko Electric Industries Co., Ltd. | Capacitor built-in substrate and method of manufacturing the same and electronic component device |
US20080291649A1 (en) * | 2006-08-10 | 2008-11-27 | Shinko Electric Industries Co., Ltd. | Capacitor built-in substrate and method of manufacturing the same and electronic component device |
US20090290317A1 (en) * | 2008-05-23 | 2009-11-26 | Shinko Electric Industries Co., Ltd. | Printed circuit board, method of fabricating printed circuit board, and semiconductor device |
US8179689B2 (en) | 2008-05-23 | 2012-05-15 | Shinko Electric Industries Co., Ltd. | Printed circuit board, method of fabricating printed circuit board, and semiconductor device |
US8390083B2 (en) | 2009-09-04 | 2013-03-05 | Analog Devices, Inc. | System with recessed sensing or processing elements |
US20110057273A1 (en) * | 2009-09-04 | 2011-03-10 | Analog Devices, Inc. | System with Recessed Sensing or Processing Elements |
US8779532B2 (en) | 2009-09-04 | 2014-07-15 | Analog Devices, Inc. | System with recessed sensing or processing elements |
US20110317381A1 (en) * | 2010-06-29 | 2011-12-29 | Samsung Electronics Co., Ltd. | Embedded chip-on-chip package and package-on-package comprising same |
US8873245B2 (en) * | 2010-06-29 | 2014-10-28 | Samsung Electronics Co., Ltd. | Embedded chip-on-chip package and package-on-package comprising same |
US9407997B2 (en) | 2010-10-12 | 2016-08-02 | Invensense, Inc. | Microphone package with embedded ASIC |
US20120119358A1 (en) * | 2010-11-11 | 2012-05-17 | Samsung Electro-Mechanics Co., Ltd. | Semicondiuctor package substrate and method for manufacturing the same |
US20150245481A1 (en) * | 2012-08-21 | 2015-08-27 | Epcos Ag | Electric Component Assembly |
US10278285B2 (en) * | 2012-08-21 | 2019-04-30 | Epcos Ag | Electric component assembly |
US9847462B2 (en) | 2013-10-29 | 2017-12-19 | Point Engineering Co., Ltd. | Array substrate for mounting chip and method for manufacturing the same |
US9666558B2 (en) | 2015-06-29 | 2017-05-30 | Point Engineering Co., Ltd. | Substrate for mounting a chip and chip package using the substrate |
Also Published As
Publication number | Publication date |
---|---|
JP3492348B2 (en) | 2004-02-03 |
TWI273612B (en) | 2007-02-11 |
TW200301493A (en) | 2003-07-01 |
US20030116843A1 (en) | 2003-06-26 |
CN1428800A (en) | 2003-07-09 |
US6914322B2 (en) | 2005-07-05 |
US20050208705A1 (en) | 2005-09-22 |
CN100492637C (en) | 2009-05-27 |
KR100919797B1 (en) | 2009-10-01 |
KR20030058917A (en) | 2003-07-07 |
JP2003197809A (en) | 2003-07-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7335531B2 (en) | Semiconductor device package and method of production and semiconductor device of same | |
US7314780B2 (en) | Semiconductor package, method of production of same, and semiconductor device | |
US7053475B2 (en) | Semiconductor device and manufacturing method therefor | |
US7279771B2 (en) | Wiring board mounting a capacitor | |
US8222747B2 (en) | Multilayer wiring substrate mounted with electronic component and method for manufacturing the same | |
US6964887B2 (en) | Method for manufacturing semiconductor device | |
US7358591B2 (en) | Capacitor device and semiconductor device having the same, and capacitor device manufacturing method | |
US20040090758A1 (en) | Multi-layered semiconductor device and method of manufacturing same | |
KR20020086741A (en) | Semiconductor device and its manufacturing method | |
JP2003031719A (en) | Semiconductor package, production method therefor and semiconductor device | |
JP2002164467A (en) | Circuit block body, its manufacturing method, wiring circuit device, its manufacturing method, semiconductor device and its manufacturing method | |
KR20160023585A (en) | Electrical interconnect structure for an embedded semiconductor device package and method of manufacturing thereof | |
KR20160032985A (en) | Package board, method for manufacturing the same and package on package having the thereof | |
US20040265482A1 (en) | Wiring substrate manufacturing method | |
KR100735825B1 (en) | Multi-layer package structure and fabrication method thereof | |
JP2001144245A (en) | Semiconductor package, manufacturing method therefor and semiconductor device | |
US20040256715A1 (en) | Wiring board, semiconductor device and process of fabricating wiring board | |
US6913814B2 (en) | Lamination process and structure of high layout density substrate | |
JP4084728B2 (en) | Package for semiconductor device and semiconductor device | |
JP3112885B2 (en) | Semiconductor component mounting module |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FEPP | Fee payment procedure |
Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
LAPS | Lapse for failure to pay maintenance fees |
Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20200226 |