US7568115B2 - Power delivery and power management of many-core processors - Google Patents

Power delivery and power management of many-core processors Download PDF

Info

Publication number
US7568115B2
US7568115B2 US11/238,489 US23848905A US7568115B2 US 7568115 B2 US7568115 B2 US 7568115B2 US 23848905 A US23848905 A US 23848905A US 7568115 B2 US7568115 B2 US 7568115B2
Authority
US
United States
Prior art keywords
die
many
voltage
core processor
power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US11/238,489
Other versions
US20070070673A1 (en
Inventor
Shekhar Borkar
Tanay Karnik
Shu-ling Garver
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BORKAR, SHEKHAR, KARNIK, TANAY, GARVER, SHU-LING
Priority to US11/238,489 priority Critical patent/US7568115B2/en
Priority to CN2010106233863A priority patent/CN102073371B/en
Priority to GB0805204A priority patent/GB2444013A/en
Priority to CN200680036147XA priority patent/CN101278250B/en
Priority to DE112006002506T priority patent/DE112006002506B4/en
Priority to KR1020087007642A priority patent/KR100974363B1/en
Priority to PCT/US2006/037522 priority patent/WO2007038529A2/en
Priority to JP2008533528A priority patent/JP2009510617A/en
Publication of US20070070673A1 publication Critical patent/US20070070673A1/en
Publication of US7568115B2 publication Critical patent/US7568115B2/en
Application granted granted Critical
Priority to JP2011245570A priority patent/JP2012038347A/en
Priority to HK11112721.8A priority patent/HK1158340A1/en
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • each Vcc supply may have multiple phases and each phase needs to have its own inductor.
  • An external VR module (“VRM”) on the motherboard is not likely to enable a many-Vcc solution because a motherboard cannot accommodate so many inductors.
  • the motherboard based power delivery system does not have enough area on either the mother board, or the socket, or the package to route separate supply voltages to each of the cores and/or other units in the many-core processor.
  • the response time of a motherboard VR typically in the order of milliseconds
  • is typically not quick enough to respond to changes of a core's voltage needs typically in the order of nanoseconds). Therefore, it is desirable to have a solution under which multi-VCC may be supplied to a many-core processor and under which voltage supply to a core may be quickly activated or shut off.
  • FIG. 2 shows another example computing system 200 where a many-core processor may be used.
  • System 200 may comprise multiple processors such as processors 220 A.
  • One or more processors in system 200 may have many cores.
  • the power needed by a many-core processor may be supplied by a power management system (e.g., 240 A, 240 M) with multiple VRs (not shown in the figure). Different VRs may provide different voltages and the output voltage of each VR may be modulated at the direction of a core to which the VR supplies power.
  • the power management system may reside in the same die as the many-core processor.
  • the power management system may also reside in a separate die from the many-core processor with the VR die mounted in the same package as the processor die.
  • FIG. 4 shows west side I/O unit 440 A and east side I/O unit 440 B in the processor die. Note that I/O interconnects may be embedded among the cores in some other embodiments. Compared to processors that have a single core or only a few cores, the number of cores in a many-core processor is large. As a result, the size of each core in a many-core processor is small compared to those cores in a single-core or multi-core processor. Although FIG. 4 shows an example processor 400 which has only 64 cores, the number of cores in a many-core processor can vary and may be much larger than 64 (e.g., 256, 512, 1024).

Abstract

According to embodiments of the disclosed subject matter in this application, a power management system with multiple voltage regulator (“VRs”) may be used to supply power to cores in a many-core processor. Each VR may supply power to a core or a part of a core. Different VRs may provide multiple voltages to a core/part in the many-core processor. The value of the output voltage of a VR may be modulated under the direction of the core/part to which the voltage regulator supplies power. In one embodiment, the multiple VRs may be integrated with cores in a single die. In another embodiment, the power management system with multiple VRs may be on a die (“the VR die”) separate from the die of the many-core processor. The VR die may be included in the same package as the many-core processor die.

Description

BACKGROUND
1. Field
This disclosure relates generally to processors and, more specifically, to processors that have many cores.
2. Description
Process technology scaling has enabled many-core super-scalar microprocessors, e.g. there may be 256 processor cores on a single die. The process technology scaling is achieved by scaling down device sizes and lowering supply voltages. A many-core processor may have better performance than a single-core or a multi-core processor because many cores may work in parallel to achieve higher performance. Additionally, a many-core processor may consume less power than a single-core or multi-core processor because each core in the many-core processor normally requires a lower voltage supply than a core in the single-core or multi-core processor although the maximum voltage may be the same. Because basic components (e.g., transistors) are smaller, lines are thinner, and distances between components/lines are finer inside a many-core processor than those in a single-core or multi-core processor, the many-core processor may be less resistant to heat. Thus, it is desirable to reduce the power consumption by a many-core processor.
In a typical computer system using a many-core processor, all of the cores in the many-core processor are supplied with the same voltage. The voltage regulator (“VR”) on the motherboard supplies a single voltage (“Vcc”) to all the cores and storage units (e.g., memories and caches) in the many-core processor and supplies another voltage (“Vtt”) to all of the input/output (“I/O”) units in the processor.
However, cores in a many-core processor may require different supply voltages. The operation of a core depends on application, core temperature, transient current consumption, reliability, and other factors. For example, in some applications, some cores may not be active until they are required to function after some other cores are deemed unreliable due to variations and time dependent degradation. Those inactive cores may only require a very low supply voltage or may be simply shut off. For those active cores, their voltage requirements may be different. Even inside a single core, non-active parts may be shut down and non-performance-critical parts may be put on lower voltage to save active power. Thus, variable core-level or even subcore-level Vcc modulation and fast activation/shut-off may provide significant power savings. Such desirable features of delivering voltages to a many-core processor require multi-Vcc supply rather than a single Vcc supply.
It is difficult to supply multi-VCC to a many-core processor through motherboard VRs. Each Vcc supply may have multiple phases and each phase needs to have its own inductor. An external VR module (“VRM”) on the motherboard is not likely to enable a many-Vcc solution because a motherboard cannot accommodate so many inductors. Additionally, the motherboard based power delivery system does not have enough area on either the mother board, or the socket, or the package to route separate supply voltages to each of the cores and/or other units in the many-core processor. Furthermore, the response time of a motherboard VR (typically in the order of milliseconds) is typically not quick enough to respond to changes of a core's voltage needs (typically in the order of nanoseconds). Therefore, it is desirable to have a solution under which multi-VCC may be supplied to a many-core processor and under which voltage supply to a core may be quickly activated or shut off.
BRIEF DESCRIPTION OF THE DRAWINGS
The features and advantages of the disclosed subject matter will become apparent from the following detailed description of the subject matter in which:
FIG. 1 shows one example computing system where a many-core processor may be used;
FIG. 2 shows another example computing system where a many-core processor may be used;
FIG. 3 shows yet another example computing system where a many-core processor may be used;
FIG. 4 illustrates a structure of an example many-core processor;
FIG. 5 illustrates a structure of an example many-core processor with each core having its own voltage regulator;
FIG. 6 illustrates a structure of another example many-core processor with voltage regulators surrounding cores;
FIG. 7 shows one example approach for many-core processor power management;
FIG. 8 shows one example for delivering power to and for managing power for a many-core processor; and
FIG. 9 shows another example for delivering power to and for managing power for a many-core processor.
 DETAILED DESCRIPTION
According to embodiments of the disclosed subject matter in this application, a power management system with multiple VRs may be used to supply power to cores in a many-core processor. Each VR may supply power to at least one core. Different VRs may provide multiple Vcc's to cores in the many-core processor. The value of the output voltage of a VR may be modulated under the direction of the core to which the voltage regulator supplies power. In one embodiment, the multiple VRs may be integrated with cores in a single die. For example, each core may have its own VR which is located adjacent to the die area of the core. In another embodiment, the multiple VRs and the cores may share a single die with VRs surrounding the cores in the die.
In another embodiment, the power management system with multiple VRs may be on a die (“the VR die”) separate from the die of the many-core processor. Separate voltage identification (“VID”) interconnects between the many-core processor die and the VR die may be used to specify the Vcc needs of each core. The VR die may be included in the same package as the many-core processor die. In one example, the VR die may be sandwiched between the package substrate and the many-core processor die. In another example, the VR die may be mounted to a side of the package substrate while the many-core processor die is mounted to the other side of the package substrate.
According to embodiments of the disclosed subject matter in the present application, cores in a many-core processor may be supplied with different voltages depending on the status of its activity, which may result in significant reduction of power consumption by the many-core processor. Additionally, a power management system according to an embodiment of the disclosed subject matter may respond quickly to specific voltage needs by a core.
Reference in the specification to “one embodiment” or “an embodiment” of the disclosed subject matter means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosed subject matter. Thus, the appearances of the phrase “in one embodiment” appearing in various places throughout the specification are not necessarily all referring to the same embodiment.
FIG. 1 shows one example computing system 100 where a many-core processor may be used. Computing system 100 may comprise one or more processors 110 coupled to a system interconnect 115. Processor 110 may be a many-core processor whose power is supplied by a power management system 105 with multiple VRs (not shown in the figure). Different VRs may provide different voltages and the output voltage of each VR may be modulated at the direction of a core to which the VR supplies power. The power management system may reside in the same die as the many-core processor. The power management system may also reside in a separate die from the many-core processor with the VR die mounted in the same package as the processor die.
The computing system 100 may also include a chipset 130 coupled to the system interconnect 115. Chipset 130 may include one or more integrated circuit packages or chips. Chipset 130 may comprise one or more device interfaces 135 to support data transfers to and/or from other components 160 of the computing system 100 such as, for example, BIOS firmware, keyboards, mice, storage devices, network interfaces, etc. Chipset 130 may be coupled to a Peripheral Component Interconnect (PCI) bus 170. Chipset 130 may include a PCI bridge 145 that provides an interface to the PCI bus 170. The PCI Bridge 145 may provide a data path between the processor 110 as well as other components 160, and peripheral devices such as, for example, an audio device 180 and a disk drive 190. Although not shown, other devices may also be coupled to the PCI bus 170.
Additionally, chipset 130 may comprise a memory controller 125 that is coupled to a main memory 150. The main memory 150 may store data and sequences of instructions that are executed by the processor 110 or any other device included in the system. The memory controller 125 may access the main memory 150 in response to memory transactions associated with the processor 110, and other devices in the computing system 100. In one embodiment, memory controller 150 may be located in processor 110 or some other circuitries. The main memory 150 may comprise various memory devices that provide addressable storage locations which the memory controller 125 may read data from and/or write data to. The main memory 150 may comprise one or more different types of memory devices such as Dynamic Random Access Memory (DRAM) devices, Synchronous DRAM (SDRAM) devices, Double Data Rate (DDR) SDRAM devices, or other memory devices.
FIG. 2 shows another example computing system 200 where a many-core processor may be used. System 200 may comprise multiple processors such as processors 220A. One or more processors in system 200 may have many cores. The power needed by a many-core processor may be supplied by a power management system (e.g., 240A, 240M) with multiple VRs (not shown in the figure). Different VRs may provide different voltages and the output voltage of each VR may be modulated at the direction of a core to which the VR supplies power. The power management system may reside in the same die as the many-core processor. The power management system may also reside in a separate die from the many-core processor with the VR die mounted in the same package as the processor die. Processors in system 200 may be connected to each other using a system interconnect 210. System interconnect 210 may be a Front Side Bus (FSB). Each processor may be connected to Input/Output (IO) devices as well as memory 230 through the system interconnect.
FIG. 3 shows yet another example computing system 300 where a many-core processor may be used. In system 300, system interconnect 310 that connects multiple processors (e.g., 320A, 320B, 320C, and 320D) is a links-based point-to-point connection. Each processor may connect to the system interconnect through a links hub (e.g., 330A, 330B, 330C, and 330D). In some embodiments, a links hub may be co-located with a memory controller, which coordinates traffic to/from a system memory. One or more processor may have many cores. The power needed by a many-core processor may be supplied by a power management system (e.g., 340A, 340B, 340C, and 340D) with multiple VRs (not shown in the figure). Different VRs may provide different voltages and the output voltage of each VR may be modulated at the direction of a core to which the VR supplies power. The power management system may reside in the same die as the many-core processor. The power management system may also reside in a separate die from the many-core processor with the VR die mounted in the same package as the processor die.
In either FIG. 1, 2, or 3, the many-core processor may be thermally coupled to a cooling system to dissipate heat generated by the processor. The cooling system may comprise a heat spreader attached on the top of the many-core processor package. The heat spreader helps dissipate heat from the many-core processor to ambient air surrounding the heat spreader. In one embodiment, the cooling system may comprise a heat pipe with one end thermally coupled to the top of the many-core processor package and the other end thermally coupled to a heat exchanger. The heat pipe helps transmit heat from the many-core processor to the heat exchanger which may dissipate the heat outside a computing system.
FIG. 4 illustrates the structure of an example many-core processor 400. Processor 400 comprises an 8-by-8 array of cores (e.g., core 410A) sitting on a two-dimensional (2D) interconnect fabric 430. Each core may have its local memory (not shown in the figure). There may also be shared memories (e.g., 420A, 420B, and 420C) attached to the interconnect fabric 430. The cores in processor 400 are surrounded by input/output (“I/O”) interconnect area. The I/O interconnects are typically on the periphery (e.g., north, south, east, and west boundaries) to enable efficient vertical current delivery to the cores. For simplicity, FIG. 4 only shows west side I/O unit 440A and east side I/O unit 440B in the processor die. Note that I/O interconnects may be embedded among the cores in some other embodiments. Compared to processors that have a single core or only a few cores, the number of cores in a many-core processor is large. As a result, the size of each core in a many-core processor is small compared to those cores in a single-core or multi-core processor. Although FIG. 4 shows an example processor 400 which has only 64 cores, the number of cores in a many-core processor can vary and may be much larger than 64 (e.g., 256, 512, 1024).
Because components in a many-core processor are in smaller dimensions than those in a single-core or multi-core processor, they are less resistant to heat. Thus, it is desirable to reduce power consumption by a many-core processor. In a typical computer system using a many-core processor, all of the cores in the many-core processor are supplied with the same voltage. The voltage regulator (“VR”) on the motherboard supplies a single voltage (“Vcc”) to all the cores and storage units (e.g., memories and caches) in the many-core processor and supplies another voltage (“Vtt”) to all of the input/output (“I/O”) units in the processor. As a result of such a single-Vcc power management scheme, a many-core processor may consume more power than it actually needs because cores may require different supply voltages.
The operation of a core depends on application, core temperature, transient current consumption, reliability, and other factors. For example, in some applications, some cores may not be active until they are required to function after some other cores are deemed unreliable due to variations and time dependent degradation. Those inactive cores may only require a very low supply voltage or may be simply shut off. For those active cores, their voltage requirements may be different. Even inside a single core, non-active parts may be shut down and non-performance-critical parts may be put on lower voltage to save active power. Thus, variable core-level or even subcore-level Vcc modulation and fast activation/shut-off may provide significant power savings. There may be several approaches to achieve variable core/subcore-level Vcc modulation and fast activation/shut-off with a power management system for a many-core processor.
FIG. 5 Illustrates one example structure 500 in which a many-core processor is powered by a power management system that can provide variable core/subcore-level Vcc modulation and the fast activation/shut-off feature. The arrangement of cores and shared memories in structure 500 is similar to that shown in FIG. 4. In structure 500, however, each core has its own local VR (e.g., VR 510A for core 410A). Also each I/O interconnect unit has its own local VR (e.g., VR 520A for I/O unit 440A, and VR 520B for I/O unit 440B). The output voltage of each local VR for a core may be modulated under the control of the core. For example, when a core is active and needs to operate at a high frequency, the core may send a signal to its local VR instructing the VR to supply a high voltage; when a core is performing non-computation intensive work and does not need to operate at a high frequency, the core may request its local VR to supply a low voltage; when a core is not active, the core may instruct its local VR to shut off its power supply. When the local VR receives such a signal from the core, the local VR will act quickly and supply the voltage as requested. Because I/O units have to communicate with external components, it may be desirable that their voltage supply not be modulated.
Although FIG. 5 illustrates one VR per core, there may be multiple cores whose power is supplied by one VR in one embodiment. For example, there is one VR for each column and one VR for each row and these VRs are shared by all of the cores in a many-core processor. In another embodiment, there may be more than one VR for each core, with different VRs supply voltages to different parts inside the core so that different parts of the core may function at different Vcc's. As illustrated by structure 500, VRs are on the same die as cores and are very close to cores to which they supply power. Such close integration between VRs and cores helps minimize the power supply path and thus significantly reduces resistive and inductive losses.
FIG. 6 illustrates another example structure 600 in which a many-core processor is powered by a power management system that can provide variable core/subcore-level Vcc modulation and the fast activation/shut-off feature. The arrangement of cores and shared memories in structure 600 is similar to that shown in FIG. 4 (shared memories and interconnect fabric are not shown in FIG. 6). Cores (e.g., 620A) are attached to the interconnect fabric through switches. I/ O units 630A, 630B, 630C, and 630D are west side I/O unit, north side I/O unit, east side I/O unit, and south side I/O unit. As in structure 500 shown in FIG. 5, in structure 600 VRs (e.g., VR 640A) reside on the same die as cores and I/O units, but are not integrated with cores and/or I/O units in the same manner as that shown in FIG. 5. In structure 600, VRs surround the die area 610 of cores and I/O units. Each VR supplies power to at least one core and/or one I/O unit. In FIG. 600, VRs reside outside the I/O area, however, VRs may reside inside the I/O area but outside the core area in one embodiment. The output voltage of each VR may be modulated under the control of a core (or cores) to which the VR supplies power. Although not shown in FIG. 6, some VRs may be integrated in a way similar to that shown in FIG. 5 while other VRs surround the die area of cores.
In either example 500 (shown in FIG. 5) or example 600 (shown in FIG. 6), the die hosting both cores of the many-core processor and VRs may be mounted to a package substrate which has multiple bins to connect the cores and VRs to a motherboard in a computing system.
In FIGS. 5 and 6, VRs and cores share a single die (“on-die VR”). Such on-die VR arrangements help shorten power delivery paths from VRs to cores and thus reduce resistive and inductive losses of power on the delivery path. Additionally, because VRs and cores to which they supply power are close to each other on the same die, it is relatively easy to route a VID signal from a core to its corresponding VR. However, each VR has multiple phases and each phase needs to have its own inductor. The on-die VR arrangements such as those shown in FIGS. 5 and 6 thus require integrating on-die inductor processing technology into the microprocessor processing technology. It may be expensive to implement such integration in the production of many-core microprocessors.
FIG. 7 shows another example 700 for delivering many Vcc's to a many-core processor. In example 700, the power management system with many VRs (e.g., VR 730A) is on a separate die (“VR die”) 720 from the many-core processor die 710. The VR die may also be referred to as VR module (“VRM”). On the VR die, units 740A and 740B may receive VID request signals from west side I/O unit 440A and ease side I/O unit 440B on the many-core processor die, respectively. In one embodiment, each core on the many-core processor die may have its corresponding VR in the VRM, e.g., core 410A may have its own VR 730A; and each I/O unit may have its own VR in the VRM, e.g., west side I/O unit 440A and east side I/O unit 440B may have their own VRs included in 740A and 740B, respectively. In another embodiment, more than one core and/or I/O unit may share one VR in the VRM. Yet in another embodiment, a core and/or an I/O unit on the many-core processor may have more than one VR to supply voltages to different parts of the core and/or the I/O unit.
Because the many-core processor and its corresponding VRM are located on separate dies, there may be separate VID interconnects routed from the many-core processor to the VRM to specify Vcc needs at various power inputs on the processor. For example, VID interconnects 750A and 750B may deliver VID request signals from west side I/O unit 440A to unit 740A and from east side I/O unit 440B to unit 740B, respectively. Additionally, the VR die may provide body bias signals to the many-core processor for active and leakage power control. Because VRs reside on a separate die, there is no need to integrate VRs with cores in a many-core processor, and it is thus not necessary to use an on-die inductor processing technology in the production of the many-core processor (on-die inductor processing is done on the VR die).
A separate VR die may be packaged with a many-core processor die in the same package. FIG. 8 shows one example 800 for packaging a VR die and a many-core processor die together in one package. As shown in the figure, VR die 820 is sandwiched between many-core die 810 and package substrate 830. Each VR on the VR die has at least one voltage output point (e.g., 880B and 890B) on the side facing the many-core processor die. Corresponding to each output point on the VR die, there is a voltage receiving point (e.g., 880A and 890A) on the side of the many-core processor die that faces the VR die. Each pair of voltage output and receiving points may be made in such a form that they couple with each other electronically when the VR die and the many-core processor are packaged together as illustrated in FIG. 8. For example, each voltage output point may be made in the form of a connection projection and its corresponding voltage receiving point may be made in the form of a connection pad. When the two dies are packaged together, each connection projection will physically contact its corresponding connection pad. Additionally, there may be connection points for VID signals on both the VR die and the many-core processor die. A VID connection point on the VR die and its corresponding connection point on the many-core processor die may be made in forms similar to those of voltage output and input connection points.
There may be a plurality of connection means (such as pins, solder balls, copper pucks, and so on) (not shown in FIG. 8) mounted in the package substrate on a side other than the side where the VR die is mounted. Such connection means may project, at least partially, out of the package substrate to connect the VR die and the many-core processor die to a motherboard of a computing system. Typically a many-core processor is connected with the motherboard through I/O units on its die, which are typically located on the boundaries of the many-core processor die as shown in FIG. 4. For the I/O units on the many-core processor die to connect to the plurality of connection means in the package substrate, through silicon vias (“TSVs”) (e.g., 850B and 870B) may be built in areas on the VR die, corresponding to the I/O areas on the many-core processor die. In addition to connections between the many-core processor die and the plurality of connection means in the package substrate, there are also connections (e.g., 840 and 860) between the VR die and the plurality of connection means in the package substrate. These connections may be for power input and/or control signals to the VR die.
FIG. 9 shows another example 900 for packaging a VR die and a many-core processor die together in one package. As shown in the figure, package substrate 930 may be sandwiched between many-core die 910 and VR die 920. Each VR on the VR die has at least one voltage output point (e.g., 980B and 990B) on the side facing the package substrate. Corresponding to each output point on the VR die, there is a voltage receiving point (e.g., 980A and 990A) on the side of the many-core processor die that faces the package substrate. Each pair of voltage output and receiving points may be electronically coupled with each other through a connection line in the package substrate. Additionally, there may be connection points for VID signals on both the VR die and the many-core processor die (e.g., 950A, 950B, 960A, and 960B). A VID connection point on the VR die and its corresponding connection point on the many-core processor die may be electronically coupled with each other in ways similar to those used to couple voltage output and input connection points.
There may be a plurality of connection means (such as pins, solder balls, copper pucks, and so on) (not shown in FIG. 9) mounted in the package substrate. The plurality of connection means may project, at least partially, out of the package substrate to connect the VR die and the many-core processor die to a motherboard of a computing system. Typically a many-core processor is connected with the motherboard through I/O units on its die, which are typically located on the boundaries of the many-core processor die as shown in FIG. 4. In addition to connections between the many-core processor die and the plurality of connection means in the package substrate, there are also connections (e.g., 940 and 970) between the VR die and the plurality of connection means in the package substrate. These connections may be for power input and/or control signals to the VR die.
In either example 800 (shown in FIG. 8) or example 900 (shown in FIG. 9), there may be a cooling system thermally coupled to a package of a VR die and a many-core processor die. For example, in example 800, a cooling system may be thermally coupled to the package from the side close to the top surface of the many-core processor die; in example 900, a cooling system may be thermally coupled to the package from the side close to the top surface of the many-core processor die and/or from the side close to the bottom surface of the VR die.
Although embodiments of the disclosed subject matter are described in the context of a many-core processor, what is disclosed in this application can be used for power delivery and power management for any integrated circuit which has multiple parts/units and part/unit-level Vcc modulation as well as fast power activation/shut-off may be needed.
Although an example embodiment of the disclosed subject matter is described with reference to block and flow diagrams in FIGS. 1-9, persons of ordinary skill in the art will readily appreciate that many other methods of implementing the disclosed subject matter may alternatively be used. For example, the order of execution of the blocks in flow diagrams may be changed, and/or some of the blocks in block/flow diagrams described may be changed, eliminated, or combined.
In the preceding description, various aspects of the disclosed subject matter have been described. For purposes of explanation, specific numbers, systems and configurations were set forth in order to provide a thorough understanding of the subject matter. However, it is apparent to one skilled in the art having the benefit of this disclosure that the subject matter may be practiced without the specific details. In other instances, well-known features, components, or modules were omitted, simplified, combined, or split in order not to obscure the disclosed subject matter.
While the disclosed subject matter has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the subject matter, which are apparent to persons skilled in the art to which the disclosed subject matter pertains are deemed to lie within the scope of the disclosed subject matter.

Claims (20)

1. An apparatus for managing power for an integrated circuit, comprising:
a package substrate;
a first die of a voltage regulator module, said first die mounted on said package substrate, said voltage regulator module including a plurality of voltage regulators; and
a second die of said integrated circuit, said package substrate, said first die, and said second die packed in the same package, said integrated circuit including a plurality of electronic units, wherein each voltage regulator in said first die is electronically coupled to said second die to supply power for and to provide a body bias signal to one or more electronic units in said second die based on specific conditions of said one or more electronic units to optimize power consumption.
2. The apparatus of claim 1, wherein said second die comprises input/output (I/O) interconnects for said plurality of electronic units, said I/O interconnects including interconnects for voltage identification (“VID”) signals.
3. The apparatus of claim 2, wherein said VID signals comprise a request from an electronic unit in said second die for a voltage supply with a specific value to a voltage regulator in said first die, said specific value being determined based on specific condition of said electronic unit, wherein upon receiving said request, said voltage regulator supplies said electronic unit with a voltage of said specific value.
4. The apparatus of claim 2, wherein said package substrate is between said first die and said second die.
5. The apparatus of claim 1, wherein each voltage regulator in said first die is aligned with one or more electronic units in said second die, to which the voltage regulator supplies power.
6. The apparatus of claim 1, wherein said integrate circuit comprises a many-core processor, said many-core processor including a plurality of cores, each of said plurality of electronic units including one of said plurality of cores.
7. The apparatus of claim 1, wherein said specific conditions of said one or more electronic units comprise one of software application running on, temperature of, transient current consumption by, reliability of, activeness of, working frequency required by, said one of more electronic units.
8. An apparatus for managing power for an integrated circuit, comprising:
a package substrate; and
a die mounted on said package substrate, said die including said integrated circuit and a plurality of voltage regulators, said integrated circuit including a plurality of electronic units, wherein each of said plurality of voltage regulators supplies power for and to provide a body bias signal to one or more of said plurality of electronic units based on specific conditions of said one or more electronic units to optimize power consumption.
9. The apparatus of claim 8, wherein said die comprises input/output (I/O) interconnects for said plurality of electronic units and interconnects for voltage identification (“VID”) signals.
10. The apparatus of claim 9, wherein said VID signals comprise a request from an electronic unit for a voltage supply with a specific value to a voltage regulator, wherein upon receiving said request, said specific value being determined based on specific condition of said electronic unit, said voltage regulator supplies said electronic unit with a voltage of said specific value.
11. The apparatus of claim 8, wherein said integrate circuit comprises a many-core processor, said many-core processor including a plurality of cores, each of said plurality of electronic units including one of said plurality of cores.
12. The apparatus of claim 8, wherein said specific conditions of said one or more electronic units comprise one of software application running on, temperature of, transient current consumption by, reliability of, activeness of, working frequency required by, said one of more electronic units.
13. A computing system, comprising:
a many-core processor, said many-core processor including a plurality of cores;
a non-volatile memory to store data for said many-core processor; and
a plurality of voltage regulators to provide power to said plurality of cores;
wherein each of said plurality of voltage regulators is located in proximity to one or more of said plurality of cores to which the voltage regulator supplies power (“power-receiving object”), and is capable of providing a voltage supply with a specific value requested by the power-receiving object to the power-receiving object and of providing a body bias signal to the power-receiving object, said specific value being determined based on specific condition of the power-receiving object to optimize power consumption of the many-core processor.
14. The system of claim 13, further comprising interconnects for voltage identification (“VID”) signals, said VID signals including a request from one of said plurality of cores for a voltage supply with a specific value to one of said plurality of voltage regulators, wherein upon receiving said request, said voltage regulator supplies said core with a voltage of said specific value, said specific value being determined based on specific condition of said core.
15. The system of claim 13, wherein said plurality of voltage regulators reside on a first die and said plurality of cores reside on a second die, said first die and said second die packed with a package substrate in the same package, wherein each voltage regulator in said first die is electronically coupled to said second die to supply power for one or more cores in said second die.
16. The system of claim 15, wherein said package substrate is between said first die and said second die.
17. The system of claim 15, wherein said first die is between said second die and said package substrate.
18. The system of claim 13, wherein said plurality of cores and said plurality of voltage regulators reside on a die, said die packaged with a package substrate.
19. The system of claim 13, further comprising a cooling system thermally coupled to at least one of said many-core processor and said plurality of voltage regulators to dissipate heat generated by at least one of said many-core processor and said plurality of voltage regulators.
20. The system of claim 13, wherein specific condition of the power-receiving object comprises one of software application running on, temperature of, transient current consumption by, reliability of, activeness of, working frequency required by, the power-receiving object.
US11/238,489 2005-09-28 2005-09-28 Power delivery and power management of many-core processors Active 2026-12-24 US7568115B2 (en)

Priority Applications (10)

Application Number Priority Date Filing Date Title
US11/238,489 US7568115B2 (en) 2005-09-28 2005-09-28 Power delivery and power management of many-core processors
KR1020087007642A KR100974363B1 (en) 2005-09-28 2006-09-26 Power delivery and power management of many-core processors
JP2008533528A JP2009510617A (en) 2005-09-28 2006-09-26 Power supply and power management for multi-core processors
GB0805204A GB2444013A (en) 2005-09-28 2006-09-26 Power delivery and power management of many-core processors
CN200680036147XA CN101278250B (en) 2005-09-28 2006-09-26 Power delivery and power management of many-core processors
DE112006002506T DE112006002506B4 (en) 2005-09-28 2006-09-26 Energy delivery and energy management in multi-core processors
CN2010106233863A CN102073371B (en) 2005-09-28 2006-09-26 Power delivery and power management of many-core processors
PCT/US2006/037522 WO2007038529A2 (en) 2005-09-28 2006-09-26 Power delivery and power management of many-core processors
JP2011245570A JP2012038347A (en) 2005-09-28 2011-11-09 Power deliverly and power management of many-core processor
HK11112721.8A HK1158340A1 (en) 2005-09-28 2011-11-24 Power delivery and power management of many-core processors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/238,489 US7568115B2 (en) 2005-09-28 2005-09-28 Power delivery and power management of many-core processors

Publications (2)

Publication Number Publication Date
US20070070673A1 US20070070673A1 (en) 2007-03-29
US7568115B2 true US7568115B2 (en) 2009-07-28

Family

ID=37795149

Family Applications (1)

Application Number Title Priority Date Filing Date
US11/238,489 Active 2026-12-24 US7568115B2 (en) 2005-09-28 2005-09-28 Power delivery and power management of many-core processors

Country Status (8)

Country Link
US (1) US7568115B2 (en)
JP (2) JP2009510617A (en)
KR (1) KR100974363B1 (en)
CN (2) CN102073371B (en)
DE (1) DE112006002506B4 (en)
GB (1) GB2444013A (en)
HK (1) HK1158340A1 (en)
WO (1) WO2007038529A2 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080136397A1 (en) * 2006-12-08 2008-06-12 Gunther Stephen H Operating integrated circuit logic blocks at independent voltages with single voltage supply
US20100229010A1 (en) * 2009-03-09 2010-09-09 Yasuyuki Nasu Computer system, method for controlling the same, and program
US20100296238A1 (en) * 2009-05-22 2010-11-25 Mowry Anthony C Heat management using power management information
US20140068289A1 (en) * 2012-08-28 2014-03-06 Noah B. Beck Mechanism for reducing interrupt latency and power consumption using heterogeneous cores
US8856568B2 (en) 2006-11-01 2014-10-07 Intel Corporation Independent power control of processing cores
US9848515B1 (en) 2016-05-27 2017-12-19 Advanced Micro Devices, Inc. Multi-compartment computing device with shared cooling device
US11687135B2 (en) 2013-05-31 2023-06-27 Tahoe Research, Ltd. Controlling power delivery to a processor via a bypass

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7263457B2 (en) * 2006-01-03 2007-08-28 Advanced Micro Devices, Inc. System and method for operating components of an integrated circuit at independent frequencies and/or voltages
US7685441B2 (en) * 2006-05-12 2010-03-23 Intel Corporation Power control unit with digitally supplied system parameters
JP4945224B2 (en) * 2006-11-30 2012-06-06 株式会社東芝 Controller, information processing apparatus, and supply voltage control method
US7692278B2 (en) * 2006-12-20 2010-04-06 Intel Corporation Stacked-die packages with silicon vias and surface activated bonding
US7977218B2 (en) * 2006-12-26 2011-07-12 Spansion Llc Thin oxide dummy tiling as charge protection
US7971074B2 (en) * 2007-06-28 2011-06-28 Intel Corporation Method, system, and apparatus for a core activity detector to facilitate dynamic power management in a distributed system
US8601292B2 (en) * 2008-03-31 2013-12-03 Intel Corporation Supply margining method and apparatus
US20090290773A1 (en) * 2008-05-21 2009-11-26 Varian Medical Systems, Inc. Apparatus and Method to Facilitate User-Modified Rendering of an Object Image
US8587595B2 (en) 2009-10-01 2013-11-19 Hand Held Products, Inc. Low power multi-core decoder system and method
US8473818B2 (en) 2009-10-12 2013-06-25 Empire Technology Development Llc Reliable communications in on-chip networks
US8635470B1 (en) * 2009-12-16 2014-01-21 Applied Micro Circuits Corporation System-on-chip with management module for controlling processor core internal voltages
US8812879B2 (en) * 2009-12-30 2014-08-19 International Business Machines Corporation Processor voltage regulation
US8990591B2 (en) * 2009-12-31 2015-03-24 Intel Corporation Power management system for selectively changing the power state of devices using an OS power management framework and non-OS power management framework
US8943334B2 (en) * 2010-09-23 2015-01-27 Intel Corporation Providing per core voltage and frequency control
US8637212B2 (en) 2010-12-22 2014-01-28 Via Technologies, Inc. Reticle set modification to produce multi-core dies
US8631256B2 (en) * 2010-12-22 2014-01-14 Via Technologies, Inc. Distributed management of a shared power source to a multi-core microprocessor
US8782451B2 (en) 2010-12-22 2014-07-15 Via Technologies, Inc. Power state synchronization in a multi-core processor
US8972707B2 (en) 2010-12-22 2015-03-03 Via Technologies, Inc. Multi-core processor with core selectively disabled by kill instruction of system software and resettable only via external pin
US9460038B2 (en) 2010-12-22 2016-10-04 Via Technologies, Inc. Multi-core microprocessor internal bypass bus
US8930676B2 (en) 2010-12-22 2015-01-06 Via Technologies, Inc. Master core discovering enabled cores in microprocessor comprising plural multi-core dies
US8635476B2 (en) 2010-12-22 2014-01-21 Via Technologies, Inc. Decentralized power management distributed among multiple processor cores
CN102609075A (en) * 2012-02-21 2012-07-25 李�一 Power management circuit of multi-core processor
US9274580B2 (en) * 2012-06-29 2016-03-01 Intel Corporation Voltage regulator supplying power exclusively to a non-core region of a processor having a supply capability threshold
US9081577B2 (en) * 2012-12-28 2015-07-14 Intel Corporation Independent control of processor core retention states
CN103914121B (en) * 2013-01-04 2017-04-19 华为技术有限公司 Multicomputer system and method and device for optimizing power consumption of same
EP2811367A1 (en) 2013-06-04 2014-12-10 Ericsson Modems SA A method for controlling powering of a mobile platform
CN103412637A (en) * 2013-08-12 2013-11-27 浪潮电子信息产业股份有限公司 Energy-saving method of phase number variable CPU VR (Central Processing Unit Voltage Regulation)
US9417675B2 (en) * 2014-05-29 2016-08-16 Silicon Storage Technology, Inc. Power sequencing for embedded flash memory devices
US9645598B2 (en) * 2014-07-14 2017-05-09 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. Controlling distributed power stages responsive to the activity level of functions in an integrated circuit
US9882383B2 (en) * 2014-12-23 2018-01-30 Intel Corporation Smart power delivery network
US10236209B2 (en) 2014-12-24 2019-03-19 Intel Corporation Passive components in vias in a stacked integrated circuit package
WO2016185599A1 (en) 2015-05-21 2016-11-24 株式会社日立製作所 Computer system and computer
US9974176B2 (en) * 2015-07-10 2018-05-15 Cisco Technology, Inc. Mass storage integration over central processing unit interfaces
JP2017084148A (en) * 2015-10-29 2017-05-18 富士通株式会社 Control apparatus, control method, and control program
US11532906B2 (en) * 2018-06-29 2022-12-20 Intel Corporation Hybrid socket for higher thermal design point processor support

Citations (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5410467A (en) 1992-03-19 1995-04-25 Astec International Limited Power converters with improved switching efficiency
EP0978781A2 (en) 1998-08-03 2000-02-09 Lucent Technologies Inc. Power reduction in a multiprocessor digital signal processor
US6335565B1 (en) 1996-12-04 2002-01-01 Hitachi, Ltd. Semiconductor device
US20020087906A1 (en) 2000-12-29 2002-07-04 Mar Clarence Y. CPU power sequence for large multiprocessor systems
US20020144036A1 (en) * 2001-03-30 2002-10-03 Osburn Edward P. Multistage configuration and power setting
US6469895B1 (en) 1995-09-05 2002-10-22 Astec International Limited Integrated circuit mounting structure including a switching power supply
WO2003014902A1 (en) 2001-08-10 2003-02-20 Shakti Systems, Inc. Distributed power supply architecture
US20030065966A1 (en) 1999-09-29 2003-04-03 Poisner David I. Over-clocking detection system utilizing a reference signal and thereafter preventing over-clocking by reducing clock rate
WO2003027820A2 (en) 2001-09-28 2003-04-03 Intel Corporation Method and apparatus for adjusting the voltage and frequency to minimize power dissipation in a multiprocessor system
US20030081389A1 (en) * 2001-10-26 2003-05-01 Raj Nair Silicon interposer-based hybrid voltage regulator system for VLSI devices
WO2003073250A2 (en) 2002-02-25 2003-09-04 Molex Incorporated Electrical connector equipped with filter
US6674646B1 (en) * 2001-10-05 2004-01-06 Skyworks Solutions, Inc. Voltage regulation for semiconductor dies and related structure
US20040142603A1 (en) 2002-07-24 2004-07-22 Walker J. Thomas Attachable modular electronic systems
US6791846B2 (en) 2000-10-30 2004-09-14 Sun Microsystems, Inc. Power distribution system with a dedicated power structure and a high performance voltage regulator
GB2399684A (en) 2003-03-18 2004-09-22 Shuttle Inc Layout for integrated motherboard
US6861739B1 (en) * 2001-05-15 2005-03-01 Lsi Logic Corporation Minimum metal consumption power distribution network on a bonded die
US20050127758A1 (en) 2003-12-12 2005-06-16 Atkinson Lee W. System and method for power management when an operating voltage is between two thresholds
EP1555595A2 (en) 2004-01-13 2005-07-20 Lg Electronics Inc. Apparatus for controlling power of processor having a plurality of cores and control method of the same
US20050207133A1 (en) 2004-03-11 2005-09-22 Mark Pavier Embedded power management control circuit
US6952748B1 (en) * 2001-01-02 2005-10-04 Advanced Micro Devices, Inc. Voltage request arbiter
US20060041763A1 (en) 2004-08-19 2006-02-23 Shekhar Borkar Power delivery system
US20060065962A1 (en) 2004-09-29 2006-03-30 Intel Corporation Control circuitry in stacked silicon
US20060071650A1 (en) 2004-09-30 2006-04-06 Narendra Siva G CPU power delivery system
US20060099734A1 (en) 2004-09-30 2006-05-11 Narendra Siva G CPU power delivery system
EP1736851A2 (en) 2005-06-10 2006-12-27 LG Electronics Inc. Controlling power supply in a multi-core processor
US7274930B2 (en) 2003-02-24 2007-09-25 Autocell Laboratories, Inc. Distance determination program for use by devices in a wireless network

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000122753A (en) * 1998-10-15 2000-04-28 Nec Eng Ltd Vrm mispackaging prevention circuit
JP2001185676A (en) * 1999-12-24 2001-07-06 Sharp Corp Semiconductor device
US6429630B2 (en) * 2000-01-27 2002-08-06 Primarion, Inc. Apparatus for providing regulated power to an integrated circuit
JP2001274265A (en) * 2000-03-28 2001-10-05 Mitsubishi Electric Corp Semiconductor device
JP4963144B2 (en) * 2000-06-22 2012-06-27 ルネサスエレクトロニクス株式会社 Semiconductor integrated circuit
AU2000274531A1 (en) * 2000-10-03 2002-04-15 Kouichi Ashiga Semiconductor device
JP2003224193A (en) * 2002-01-30 2003-08-08 Matsushita Electric Ind Co Ltd Semiconductor device and its driving method
JP4231708B2 (en) * 2003-02-25 2009-03-04 株式会社リコー Regulator built-in semiconductor device
EP1636685A2 (en) * 2003-06-10 2006-03-22 Koninklijke Philips Electronics N.V. Embedded computing system with reconfigurable power supply and/or clock frequency domains
US7079148B2 (en) * 2003-07-23 2006-07-18 Hewlett-Packard Development Company, L.P. Non-volatile memory parallel processor

Patent Citations (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5410467A (en) 1992-03-19 1995-04-25 Astec International Limited Power converters with improved switching efficiency
US6469895B1 (en) 1995-09-05 2002-10-22 Astec International Limited Integrated circuit mounting structure including a switching power supply
US6335565B1 (en) 1996-12-04 2002-01-01 Hitachi, Ltd. Semiconductor device
EP0978781A2 (en) 1998-08-03 2000-02-09 Lucent Technologies Inc. Power reduction in a multiprocessor digital signal processor
US20030065966A1 (en) 1999-09-29 2003-04-03 Poisner David I. Over-clocking detection system utilizing a reference signal and thereafter preventing over-clocking by reducing clock rate
US6791846B2 (en) 2000-10-30 2004-09-14 Sun Microsystems, Inc. Power distribution system with a dedicated power structure and a high performance voltage regulator
US20020087906A1 (en) 2000-12-29 2002-07-04 Mar Clarence Y. CPU power sequence for large multiprocessor systems
US6952748B1 (en) * 2001-01-02 2005-10-04 Advanced Micro Devices, Inc. Voltage request arbiter
US20020144036A1 (en) * 2001-03-30 2002-10-03 Osburn Edward P. Multistage configuration and power setting
US6861739B1 (en) * 2001-05-15 2005-03-01 Lsi Logic Corporation Minimum metal consumption power distribution network on a bonded die
WO2003014902A1 (en) 2001-08-10 2003-02-20 Shakti Systems, Inc. Distributed power supply architecture
WO2003027820A2 (en) 2001-09-28 2003-04-03 Intel Corporation Method and apparatus for adjusting the voltage and frequency to minimize power dissipation in a multiprocessor system
US6674646B1 (en) * 2001-10-05 2004-01-06 Skyworks Solutions, Inc. Voltage regulation for semiconductor dies and related structure
US20030081389A1 (en) * 2001-10-26 2003-05-01 Raj Nair Silicon interposer-based hybrid voltage regulator system for VLSI devices
WO2003073250A2 (en) 2002-02-25 2003-09-04 Molex Incorporated Electrical connector equipped with filter
US20040142603A1 (en) 2002-07-24 2004-07-22 Walker J. Thomas Attachable modular electronic systems
US7274930B2 (en) 2003-02-24 2007-09-25 Autocell Laboratories, Inc. Distance determination program for use by devices in a wireless network
GB2399684A (en) 2003-03-18 2004-09-22 Shuttle Inc Layout for integrated motherboard
US20050127758A1 (en) 2003-12-12 2005-06-16 Atkinson Lee W. System and method for power management when an operating voltage is between two thresholds
EP1555595A2 (en) 2004-01-13 2005-07-20 Lg Electronics Inc. Apparatus for controlling power of processor having a plurality of cores and control method of the same
US20050207133A1 (en) 2004-03-11 2005-09-22 Mark Pavier Embedded power management control circuit
US20060041763A1 (en) 2004-08-19 2006-02-23 Shekhar Borkar Power delivery system
US20060065962A1 (en) 2004-09-29 2006-03-30 Intel Corporation Control circuitry in stacked silicon
US20060071650A1 (en) 2004-09-30 2006-04-06 Narendra Siva G CPU power delivery system
US20060099734A1 (en) 2004-09-30 2006-05-11 Narendra Siva G CPU power delivery system
EP1736851A2 (en) 2005-06-10 2006-12-27 LG Electronics Inc. Controlling power supply in a multi-core processor

Non-Patent Citations (7)

* Cited by examiner, † Cited by third party
Title
A Mason et al. "A Low-Power Wireless Microinstrumentation System for Environmental Monitoring", IEEE IX International Conference on Solid State Sensors and Actuators, Jun. 25-29, 1995, pp. 107-110.
International Preliminary Report on Patentability for related PCT matter dated Apr. 10, 2008.
International Search Report for related PCT matter dated May 7, 2007.
J. W. Tschanz et al., "Adaptive Body Bias for Reducing Impacts of Die-to-Die and Within-Die Parameter Variations on Microprocessor Frequency and Leakage", IEEE Journal of Solid State Circuits, vol. 37, No. 11 Nov. 2002.
PCT Search Report PCT/US2005/035475, mailed Feb. 8, 2006, for corresponding foreign matter P20117PCT.
Rhee, et al: Many-to-Many Core-Switch Mapping in 2-D Mesh NoC Architectures; Korea; 6 pages.
Simpson: Linear and Switching Voltage Regulator Fundamentals; National Semiconductor; 29 pages.

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8856568B2 (en) 2006-11-01 2014-10-07 Intel Corporation Independent power control of processing cores
US9021279B2 (en) 2006-11-01 2015-04-28 Intel Corporation Independent power control of processing cores
US8996899B2 (en) 2006-11-01 2015-03-31 Intel Corporation Independent power control of processing cores
US20080136397A1 (en) * 2006-12-08 2008-06-12 Gunther Stephen H Operating integrated circuit logic blocks at independent voltages with single voltage supply
US8397090B2 (en) * 2006-12-08 2013-03-12 Intel Corporation Operating integrated circuit logic blocks at independent voltages with single voltage supply
US20100229010A1 (en) * 2009-03-09 2010-09-09 Yasuyuki Nasu Computer system, method for controlling the same, and program
US8522060B2 (en) * 2009-03-09 2013-08-27 Nec Corporation Computer system, method for controlling the same, and program
US8064197B2 (en) * 2009-05-22 2011-11-22 Advanced Micro Devices, Inc. Heat management using power management information
US8665592B2 (en) 2009-05-22 2014-03-04 Advanced Micro Devices, Inc. Heat management using power management information
US20100296238A1 (en) * 2009-05-22 2010-11-25 Mowry Anthony C Heat management using power management information
US20140068289A1 (en) * 2012-08-28 2014-03-06 Noah B. Beck Mechanism for reducing interrupt latency and power consumption using heterogeneous cores
US9009508B2 (en) * 2012-08-28 2015-04-14 Advanced Micro Devices, Inc. Mechanism for reducing interrupt latency and power consumption using heterogeneous cores
US11687135B2 (en) 2013-05-31 2023-06-27 Tahoe Research, Ltd. Controlling power delivery to a processor via a bypass
US9848515B1 (en) 2016-05-27 2017-12-19 Advanced Micro Devices, Inc. Multi-compartment computing device with shared cooling device

Also Published As

Publication number Publication date
CN102073371A (en) 2011-05-25
WO2007038529A2 (en) 2007-04-05
KR100974363B1 (en) 2010-08-05
CN101278250A (en) 2008-10-01
CN101278250B (en) 2011-04-13
WO2007038529A3 (en) 2007-06-28
DE112006002506T5 (en) 2008-09-25
KR20080039531A (en) 2008-05-07
CN102073371B (en) 2013-03-27
GB2444013A (en) 2008-05-21
JP2009510617A (en) 2009-03-12
JP2012038347A (en) 2012-02-23
HK1158340A1 (en) 2012-07-13
GB0805204D0 (en) 2008-04-30
US20070070673A1 (en) 2007-03-29
DE112006002506B4 (en) 2012-08-16

Similar Documents

Publication Publication Date Title
US7568115B2 (en) Power delivery and power management of many-core processors
US10192598B2 (en) Memory device comprising programmable command-and-address and/or data interfaces
JP5579811B2 (en) CPU power distribution system
EP1516339B1 (en) Memory buffer arrangement
US7671456B2 (en) Power management integrated circuit
US8907462B2 (en) Integrated circuit package
US20080040562A1 (en) Systems and methods for providing distributed autonomous power management in a memory system
US20110082971A1 (en) Information handling system memory module optimization
US10698464B2 (en) Multi-element memory device with power control for individual elements
US20120110363A1 (en) Method and system for power-efficient and non-signal-degrading voltage regulation in memory subsystems
US7512731B2 (en) Computer system and memory bridge for processor socket thereof
KR20230096845A (en) Fast self-refresh exit power state
US20210232504A1 (en) Avoiding processor stall when accessing coherent memory device in low power
US7032060B2 (en) Control chip supporting plurality of buses and control chip set thereof
CN220368846U (en) Printed circuit board and processor board card
TW202318181A (en) Routing of memory transactions
US20140089687A1 (en) Power management integrated circuit
Subramanyam et al. Intel 945GMS Express Chipset for Small Form Factor Platform Based on Intel Centrino Duo Mobile Technology.
KR20180099223A (en) Memory module capable of reducing power consumption, operation method thereof and semiconductor system including the same

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTEL CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BORKAR, SHEKHAR;KARNIK, TANAY;GARVER, SHU-LING;REEL/FRAME:017062/0243;SIGNING DATES FROM 20050920 TO 20050925

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

SULP Surcharge for late payment
FPAY Fee payment

Year of fee payment: 8

FEPP Fee payment procedure

Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FEPP Fee payment procedure

Free format text: 11.5 YR SURCHARGE- LATE PMT W/IN 6 MO, LARGE ENTITY (ORIGINAL EVENT CODE: M1556); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 12