US7633144B1 - Semiconductor package - Google Patents

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Publication number
US7633144B1
US7633144B1 US11/440,662 US44066206A US7633144B1 US 7633144 B1 US7633144 B1 US 7633144B1 US 44066206 A US44066206 A US 44066206A US 7633144 B1 US7633144 B1 US 7633144B1
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semiconductor die
semiconductor
semiconductor package
substrate
die
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US11/440,662
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Youn Sang Kim
Bong Chan Kim
Yoon Joo Kim
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Amkor Technology Singapore Holding Pte Ltd
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Amkor Technology Inc
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Priority to US11/440,662 priority Critical patent/US7633144B1/en
Assigned to AMKOR TECHNOLOGY, INC. reassignment AMKOR TECHNOLOGY, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KIM, BONG CHAN, KIM, YOON JOO, KIM, YOUN SANG
Assigned to BANK OF AMERICA, N.A. reassignment BANK OF AMERICA, N.A. PATENT SECURITY AGREEMENT Assignors: AMKOR TECHNOLOGY, INC.
Priority to US12/589,868 priority patent/US8129849B1/en
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Publication of US7633144B1 publication Critical patent/US7633144B1/en
Assigned to BANK OF AMERICA, N.A. reassignment BANK OF AMERICA, N.A. PATENT SECURITY AGREEMENT Assignors: AMKOR TECHNOLOGY, INC.
Assigned to BANK OF AMERICA, N.A., AS AGENT reassignment BANK OF AMERICA, N.A., AS AGENT SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: AMKOR TECHNOLOGY, INC.
Assigned to AMKOR TECHNOLOGY SINGAPORE HOLDING PTE.LTD. reassignment AMKOR TECHNOLOGY SINGAPORE HOLDING PTE.LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: AMKOR TECHNOLOGY, INC.
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Definitions

  • the present invention relates to semiconductor package and method of making the same.
  • a lead frame is replaced by a printed circuit board, so as to lower the inductance and greatly improve electric capability, heat discharging capability and surface mounting capability of the semiconductor package.
  • a semiconductor die is mounted on a printed circuit board by using an adhesive, die pads are in turn wire-bonded to bond fingers of the printed circuit board by conductive wires, and then the semiconductor die is encapsulated by using an Epoxy Molding Compound (EMC).
  • EMC Epoxy Molding Compound
  • the encapsulation of the semiconductor die is performed by a transfer molding in which melted EMC is injected into a mold.
  • a transfer molding in which melted EMC is injected into a mold.
  • it is typical to secure a distance of at least 10 mil between a surface of the semiconductor die and a surface of molded semiconductor package in order to avoid occurrence of voids in the semiconductor package as well as to prevent incomplete molding of the semiconductor package.
  • such a transfer molding using the EMC may cause big limit in realization of ultra-small or ultra-slim semiconductor packages, which is a recently popular trend.
  • the EMC is injected into the semiconductor package from one side of the semiconductor die, which may cause a wire sweeping phenomenon in which conductive wires are gathered on one side of the semiconductor package.
  • the wire sweeping may separate the bonded conductive wires from the bond pads of the semiconductor die or the bond fingers of the printed circuit board, thereby causing disconnection of the conductive wires and electrical interconnection of the conductive wires, which may induce the electrical short-circuit.
  • the completed semiconductor package only comes in a black color. Therefore, the semiconductor package fails to satisfy a consumer expectation of various colored semiconductor packages, thereby reducing a consumer's purchasing desire.
  • a substrate and a semiconductor die are covered with and encapsulated by vertically pressing thermosetting resin having fluidity in a predetermined temperature range and denaturalizing itself in gel.
  • thermosetting resin having fluidity in a predetermined temperature range and denaturalizing itself in gel.
  • an upper portion of a semiconductor die and a part of conductive wires are covered and encapsulated with thermosetting resin in order to form an empty space at the sides of the semiconductor package.
  • supporting portions having various colors, e.g., other than black may be attached to the semiconductor package.
  • at least one semiconductor die may be vertically stacked.
  • FIG. 1 is a sectional view showing a semiconductor package according to an embodiment of the present invention
  • FIGS. 2A through 2F are sectional views illustrating a method of making the semiconductor package according to the embodiment of the present invention shown in FIG. 1 ;
  • FIG. 3 is a sectional view showing a semiconductor package according to another embodiment of the present invention.
  • FIG. 4 is a sectional view showing a semiconductor package according to still another embodiment of the present invention.
  • FIG. 5 is a sectional view showing a semiconductor package according to still another embodiment of the present invention.
  • FIGS. 6A through 6C are sectional views illustrating a gang process of the semiconductor package according to the embodiment of the present invention in FIG. 1 ;
  • FIGS. 7 , 8 , 9 and 10 are sectional views showing semiconductor packages according to other embodiments of the present invention.
  • FIG. 1 there is shown a sectional view of a semiconductor package according to an embodiment of the present invention.
  • the semiconductor package 100 includes a substrate 110 substantially having a plate shape, a semiconductor die 120 adhered to an upper surface of the substrate 110 , a plurality of conductive wires 130 electrically connecting the semiconductor die 120 to the substrate 110 , an encapsulant 140 covering the semiconductor die 120 and the conductive wires 130 which are located on the upper surface of the substrate 110 , for protecting the semiconductor die 120 and the conductive wires 130 from exterior environment, and a plurality of solder balls 150 welded to a lower surface of the substrate 110 and used for mounting the semiconductor package to an exterior device.
  • the semiconductor package is completed through the gang process, and then is singulated into the individual semiconductor package.
  • a semiconductor package and a method of making the same with respect to a unit of the semiconductor package will be described. Further, it will be illustrated an example of the semiconductor package in which a printed circuit board is used as the substrate 110 , but it will be noted that the substrate is not limited to only the printed circuit board and that a tape substrate and a lead frame may be used as a substrate. Therefore, the substrate 110 is not limited to these members.
  • the semiconductor package will be described as an example in which the semiconductor die 120 is electrically connected to the substrate 110 in a wire bonding manner, but it is understood that it is possible to use various bonding manners including a stud bump bonding manner and a flip chip manner. Therefore, the bonding manner is not limited.
  • the substrate 110 includes a thermosetting resin layer 111 which is a substantially flat plate, a plurality of upper conductive patterns 112 formed on an upper surface of the resin layer 111 , a plurality of lower conductive patterns 113 formed on a lower surface of the resin layer 111 , a plurality of conductive vias 115 electrically connecting the upper conductive patterns 112 to the lower conductive patterns 113 , an upper solder mask 117 covering a portion of the upper surface of the resin layer 111 and the upper conductive patterns 112 , and a lower solder mask 118 covering a portion of the upper surface of the resin layer 111 and the lower conductive patterns 113 .
  • the upper and lower conductive patterns 112 and 113 are suitably made of copper material, but the material of the upper and lower conductive patterns is not limited to the copper. Portions of the upper conductive patterns 112 which are connected to the conductive wires 130 are referred to as bond fingers, while portions of the lower conductive patterns 113 which are connected to the solder balls 150 are referred to as ball lands. Further, plated layers are formed of nickel and aurum (gold) on the bond fingers and the ball lands, respectively. This is to rigidly connect or fusion-weld the conductive wires 130 and the solder balls 150 to the bond fingers and the ball lands, respectively.
  • the ball lands and the bond fingers need not be covered with the solder masks 117 and 118 .
  • the upper and lower conductive patterns 112 and 113 are formed in a photolithographic manner, but the process of forming the upper and lower conductive patterns 112 and 113 is not limited.
  • the conductive vias 115 are formed in a form of hole which penetrates the upper and lower surfaces of the resin layer 111 in order to electrically connect the upper conductive pattern 112 and the lower conductive pattern 113 to each other.
  • the conductive vias 115 respectively have an inner surface coated with copper.
  • the plurality of conductive vias 115 may be formed, but the number of the conductive vias 115 is not limited to two vias formed at both sides of the substrate 110 as shown in FIG. 2 .
  • the upper solder mask 117 a portion of the upper solder mask 117 covering the bond fingers has a height substantially identical to that of another portion which covers the conductive pattern.
  • the portion covering the lower conductive pattern 113 has a thickness substantially identical to that.
  • the upper and lower solder masks 117 and 118 may be formed of epoxy resin, acryl resin or equivalent material thereof. However, the material and forming method of the solder masks 117 and 118 are not limited.
  • the adhesive 121 may generally be epoxy resin, adhesive tape, adhesive film, or the equivalent material thereof, but is not limited to these materials. As shown in FIG. 1 , the adhesive layer 121 has a sectional shape which is gradually narrower toward an upper portion thereof, but the sectional shape of the adhesive layer 121 is not limited.
  • the semiconductor die 120 is adhered to the surface of the upper solder mask 117 which is substantially horizontal surface because the upper solder mask 117 has an even thickness or flatness throughout the entire region thereof regardless of the existence of the upper conductive pattern 112 . Since the adhesive 121 attaches the lower surface of the semiconductor die 120 to the upper surface of the upper solder mask 117 having a high flatness, the semiconductor die 120 can be rigidly adhered to the upper solder mask 117 .
  • the semiconductor die 120 is a substantially rectangular hexahedron with upper and lower flat surfaces.
  • the shape of the semiconductor die 120 is not limited.
  • Die pads 123 are formed on a portion of the upper surface of the semiconductor die 120 in order to electrically connect the semiconductor die 120 to the outside. The die pads 123 are formed such that an upper surface thereof is located at a level identical with, or at a level lower than, the upper surface of the semiconductor die 120 .
  • the conductive wires 130 electrically connect the semiconductor die 120 to the substrate 110 . More particularly, the conductive wires 130 electrically connect the die pads 123 of the semiconductor die 120 to the bond fingers of the substrate 110 . At this time, the conductive wires 130 are bonded to the die pads 123 in a stitch bonding manner and attached to the bond fingers in a ball bonding manner, respectively.
  • one end of a conductive wire 130 is formed with a ball having a predetermined size by electric discharge, which is then fusion-welded to a surface of the bond finger, while the other end of the conductive wire 130 is extended and bonded to the die pad 123 without formation of a ball by stitch-boding using through application of ultrasonic waves and heat. Therefore, an angle between the conductive wire 130 and the surface of the bond finger is larger than an angle between the conductive wire 130 and the die pad 123 . Since the conductive wires 130 are rubbed on and attached to the die pad 123 without balls, the conductive wires 130 must reach the surface of the die pad 123 .
  • the conductive wire 130 may be a gold wire, an aluminum wire, and the equivalent materials thereof, but is not limited to these materials.
  • the encapsulant 140 includes an adhering portion 141 made of thermosetting resin having fluidity in a predetermined temperature range, and a supporting portion 145 attached to an upper surface of the adhering portion 141 so as to support the adhering portion 141 .
  • the encapsulant 140 encloses the semiconductor die 120 and the conductive wires 130 on the substrate 110 , thereby protecting them from the exterior environment.
  • the encapsulant 140 is formed of material having fluidity in a pressing manner, instead of transfer molding manner using the epoxy molding compound.
  • the encapsulant 140 causes the semiconductor package 100 to have a reduced height, while preventing the conductive wires 130 from being cut or subjected to electric short due to the wire sweeping.
  • the adhering portion 141 is formed of thermosetting resin having fluidity in a predetermined temperature range and then is cured when the adhering portion is heated.
  • the adhering portion 141 is denaturalized in a gel state at a temperature of 50° C. to 200° C. and cured in a range of the temperature of 50° C. to 200° C., for example over a temperature of about 160° C.
  • the temperature of the adhering portion 141 in the gel state and the curing temperature of the adhering portion 141 are examples, but are not limited to the above-mentioned temperature ranges.
  • the adhering portion 141 has a thickness of about 2 mil to 3 mil after the adhering portion 141 is pressed, but the thickness of the adhering portion 141 is not limited.
  • the adhering portion 141 covers the entire upper surface of the substrate 110 , the semiconductor die 120 , and the conductive wires 130 .
  • the adhering portion 141 is heated to the temperature of 50° C. to 200° C. and denaturalized in the gel having the fluidity, which is in turn pressed downward to cover the upper surface of the substrate 110 , the semiconductor die 120 , and the conductive wires 130 . Finally, the adhering portion 141 is heated for a half hour to six hours, resulting in the cured adhering portion 141 .
  • the supporting portion 145 is formed to cover an upper surface of the adhering portion 141 .
  • the supporting portion 145 is made of insulation substance such as polyimide and epoxy, or the equivalent materials thereof, but the material of the supporting portion 145 is not limited to these materials. Further, the supporting portion 145 has enough hardness to maintain flatness entirely.
  • the supporting portion 145 is adhered to the upper surface of the adhering portion by an adhesive. That is, the supporting portion 145 is adhered in advance to the adhering portion 141 by heat and/or pressure. Therefore, the supporting portion 145 and the adhering portion 141 are adhered to each other before the encapsulant 140 is pressed.
  • the supporting portion 145 has a substantially identical area with that of the surface of the adhering portion 141 .
  • the area of the supporting portion 145 is not limited.
  • the supporting portion 145 may be formed with a thickness of about 0.5 mil to 1 mil, but the thickness of the supporting portion 145 is not limited.
  • the supporting portion 145 is made of material having the high heat conductivity so as to smoothly discharge heat.
  • the supporting portion 145 may be dyed with various colors it is possible to make the semiconductor packages having various colors, e.g., other than black, according to consumer's favorite, thereby increasing consumer's desire for purchasing the semiconductor packages.
  • the encapsulant 140 is formed with a thickness of 2.5 mil to 4 mil on the upper surface of the semiconductor die 120 in spite of attaching the supporting portion 145 to the adhering portion 141 .
  • the encapsulant when the encapsulant is formed in the conventional transfer molding manner, the encapsulant generally has a thickness of about 10 mil from the upper surface of the semiconductor die to the upper surface of the semiconductor package.
  • the encapsulant 140 according to the present invention has the thickness reduced by up to about 6 mil to 7 mil, as compared with the above-mentioned encapsulant formed using the transfer molding method, so that the encapsulant 140 is advantageous for making the extremely thin semiconductor package.
  • solder balls 150 are fusion-welded to the ball lands exposed downward through the lower solder mask 118 which is formed on the lower surface of the substrate 110 .
  • the solder balls 150 are fusion-welded to the ball lands in such a manner that the substrate passes through a furnace after flux is injected into solder and then an amount of solder necessary for forming each solder ball is dropped on each ball land. While the substrate passes through the furnace, the flux is volatilized and only the solder balls 150 are fusion-welded to the lower conductive pattern 113 .
  • These solder balls 150 are surface-mounted on the exterior device by using a reflow process, so as to enable the semiconductor package 100 to transmit and receive electric signals to/from the exterior device.
  • FIGS. 2A through 2F there are shown sectional views illustrating the method of making the semiconductor package according to an embodiment of the present invention.
  • the method of making the semiconductor package 100 includes an operation of forming the substrate 110 , an operation of forming solder masks 117 and 118 on the upper and lower surfaces of the substrate 110 , an operation of attaching the semiconductor die 120 to the substrate 110 by an adhesive 121 , an operation of bonding wires 130 to the die pads 123 of the semiconductor die 120 and the bond fingers of the substrate 110 in order to electrically connect the semiconductor die 120 to the substrate 110 , an operation of pressing the encapsulant 140 , and an operation of fusion-welding the solder balls 150 to the ball land of the lower surface of the substrate 110 .
  • the operation of pressing the encapsulant 140 includes an operation of attaching the supporting portion 145 to the adhering portion 141 , and a first heat operation of heating the adhering portion 141 having fluidity. Furthermore, in the operation of pressing the encapsulant 140 , it may be performed a second heating operation of heating the adhering portion 140 up to a predetermined temperature in order to cure the adhering portion 140 after the first heating operation.
  • a thermosetting resin layer 111 having a substantially plate shape has a plurality of upper conductive patterns 112 formed on an upper surface thereof, and a plurality of lower conductive patterns 113 formed on a lower surface thereof.
  • the conductive patterns 112 and 113 are formed of copper having the high conductivity using a photolithography method.
  • the material or forming method of the conductive patterns 112 and 113 are not limited.
  • a plurality of conductive vias 115 are formed in order to electrically connect the upper and lower conductive patterns 112 and 113 to each other.
  • solder mask 117 and 118 there is shown a sectional view illustrating the operation of forming solder mask 117 and 118 .
  • the solder masks 117 and 118 are formed on the conductive patterns 112 and 113 of the substrate 110 in such a manner that regions corresponding to bond fingers and ball lands of the conductive patterns 112 and 113 are exposed. More particularly, the upper solder mask 117 is formed on the upper conductive pattern 112 , while the lower solder mask 118 is formed on the lower conductive pattern 118 .
  • the upper solder mask 117 may cover the bond fingers in such a manner that a portion of the bold finger to which the conductive wire 130 is bonded is exposed to exterior, or in such a manner that the entire upper conductive patterns 112 corresponding to the bold fingers are exposed. Furthermore, the upper solder mask 117 is formed to have even thickness throughout the substrate 110 .
  • the operation of forming the solder masks 117 and 118 is carried out in order to coat and protect the conductive patterns, except for a portion of the conductive patterns that must be electrically connected to the exterior through the conductive wires 130 or the solder balls 150 , with insulation material.
  • the solder masks 117 and 118 may be formed of epoxy, acryl, or the equivalent materials by using the photolithographic method. However, the material or forming method of the solder masks 117 and 118 is not limited.
  • FIG. 2C next, there is shown a sectional view illustrating the operation of attaching the semiconductor die 120 to the substrate 110 .
  • the semiconductor die 120 is attached to a center portion of the upper surface of the substrate 110 .
  • FIG. 2D there is shown a sectional view illustrating the operation of bonding wires.
  • the die pads 123 of the semiconductor die 120 are electrically connected to the bond fingers of the substrate 110 by the conductive wires 130 .
  • the conductive wires extend at a predetermined distance from a capillary (not shown) and then have ball formed at one end of the conductive wires by an electric discharge to have a predetermined size.
  • the balls of the conductive wires are in close contact with the bond fingers of the substrate 110 respectively.
  • the operation of pressing the encapsulant 140 is performed after the operation of attaching the supporting portion 145 to the adhering portion 141 and the first heating operation of heating the adhering portion 141 in the flowing state.
  • the operation of attaching the supporting portion 145 is a process in which the adhering portion 141 is formed to have the substantially flat plat shape and then the supporting portion 145 is attached to the upper surface of the adhering portion 141 by the adhesive.
  • the first heating operation is a process in which the adhering portion 141 is heated and then is denaturalized in the gel having the fluidity. The first heating operation is carried out at a temperature of 50° C. to 200° C., so that the adhering portion 141 is substantially changed into a liquid state having enough fluidity.
  • the encapsulant 140 including the adhering portion 141 is vertically pressed in the gel state on the substrate 110 , the semiconductor die 120 and the conductive wires 130 , thereby having no effect on the conductive wires 130 and preventing the wire sweeping phenomenon.
  • FIG. 2E there is shown a sectional view illustrating the operation of pressing the encapsulant 140 .
  • the encapsulant 140 is pressed downward from the upper portion of the semiconductor die 120 , so as to cover the entire upper surface of the substrate 110 .
  • the adhering portion 141 is formed to cover the substrate 110 , the semiconductor die 120 and the conductive wires 130 , but it is necessary to adjust the thickness of the adhering portion 141 before the adhering portion 141 is pressed, in order to form the adhering portion 141 having a minimized thickness.
  • the second heating operation is performed in which the pressed adhering portion 141 is heated to a predetermined temperature so as to cure the adhering portion 141 , after the operation of pressing the encapsulant 140 .
  • the second heating operation is carried out at a temperature of 50° C. to 200° C. for a half hour to six hours, so that the adhering portion in the gel state is cured into a rigid solid state.
  • FIG. 2F there is shown a sectional view illustrating the operation of fusion-welding the solder balls.
  • the ball lands of the lower conductive patterns 113 to be a portion at which the solder balls 150 are formed is not covered with the lower solder mask 118 and exposed to the exterior.
  • flux is injected into the ball lands and then an amount of solder material, enough to form the solder balls, is dropped on the flux.
  • the fusion-welding of the solder balls is performed in a furnace. The flux is volatilized and discharged out of the furnace. As a result, the solder balls 150 are fusion-welded and electrically connected to the lower conductive pattern 113 .
  • the semiconductor package 100 according to the present invention has the encapsulant 140 remarkably reduced in thickness, as compared with the semiconductor package made in the transfer molding manner. As a result, the semiconductor package becomes thin and can be widely applied to electric/electron devices requiring extremely small-sized and extremely thin semiconductor package. Further, in the semiconductor package 100 according to the present invention, the encapsulant 140 in gel is vertically pressed downward so as not to apply force to the conductive wires 130 , thereby preventing open circuit or short circuit from being caused due to the wire sweeping phenomenon.
  • FIG. 3 there is shown a sectional view of the semiconductor package according to another embodiment of the present invention.
  • the semiconductor package 200 according to another embodiment of the present invention has a structure similar to the semiconductor package 100 according to the embodiment of FIG. 1 .
  • the description of the same element as that of the semiconductor package 100 will be omitted.
  • the method of making the semiconductor package 100 according to the embodiment shown in FIG. 3 is identical with the method of making the semiconductor package 100 according to the embodiment shown in FIG. 1 . Therefore, the description of the method of making the semiconductor package will be omitted.
  • the semiconductor package 200 includes a substrate 210 having a substantially flat plate shape, a semiconductor die 220 adhered to an upper surface of the substrate 210 , a plurality of conductive wires 230 electrically connecting the semiconductor die 220 to the substrate 210 , an encapsulant 240 covering the semiconductor die 220 and the conductive wires 230 disposed on the upper surface of the substrate 210 , so as to protect them from exterior environment, and a plurality of solder balls 250 fusion-welded to a lower surface of the substrate 210 and mounted on an exterior device.
  • the substrate 210 has a plurality of conductive patterns 212 and 213 which are formed upper and lower surfaces of a plate shaped thermosetting resin layer 211 , respectively.
  • the substrate 210 also has conductive vias 215 to electrically connect the upper conductive patterns 212 formed on the upper surface of the substrate 210 to the lower conductive patterns 213 formed on the lower surface of the substrate 210 .
  • the substrate 210 includes an upper solder mask 217 covering a portion of an upper surface of the upper conductive patterns 212 and the resin layer 211 , and a lower solder mask 218 covering a portion of a lower surface of the lower conductive patterns 213 and the resin layer 211 .
  • the semiconductor die 220 is attached to a center portion of the upper surface of the substrate 210 by an adhesive 221 , and has die pads 223 formed on the upper surface thereof to which the conductive wires 230 are bonded.
  • the conductive wires 230 electrically connect the die pads 223 of semiconductor die 220 to bond fingers of the substrate 210 . At this time, the conductive wires 230 are first bonded to the bond fingers in a ball bonding manner, which in turn is bonded to the die pads 223 in a stitch bonding manner, as described above relating to the afore-mentioned previous embodiment.
  • the encapsulant 240 includes an adhering portion 241 and a supporting portion 245 .
  • the adhering portion 241 is formed of thermosetting resin having fluidity at a predetermined temperature range, while the supporting portion 245 is formed of polyimide, epoxy, or the equivalent materials thereof.
  • the encapsulant 240 is formed to cover the semiconductor die 220 and the conductive wires 230 so that a part of the upper surface of the substrate 210 is exposed to the exterior. In other words, the encapsulant 240 is downward pressed over the upper surface of the semiconductor die 220 and the conductive wires 230 , in order to enclose the upper surface of the semiconductor die 220 and an upper portion of the conductive wires 230 .
  • the space portion 247 may be filled with epoxy molding compound by a separate encapsulation process or remain empty, after the semiconductor package 200 is mounted on a printed circuit board.
  • the space portion 247 is filled with the epoxy molding compound in the transfer molding manner.
  • the adhering portion 241 secures the upper portion of the conductive wires 230 , there is no danger that the wire sweeping occurs although the epoxy molding compound is filled in the space portion.
  • an amount of the adhering portion 241 must be adjusted before the adhering portion 241 is pressed. At this time, the amount of the adhering portion 241 is smaller than that of adhering portion 141 shown in FIG. 1 , thereby obtaining the same structure as that of this embodiment of the present invention. That is, the amount of the adhering portion 241 is adjusted so that a size of the region in which the encapsulant 240 is formed can be adjusted.
  • solder balls 250 are fusion-welded to the ball lands downwardly exposed through the lower solder mask 218 , respectively.
  • the solder balls 250 play the role of electrically connecting a wiring pattern and the semiconductor package 200 to each other.
  • the semiconductor package 200 is coupled to a printed circuit board by a coupling force of the solder balls 250 .
  • the epoxy molding compound filled in the space portion 247 plays the role of securing the semiconductor package 200 . Further, it is possible to reduce the amount of the adhering portion 241 used for the semiconductor package 200 , thereby reducing the manufacturing cost of the semiconductor package 200 .
  • FIG. 4 there is shown a sectional view of a semiconductor package according to still another embodiment of the present invention.
  • the semiconductor package 300 according to still another embodiment of the present invention has a structure similar to the semiconductor package 100 according to the embodiment shown in FIG. 1 , the description of the same elements as those of the semiconductor package 100 will be omitted.
  • the method of making the semiconductor package 300 according to the embodiment shown in FIG. 4 is similar to the method of making the semiconductor package 100 , no views illustrating the method of making the semiconductor package 300 are shown, and only difference from the previous embodiments will be described.
  • the semiconductor package 300 includes a plate shaped substrate 310 , a semiconductor die 320 adhered to an upper surface of the substrate 310 , a plurality of conductive wires 330 for electrically connecting the semiconductor die 320 to the substrate 310 , an encapsulant 340 for covering and protecting the semiconductor die 320 and the conductive wires 330 disposed on the upper surface of the substrate 310 from the exterior environment, and a plurality of solder balls 350 fusion-welded to a lower surface of the substrate 310 and mounted on an exterior device.
  • the substrate 310 has a plurality of conductive patterns 312 and 313 formed on upper and lower surfaces of the plate shaped thermosetting resin layer 311 , and conductive vias 315 formed therein so as to electrically connect the upper conductive patterns 312 to the lower conductive patterns 313 .
  • the substrate 310 includes an upper solder mask 317 covering a portion of an upper surface of the resin layer 311 and the upper conductive patterns 312 , and a lower solder mask 318 covering a portion of a lower surface of the resin layer 311 and the lower conductive patterns 313 .
  • the semiconductor die 320 is attached to a center portion of the upper surface of the substrate 310 by an adhesive 321 , and has die pads 323 formed thereon to which the conductive wires 330 is bonded.
  • the conductive wires 330 electrically connect the die pads 323 of the semiconductor die 320 to bond fingers of the substrate 310 . At this time, the conductive wires 330 is first bonded to the bond fingers in a ball bonding manner, which in turn is bonded to the die pads in a stitch bonding manner.
  • the encapsulant 340 only has an adhering portion, which can be colored.
  • the encapsulant 340 is made of thermosetting resin having fluidity in a predetermined temperature range.
  • a supporting portion is attached to an upper surface of the adhering portion until the encapsulant 340 is pressed and then cured. When the encapsulant 340 is cured, the supporting portion is separated from the upper surface of the adhering portion and only the adhering portion remains.
  • the supporting portion is attached to the adhering portion in order to maintain a shape of the adhering portion having sufficient fluidity and to easily perform the pressing operation. Therefore, even if the supporting portion is removed from the adhering portion after the pressing operation, there is no problem. However, when the supporting portion is separated from the adhering portion right after the pressing operation, it has an effect on the conductive wires 330 , etc. Therefore, it is suitable to remove the supporting portion from the adhering portion after completely curing the adhering portion.
  • the encapsulant 340 may be formed to cover only the semiconductor die 320 and the conductive wires 330 so that a portion of the upper surface of the substrate 310 is exposed to the exterior, like the embodiment shown in FIG. 3 . That is, the encapsulant 340 may be formed such that empty space exists in the encapsulant 340 , though not shown in FIG. 4 .
  • solder balls 350 are fusion-welded to the ball lands downward exposed through the lower solder mask 318 which is formed on the lower surface.
  • the solder balls 350 plays the role of electrically connecting a wire pattern of a printed circuit board to the semiconductor package 300 when the semiconductor package 300 is mounted on a surface of the printed circuit board.
  • the supporting portion is removed from the semiconductor package 300 , thereby reducing the thickness of the semiconductor package 300 .
  • the method of making the semiconductor package 300 according to still another embodiment of the present invention includes the operation of removing the supporting portion in addition to the operations described above relating to FIGS. 2A to 2F . That is, the method of making the semiconductor package 300 according to the embodiment shown in FIG. 4 includes the operation of making the substrate 310 , the operation of attaching the semiconductor die 320 to the substrate 310 by adhesive 321 , the operation of bonding conductive wires 330 to electrically connect the semiconductor die 320 to bond fingers of the substrate 310 , the operation of pressing the encapsulant 340 , and the operation of fusion-welding solder balls 350 to ball lands on a lower surface of the substrate 310 .
  • the operation of pressing the encapsulant 340 includes the operation of attaching the supporting portion to the adhering portion and a first heating operation of heating the adhering portion to flowing state.
  • the method of making the semiconductor package further includes a second heating operation of heating the adhering portion at a predetermined temperature in order to cure the adhering portion and the operation of removing the supporting portion from the adhering portion, after the operation of pressing the encapsulant 340 .
  • FIG. 5 there is shown a sectional view of the semiconductor package according to still another embodiment of the present invention.
  • the semiconductor package 400 according to still another embodiment of the present invention has a structure similar to that of the semiconductor package 100 according to the embodiment shown in FIG. 1 . Therefore, differences from the semiconductor package 100 shown in FIG. 1 will be described.
  • the method of making the semiconductor package 400 according to the embodiment of FIG. 5 is similar to the method of making the semiconductor package 100 according to the embodiment of FIG. 1 . Therefore, differences from the method of making the semiconductor package 400 according to still another embodiment of the present invention will be described.
  • the semiconductor package 400 includes a plate shaped substrate 410 , at least two semiconductor dies 420 _ 1 and 420 _ 2 attached to an upper surface of the substrate 410 , a plurality of conductive wires 430 for electrically connecting the semiconductor dies 420 _ 1 and 420 _ 2 to the substrate 410 , an encapsulant 440 for covering and protecting the conductive wires 430 from the exterior environment, and a plurality of solder balls 450 fusion-welded to a lower surface of the substrate 410 and mounted to an exterior device.
  • the substrate 410 is formed such that a plurality of conductive patterns 412 and 413 are formed on upper and lower surfaces of plate shaped thermosetting resin layer 411 , while having conductive vias 415 formed therein in order to electrically connect the upper conductive patterns 412 formed on the upper surface thereof to the lower conductive patterns 413 formed on the lower surface thereof.
  • the substrate 410 includes an upper solder mask 417 covering a portion of an upper surface of the resin layer 411 and the upper conductive patterns 412 , and a lower solder mask 418 covering a portion of a lower surface of the resin layer 411 and the lower conductive patterns 413 .
  • Portions of the upper conductive patterns 412 corresponding to a bond finger connected to first semiconductor die 420 _ 1 and a bond finger connected to second semiconductor die 420 _ 2 , respectively, are separately formed and insulated.
  • the semiconductor die 420 _ 1 and 420 _ 2 are vertically stacked.
  • the two semiconductor dies 420 _ 1 and 420 _ 2 are stacked as shown in FIG. 5 , but it is understood that at least two semiconductor dies may be stacked.
  • the number of the semiconductor dies is not limited.
  • the first semiconductor die 420 _ 1 is attached to a center portion of the upper surface of the substrate 410 by adhesive 421 , which has die pads 423 _ 1 formed thereon to which the conductive wires 430 are bonded.
  • the second semiconductor die 420 _ 2 is attached to an upper surface of the first semiconductor die 420 _ 1 by adhesive 422 .
  • the second semiconductor die 420 _ 2 has die pads 423 _ 2 formed thereon to which the conductive wires 430 are bonded.
  • the first semiconductor die 420 _ 1 and the second semiconductor die 420 _ 2 may be formed to have an identical size. However, it is understood that the second semiconductor die 420 _ 2 may have a smaller size than that of the first semiconductor die 420 _ 1 , for example, see semiconductor package 400 A of FIG. 7 .
  • the semiconductor dies 420 _ 1 and 420 _ 2 are not limited to the above-mentioned size.
  • the semiconductor dies 420 _ 1 and 420 _ 2 have die pads 423 _ 1 and 423 _ 2 , respectively. Separate conductive wires 430 are connected to bond fingers, respectively.
  • the conductive wires 430 electrically connect the die pad 423 _ 1 of the first semiconductor die 420 _ 1 and the die pad 423 _ 2 of the second semiconductor die 420 _ 2 to the bond fingers of the substrate 410 , respectively. At this time, the conductive wires 430 are first bonded to the bond finger in a ball bonding manner, and then are bonded to the die pad in a stitch bonding manner, respectively, as described above relating to the previous embodiments.
  • the encapsulant 440 includes an adhering portion 441 and a supporting portion 445 .
  • the adhering portion 441 is formed of thermosetting resin having fluidity in a range of predetermined temperature.
  • the supporting portion 445 is made of polyimide, epoxy, and the like.
  • the encapsulant 440 is formed to cover the entire of the upper surface of the substrate 410 as shown in FIG. 5 .
  • the encapsulant 440 may be formed so that a portion of the substrate is exposed to the exterior, like the embodiment shown in FIG. 3 . That is, the structure in the embodiments of FIGS. 1 and 3 are selectively applied to the embodiment of FIG. 5 .
  • Such examples are illustrated by semiconductor packages 400 A, 400 B of FIGS. 7 , 8 , where a space portion 447 is formed in encapsulant 440 , but otherwise where similar elements are labeled with the same reference number.
  • the solder balls 450 are fusion-welded to ball lands downward exposed through a lower solder mask 418 on the lower surface of the substrate 410 .
  • the solder balls 450 play the role of electrically connecting a wire pattern of a printed circuit board to the semiconductor package 400 when the semiconductor package 400 is mounted on a surface of the printed circuit board.
  • the semiconductor package 400 has at least two semiconductor dies mounted therein, so as to exhibit a more excellent performance, while having a more reduced thickness in spite of the semiconductor package in which the semiconductor dies are stacked.
  • the method of the semiconductor package 400 according to still another embodiment of the present invention includes the operation of attaching a second semiconductor die in addition to the method of making the semiconductor package 400 illustrated in FIGS. 2A through 2F . That is, the method of making the semiconductor package 400 according to the embodiment of FIG.
  • the operation of manufacturing a substrate 410 includes the operation of manufacturing a substrate 410 , the operation of forming solder masks 417 and 418 on upper and lower surfaces of the substrate 410 , the operation of attaching a first semiconductor die 420 _ 1 to the substrate 410 by using adhesive 421 , the operation of attaching a second semiconductor die 420 _ 2 to an upper surface of the first semiconductor die 420 _ 1 by using adhesive 422 , the operation of electrically connecting the semiconductor dies 420 _ 1 and 420 _ 2 to bond fingers of the substrate 410 by means of conductive wires 430 , respectively, the operation of pressing an encapsulant 440 , and the operation of fusion-welding solder balls 450 to ball lands on a lower surface of the substrate 410 .
  • the operation of pressing the encapsulant 440 is performed after the operation of attaching a supporting portion 445 to an adhering portion 441 , and a first heating operation of heating the adhering portion 441 in flowing state.
  • the method of making the semiconductor package further includes a second heating operation of heating the pressed adhering portion 441 to a predetermined temperature so as to cure the adhering portion 441 , after the operation of pressing the encapsulant 440 .
  • FIGS. 6A through 6C there is shown a sectional view illustrating a gang process for the semiconductor package according to the embodiment of FIG. 1 .
  • the embodiments of FIGS. 3 and 5 can be manufactured by a method similar to the gang process for the semiconductor package according to the embodiment of FIG. 1 .
  • the method of manufacturing a unit is described in detail with reference to FIGS. 2A through 2F , the method of making the semiconductor package based on the gang process will be described in brief, hereinafter.
  • the gang process for the semiconductor package 100 includes the operation of preparing encapsulant 140 , the operation of pressing the encapsulant 140 , the operation of fusion-welding solder balls, and a singulation operation of sawing the semiconductor package in each unit.
  • the operation of preparing the encapsulant 140 includes the operation of bonding conductive wires 130 to the semiconductor die 120 and the substrate 110 in a wire bonding manner after a plurality of semiconductor dies 120 is arranged in line, in a row, or in matrix on a large area of substrate 110 , and the operation of attaching a supporting portion 145 to an adhering portion 141 and heating the adhering portion to have fluidity.
  • the adhering portion 141 is adjusted to have a minimal thickness, while enclosing the entire upper portion of the substrate 110 so that empty space is not formed at both sides of the semiconductor package.
  • FIG. 6B there is shown a sectional view illustrating the operations of pressing the encapsulant 140 and fusion-welding solder balls 150 .
  • the operation of pressing the encapsulant 140 includes the operation of vertically pressing the adhering portion 141 in gel having fluidity, and the operation of heating the adhering portion 141 over a predetermined temperature so as to cure the adhering portion 141 . At this time, in the operation of pressing the encapsulant 140 , there are required for heat over a predetermined temperature and enough pressure to make the thickness of the semiconductor package be minimal.
  • the solder balls 150 are fusion-welded to the lower conductive pattern 113 exposed to the exterior because the lower solder mask 118 is not formed on the lower conductive pattern 113 .
  • FIG. 6C there is shown a sectional view illustrating the singulation operation.
  • the semiconductor package is sawed from the encapsulant 140 to the lower surface of the substrate 110 in each unit, in order to satisfy a standard for unit.
  • the singulation operation is finished, a plurality of units is produced.
  • FIG. 7 there is shown a sectional view of the semiconductor package according to still another embodiment of the present invention.
  • the semiconductor package 400 A according to still another embodiment of the present invention has a structure similar to that of the semiconductor package 400 according to the embodiment shown in FIG. 5 . Therefore, differences from the semiconductor package 400 shown in FIG. 5 will be described.
  • the second semiconductor die 420 _ 2 is of a smaller size than that of the first semiconductor die 420 _ 1 . More particularly, the second semiconductor die 420 _ 2 is attached to an upper surface of the first semiconductor die 420 _ 1 inward of the die pads 423 _ 1 of the first semiconductor die 420 _ 1 by adhesive 422 .
  • the semiconductor package 400 A includes an encapsulant 440 .
  • the encapsulant 440 includes an adhering portion 441 and a supporting portion 445 .
  • the adhering portion 441 is formed of thermosetting resin having fluidity at a predetermined temperature range, while the supporting portion 445 is formed of polyimide, epoxy, or the equivalent materials thereof.
  • the encapsulant 440 is formed to cover at least a part of the semiconductor die 420 _ 2 and the conductive wires 430 attached to the semiconductor die 420 _ 2 so that a part of the upper surface of the substrate 410 and the semiconductor die 420 _ 1 are exposed to the exterior.
  • the encapsulant 440 is downward pressed over the upper surface of the semiconductor die 420 _ 2 and at least a part of the conductive wires 430 attached thereto, in order to enclose the upper surface of the semiconductor die 420 _ 2 and an upper portion of the conductive wires 430 attached thereto. Therefore, a portion of the semiconductor package 400 A is not enclosed by the encapsulant 440 to have empty space portion 447 .
  • the space portion 447 may be filled with epoxy molding compound by a separate encapsulation process or remain empty, after the semiconductor package 400 A is mounted on a printed circuit board.
  • FIG. 8 there is shown a sectional view of the semiconductor package according to still another embodiment of the present invention.
  • the semiconductor package 400 B according to still another embodiment of the present invention has a structure similar to that of the semiconductor package 400 according to the embodiment shown in FIG. 5 . Therefore, differences from the semiconductor package 400 shown in FIG. 5 will be described.
  • the semiconductor package 400 B includes an encapsulant 440 .
  • the encapsulant 440 includes an adhering portion 441 and a supporting portion 445 .
  • the adhering portion 441 is formed of thermosetting resin having fluidity at a predetermined temperature range, while the supporting portion 445 is formed of polyimide, epoxy, or the equivalent materials thereof.
  • the encapsulant 440 is formed to cover the semiconductor die 420 _ 2 and the conductive wires 430 attached to the semiconductor die 420 _ 2 so that a part of the upper surface of the substrate 410 and the semiconductor die 420 _ 1 are exposed to the exterior.
  • the encapsulant 440 is downward pressed over the upper surface of the semiconductor die 420 _ 2 and the conductive wires 430 attached thereto, in order to enclose the upper surface of the semiconductor die 420 _ 2 and an upper portion of the conductive wires 430 attached thereto. Therefore, a portion of the semiconductor package 400 B is not enclosed by the encapsulant 440 to have empty space portion 447 .
  • the space portion 447 may be filled with epoxy molding compound by a separate encapsulation process or remain empty, after the semiconductor package 400 B is mounted on a printed circuit board.
  • FIG. 9 there is shown a sectional view of the semiconductor package according to still another embodiment of the present invention.
  • the semiconductor package 400 C according to still another embodiment of the present invention has a structure similar to that of the semiconductor package 400 A according to the embodiment shown in FIG. 7 . Therefore, differences from the semiconductor package 400 A shown in FIG. 7 will be described.
  • the semiconductor package 400 C includes an encapsulant 440 .
  • the encapsulant 440 includes an adhering portion 441 and a supporting portion 445 .
  • the adhering portion 441 is formed of thermosetting resin having fluidity at a predetermined temperature range, while the supporting portion 445 is formed of polyimide, epoxy, or the equivalent materials thereof.
  • the encapsulant 440 is formed to cover the semiconductor dies 420 _ 1 , 420 _ 2 and the conductive wires 430 attached to the die pads 423 _ 2 , 423 _ 1 so that a part of the upper surface of the substrate 410 is exposed to the exterior.
  • the encapsulant 440 is downward pressed over the entire semiconductor die 420 _ 2 and the upper surface of the semiconductor die 420 _ 1 and the conductive wires 430 , in order to enclose the entire semiconductor die 420 _ 2 , the upper surface of the semiconductor die 420 _ 1 , and an upper portion of the conductive wires 430 . Therefore, a portion of the semiconductor package 400 C is not enclosed by the encapsulant 440 to have empty space portion 447 .
  • the space portion 447 may be filled with epoxy molding compound by a separate encapsulation process or remain empty, after the semiconductor package 400 C is mounted on a printed circuit board. In a case where the space portion 447 is filled with the epoxy molding compound, the space portion 447 is filled with the epoxy molding compound in the transfer molding manner. At this time, since the adhering portion 441 secures the upper portion of the conductive wires 430 , there is no danger that the wire sweeping occurs although the epoxy molding compound is filled in the space portion.
  • FIG. 10 there is shown a sectional view of the semiconductor package according to still another embodiment of the present invention.
  • the semiconductor package 400 D according to still another embodiment of the present invention has a structure similar to that of the semiconductor package 400 B according to the embodiment shown in FIG. 8 . Therefore, differences from the semiconductor package 400 B shown in FIG. 8 will be described.
  • the semiconductor package 400 D includes an encapsulant 440 .
  • the encapsulant 440 includes an adhering portion 441 and a supporting portion 445 .
  • the adhering portion 441 is formed of thermosetting resin having fluidity at a predetermined temperature range, while the supporting portion 445 is formed of polyimide, epoxy, or the equivalent materials thereof.
  • the encapsulant 440 is formed to cover the semiconductor dies 420 _ 1 , 420 _ 2 and the conductive wires 430 attached to the die pads 423 _ 2 , 423 _ 1 so that a part of the upper surface of the substrate 410 is exposed to the exterior.
  • the encapsulant 440 is downward pressed over the entire semiconductor die 420 _ 2 and the upper surface of the semiconductor die 420 _ 1 and the conductive wires 430 , in order to enclose the entire semiconductor die 420 _ 2 , the upper surface of the semiconductor die 420 _ 1 , and an upper portion of the conductive wires 430 . Therefore, a portion of the semiconductor package 400 D is not enclosed by the encapsulant 440 to have empty space portion 447 .
  • the space portion 447 may be filled with epoxy molding compound by a separate encapsulation process or remain empty, after the semiconductor package 400 D is mounted on a printed circuit board. In a case where the space portion 447 is filled with the epoxy molding compound, the space portion 447 is filled with the epoxy molding compound in the transfer molding manner. At this time, since the adhering portion 441 secures the upper portion of the conductive wires 430 , there is no danger that the wire sweeping occurs although the epoxy molding compound is filled in the space portion.

Abstract

Disclosed are a semiconductor package and a method of making the same. In the semiconductor package, a substrate and a semiconductor die are covered with and encapsulated by vertically pressing thermosetting resin having fluidity in a predetermined temperature range and denaturalizing itself in gel. Thus, it is possible to reduce a thickness of the semiconductor package and prevent wire sweeping.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor package and method of making the same.
2. Description of the Related Art
In recent semiconductor packages, a lead frame is replaced by a printed circuit board, so as to lower the inductance and greatly improve electric capability, heat discharging capability and surface mounting capability of the semiconductor package.
In such a semiconductor package, a semiconductor die is mounted on a printed circuit board by using an adhesive, die pads are in turn wire-bonded to bond fingers of the printed circuit board by conductive wires, and then the semiconductor die is encapsulated by using an Epoxy Molding Compound (EMC).
On the other hand, as the weight and size of small sized and portable electric/electronic devices, such as cellular phone, digital video camcorders, digital cameras, lap-top computers, etc., gradually reduces more and more, it is necessary to also reduce the weight and size of semiconductor packages mounted in the electric/electronic devices. This requirement has caused appearance of ultra-small sized semiconductor packages such as chip size package and wafer level chip size package.
The encapsulation of the semiconductor die is performed by a transfer molding in which melted EMC is injected into a mold. In the semiconductor package, it is typical to secure a distance of at least 10 mil between a surface of the semiconductor die and a surface of molded semiconductor package in order to avoid occurrence of voids in the semiconductor package as well as to prevent incomplete molding of the semiconductor package. However, such a transfer molding using the EMC may cause big limit in realization of ultra-small or ultra-slim semiconductor packages, which is a recently popular trend.
Further, in the transfer molding using the EMC, the EMC is injected into the semiconductor package from one side of the semiconductor die, which may cause a wire sweeping phenomenon in which conductive wires are gathered on one side of the semiconductor package.
Moreover, the wire sweeping may separate the bonded conductive wires from the bond pads of the semiconductor die or the bond fingers of the printed circuit board, thereby causing disconnection of the conductive wires and electrical interconnection of the conductive wires, which may induce the electrical short-circuit.
Furthermore, according to the transfer molding manner using EMC, the completed semiconductor package only comes in a black color. Therefore, the semiconductor package fails to satisfy a consumer expectation of various colored semiconductor packages, thereby reducing a consumer's purchasing desire.
SUMMARY OF THE INVENTION
In accordance with one embodiment, in a semiconductor package, a substrate and a semiconductor die are covered with and encapsulated by vertically pressing thermosetting resin having fluidity in a predetermined temperature range and denaturalizing itself in gel. In another semiconductor package, an upper portion of a semiconductor die and a part of conductive wires are covered and encapsulated with thermosetting resin in order to form an empty space at the sides of the semiconductor package. In still another semiconductor package, supporting portions having various colors, e.g., other than black, may be attached to the semiconductor package. In still another semiconductor package, at least one semiconductor die may be vertically stacked. In the method of making a semiconductor package, after a semiconductor die is bonded and connected to an upper surface of a substrate in a wire bonding manner, encapsulant is vertically pressed over the semiconductor die, thereby achieving the semiconductor package. Thus, it is possible to reduce a thickness of the semiconductor package and prevent wire sweeping.
The present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a sectional view showing a semiconductor package according to an embodiment of the present invention;
FIGS. 2A through 2F are sectional views illustrating a method of making the semiconductor package according to the embodiment of the present invention shown in FIG. 1;
FIG. 3 is a sectional view showing a semiconductor package according to another embodiment of the present invention;
FIG. 4 is a sectional view showing a semiconductor package according to still another embodiment of the present invention;
FIG. 5 is a sectional view showing a semiconductor package according to still another embodiment of the present invention;
FIGS. 6A through 6C are sectional views illustrating a gang process of the semiconductor package according to the embodiment of the present invention in FIG. 1; and
FIGS. 7, 8, 9 and 10 are sectional views showing semiconductor packages according to other embodiments of the present invention.
Common reference numerals are used throughout the drawings and the detailed description to indicate the same elements.
DETAILED DESCRIPTION
Referring to FIG. 1, there is shown a sectional view of a semiconductor package according to an embodiment of the present invention.
As shown in FIG. 1, the semiconductor package 100 according to the embodiment of the present invention includes a substrate 110 substantially having a plate shape, a semiconductor die 120 adhered to an upper surface of the substrate 110, a plurality of conductive wires 130 electrically connecting the semiconductor die 120 to the substrate 110, an encapsulant 140 covering the semiconductor die 120 and the conductive wires 130 which are located on the upper surface of the substrate 110, for protecting the semiconductor die 120 and the conductive wires 130 from exterior environment, and a plurality of solder balls 150 welded to a lower surface of the substrate 110 and used for mounting the semiconductor package to an exterior device. Here, if the above-mentioned structure is defined to a unit, a plurality of units is arranged in a line or in a row, or in lines or in rows in a gang process. Generally, the semiconductor package is completed through the gang process, and then is singulated into the individual semiconductor package. Hereinafter, a semiconductor package and a method of making the same with respect to a unit of the semiconductor package will be described. Further, it will be illustrated an example of the semiconductor package in which a printed circuit board is used as the substrate 110, but it will be noted that the substrate is not limited to only the printed circuit board and that a tape substrate and a lead frame may be used as a substrate. Therefore, the substrate 110 is not limited to these members. Further, the semiconductor package will be described as an example in which the semiconductor die 120 is electrically connected to the substrate 110 in a wire bonding manner, but it is understood that it is possible to use various bonding manners including a stud bump bonding manner and a flip chip manner. Therefore, the bonding manner is not limited.
The substrate 110 includes a thermosetting resin layer 111 which is a substantially flat plate, a plurality of upper conductive patterns 112 formed on an upper surface of the resin layer 111, a plurality of lower conductive patterns 113 formed on a lower surface of the resin layer 111, a plurality of conductive vias 115 electrically connecting the upper conductive patterns 112 to the lower conductive patterns 113, an upper solder mask 117 covering a portion of the upper surface of the resin layer 111 and the upper conductive patterns 112, and a lower solder mask 118 covering a portion of the upper surface of the resin layer 111 and the lower conductive patterns 113.
Here, the upper and lower conductive patterns 112 and 113 are suitably made of copper material, but the material of the upper and lower conductive patterns is not limited to the copper. Portions of the upper conductive patterns 112 which are connected to the conductive wires 130 are referred to as bond fingers, while portions of the lower conductive patterns 113 which are connected to the solder balls 150 are referred to as ball lands. Further, plated layers are formed of nickel and aurum (gold) on the bond fingers and the ball lands, respectively. This is to rigidly connect or fusion-weld the conductive wires 130 and the solder balls 150 to the bond fingers and the ball lands, respectively. Of course, in order to perform the connection and fusion-welding with respect to the ball lands and the bond fingers, the ball lands and the bond fingers need not be covered with the solder masks 117 and 118. Suitably, the upper and lower conductive patterns 112 and 113 are formed in a photolithographic manner, but the process of forming the upper and lower conductive patterns 112 and 113 is not limited.
On the other hand, the conductive vias 115 are formed in a form of hole which penetrates the upper and lower surfaces of the resin layer 111 in order to electrically connect the upper conductive pattern 112 and the lower conductive pattern 113 to each other. The conductive vias 115 respectively have an inner surface coated with copper. The plurality of conductive vias 115 may be formed, but the number of the conductive vias 115 is not limited to two vias formed at both sides of the substrate 110 as shown in FIG. 2.
In the upper solder mask 117, a portion of the upper solder mask 117 covering the bond fingers has a height substantially identical to that of another portion which covers the conductive pattern. Likewise, in the lower solder mask 118, the portion covering the lower conductive pattern 113 has a thickness substantially identical to that. The upper and lower solder masks 117 and 118 may be formed of epoxy resin, acryl resin or equivalent material thereof. However, the material and forming method of the solder masks 117 and 118 are not limited.
Meanwhile, the semiconductor die 120 is adhered by an adhesive 121 to a center portion of the upper surface of the substrate 110. The adhesive 121 may generally be epoxy resin, adhesive tape, adhesive film, or the equivalent material thereof, but is not limited to these materials. As shown in FIG. 1, the adhesive layer 121 has a sectional shape which is gradually narrower toward an upper portion thereof, but the sectional shape of the adhesive layer 121 is not limited. The semiconductor die 120 is adhered to the surface of the upper solder mask 117 which is substantially horizontal surface because the upper solder mask 117 has an even thickness or flatness throughout the entire region thereof regardless of the existence of the upper conductive pattern 112. Since the adhesive 121 attaches the lower surface of the semiconductor die 120 to the upper surface of the upper solder mask 117 having a high flatness, the semiconductor die 120 can be rigidly adhered to the upper solder mask 117.
However, the flatness of the upper surface of the upper solder mask 117 is not limited. The semiconductor die 120 is a substantially rectangular hexahedron with upper and lower flat surfaces. However, the shape of the semiconductor die 120 is not limited. Die pads 123 are formed on a portion of the upper surface of the semiconductor die 120 in order to electrically connect the semiconductor die 120 to the outside. The die pads 123 are formed such that an upper surface thereof is located at a level identical with, or at a level lower than, the upper surface of the semiconductor die 120.
Next, the conductive wires 130 electrically connect the semiconductor die 120 to the substrate 110. More particularly, the conductive wires 130 electrically connect the die pads 123 of the semiconductor die 120 to the bond fingers of the substrate 110. At this time, the conductive wires 130 are bonded to the die pads 123 in a stitch bonding manner and attached to the bond fingers in a ball bonding manner, respectively. More particularly, when the conductive wires 130 are bonded to the bond fingers and the die pads 123, one end of a conductive wire 130 is formed with a ball having a predetermined size by electric discharge, which is then fusion-welded to a surface of the bond finger, while the other end of the conductive wire 130 is extended and bonded to the die pad 123 without formation of a ball by stitch-boding using through application of ultrasonic waves and heat. Therefore, an angle between the conductive wire 130 and the surface of the bond finger is larger than an angle between the conductive wire 130 and the die pad 123. Since the conductive wires 130 are rubbed on and attached to the die pad 123 without balls, the conductive wires 130 must reach the surface of the die pad 123. As a result, it is possible to lower the height of the conductive wire 130 entirely, thereby also decreasing the height of the encapsulant 140. The conductive wire 130 may be a gold wire, an aluminum wire, and the equivalent materials thereof, but is not limited to these materials.
Meanwhile, the encapsulant 140 includes an adhering portion 141 made of thermosetting resin having fluidity in a predetermined temperature range, and a supporting portion 145 attached to an upper surface of the adhering portion 141 so as to support the adhering portion 141. The encapsulant 140 encloses the semiconductor die 120 and the conductive wires 130 on the substrate 110, thereby protecting them from the exterior environment. The encapsulant 140 is formed of material having fluidity in a pressing manner, instead of transfer molding manner using the epoxy molding compound. Thus, the encapsulant 140 causes the semiconductor package 100 to have a reduced height, while preventing the conductive wires 130 from being cut or subjected to electric short due to the wire sweeping.
The adhering portion 141 is formed of thermosetting resin having fluidity in a predetermined temperature range and then is cured when the adhering portion is heated. The adhering portion 141 is denaturalized in a gel state at a temperature of 50° C. to 200° C. and cured in a range of the temperature of 50° C. to 200° C., for example over a temperature of about 160° C. However, it is understood that the temperature of the adhering portion 141 in the gel state and the curing temperature of the adhering portion 141 are examples, but are not limited to the above-mentioned temperature ranges. Further, the adhering portion 141 has a thickness of about 2 mil to 3 mil after the adhering portion 141 is pressed, but the thickness of the adhering portion 141 is not limited. The adhering portion 141 covers the entire upper surface of the substrate 110, the semiconductor die 120, and the conductive wires 130. The adhering portion 141 is heated to the temperature of 50° C. to 200° C. and denaturalized in the gel having the fluidity, which is in turn pressed downward to cover the upper surface of the substrate 110, the semiconductor die 120, and the conductive wires 130. Finally, the adhering portion 141 is heated for a half hour to six hours, resulting in the cured adhering portion 141.
The supporting portion 145 is formed to cover an upper surface of the adhering portion 141. The supporting portion 145 is made of insulation substance such as polyimide and epoxy, or the equivalent materials thereof, but the material of the supporting portion 145 is not limited to these materials. Further, the supporting portion 145 has enough hardness to maintain flatness entirely. At this time, the supporting portion 145 is adhered to the upper surface of the adhering portion by an adhesive. That is, the supporting portion 145 is adhered in advance to the adhering portion 141 by heat and/or pressure. Therefore, the supporting portion 145 and the adhering portion 141 are adhered to each other before the encapsulant 140 is pressed. Suitably, the supporting portion 145 has a substantially identical area with that of the surface of the adhering portion 141. However, the area of the supporting portion 145 is not limited. The supporting portion 145 may be formed with a thickness of about 0.5 mil to 1 mil, but the thickness of the supporting portion 145 is not limited. The supporting portion 145 is made of material having the high heat conductivity so as to smoothly discharge heat. Furthermore, since the supporting portion 145 may be dyed with various colors it is possible to make the semiconductor packages having various colors, e.g., other than black, according to consumer's favorite, thereby increasing consumer's desire for purchasing the semiconductor packages.
The encapsulant 140 is formed with a thickness of 2.5 mil to 4 mil on the upper surface of the semiconductor die 120 in spite of attaching the supporting portion 145 to the adhering portion 141. In contrast, when the encapsulant is formed in the conventional transfer molding manner, the encapsulant generally has a thickness of about 10 mil from the upper surface of the semiconductor die to the upper surface of the semiconductor package. However, the encapsulant 140 according to the present invention has the thickness reduced by up to about 6 mil to 7 mil, as compared with the above-mentioned encapsulant formed using the transfer molding method, so that the encapsulant 140 is advantageous for making the extremely thin semiconductor package.
Further, the solder balls 150 are fusion-welded to the ball lands exposed downward through the lower solder mask 118 which is formed on the lower surface of the substrate 110. The solder balls 150 are fusion-welded to the ball lands in such a manner that the substrate passes through a furnace after flux is injected into solder and then an amount of solder necessary for forming each solder ball is dropped on each ball land. While the substrate passes through the furnace, the flux is volatilized and only the solder balls 150 are fusion-welded to the lower conductive pattern 113. These solder balls 150 are surface-mounted on the exterior device by using a reflow process, so as to enable the semiconductor package 100 to transmit and receive electric signals to/from the exterior device.
Referring to FIGS. 2A through 2F, there are shown sectional views illustrating the method of making the semiconductor package according to an embodiment of the present invention.
As shown in FIG. 2A to 2F, the method of making the semiconductor package 100 includes an operation of forming the substrate 110, an operation of forming solder masks 117 and 118 on the upper and lower surfaces of the substrate 110, an operation of attaching the semiconductor die 120 to the substrate 110 by an adhesive 121, an operation of bonding wires 130 to the die pads 123 of the semiconductor die 120 and the bond fingers of the substrate 110 in order to electrically connect the semiconductor die 120 to the substrate 110, an operation of pressing the encapsulant 140, and an operation of fusion-welding the solder balls 150 to the ball land of the lower surface of the substrate 110. Further, the operation of pressing the encapsulant 140 includes an operation of attaching the supporting portion 145 to the adhering portion 141, and a first heat operation of heating the adhering portion 141 having fluidity. Furthermore, in the operation of pressing the encapsulant 140, it may be performed a second heating operation of heating the adhering portion 140 up to a predetermined temperature in order to cure the adhering portion 140 after the first heating operation.
Referring to FIG. 2A again, there is shown a sectional view illustrating the operation of making the substrate 110. As shown in FIG. 2, a thermosetting resin layer 111 having a substantially plate shape has a plurality of upper conductive patterns 112 formed on an upper surface thereof, and a plurality of lower conductive patterns 113 formed on a lower surface thereof. Suitably, the conductive patterns 112 and 113 are formed of copper having the high conductivity using a photolithography method. However, the material or forming method of the conductive patterns 112 and 113 are not limited. After the conductive patterns 112 and 113 are formed, a plurality of conductive vias 115 are formed in order to electrically connect the upper and lower conductive patterns 112 and 113 to each other.
Referring to FIG. 2B again, there is shown a sectional view illustrating the operation of forming solder mask 117 and 118. As shown in FIG. 2B, the solder masks 117 and 118 are formed on the conductive patterns 112 and 113 of the substrate 110 in such a manner that regions corresponding to bond fingers and ball lands of the conductive patterns 112 and 113 are exposed. More particularly, the upper solder mask 117 is formed on the upper conductive pattern 112, while the lower solder mask 118 is formed on the lower conductive pattern 118. The upper solder mask 117 may cover the bond fingers in such a manner that a portion of the bold finger to which the conductive wire 130 is bonded is exposed to exterior, or in such a manner that the entire upper conductive patterns 112 corresponding to the bold fingers are exposed. Furthermore, the upper solder mask 117 is formed to have even thickness throughout the substrate 110. The operation of forming the solder masks 117 and 118 is carried out in order to coat and protect the conductive patterns, except for a portion of the conductive patterns that must be electrically connected to the exterior through the conductive wires 130 or the solder balls 150, with insulation material. In this operation, the solder masks 117 and 118 may be formed of epoxy, acryl, or the equivalent materials by using the photolithographic method. However, the material or forming method of the solder masks 117 and 118 is not limited.
Referring to FIG. 2C next, there is shown a sectional view illustrating the operation of attaching the semiconductor die 120 to the substrate 110. As shown in FIG. 2C, the semiconductor die 120 is attached to a center portion of the upper surface of the substrate 110.
Referring to FIG. 2D next, there is shown a sectional view illustrating the operation of bonding wires. As shown in FIG. 2D, the die pads 123 of the semiconductor die 120 are electrically connected to the bond fingers of the substrate 110 by the conductive wires 130. First, the conductive wires extend at a predetermined distance from a capillary (not shown) and then have ball formed at one end of the conductive wires by an electric discharge to have a predetermined size. Next, the balls of the conductive wires are in close contact with the bond fingers of the substrate 110 respectively. At the same time, energy such as ultrasonic vibration is applied from the capillary to the balls of the conductive wires 130 and heat also is applied from the exterior to the ball of the conductive wires, thereby bonding the conductive wires to the substrate 110. Then, a looping process is performed in which a tip of the capillary is rubbed on a surface of the bond pads when the capillary reaches the bond pads of the semiconductor die 120 while the ultrasonic vibration and heat are applied to the capillary tip, thereby achieving the stitch bonding. Then, a clamp (not shown) is closed and a cutting of the conductive wires 130 is carried out.
Though not shown, the operation of pressing the encapsulant 140 is performed after the operation of attaching the supporting portion 145 to the adhering portion 141 and the first heating operation of heating the adhering portion 141 in the flowing state. The operation of attaching the supporting portion 145 is a process in which the adhering portion 141 is formed to have the substantially flat plat shape and then the supporting portion 145 is attached to the upper surface of the adhering portion 141 by the adhesive. The first heating operation is a process in which the adhering portion 141 is heated and then is denaturalized in the gel having the fluidity. The first heating operation is carried out at a temperature of 50° C. to 200° C., so that the adhering portion 141 is substantially changed into a liquid state having enough fluidity. Therefore, the encapsulant 140 including the adhering portion 141 is vertically pressed in the gel state on the substrate 110, the semiconductor die 120 and the conductive wires 130, thereby having no effect on the conductive wires 130 and preventing the wire sweeping phenomenon.
Referring to FIG. 2E next, there is shown a sectional view illustrating the operation of pressing the encapsulant 140.
As shown in FIG. 2E, the encapsulant 140 is pressed downward from the upper portion of the semiconductor die 120, so as to cover the entire upper surface of the substrate 110. At this time, the adhering portion 141 is formed to cover the substrate 110, the semiconductor die 120 and the conductive wires 130, but it is necessary to adjust the thickness of the adhering portion 141 before the adhering portion 141 is pressed, in order to form the adhering portion 141 having a minimized thickness.
Though not shown, the second heating operation is performed in which the pressed adhering portion 141 is heated to a predetermined temperature so as to cure the adhering portion 141, after the operation of pressing the encapsulant 140. The second heating operation is carried out at a temperature of 50° C. to 200° C. for a half hour to six hours, so that the adhering portion in the gel state is cured into a rigid solid state.
Referring next to FIG. 2F, there is shown a sectional view illustrating the operation of fusion-welding the solder balls.
As shown in FIG. 2F, the ball lands of the lower conductive patterns 113 to be a portion at which the solder balls 150 are formed is not covered with the lower solder mask 118 and exposed to the exterior. First, flux is injected into the ball lands and then an amount of solder material, enough to form the solder balls, is dropped on the flux. Then, the fusion-welding of the solder balls is performed in a furnace. The flux is volatilized and discharged out of the furnace. As a result, the solder balls 150 are fusion-welded and electrically connected to the lower conductive pattern 113.
As described above, the semiconductor package 100 according to the present invention has the encapsulant 140 remarkably reduced in thickness, as compared with the semiconductor package made in the transfer molding manner. As a result, the semiconductor package becomes thin and can be widely applied to electric/electron devices requiring extremely small-sized and extremely thin semiconductor package. Further, in the semiconductor package 100 according to the present invention, the encapsulant 140 in gel is vertically pressed downward so as not to apply force to the conductive wires 130, thereby preventing open circuit or short circuit from being caused due to the wire sweeping phenomenon.
Referring to FIG. 3, there is shown a sectional view of the semiconductor package according to another embodiment of the present invention. As shown in FIG. 3, the semiconductor package 200 according to another embodiment of the present invention has a structure similar to the semiconductor package 100 according to the embodiment of FIG. 1. The description of the same element as that of the semiconductor package 100 will be omitted. Further, the method of making the semiconductor package 100 according to the embodiment shown in FIG. 3 is identical with the method of making the semiconductor package 100 according to the embodiment shown in FIG. 1. Therefore, the description of the method of making the semiconductor package will be omitted.
As shown in FIG. 3, the semiconductor package 200 according to another embodiment of the present invention includes a substrate 210 having a substantially flat plate shape, a semiconductor die 220 adhered to an upper surface of the substrate 210, a plurality of conductive wires 230 electrically connecting the semiconductor die 220 to the substrate 210, an encapsulant 240 covering the semiconductor die 220 and the conductive wires 230 disposed on the upper surface of the substrate 210, so as to protect them from exterior environment, and a plurality of solder balls 250 fusion-welded to a lower surface of the substrate 210 and mounted on an exterior device.
First, the substrate 210 has a plurality of conductive patterns 212 and 213 which are formed upper and lower surfaces of a plate shaped thermosetting resin layer 211, respectively. The substrate 210 also has conductive vias 215 to electrically connect the upper conductive patterns 212 formed on the upper surface of the substrate 210 to the lower conductive patterns 213 formed on the lower surface of the substrate 210. Further, the substrate 210 includes an upper solder mask 217 covering a portion of an upper surface of the upper conductive patterns 212 and the resin layer 211, and a lower solder mask 218 covering a portion of a lower surface of the lower conductive patterns 213 and the resin layer 211.
Meanwhile, the semiconductor die 220 is attached to a center portion of the upper surface of the substrate 210 by an adhesive 221, and has die pads 223 formed on the upper surface thereof to which the conductive wires 230 are bonded.
The conductive wires 230 electrically connect the die pads 223 of semiconductor die 220 to bond fingers of the substrate 210. At this time, the conductive wires 230 are first bonded to the bond fingers in a ball bonding manner, which in turn is bonded to the die pads 223 in a stitch bonding manner, as described above relating to the afore-mentioned previous embodiment.
The encapsulant 240 includes an adhering portion 241 and a supporting portion 245. The adhering portion 241 is formed of thermosetting resin having fluidity at a predetermined temperature range, while the supporting portion 245 is formed of polyimide, epoxy, or the equivalent materials thereof. At this time, the encapsulant 240 is formed to cover the semiconductor die 220 and the conductive wires 230 so that a part of the upper surface of the substrate 210 is exposed to the exterior. In other words, the encapsulant 240 is downward pressed over the upper surface of the semiconductor die 220 and the conductive wires 230, in order to enclose the upper surface of the semiconductor die 220 and an upper portion of the conductive wires 230. Therefore, a portion of the semiconductor package 200 is not enclosed by the encapsulant 240 to have empty space portion 247. The space portion 247 may be filled with epoxy molding compound by a separate encapsulation process or remain empty, after the semiconductor package 200 is mounted on a printed circuit board. In a case where the space portion 247 is filled with the epoxy molding compound, the space portion 247 is filled with the epoxy molding compound in the transfer molding manner. At this time, since the adhering portion 241 secures the upper portion of the conductive wires 230, there is no danger that the wire sweeping occurs although the epoxy molding compound is filled in the space portion. In order to form the encapsulant 240 so that the encapsulant 240 covers a portion of the semiconductor package 200, an amount of the adhering portion 241 must be adjusted before the adhering portion 241 is pressed. At this time, the amount of the adhering portion 241 is smaller than that of adhering portion 141 shown in FIG. 1, thereby obtaining the same structure as that of this embodiment of the present invention. That is, the amount of the adhering portion 241 is adjusted so that a size of the region in which the encapsulant 240 is formed can be adjusted.
On the other hand, the solder balls 250 are fusion-welded to the ball lands downwardly exposed through the lower solder mask 218, respectively. The solder balls 250 play the role of electrically connecting a wiring pattern and the semiconductor package 200 to each other.
Therefore, The semiconductor package 200 is coupled to a printed circuit board by a coupling force of the solder balls 250. Moreover, in the semiconductor package 200 according to another embodiment of the present invention, the epoxy molding compound filled in the space portion 247 plays the role of securing the semiconductor package 200. Further, it is possible to reduce the amount of the adhering portion 241 used for the semiconductor package 200, thereby reducing the manufacturing cost of the semiconductor package 200.
Referring to FIG. 4, there is shown a sectional view of a semiconductor package according to still another embodiment of the present invention. As shown in FIG. 4, the semiconductor package 300 according to still another embodiment of the present invention has a structure similar to the semiconductor package 100 according to the embodiment shown in FIG. 1, the description of the same elements as those of the semiconductor package 100 will be omitted. Further, since the method of making the semiconductor package 300 according to the embodiment shown in FIG. 4 is similar to the method of making the semiconductor package 100, no views illustrating the method of making the semiconductor package 300 are shown, and only difference from the previous embodiments will be described.
As shown in FIG. 4, the semiconductor package 300 according to still another embodiment of the present invention includes a plate shaped substrate 310, a semiconductor die 320 adhered to an upper surface of the substrate 310, a plurality of conductive wires 330 for electrically connecting the semiconductor die 320 to the substrate 310, an encapsulant 340 for covering and protecting the semiconductor die 320 and the conductive wires 330 disposed on the upper surface of the substrate 310 from the exterior environment, and a plurality of solder balls 350 fusion-welded to a lower surface of the substrate 310 and mounted on an exterior device.
First, the substrate 310 has a plurality of conductive patterns 312 and 313 formed on upper and lower surfaces of the plate shaped thermosetting resin layer 311, and conductive vias 315 formed therein so as to electrically connect the upper conductive patterns 312 to the lower conductive patterns 313. Further, the substrate 310 includes an upper solder mask 317 covering a portion of an upper surface of the resin layer 311 and the upper conductive patterns 312, and a lower solder mask 318 covering a portion of a lower surface of the resin layer 311 and the lower conductive patterns 313.
Next, the semiconductor die 320 is attached to a center portion of the upper surface of the substrate 310 by an adhesive 321, and has die pads 323 formed thereon to which the conductive wires 330 is bonded.
The conductive wires 330 electrically connect the die pads 323 of the semiconductor die 320 to bond fingers of the substrate 310. At this time, the conductive wires 330 is first bonded to the bond fingers in a ball bonding manner, which in turn is bonded to the die pads in a stitch bonding manner.
Here, the encapsulant 340 only has an adhering portion, which can be colored. The encapsulant 340 is made of thermosetting resin having fluidity in a predetermined temperature range. A supporting portion is attached to an upper surface of the adhering portion until the encapsulant 340 is pressed and then cured. When the encapsulant 340 is cured, the supporting portion is separated from the upper surface of the adhering portion and only the adhering portion remains. The supporting portion is attached to the adhering portion in order to maintain a shape of the adhering portion having sufficient fluidity and to easily perform the pressing operation. Therefore, even if the supporting portion is removed from the adhering portion after the pressing operation, there is no problem. However, when the supporting portion is separated from the adhering portion right after the pressing operation, it has an effect on the conductive wires 330, etc. Therefore, it is suitable to remove the supporting portion from the adhering portion after completely curing the adhering portion.
Further, the encapsulant 340 may be formed to cover only the semiconductor die 320 and the conductive wires 330 so that a portion of the upper surface of the substrate 310 is exposed to the exterior, like the embodiment shown in FIG. 3. That is, the encapsulant 340 may be formed such that empty space exists in the encapsulant 340, though not shown in FIG. 4.
Meanwhile, the solder balls 350 are fusion-welded to the ball lands downward exposed through the lower solder mask 318 which is formed on the lower surface. The solder balls 350 plays the role of electrically connecting a wire pattern of a printed circuit board to the semiconductor package 300 when the semiconductor package 300 is mounted on a surface of the printed circuit board.
As described above, in the semiconductor package 300 according to still another embodiment of the present invention, the supporting portion is removed from the semiconductor package 300, thereby reducing the thickness of the semiconductor package 300.
Hereinafter, the method of making the semiconductor package 300 according to still another embodiment of the present invention will be described.
The method of making the semiconductor package 300 according to still another embodiment of the present invention includes the operation of removing the supporting portion in addition to the operations described above relating to FIGS. 2A to 2F. That is, the method of making the semiconductor package 300 according to the embodiment shown in FIG. 4 includes the operation of making the substrate 310, the operation of attaching the semiconductor die 320 to the substrate 310 by adhesive 321, the operation of bonding conductive wires 330 to electrically connect the semiconductor die 320 to bond fingers of the substrate 310, the operation of pressing the encapsulant 340, and the operation of fusion-welding solder balls 350 to ball lands on a lower surface of the substrate 310. Further, the operation of pressing the encapsulant 340 includes the operation of attaching the supporting portion to the adhering portion and a first heating operation of heating the adhering portion to flowing state. In addition, the method of making the semiconductor package further includes a second heating operation of heating the adhering portion at a predetermined temperature in order to cure the adhering portion and the operation of removing the supporting portion from the adhering portion, after the operation of pressing the encapsulant 340.
Referring to FIG. 5, there is shown a sectional view of the semiconductor package according to still another embodiment of the present invention. As shown in FIG. 5, the semiconductor package 400 according to still another embodiment of the present invention has a structure similar to that of the semiconductor package 100 according to the embodiment shown in FIG. 1. Therefore, differences from the semiconductor package 100 shown in FIG. 1 will be described. Further, the method of making the semiconductor package 400 according to the embodiment of FIG. 5 is similar to the method of making the semiconductor package 100 according to the embodiment of FIG. 1. Therefore, differences from the method of making the semiconductor package 400 according to still another embodiment of the present invention will be described.
As shown in FIG. 5, the semiconductor package 400 according to still another embodiment of the present invention includes a plate shaped substrate 410, at least two semiconductor dies 420_1 and 420_2 attached to an upper surface of the substrate 410, a plurality of conductive wires 430 for electrically connecting the semiconductor dies 420_1 and 420_2 to the substrate 410, an encapsulant 440 for covering and protecting the conductive wires 430 from the exterior environment, and a plurality of solder balls 450 fusion-welded to a lower surface of the substrate 410 and mounted to an exterior device.
First, the substrate 410 is formed such that a plurality of conductive patterns 412 and 413 are formed on upper and lower surfaces of plate shaped thermosetting resin layer 411, while having conductive vias 415 formed therein in order to electrically connect the upper conductive patterns 412 formed on the upper surface thereof to the lower conductive patterns 413 formed on the lower surface thereof. Further, the substrate 410 includes an upper solder mask 417 covering a portion of an upper surface of the resin layer 411 and the upper conductive patterns 412, and a lower solder mask 418 covering a portion of a lower surface of the resin layer 411 and the lower conductive patterns 413. Portions of the upper conductive patterns 412 corresponding to a bond finger connected to first semiconductor die 420_1 and a bond finger connected to second semiconductor die 420_2, respectively, are separately formed and insulated.
The semiconductor die 420_1 and 420_2 are vertically stacked. The two semiconductor dies 420_1 and 420_2 are stacked as shown in FIG. 5, but it is understood that at least two semiconductor dies may be stacked. Here, the number of the semiconductor dies is not limited. The first semiconductor die 420_1 is attached to a center portion of the upper surface of the substrate 410 by adhesive 421, which has die pads 423_1 formed thereon to which the conductive wires 430 are bonded. Further, the second semiconductor die 420_2 is attached to an upper surface of the first semiconductor die 420_1 by adhesive 422. Similarly, the second semiconductor die 420_2 has die pads 423_2 formed thereon to which the conductive wires 430 are bonded. At this time, the first semiconductor die 420_1 and the second semiconductor die 420_2 may be formed to have an identical size. However, it is understood that the second semiconductor die 420_2 may have a smaller size than that of the first semiconductor die 420_1, for example, see semiconductor package 400A of FIG. 7. Referring still to FIG. 5, the semiconductor dies 420_1 and 420_2 are not limited to the above-mentioned size. The semiconductor dies 420_1 and 420_2 have die pads 423_1 and 423_2, respectively. Separate conductive wires 430 are connected to bond fingers, respectively.
The conductive wires 430 electrically connect the die pad 423_1 of the first semiconductor die 420_1 and the die pad 423_2 of the second semiconductor die 420_2 to the bond fingers of the substrate 410, respectively. At this time, the conductive wires 430 are first bonded to the bond finger in a ball bonding manner, and then are bonded to the die pad in a stitch bonding manner, respectively, as described above relating to the previous embodiments.
Next, the encapsulant 440 includes an adhering portion 441 and a supporting portion 445. The adhering portion 441 is formed of thermosetting resin having fluidity in a range of predetermined temperature. The supporting portion 445 is made of polyimide, epoxy, and the like. At this time, the encapsulant 440 is formed to cover the entire of the upper surface of the substrate 410 as shown in FIG. 5. As not shown in FIG. 5, the encapsulant 440 may be formed so that a portion of the substrate is exposed to the exterior, like the embodiment shown in FIG. 3. That is, the structure in the embodiments of FIGS. 1 and 3 are selectively applied to the embodiment of FIG. 5. Such examples are illustrated by semiconductor packages 400A, 400B of FIGS. 7, 8, where a space portion 447 is formed in encapsulant 440, but otherwise where similar elements are labeled with the same reference number.
The solder balls 450 are fusion-welded to ball lands downward exposed through a lower solder mask 418 on the lower surface of the substrate 410. The solder balls 450 play the role of electrically connecting a wire pattern of a printed circuit board to the semiconductor package 400 when the semiconductor package 400 is mounted on a surface of the printed circuit board.
As described above, the semiconductor package 400 according to still another embodiment of the present invention has at least two semiconductor dies mounted therein, so as to exhibit a more excellent performance, while having a more reduced thickness in spite of the semiconductor package in which the semiconductor dies are stacked.
Hereinafter, the method of making the semiconductor package 400 according to still another embodiment of the present invention.
The method of the semiconductor package 400 according to still another embodiment of the present invention includes the operation of attaching a second semiconductor die in addition to the method of making the semiconductor package 400 illustrated in FIGS. 2A through 2F. That is, the method of making the semiconductor package 400 according to the embodiment of FIG. 5 includes the operation of manufacturing a substrate 410, the operation of forming solder masks 417 and 418 on upper and lower surfaces of the substrate 410, the operation of attaching a first semiconductor die 420_1 to the substrate 410 by using adhesive 421, the operation of attaching a second semiconductor die 420_2 to an upper surface of the first semiconductor die 420_1 by using adhesive 422, the operation of electrically connecting the semiconductor dies 420_1 and 420_2 to bond fingers of the substrate 410 by means of conductive wires 430, respectively, the operation of pressing an encapsulant 440, and the operation of fusion-welding solder balls 450 to ball lands on a lower surface of the substrate 410. Meanwhile, the operation of pressing the encapsulant 440 is performed after the operation of attaching a supporting portion 445 to an adhering portion 441, and a first heating operation of heating the adhering portion 441 in flowing state. The method of making the semiconductor package further includes a second heating operation of heating the pressed adhering portion 441 to a predetermined temperature so as to cure the adhering portion 441, after the operation of pressing the encapsulant 440.
Referring to FIGS. 6A through 6C, there is shown a sectional view illustrating a gang process for the semiconductor package according to the embodiment of FIG. 1. Though not shown, the embodiments of FIGS. 3 and 5 can be manufactured by a method similar to the gang process for the semiconductor package according to the embodiment of FIG. 1. Furthermore, since the method of manufacturing a unit is described in detail with reference to FIGS. 2A through 2F, the method of making the semiconductor package based on the gang process will be described in brief, hereinafter.
As shown in FIGS. 6A, 6B, 6C, the gang process for the semiconductor package 100 according to the embodiment of FIG. 1 includes the operation of preparing encapsulant 140, the operation of pressing the encapsulant 140, the operation of fusion-welding solder balls, and a singulation operation of sawing the semiconductor package in each unit.
Referring to FIG. 6A, first, there is shown the operation of preparing encapsulant 140. The operation of preparing the encapsulant 140 includes the operation of bonding conductive wires 130 to the semiconductor die 120 and the substrate 110 in a wire bonding manner after a plurality of semiconductor dies 120 is arranged in line, in a row, or in matrix on a large area of substrate 110, and the operation of attaching a supporting portion 145 to an adhering portion 141 and heating the adhering portion to have fluidity. At this time, it is mentioned above that the adhering portion 141 is adjusted to have a minimal thickness, while enclosing the entire upper portion of the substrate 110 so that empty space is not formed at both sides of the semiconductor package.
Referring to FIG. 6B next, there is shown a sectional view illustrating the operations of pressing the encapsulant 140 and fusion-welding solder balls 150.
The operation of pressing the encapsulant 140 includes the operation of vertically pressing the adhering portion 141 in gel having fluidity, and the operation of heating the adhering portion 141 over a predetermined temperature so as to cure the adhering portion 141. At this time, in the operation of pressing the encapsulant 140, there are required for heat over a predetermined temperature and enough pressure to make the thickness of the semiconductor package be minimal.
In the operation of fusion-welding the solder balls 150, the solder balls 150 are fusion-welded to the lower conductive pattern 113 exposed to the exterior because the lower solder mask 118 is not formed on the lower conductive pattern 113.
Referring next to FIG. 6C, there is shown a sectional view illustrating the singulation operation.
In the singulation operation, the semiconductor package is sawed from the encapsulant 140 to the lower surface of the substrate 110 in each unit, in order to satisfy a standard for unit. When the singulation operation is finished, a plurality of units is produced.
Referring to FIG. 7, there is shown a sectional view of the semiconductor package according to still another embodiment of the present invention. As shown in FIG. 7, the semiconductor package 400A according to still another embodiment of the present invention has a structure similar to that of the semiconductor package 400 according to the embodiment shown in FIG. 5. Therefore, differences from the semiconductor package 400 shown in FIG. 5 will be described.
As shown in FIG. 7, the second semiconductor die 420_2 is of a smaller size than that of the first semiconductor die 420_1. More particularly, the second semiconductor die 420_2 is attached to an upper surface of the first semiconductor die 420_1 inward of the die pads 423_1 of the first semiconductor die 420_1 by adhesive 422.
As also shown in FIG. 7, the semiconductor package 400A according to still another embodiment of the present invention includes an encapsulant 440. The encapsulant 440 includes an adhering portion 441 and a supporting portion 445. The adhering portion 441 is formed of thermosetting resin having fluidity at a predetermined temperature range, while the supporting portion 445 is formed of polyimide, epoxy, or the equivalent materials thereof. At this time, the encapsulant 440 is formed to cover at least a part of the semiconductor die 420_2 and the conductive wires 430 attached to the semiconductor die 420_2 so that a part of the upper surface of the substrate 410 and the semiconductor die 420_1 are exposed to the exterior. In other words, the encapsulant 440 is downward pressed over the upper surface of the semiconductor die 420_2 and at least a part of the conductive wires 430 attached thereto, in order to enclose the upper surface of the semiconductor die 420_2 and an upper portion of the conductive wires 430 attached thereto. Therefore, a portion of the semiconductor package 400A is not enclosed by the encapsulant 440 to have empty space portion 447. The space portion 447 may be filled with epoxy molding compound by a separate encapsulation process or remain empty, after the semiconductor package 400A is mounted on a printed circuit board.
Referring to FIG. 8, there is shown a sectional view of the semiconductor package according to still another embodiment of the present invention. As shown in FIG. 8, the semiconductor package 400B according to still another embodiment of the present invention has a structure similar to that of the semiconductor package 400 according to the embodiment shown in FIG. 5. Therefore, differences from the semiconductor package 400 shown in FIG. 5 will be described.
As shown in FIG. 8, the semiconductor package 400B according to still another embodiment of the present invention includes an encapsulant 440. The encapsulant 440 includes an adhering portion 441 and a supporting portion 445. The adhering portion 441 is formed of thermosetting resin having fluidity at a predetermined temperature range, while the supporting portion 445 is formed of polyimide, epoxy, or the equivalent materials thereof. At this time, the encapsulant 440 is formed to cover the semiconductor die 420_2 and the conductive wires 430 attached to the semiconductor die 420_2 so that a part of the upper surface of the substrate 410 and the semiconductor die 420_1 are exposed to the exterior. In other words, the encapsulant 440 is downward pressed over the upper surface of the semiconductor die 420_2 and the conductive wires 430 attached thereto, in order to enclose the upper surface of the semiconductor die 420_2 and an upper portion of the conductive wires 430 attached thereto. Therefore, a portion of the semiconductor package 400B is not enclosed by the encapsulant 440 to have empty space portion 447. The space portion 447 may be filled with epoxy molding compound by a separate encapsulation process or remain empty, after the semiconductor package 400B is mounted on a printed circuit board.
Referring to FIG. 9, there is shown a sectional view of the semiconductor package according to still another embodiment of the present invention. As shown in FIG. 9, the semiconductor package 400C according to still another embodiment of the present invention has a structure similar to that of the semiconductor package 400A according to the embodiment shown in FIG. 7. Therefore, differences from the semiconductor package 400A shown in FIG. 7 will be described.
As shown in FIG. 9, the semiconductor package 400C according to still another embodiment of the present invention includes an encapsulant 440. The encapsulant 440 includes an adhering portion 441 and a supporting portion 445. The adhering portion 441 is formed of thermosetting resin having fluidity at a predetermined temperature range, while the supporting portion 445 is formed of polyimide, epoxy, or the equivalent materials thereof. At this time, the encapsulant 440 is formed to cover the semiconductor dies 420_1, 420_2 and the conductive wires 430 attached to the die pads 423_2, 423_1 so that a part of the upper surface of the substrate 410 is exposed to the exterior. In other words, the encapsulant 440 is downward pressed over the entire semiconductor die 420_2 and the upper surface of the semiconductor die 420_1 and the conductive wires 430, in order to enclose the entire semiconductor die 420_2, the upper surface of the semiconductor die 420_1, and an upper portion of the conductive wires 430. Therefore, a portion of the semiconductor package 400C is not enclosed by the encapsulant 440 to have empty space portion 447.
The space portion 447 may be filled with epoxy molding compound by a separate encapsulation process or remain empty, after the semiconductor package 400C is mounted on a printed circuit board. In a case where the space portion 447 is filled with the epoxy molding compound, the space portion 447 is filled with the epoxy molding compound in the transfer molding manner. At this time, since the adhering portion 441 secures the upper portion of the conductive wires 430, there is no danger that the wire sweeping occurs although the epoxy molding compound is filled in the space portion.
Referring to FIG. 10, there is shown a sectional view of the semiconductor package according to still another embodiment of the present invention. As shown in FIG. 10, the semiconductor package 400D according to still another embodiment of the present invention has a structure similar to that of the semiconductor package 400B according to the embodiment shown in FIG. 8. Therefore, differences from the semiconductor package 400B shown in FIG. 8 will be described.
As shown in FIG. 10, the semiconductor package 400D according to still another embodiment of the present invention includes an encapsulant 440. The encapsulant 440 includes an adhering portion 441 and a supporting portion 445. The adhering portion 441 is formed of thermosetting resin having fluidity at a predetermined temperature range, while the supporting portion 445 is formed of polyimide, epoxy, or the equivalent materials thereof. At this time, the encapsulant 440 is formed to cover the semiconductor dies 420_1, 420_2 and the conductive wires 430 attached to the die pads 423_2, 423_1 so that a part of the upper surface of the substrate 410 is exposed to the exterior. In other words, the encapsulant 440 is downward pressed over the entire semiconductor die 420_2 and the upper surface of the semiconductor die 420_1 and the conductive wires 430, in order to enclose the entire semiconductor die 420_2, the upper surface of the semiconductor die 420_1, and an upper portion of the conductive wires 430. Therefore, a portion of the semiconductor package 400D is not enclosed by the encapsulant 440 to have empty space portion 447.
The space portion 447 may be filled with epoxy molding compound by a separate encapsulation process or remain empty, after the semiconductor package 400D is mounted on a printed circuit board. In a case where the space portion 447 is filled with the epoxy molding compound, the space portion 447 is filled with the epoxy molding compound in the transfer molding manner. At this time, since the adhering portion 441 secures the upper portion of the conductive wires 430, there is no danger that the wire sweeping occurs although the epoxy molding compound is filled in the space portion.
This disclosure provides exemplary embodiments of the present invention. The scope of the present invention is not limited by these exemplary embodiments. Numerous variations, whether explicitly provided for by the specification or implied by the specification, such as variations in structure, dimension, type of material and manufacturing process, may be implemented by one skilled in the art in view of this disclosure.

Claims (15)

1. A semiconductor package comprising:
a substrate, which has a plurality of conductive patterns formed on upper and lower surfaces of the substrate and a solder mask layer formed on the lower surface of the substrate;
a semiconductor die adhered by adhesive to the upper surface of the substrate;
a plurality of conductive wires for electrically connecting die pads on an upper surface of the semiconductor die to bond fingers on the upper surface of the substrate;
encapsulant pressed downward over an upper portion of the semiconductor die so as to cover the semiconductor die placed on the upper surface of the substrate and the conductive wires, wherein the encapsulant covers only a first part of the semiconductor die and only a first part of the conductive wires leaving a second part of the semiconductor die and a second part of the conductive wires exposed to an exterior of the semiconductor package through a space portion existing at a side of the semiconductor package, wherein the first part of the conductive wires comprises the entire upper portion of the conductive wires above a plane defined by the upper surface of the semiconductor die; and
a plurality of solder balls fusion-welded to the conductive pattern formed on the lower surface of the substrate.
2. The semiconductor package as claimed in claim 1, wherein the encapsulant includes an adhering portion made of thermosetting resin having fluidity in a predetermined temperature range.
3. The semiconductor package as claimed in claim 1, further comprising a second semiconductor die adhered to the upper surface of the semiconductor die, wherein the encapsulant covers at least a part of the second semiconductor die.
4. The semiconductor package as claimed in claim 3, wherein the encapsulant covers the entire second semiconductor die and the upper surface of the semiconductor die.
5. The semiconductor package as claimed in claim 3, wherein the second semiconductor die is smaller than the semiconductor die.
6. The semiconductor package as claimed in claim 2, wherein the encapsulant includes a supporting portion that is located on an upper surface of the adhering portion so as to support the adhering portion.
7. The semiconductor package as claimed in claim 1, wherein at least one semiconductor die is stacked.
8. The semiconductor package as claimed in claim 1, wherein the conductive wires have one end bonded to the die pads in a stitch bonding manner and the other end attached to the bond fingers in a ball bonding manner.
9. A semiconductor package comprising:
a substrate;
a semiconductor die coupled to an upper surface of the substrate;
conductive wires electrically connecting die pads on an upper surface of the semiconductor die to bond fingers on the upper surface of the substrate;
an encapsulant covering the semiconductor die and the conductive wires, wherein the encapsulant covers only a first part of the semiconductor die and only a first part of the conductive wires leaving a second part of the semiconductor die and a second part of the conductive wires exposed to an exterior of the semiconductor package through a space portion existing at a side of the semiconductor package, wherein the first part of the semiconductor die comprises the upper surface of the semiconductor die and an upper portion of sides of the semiconductor die, wherein the second part of the semiconductor die comprises a lower portion of the sides of the semiconductor die, the encapsulant comprising:
an adhering portion made of thermosetting resin having fluidity in a predetermined temperature range; and
a supporting portion that is located on an upper surface of the adhering portion, the supporting portion supporting the adhering portion, the supporting portion having a lower surface with a total area identical with the total area of the upper surface of the adhering portion, the supporting portion being selected from the group consisting of polyimide and epoxy.
10. The semiconductor package as claimed in claim 9, further comprising a second semiconductor die adhered to the upper surface of the semiconductor die, wherein the encapsulant covers the second semiconductor die.
11. The semiconductor package as claimed in claim 10, wherein the encapsulant covers the entire second semiconductor die and the upper surface of the semiconductor die.
12. The semiconductor package as claimed in claim 10, wherein the second semiconductor die is smaller than the semiconductor die.
13. The semiconductor package as claimed in claim 12, wherein the second semiconductor die is adhered to the upper surface of the semiconductor die inward of the die pads.
14. The semiconductor package as claimed in claim 9, wherein the conductive wires have one end bonded to the die pads in a stitch bonding manner and the other end attached to the bond fingers in a ball bonding manner.
15. A semiconductor package comprising:
a substrate;
a semiconductor die coupled to an upper surface of the substrate;
a second semiconductor die coupled to an upper surface of the semiconductor die;
conductive wires electrically connecting die pads of the semiconductor die and the second semiconductor die to bond fingers on the upper surface of the substrate;
an encapsulant covering at least a part of the second semiconductor die, wherein the encapsulant covers only a first part of the second semiconductor die leaving a second part of the second semiconductor die and the semiconductor die exposed to an exterior of the semiconductor package through a space portion existing at a side of the semiconductor package, wherein the first part of the second semiconductor die comprises an upper surface of the second semiconductor die and an upper portion of sides of the second semiconductor die, wherein the second part of the second semiconductor die comprises a lower portion of the sides of the second semiconductor die, the encapsulant comprising:
an adhering portion made of thermosetting resin having fluidity in a predetermined temperature range; and
a supporting portion that is located on an upper surface of the adhering portion, the supporting portion supporting the adhering portion, the supporting portion having a lower surface with a total area identical with the total area of the upper surface of the adhering portion, the supporting portion being selected from the group consisting of polyimide and epoxy.
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Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090127683A1 (en) * 2007-11-16 2009-05-21 Byung Tai Do Integrated circuit package system with insulator
US20090135296A1 (en) * 2007-11-27 2009-05-28 Hon Hai Precision Industry Co., Ltd. Imaging module package
US7999371B1 (en) 2010-02-09 2011-08-16 Amkor Technology, Inc. Heat spreader package and method
US8072083B1 (en) 2006-02-17 2011-12-06 Amkor Technology, Inc. Stacked electronic component package having film-on-wire spacer
US8143727B2 (en) 2001-03-09 2012-03-27 Amkor Technology, Inc. Adhesive on wire stacked semiconductor package
EP2469613A3 (en) * 2010-12-21 2013-06-05 Panasonic Corporation Light emitting device and illumination apparatus using the same
CN103311204A (en) * 2012-03-06 2013-09-18 特里奎恩特半导体公司 Flip-chip packaging techniques and configurations
CN103390564A (en) * 2012-05-08 2013-11-13 Nxp股份有限公司 Film based IC packaging method and packaged IC device
US8722467B2 (en) * 2012-06-30 2014-05-13 Alpha & Omega Semiconductor, Inc. Method of using bonding ball array as height keeper and paste holder in semiconductor device package
US20140183726A1 (en) * 2012-12-28 2014-07-03 Samsung Electro-Mechanics Co., Ltd. Package substrate, method for manufacturing the same, and package on package substrate
CN106373935A (en) * 2016-10-20 2017-02-01 江苏长电科技股份有限公司 Paddle-free frame package process and package structure
US20180096860A1 (en) * 2016-09-30 2018-04-05 Texas Instruments Incorporated Leadframe Having Organic, Polymerizable Photo-Imageable Adhesion Layer
US10658300B2 (en) 2018-01-17 2020-05-19 Samsung Electronics Co., Ltd. Semiconductor package and semiconductor device including the same
CN112893018A (en) * 2021-02-04 2021-06-04 深圳群芯微电子有限责任公司 Adhesive dispensing packaging device for automobile integrated circuit chip
US11133287B2 (en) 2019-08-20 2021-09-28 SK Hynix Inc. Semiconductor package including stacked semiconductor chips and method for fabricating the same
US20210400805A1 (en) * 2018-12-25 2021-12-23 Uniflex Technology Inc. Substrate structure with high reflectance and method for manufacturing the same
US11862603B2 (en) * 2019-11-27 2024-01-02 Samsung Electronics Co., Ltd. Semiconductor packages with chips partially embedded in adhesive

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140284779A1 (en) * 2013-03-20 2014-09-25 Texas Instruments Incorporated Semiconductor device having reinforced wire bonds to metal terminals
US9799626B2 (en) * 2014-09-15 2017-10-24 Invensas Corporation Semiconductor packages and other circuit modules with porous and non-porous stabilizing layers

Citations (105)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3880528A (en) 1973-07-02 1975-04-29 Tektronix Inc Light probe
US4055761A (en) 1975-03-14 1977-10-25 Nippon Kogaku K.K. Light receiving device for photoelectric conversion element
US4491865A (en) 1982-09-29 1985-01-01 Welch Allyn, Inc. Image sensor assembly
US4567643A (en) 1983-10-24 1986-02-04 Sintra-Alcatel Method of replacing an electronic component connected to conducting tracks on a support substrate
US4763188A (en) 1986-08-08 1988-08-09 Thomas Johnson Packaging system for multiple semiconductor devices
US4896217A (en) 1987-06-10 1990-01-23 Hitachi, Ltd. Solid-state imaging device including a transparent conductor between an optical low-pass filter and an imaging sensor
US4947234A (en) 1986-09-23 1990-08-07 Siemens Aktiengesellschaft Semiconductor component with power MOSFET and control circuit
US4999142A (en) 1988-06-07 1991-03-12 Matsushita Electric Industrial Co., Ltd. Method of molding a lens array
US5012323A (en) 1989-11-20 1991-04-30 Micron Technology, Inc. Double-die semiconductor package having a back-bonded die and a face-bonded die interconnected on a single leadframe
US5023442A (en) 1988-06-21 1991-06-11 Rohm Co., Ltd. Apparatus for optically writing information
US5025306A (en) 1988-08-09 1991-06-18 Texas Instruments Incorporated Assembly of semiconductor chips
US5068713A (en) 1988-08-18 1991-11-26 Seiko Epson Corporation Solid state image sensing device
US5122861A (en) 1988-11-25 1992-06-16 Fuji Photo Film Co., Ltd. Solid state image pickup device having particular package structure
US5220198A (en) 1990-08-27 1993-06-15 Olympus Optical Co., Ltd. Solid state imaging apparatus in which a solid state imaging device chip and substrate are face-bonded with each other
US5274456A (en) 1987-12-28 1993-12-28 Hitachi, Ltd. Semiconductor device and video camera unit using it and their manufacturing method
US5291061A (en) 1993-04-06 1994-03-01 Micron Semiconductor, Inc. Multi-chip stacked devices
US5323060A (en) 1993-06-02 1994-06-21 Micron Semiconductor, Inc. Multichip module having a stacked chip arrangement
US5328079A (en) * 1993-03-19 1994-07-12 National Semiconductor Corporation Method of and arrangement for bond wire connecting together certain integrated circuit components
US5347429A (en) 1990-11-14 1994-09-13 Hitachi, Ltd. Plastic-molded-type semiconductor device
US5365101A (en) 1990-08-31 1994-11-15 Sumitomo Electric Industries, Ltd. Photo-sensing device
US5383034A (en) 1991-09-30 1995-01-17 Rohm Co., Ltd. Image sensor with improved mount for transparent cover
US5400072A (en) 1988-12-23 1995-03-21 Hitachi, Ltd. Video camera unit having an airtight mounting arrangement for an image sensor chip
US5412229A (en) 1990-08-31 1995-05-02 Sumitomo Electric Industries, Ltd. Semiconductor light detecting device making use of a photodiode chip
US5422435A (en) 1992-05-22 1995-06-06 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
US5434682A (en) 1991-09-30 1995-07-18 Rohm Co., Ltd. Image sensor
US5436492A (en) 1992-06-23 1995-07-25 Sony Corporation Charge-coupled device image sensor
US5444520A (en) 1993-05-17 1995-08-22 Kyocera Corporation Image devices
US5463229A (en) 1993-04-07 1995-10-31 Mitsui Toatsu Chemicals, Incorporated Circuit board for optical devices
US5463253A (en) 1990-03-15 1995-10-31 Fujitsu Limited Semiconductor device having a plurality of chips
US5489995A (en) 1992-06-11 1996-02-06 Canon Kabushiki Kaisha Contact type image sensor, producing method of the same, and information processing apparatus
US5523608A (en) 1992-09-01 1996-06-04 Sharp Kabushiki Kaisha Solid state imaging device having a solid state image sensor and its peripheral IC mounted on one package
US5570204A (en) 1993-12-28 1996-10-29 Ricoh Company, Ltd. Image reader with flare prevention using light shield plates
US5581094A (en) 1993-11-18 1996-12-03 Mitsubishi Denki Kabushiki Kaisha Photodetector, a photodector array comprising photodetectors, an object detector comprising the photodetecter array and an object detecting procedure
US5604362A (en) 1995-04-24 1997-02-18 Xerox Corporation Filter architecture for a photosensitive chip
US5617131A (en) 1993-10-28 1997-04-01 Kyocera Corporation Image device having a spacer with image arrays disposed in holes thereof
US5655189A (en) 1994-05-27 1997-08-05 Kyocera Corporation Image device having thermally stable light emitting/receiving arrays and opposing lenses
US5672902A (en) 1987-06-26 1997-09-30 Canon Kabushiki Kaisha Image sensor
US5689135A (en) 1995-12-19 1997-11-18 Micron Technology, Inc. Multi-chip device and method of fabrication employing leads over and under processes
US5696031A (en) 1996-11-20 1997-12-09 Micron Technology, Inc. Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US5715147A (en) 1990-12-20 1998-02-03 Kabushiki Kaisha Toshiba Semiconductor device having an interconnecting circuit board
US5721452A (en) 1995-08-16 1998-02-24 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
US5739581A (en) 1995-11-17 1998-04-14 National Semiconductor Corporation High density integrated circuit package assembly with a heatsink between stacked dies
US5783815A (en) 1995-10-24 1998-07-21 Sony Corporation Light receiving device having lens fitting element
US5804827A (en) 1995-10-27 1998-09-08 Nikon Corporation Infrared ray detection device and solid-state imaging apparatus
US5811799A (en) 1997-07-31 1998-09-22 Wu; Liang-Chung Image sensor package having a wall with a sealed cover
US5815372A (en) 1997-03-25 1998-09-29 Intel Corporation Packaging multiple dies on a ball grid array substrate
US5821532A (en) 1997-06-16 1998-10-13 Eastman Kodak Company Imager package substrate
US5825560A (en) 1995-02-28 1998-10-20 Canon Kabushiki Xaisha Optical apparatus
US5861654A (en) 1995-11-28 1999-01-19 Eastman Kodak Company Image sensor assembly
US5866949A (en) 1996-12-02 1999-02-02 Minnesota Mining And Manufacturing Company Chip scale ball grid array for integrated circuit packaging
US5886412A (en) 1995-08-16 1999-03-23 Micron Technology, Inc. Angularly offset and recessed stacked die multichip device
US5888606A (en) 1994-11-29 1999-03-30 Lintec Corporation Method of preventing transfer of adhesive substance to dicing ring frame, pressure-sensitive adhesive sheet for use in the method and wafer working sheet having the pressure-sensitive adhesive sheet
US5894380A (en) 1995-12-15 1999-04-13 Hitachi, Ltd. Recording/reproducing separation type magnetic head
US5902993A (en) 1992-12-28 1999-05-11 Kyocera Corporation Image scanner for image inputting in computers, facsimiles word processor, and the like
US5904497A (en) 1997-08-22 1999-05-18 Micron Technology, Inc. Method and apparatus for semiconductor assembly which includes testing of chips and replacement of bad chips prior to final assembly
US5932875A (en) 1997-07-07 1999-08-03 Rockwell Science Center, Inc. Single piece integrated package and optical lid
US5952725A (en) 1996-02-20 1999-09-14 Micron Technology, Inc. Stacked semiconductor devices
US5998878A (en) 1995-07-13 1999-12-07 Eastman Kodak Company Image sensor assembly and packaging method
US6005778A (en) 1995-06-15 1999-12-21 Honeywell Inc. Chip stacking and capacitor mounting arrangement including spacers
US6011294A (en) 1996-04-08 2000-01-04 Eastman Kodak Company Low cost CCD packaging
US6011661A (en) 1998-04-07 2000-01-04 Weng; Leo Optical holder for an optical apparatus
US6013948A (en) 1995-11-27 2000-01-11 Micron Technology, Inc. Stackable chip scale semiconductor package with mating contacts on opposed surfaces
US6020582A (en) 1998-03-31 2000-02-01 Intel Corporation Light selective element for imaging applications
US6037655A (en) 1998-01-12 2000-03-14 Eastman Kodak Company Linear image sensor package assembly
US6051886A (en) 1995-08-16 2000-04-18 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
US6057598A (en) 1997-01-31 2000-05-02 Vlsi Technology, Inc. Face on face flip chip integration
US6060722A (en) 1995-05-15 2000-05-09 Havens; William H. Optical reader having illumination assembly including improved aiming pattern generator
US6072232A (en) 1998-10-13 2000-06-06 Intel Corporation Windowed non-ceramic package having embedded frame
US6072243A (en) 1996-11-26 2000-06-06 Sharp Kabushiki Kaisha Semiconductor integrated circuit device capable of surely electrically insulating two semiconductor chips from each other and fabricating method thereof
US6080264A (en) 1996-05-20 2000-06-27 Micron Technology, Inc. Combination of semiconductor interconnect
US6084297A (en) * 1998-09-03 2000-07-04 Micron Technology, Inc. Cavity ball grid array apparatus
US6118176A (en) 1999-04-26 2000-09-12 Advanced Semiconductor Engineering, Inc. Stacked chip assembly utilizing a lead frame
US6122009A (en) 1995-05-31 2000-09-19 Sony Corporation Image pickup apparatus fabrication method thereof image pickup adaptor apparatus signal processing apparatus signal processing method thereof information processing apparatus and information processing method
US6130448A (en) 1998-08-21 2000-10-10 Gentex Corporation Optical sensor package and method of making same
US6133637A (en) 1997-01-24 2000-10-17 Rohm Co., Ltd. Semiconductor device having a plurality of semiconductor chips
US6147389A (en) 1999-06-04 2000-11-14 Silicon Film Technologies, Inc. Image sensor package with image plane reference
US6153927A (en) 1999-09-30 2000-11-28 Intel Corporation Packaged integrated processor and spatial light modulator
US6157080A (en) * 1997-11-06 2000-12-05 Sharp Kabushiki Kaisha Semiconductor device using a chip scale package
US6163076A (en) 1999-06-04 2000-12-19 Advanced Semiconductor Engineering, Inc. Stacked structure of semiconductor package
US6184514B1 (en) 1998-12-18 2001-02-06 Eastman Kodak Company Plastic cover for image sensors
US6215193B1 (en) 1999-04-21 2001-04-10 Advanced Semiconductor Engineering, Inc. Multichip modules and manufacturing method therefor
US6214641B1 (en) 1996-06-25 2001-04-10 Micron Technology, Inc. Method of fabricating a multi-chip module
US6252305B1 (en) 2000-02-29 2001-06-26 Advanced Semiconductor Engineering, Inc. Multichip module having a stacked chip arrangement
US6258626B1 (en) 2000-07-06 2001-07-10 Advanced Semiconductor Engineering, Inc. Method of making stacked chip package
US6316838B1 (en) 1999-10-29 2001-11-13 Fujitsu Limited Semiconductor device
US6326696B1 (en) 1998-02-04 2001-12-04 International Business Machines Corporation Electronic package with interconnected chips
US6333562B1 (en) 2000-07-13 2001-12-25 Advanced Semiconductor Engineering, Inc. Multichip module having stacked chip arrangement
US6339255B1 (en) 1998-10-24 2002-01-15 Hyundai Electronics Industries Co., Ltd. Stacked semiconductor chips in a single semiconductor package
US6340846B1 (en) 2000-12-06 2002-01-22 Amkor Technology, Inc. Making semiconductor packages with stacked dies and reinforced wire bonds
US6351028B1 (en) 1999-02-08 2002-02-26 Micron Technology, Inc. Multiple die stack apparatus employing T-shaped interposer elements
US6359340B1 (en) 2000-07-28 2002-03-19 Advanced Semiconductor Engineering, Inc. Multichip module having a stacked chip arrangement
US6365966B1 (en) 2000-08-07 2002-04-02 Advanced Semiconductor Engineering, Inc. Stacked chip scale package
US6380615B1 (en) 1999-06-29 2002-04-30 Hyundai Electronics Industries Co., Ltd. Chip size stack package, memory module having the same, and method of fabricating the module
US6384472B1 (en) 2000-03-24 2002-05-07 Siliconware Precision Industries Co., Ltd Leadless image sensor package structure and method for making the same
US6384397B1 (en) 2000-05-10 2002-05-07 National Semiconductor Corporation Low cost die sized module for imaging application having a lens housing assembly
US6388313B1 (en) 2001-01-30 2002-05-14 Siliconware Precision Industries Co., Ltd. Multi-chip module
US6387728B1 (en) 1999-11-09 2002-05-14 Advanced Semiconductor Engineering, Inc. Method for fabricating a stacked chip package
US20020130398A1 (en) * 2000-05-19 2002-09-19 Siliconware Precision Industries Co., Ltd. Semiconductor package which has no resinous flash formed on lead frame and method for manufacturing the same
US20030047754A1 (en) * 2001-09-13 2003-03-13 Siliconware Precision Industries Co., Ltd. Multi-chip semiconductor package
US20040051168A1 (en) * 2002-06-25 2004-03-18 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for manufacturing the same
US6713857B1 (en) * 2002-12-05 2004-03-30 Ultra Tera Corporation Low profile stacked multi-chip semiconductor package with chip carrier having opening and fabrication method of the semiconductor package
US20040119152A1 (en) * 2002-10-08 2004-06-24 Chippac, Inc. Semiconductor multi-package module having inverted bump chip carrier second package
US6798049B1 (en) * 1999-08-24 2004-09-28 Amkor Technology Inc. Semiconductor package and method for fabricating the same
US6838761B2 (en) * 2002-09-17 2005-01-04 Chippac, Inc. Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield
US20050179127A1 (en) * 2004-02-13 2005-08-18 Shinya Takyu Stack MCP and manufacturing method thereof

Family Cites Families (74)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3281606A (en) 1963-07-26 1966-10-25 Texas Instruments Inc Small light sensor package
GB2146504A (en) 1983-09-09 1985-04-17 Electronic Automation Ltd Image recording device
WO1993023982A1 (en) 1992-05-11 1993-11-25 Nchip, Inc. Stacked devices for multichip modules
JPH0872086A (en) * 1994-09-02 1996-03-19 Asahi Chem Ind Co Ltd Low-pressure injection molding method
US6498624B1 (en) 1995-02-28 2002-12-24 Canon Kabushiki Kaisha Optical apparatus and image sensing apparatus mounted on the same surface of a board
US6392703B1 (en) 1995-02-28 2002-05-21 Canon Kabushiki Kaisha Optical apparatus for forming an object image on a sensing element
US6583444B2 (en) * 1997-02-18 2003-06-24 Tessera, Inc. Semiconductor packages having light-sensitive chips
JPH10321827A (en) 1997-05-16 1998-12-04 Sony Corp Image-pickup device and camera
JP3988239B2 (en) 1998-03-19 2007-10-10 ソニー株式会社 Solid-state imaging device and manufacturing method thereof
US6762796B1 (en) 1998-08-10 2004-07-13 Olympus Optical Co., Ltd. Image pickup module having integrated lens and semiconductor chip
DE19958229B4 (en) 1998-12-09 2007-05-31 Fuji Electric Co., Ltd., Kawasaki Optical semiconductor sensor device
KR100319608B1 (en) 1999-03-09 2002-01-05 김영환 A stacked semiconductor package and the fabricating method thereof
JP3685947B2 (en) 1999-03-15 2005-08-24 新光電気工業株式会社 Semiconductor device and manufacturing method thereof
KR100384333B1 (en) 1999-06-07 2003-05-16 앰코 테크놀로지 코리아 주식회사 fabrication method of semiconductor chip for semiconductor package from wafer
US6359334B1 (en) 1999-06-08 2002-03-19 Micron Technology, Inc. Thermally conductive adhesive tape for semiconductor devices and method using the same
JP3344372B2 (en) 1999-06-29 2002-11-11 日本電気株式会社 Method for manufacturing semiconductor device
JP2001119006A (en) 1999-10-19 2001-04-27 Sony Corp Imaging device and manufacturing method therefor
US6627864B1 (en) 1999-11-22 2003-09-30 Amkor Technology, Inc. Thin image sensor package
KR20010064907A (en) 1999-12-20 2001-07-11 마이클 디. 오브라이언 wire bonding method and semiconductor package using it
JP3429245B2 (en) 2000-03-07 2003-07-22 沖電気工業株式会社 Semiconductor device and manufacturing method thereof
US6437446B1 (en) 2000-03-16 2002-08-20 Oki Electric Industry Co., Ltd. Semiconductor device having first and second chips
KR100559664B1 (en) 2000-03-25 2006-03-10 앰코 테크놀로지 코리아 주식회사 Semiconductor package
JP2001308262A (en) 2000-04-26 2001-11-02 Mitsubishi Electric Corp Resin-sealed bga type semiconductor device
US6531784B1 (en) 2000-06-02 2003-03-11 Amkor Technology, Inc. Semiconductor package with spacer strips
TW445610B (en) 2000-06-16 2001-07-11 Siliconware Precision Industries Co Ltd Stacked-die packaging structure
US6476475B1 (en) 2000-06-29 2002-11-05 Advanced Micro Devices, Inc. Stacked SRAM die package
TW459361B (en) 2000-07-17 2001-10-11 Siliconware Precision Industries Co Ltd Three-dimensional multiple stacked-die packaging structure
US6472758B1 (en) 2000-07-20 2002-10-29 Amkor Technology, Inc. Semiconductor package including stacked semiconductor dies and bond wires
KR20020015214A (en) 2000-08-21 2002-02-27 마이클 디. 오브라이언 Semiconductor package
US6552416B1 (en) 2000-09-08 2003-04-22 Amkor Technology, Inc. Multiple die lead frame package with enhanced die-to-die interconnect routing using internal lead trace wiring
JP2002093992A (en) 2000-09-13 2002-03-29 Seiko Epson Corp Semiconductor device and manufacturing method therefor
JP3827520B2 (en) * 2000-11-02 2006-09-27 株式会社ルネサステクノロジ Semiconductor device
JP3913481B2 (en) 2001-01-24 2007-05-09 シャープ株式会社 Semiconductor device and manufacturing method of semiconductor device
US6509560B1 (en) 2000-11-13 2003-01-21 Amkor Technology, Inc. Chip size image sensor in wirebond package with step-up ring for electrical contact
JP2002151531A (en) * 2000-11-15 2002-05-24 Matsushita Electric Ind Co Ltd Method for manufacturing semiconductor device
JP4501279B2 (en) 2000-12-27 2010-07-14 ソニー株式会社 Integrated electronic component and method for integrating the same
US6503776B2 (en) 2001-01-05 2003-01-07 Advanced Semiconductor Engineering, Inc. Method for fabricating stacked chip package
TW473951B (en) 2001-01-17 2002-01-21 Siliconware Precision Industries Co Ltd Non-leaded quad flat image sensor package
JP2002222889A (en) 2001-01-24 2002-08-09 Nec Kyushu Ltd Semiconductor device and method of manufacturing the same
KR100401020B1 (en) 2001-03-09 2003-10-08 앰코 테크놀로지 코리아 주식회사 Stacking structure of semiconductor chip and semiconductor package using it
US6603072B1 (en) 2001-04-06 2003-08-05 Amkor Technology, Inc. Making leadframe semiconductor packages with stacked dies and interconnecting interposer
US6437449B1 (en) 2001-04-06 2002-08-20 Amkor Technology, Inc. Making semiconductor devices having stacked dies with biased back surfaces
US6559526B2 (en) 2001-04-26 2003-05-06 Macronix International Co., Ltd. Multiple-step inner lead of leadframe
JP4454181B2 (en) 2001-05-15 2010-04-21 富士通マイクロエレクトロニクス株式会社 Semiconductor device
US6900528B2 (en) 2001-06-21 2005-05-31 Micron Technology, Inc. Stacked mass storage flash memory package
US20030038356A1 (en) 2001-08-24 2003-02-27 Derderian James M Semiconductor devices including stacking spacers thereon, assemblies including the semiconductor devices, and methods
US7518223B2 (en) 2001-08-24 2009-04-14 Micron Technology, Inc. Semiconductor devices and semiconductor device assemblies including a nonconfluent spacer layer
DE10142120A1 (en) 2001-08-30 2003-03-27 Infineon Technologies Ag Electronic component has semiconductor chips whose passive back sides are fastened to top side of carrier substrate and active chip surface, respectively
US6555917B1 (en) 2001-10-09 2003-04-29 Amkor Technology, Inc. Semiconductor package having stacked semiconductor chips and method of making the same
US6514795B1 (en) 2001-10-10 2003-02-04 Micron Technology, Inc. Packaged stacked semiconductor die and method of preparing same
US6620651B2 (en) 2001-10-23 2003-09-16 National Starch And Chemical Investment Holding Corporation Adhesive wafers for die attach application
US20030127719A1 (en) 2002-01-07 2003-07-10 Picta Technology, Inc. Structure and process for packaging multi-chip
US6731011B2 (en) 2002-02-19 2004-05-04 Matrix Semiconductor, Inc. Memory module having interconnected and stacked integrated circuits
US6885093B2 (en) 2002-02-28 2005-04-26 Freescale Semiconductor, Inc. Stacked die semiconductor device
US20030178715A1 (en) 2002-03-20 2003-09-25 Bae Systems Method for stacking chips within a multichip module package
KR20030075860A (en) 2002-03-21 2003-09-26 삼성전자주식회사 Structure for stacking semiconductor chip and stacking method
JP3688249B2 (en) 2002-04-05 2005-08-24 Necエレクトロニクス株式会社 Manufacturing method of semiconductor device
JP3912223B2 (en) 2002-08-09 2007-05-09 富士通株式会社 Semiconductor device and manufacturing method thereof
US6713856B2 (en) 2002-09-03 2004-03-30 Ultratera Corporation Stacked chip package with enhanced thermal conductivity
KR100472286B1 (en) 2002-09-13 2005-03-10 삼성전자주식회사 Semiconductor chip package that adhesive tape is attached on the bonding wire
JP3702961B2 (en) * 2002-10-04 2005-10-05 東洋通信機株式会社 Manufacturing method of surface mount type SAW device
KR100508682B1 (en) 2002-11-20 2005-08-17 삼성전자주식회사 Stack chip package of heat emission type using dummy wire
JP4519398B2 (en) * 2002-11-26 2010-08-04 Towa株式会社 Resin sealing method and semiconductor device manufacturing method
JP2004193363A (en) 2002-12-11 2004-07-08 Fujitsu Ltd Semiconductor device and method of manufacturing the same
JP3689694B2 (en) 2002-12-27 2005-08-31 松下電器産業株式会社 Semiconductor device and manufacturing method thereof
JP4705748B2 (en) 2003-05-30 2011-06-22 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
US6833287B1 (en) 2003-06-16 2004-12-21 St Assembly Test Services Inc. System for semiconductor package with stacked dies
KR100594229B1 (en) 2003-09-19 2006-07-03 삼성전자주식회사 Semiconductor package including a chip or plural chips and method for manufacturing the semiconductor package
JP4381779B2 (en) 2003-11-17 2009-12-09 株式会社ルネサステクノロジ Multi-chip module
JP5197961B2 (en) 2003-12-17 2013-05-15 スタッツ・チップパック・インコーポレイテッド Multi-chip package module and manufacturing method thereof
US6937477B2 (en) 2004-01-21 2005-08-30 Global Advanced Packaging Technology H.K. Limited Structure of gold fingers
JP4434778B2 (en) 2004-02-25 2010-03-17 Necエレクトロニクス株式会社 Semiconductor device
US7205651B2 (en) 2004-04-16 2007-04-17 St Assembly Test Services Ltd. Thermally enhanced stacked die package and fabrication method
US7215031B2 (en) 2004-11-10 2007-05-08 Oki Electric Industry Co., Ltd. Multi chip package

Patent Citations (110)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3880528A (en) 1973-07-02 1975-04-29 Tektronix Inc Light probe
US4055761A (en) 1975-03-14 1977-10-25 Nippon Kogaku K.K. Light receiving device for photoelectric conversion element
US4491865A (en) 1982-09-29 1985-01-01 Welch Allyn, Inc. Image sensor assembly
US4567643A (en) 1983-10-24 1986-02-04 Sintra-Alcatel Method of replacing an electronic component connected to conducting tracks on a support substrate
US4763188A (en) 1986-08-08 1988-08-09 Thomas Johnson Packaging system for multiple semiconductor devices
US4947234A (en) 1986-09-23 1990-08-07 Siemens Aktiengesellschaft Semiconductor component with power MOSFET and control circuit
US4896217A (en) 1987-06-10 1990-01-23 Hitachi, Ltd. Solid-state imaging device including a transparent conductor between an optical low-pass filter and an imaging sensor
US5672902A (en) 1987-06-26 1997-09-30 Canon Kabushiki Kaisha Image sensor
US5274456A (en) 1987-12-28 1993-12-28 Hitachi, Ltd. Semiconductor device and video camera unit using it and their manufacturing method
US4999142A (en) 1988-06-07 1991-03-12 Matsushita Electric Industrial Co., Ltd. Method of molding a lens array
US5023442A (en) 1988-06-21 1991-06-11 Rohm Co., Ltd. Apparatus for optically writing information
US5025306A (en) 1988-08-09 1991-06-18 Texas Instruments Incorporated Assembly of semiconductor chips
US5068713A (en) 1988-08-18 1991-11-26 Seiko Epson Corporation Solid state image sensing device
US5122861A (en) 1988-11-25 1992-06-16 Fuji Photo Film Co., Ltd. Solid state image pickup device having particular package structure
US5400072A (en) 1988-12-23 1995-03-21 Hitachi, Ltd. Video camera unit having an airtight mounting arrangement for an image sensor chip
US5012323A (en) 1989-11-20 1991-04-30 Micron Technology, Inc. Double-die semiconductor package having a back-bonded die and a face-bonded die interconnected on a single leadframe
US5463253A (en) 1990-03-15 1995-10-31 Fujitsu Limited Semiconductor device having a plurality of chips
US5220198A (en) 1990-08-27 1993-06-15 Olympus Optical Co., Ltd. Solid state imaging apparatus in which a solid state imaging device chip and substrate are face-bonded with each other
US5412229A (en) 1990-08-31 1995-05-02 Sumitomo Electric Industries, Ltd. Semiconductor light detecting device making use of a photodiode chip
US5365101A (en) 1990-08-31 1994-11-15 Sumitomo Electric Industries, Ltd. Photo-sensing device
US5347429A (en) 1990-11-14 1994-09-13 Hitachi, Ltd. Plastic-molded-type semiconductor device
US5715147A (en) 1990-12-20 1998-02-03 Kabushiki Kaisha Toshiba Semiconductor device having an interconnecting circuit board
US5383034A (en) 1991-09-30 1995-01-17 Rohm Co., Ltd. Image sensor with improved mount for transparent cover
US5434682A (en) 1991-09-30 1995-07-18 Rohm Co., Ltd. Image sensor
US5422435A (en) 1992-05-22 1995-06-06 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
US5495398A (en) 1992-05-22 1996-02-27 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
US5502289A (en) 1992-05-22 1996-03-26 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
US5489995A (en) 1992-06-11 1996-02-06 Canon Kabushiki Kaisha Contact type image sensor, producing method of the same, and information processing apparatus
US5436492A (en) 1992-06-23 1995-07-25 Sony Corporation Charge-coupled device image sensor
US5523608A (en) 1992-09-01 1996-06-04 Sharp Kabushiki Kaisha Solid state imaging device having a solid state image sensor and its peripheral IC mounted on one package
US5902993A (en) 1992-12-28 1999-05-11 Kyocera Corporation Image scanner for image inputting in computers, facsimiles word processor, and the like
US5328079A (en) * 1993-03-19 1994-07-12 National Semiconductor Corporation Method of and arrangement for bond wire connecting together certain integrated circuit components
USRE36613E (en) 1993-04-06 2000-03-14 Micron Technology, Inc. Multi-chip stacked devices
US5291061A (en) 1993-04-06 1994-03-01 Micron Semiconductor, Inc. Multi-chip stacked devices
US5463229A (en) 1993-04-07 1995-10-31 Mitsui Toatsu Chemicals, Incorporated Circuit board for optical devices
US5444520A (en) 1993-05-17 1995-08-22 Kyocera Corporation Image devices
US5323060A (en) 1993-06-02 1994-06-21 Micron Semiconductor, Inc. Multichip module having a stacked chip arrangement
US5617131A (en) 1993-10-28 1997-04-01 Kyocera Corporation Image device having a spacer with image arrays disposed in holes thereof
US5581094A (en) 1993-11-18 1996-12-03 Mitsubishi Denki Kabushiki Kaisha Photodetector, a photodector array comprising photodetectors, an object detector comprising the photodetecter array and an object detecting procedure
US5570204A (en) 1993-12-28 1996-10-29 Ricoh Company, Ltd. Image reader with flare prevention using light shield plates
US5655189A (en) 1994-05-27 1997-08-05 Kyocera Corporation Image device having thermally stable light emitting/receiving arrays and opposing lenses
US5888606A (en) 1994-11-29 1999-03-30 Lintec Corporation Method of preventing transfer of adhesive substance to dicing ring frame, pressure-sensitive adhesive sheet for use in the method and wafer working sheet having the pressure-sensitive adhesive sheet
US5825560A (en) 1995-02-28 1998-10-20 Canon Kabushiki Xaisha Optical apparatus
US5604362A (en) 1995-04-24 1997-02-18 Xerox Corporation Filter architecture for a photosensitive chip
US6060722A (en) 1995-05-15 2000-05-09 Havens; William H. Optical reader having illumination assembly including improved aiming pattern generator
US6122009A (en) 1995-05-31 2000-09-19 Sony Corporation Image pickup apparatus fabrication method thereof image pickup adaptor apparatus signal processing apparatus signal processing method thereof information processing apparatus and information processing method
US6005778A (en) 1995-06-15 1999-12-21 Honeywell Inc. Chip stacking and capacitor mounting arrangement including spacers
US5998878A (en) 1995-07-13 1999-12-07 Eastman Kodak Company Image sensor assembly and packaging method
US5886412A (en) 1995-08-16 1999-03-23 Micron Technology, Inc. Angularly offset and recessed stacked die multichip device
US5721452A (en) 1995-08-16 1998-02-24 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
US6051886A (en) 1995-08-16 2000-04-18 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
US5783815A (en) 1995-10-24 1998-07-21 Sony Corporation Light receiving device having lens fitting element
US5804827A (en) 1995-10-27 1998-09-08 Nikon Corporation Infrared ray detection device and solid-state imaging apparatus
US5739581A (en) 1995-11-17 1998-04-14 National Semiconductor Corporation High density integrated circuit package assembly with a heatsink between stacked dies
US6013948A (en) 1995-11-27 2000-01-11 Micron Technology, Inc. Stackable chip scale semiconductor package with mating contacts on opposed surfaces
US5861654A (en) 1995-11-28 1999-01-19 Eastman Kodak Company Image sensor assembly
US5894380A (en) 1995-12-15 1999-04-13 Hitachi, Ltd. Recording/reproducing separation type magnetic head
US5689135A (en) 1995-12-19 1997-11-18 Micron Technology, Inc. Multi-chip device and method of fabrication employing leads over and under processes
US5952725A (en) 1996-02-20 1999-09-14 Micron Technology, Inc. Stacked semiconductor devices
US6140149A (en) 1996-02-20 2000-10-31 Micron Technology, Inc. Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US6011294A (en) 1996-04-08 2000-01-04 Eastman Kodak Company Low cost CCD packaging
US6080264A (en) 1996-05-20 2000-06-27 Micron Technology, Inc. Combination of semiconductor interconnect
US6214641B1 (en) 1996-06-25 2001-04-10 Micron Technology, Inc. Method of fabricating a multi-chip module
US5973403A (en) 1996-11-20 1999-10-26 Micron Technology, Inc. Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US5696031A (en) 1996-11-20 1997-12-09 Micron Technology, Inc. Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US6072243A (en) 1996-11-26 2000-06-06 Sharp Kabushiki Kaisha Semiconductor integrated circuit device capable of surely electrically insulating two semiconductor chips from each other and fabricating method thereof
US5866949A (en) 1996-12-02 1999-02-02 Minnesota Mining And Manufacturing Company Chip scale ball grid array for integrated circuit packaging
US6133637A (en) 1997-01-24 2000-10-17 Rohm Co., Ltd. Semiconductor device having a plurality of semiconductor chips
US6057598A (en) 1997-01-31 2000-05-02 Vlsi Technology, Inc. Face on face flip chip integration
US5815372A (en) 1997-03-25 1998-09-29 Intel Corporation Packaging multiple dies on a ball grid array substrate
US5821532A (en) 1997-06-16 1998-10-13 Eastman Kodak Company Imager package substrate
US5932875A (en) 1997-07-07 1999-08-03 Rockwell Science Center, Inc. Single piece integrated package and optical lid
US5811799A (en) 1997-07-31 1998-09-22 Wu; Liang-Chung Image sensor package having a wall with a sealed cover
US5904497A (en) 1997-08-22 1999-05-18 Micron Technology, Inc. Method and apparatus for semiconductor assembly which includes testing of chips and replacement of bad chips prior to final assembly
US6157080A (en) * 1997-11-06 2000-12-05 Sharp Kabushiki Kaisha Semiconductor device using a chip scale package
US6037655A (en) 1998-01-12 2000-03-14 Eastman Kodak Company Linear image sensor package assembly
US6326696B1 (en) 1998-02-04 2001-12-04 International Business Machines Corporation Electronic package with interconnected chips
US6020582A (en) 1998-03-31 2000-02-01 Intel Corporation Light selective element for imaging applications
US6011661A (en) 1998-04-07 2000-01-04 Weng; Leo Optical holder for an optical apparatus
US6130448A (en) 1998-08-21 2000-10-10 Gentex Corporation Optical sensor package and method of making same
US6084297A (en) * 1998-09-03 2000-07-04 Micron Technology, Inc. Cavity ball grid array apparatus
US6072232A (en) 1998-10-13 2000-06-06 Intel Corporation Windowed non-ceramic package having embedded frame
US6339255B1 (en) 1998-10-24 2002-01-15 Hyundai Electronics Industries Co., Ltd. Stacked semiconductor chips in a single semiconductor package
US6184514B1 (en) 1998-12-18 2001-02-06 Eastman Kodak Company Plastic cover for image sensors
US6351028B1 (en) 1999-02-08 2002-02-26 Micron Technology, Inc. Multiple die stack apparatus employing T-shaped interposer elements
US6215193B1 (en) 1999-04-21 2001-04-10 Advanced Semiconductor Engineering, Inc. Multichip modules and manufacturing method therefor
US6118176A (en) 1999-04-26 2000-09-12 Advanced Semiconductor Engineering, Inc. Stacked chip assembly utilizing a lead frame
US6163076A (en) 1999-06-04 2000-12-19 Advanced Semiconductor Engineering, Inc. Stacked structure of semiconductor package
US6147389A (en) 1999-06-04 2000-11-14 Silicon Film Technologies, Inc. Image sensor package with image plane reference
US6380615B1 (en) 1999-06-29 2002-04-30 Hyundai Electronics Industries Co., Ltd. Chip size stack package, memory module having the same, and method of fabricating the module
US6798049B1 (en) * 1999-08-24 2004-09-28 Amkor Technology Inc. Semiconductor package and method for fabricating the same
US6153927A (en) 1999-09-30 2000-11-28 Intel Corporation Packaged integrated processor and spatial light modulator
US6316838B1 (en) 1999-10-29 2001-11-13 Fujitsu Limited Semiconductor device
US6387728B1 (en) 1999-11-09 2002-05-14 Advanced Semiconductor Engineering, Inc. Method for fabricating a stacked chip package
US6252305B1 (en) 2000-02-29 2001-06-26 Advanced Semiconductor Engineering, Inc. Multichip module having a stacked chip arrangement
US6384472B1 (en) 2000-03-24 2002-05-07 Siliconware Precision Industries Co., Ltd Leadless image sensor package structure and method for making the same
US6384397B1 (en) 2000-05-10 2002-05-07 National Semiconductor Corporation Low cost die sized module for imaging application having a lens housing assembly
US20020130398A1 (en) * 2000-05-19 2002-09-19 Siliconware Precision Industries Co., Ltd. Semiconductor package which has no resinous flash formed on lead frame and method for manufacturing the same
US6258626B1 (en) 2000-07-06 2001-07-10 Advanced Semiconductor Engineering, Inc. Method of making stacked chip package
US6333562B1 (en) 2000-07-13 2001-12-25 Advanced Semiconductor Engineering, Inc. Multichip module having stacked chip arrangement
US6359340B1 (en) 2000-07-28 2002-03-19 Advanced Semiconductor Engineering, Inc. Multichip module having a stacked chip arrangement
US6365966B1 (en) 2000-08-07 2002-04-02 Advanced Semiconductor Engineering, Inc. Stacked chip scale package
US6340846B1 (en) 2000-12-06 2002-01-22 Amkor Technology, Inc. Making semiconductor packages with stacked dies and reinforced wire bonds
US6388313B1 (en) 2001-01-30 2002-05-14 Siliconware Precision Industries Co., Ltd. Multi-chip module
US20030047754A1 (en) * 2001-09-13 2003-03-13 Siliconware Precision Industries Co., Ltd. Multi-chip semiconductor package
US20040051168A1 (en) * 2002-06-25 2004-03-18 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for manufacturing the same
US6838761B2 (en) * 2002-09-17 2005-01-04 Chippac, Inc. Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield
US20040119152A1 (en) * 2002-10-08 2004-06-24 Chippac, Inc. Semiconductor multi-package module having inverted bump chip carrier second package
US6713857B1 (en) * 2002-12-05 2004-03-30 Ultra Tera Corporation Low profile stacked multi-chip semiconductor package with chip carrier having opening and fabrication method of the semiconductor package
US20050179127A1 (en) * 2004-02-13 2005-08-18 Shinya Takyu Stack MCP and manufacturing method thereof

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
Oh et al., "A Stacked Semiconductor Package Having an Insulator to Prevent Shorting of Wirebonds", U.S. Appl. No. 10/015,374, filed Dec. 12, 2001.
Oh et al., "Adhesive on Wire Stacked Semiconductor Package", U.S. Appl. No. 12/317,649. filed Dec. 23,2008.
Oh et al., "Method of Forming a Stacked Semiconductor Package", U.S. Appl. No. 11/286,970, filed Nov. 22, 2005.
St. Amand et al., U.S. Appl. No. 11/356,919, entitled "Stacked electronic component package having single-sided film spacer", filed Feb. 17, 2006.
St. Amand et al., U.S. Appl. No. 11/356,921, entitled "Stacked electronic component package film-on-wire spacer", filed Feb. 17, 2006.

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8143727B2 (en) 2001-03-09 2012-03-27 Amkor Technology, Inc. Adhesive on wire stacked semiconductor package
US8072083B1 (en) 2006-02-17 2011-12-06 Amkor Technology, Inc. Stacked electronic component package having film-on-wire spacer
US20090127683A1 (en) * 2007-11-16 2009-05-21 Byung Tai Do Integrated circuit package system with insulator
US8049314B2 (en) * 2007-11-16 2011-11-01 Stats Chippac Ltd. Integrated circuit package system with insulator over circuitry
US20090135296A1 (en) * 2007-11-27 2009-05-28 Hon Hai Precision Industry Co., Ltd. Imaging module package
US7999371B1 (en) 2010-02-09 2011-08-16 Amkor Technology, Inc. Heat spreader package and method
US8441120B1 (en) 2010-02-09 2013-05-14 Amkor Technology, Inc. Heat spreader package
US8592836B2 (en) 2010-12-21 2013-11-26 Panasonic Corporation Light emitting device and illumination apparatus using same
EP2469613A3 (en) * 2010-12-21 2013-06-05 Panasonic Corporation Light emitting device and illumination apparatus using the same
CN103311204A (en) * 2012-03-06 2013-09-18 特里奎恩特半导体公司 Flip-chip packaging techniques and configurations
CN103390564A (en) * 2012-05-08 2013-11-13 Nxp股份有限公司 Film based IC packaging method and packaged IC device
US8722467B2 (en) * 2012-06-30 2014-05-13 Alpha & Omega Semiconductor, Inc. Method of using bonding ball array as height keeper and paste holder in semiconductor device package
US20140183726A1 (en) * 2012-12-28 2014-07-03 Samsung Electro-Mechanics Co., Ltd. Package substrate, method for manufacturing the same, and package on package substrate
US20180096860A1 (en) * 2016-09-30 2018-04-05 Texas Instruments Incorporated Leadframe Having Organic, Polymerizable Photo-Imageable Adhesion Layer
US10672692B2 (en) * 2016-09-30 2020-06-02 Texas Instruments Incorporated Leadframe having organic, polymerizable photo-imageable adhesion layer
CN106373935A (en) * 2016-10-20 2017-02-01 江苏长电科技股份有限公司 Paddle-free frame package process and package structure
CN106373935B (en) * 2016-10-20 2019-04-16 江苏长电科技股份有限公司 A kind of island-free framework encapsulation technique and its encapsulating structure
US10658300B2 (en) 2018-01-17 2020-05-19 Samsung Electronics Co., Ltd. Semiconductor package and semiconductor device including the same
US20210400805A1 (en) * 2018-12-25 2021-12-23 Uniflex Technology Inc. Substrate structure with high reflectance and method for manufacturing the same
US11133287B2 (en) 2019-08-20 2021-09-28 SK Hynix Inc. Semiconductor package including stacked semiconductor chips and method for fabricating the same
US11862603B2 (en) * 2019-11-27 2024-01-02 Samsung Electronics Co., Ltd. Semiconductor packages with chips partially embedded in adhesive
CN112893018A (en) * 2021-02-04 2021-06-04 深圳群芯微电子有限责任公司 Adhesive dispensing packaging device for automobile integrated circuit chip
CN112893018B (en) * 2021-02-04 2021-12-21 深圳群芯微电子有限责任公司 Adhesive dispensing packaging device for automobile integrated circuit chip

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