US7636267B2 - Semiconductor memory device - Google Patents
Semiconductor memory device Download PDFInfo
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- US7636267B2 US7636267B2 US11/645,174 US64517406A US7636267B2 US 7636267 B2 US7636267 B2 US 7636267B2 US 64517406 A US64517406 A US 64517406A US 7636267 B2 US7636267 B2 US 7636267B2
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/025—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in signal lines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/005—Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
Definitions
- the present invention relates to a semiconductor memory device, and in particular to a semiconductor memory device having a test mode for screening the semiconductor memory device.
- the semiconductor memory device has recently been making further progress in increase of the capacity and the operation speed of semiconductor devices. Along with such progress, the configuration within the semiconductor device has been more refined and the voltage has been decreased. These semiconductor memory devices are provided to customers after defective products are screened out by subjecting produced semiconductor wafers to wafer testing and subjecting packaged devices to a screening test. However, defects may occur which are difficult to find by the wafer test or screening test.
- bit-line to bit-line short defect of memory cells Even if there is a short between bit lines, it will be very difficult to detect if the resistance value of the short is high. Additionally, a long test time is required to detect the short.
- the resistance value at a part having the bit-line to bit-line short will be decreased to cause increase of leak current while the electronic equipment is used by the customer. Therefore, it is urgently desired to develop a technique capable of detecting a high resistance short in a screening test.
- Patent Publication 1 Japanese Laid-Open Patent Publication No. 2002-074995 for example relates to the bit-line to bit-line short defects.
- a defect detection method disclosed in this patent publication will be briefly described with reference to FIGS. 1 and 2 .
- FIG. 1 is connection diagram showing components relating to memory bit lines in a semiconductor memory device, and FIG. 2 is a timing chart thereof.
- the memory arrays shown in FIG. 1 employ shared type sense amplifiers, whose connection with the bit lines is controlled by transfer gates TG.
- the shared type sense amplifiers exchange data with memory cells by switching and connecting bit lines of a selected memory array by means of the transfer gates TG.
- the transfer gates TGL and TGR are activated and connected to the sense amplifiers SA.
- a transfer gate TGL 0 or TGR 0 is activated and connected to the sense amplifier SA.
- FIG. 2A shows a timing chart of a first embodiment of the prior art
- FIG. 2B shows a timing chart of a second embodiment of the prior art
- FIGS. 2A and 2B illustrate signal waveforms of (a) a command, (b) a bank control signal, (c) a memory array selection signal, (d) a word line, (e) the transfer gates (f) the sense amplifier, (g) the first bit line, and (h) the second bit line.
- the description here will be made of a case where bit-line to bit-line short has occurred between the first and second bit lines (BL 1 and BL 2 ).
- the detection of high resistance short is carried out as follows:
- the transfer gates TGR and TGL are turned OFF by the falling edge of a write (or read) command with the word line kept in the selected state. This state is kept for a predetermined time and then changed to the pre-charge state after the word line is placed in the non-selected state.
- the implementation of the prior art involves two major problems.
- One of the problems relates to the fact that, in short detection, the transfer gates TG or the sense amplifiers SA are turned off to render the bit lines floating, and the charges in the bit lines are charged or discharged, and canceled with each other by resistance shorting between the bit lines which are in the floating state.
- the charge/discharge time is determined based on a time constant ⁇ that is determined by the value of the shorting resistance and the capacity of the bit lines.
- the resistance value is originally high, and hence the time constant ⁇ becomes a large time constant. This means that it takes a long time to detect the bit-line to bit-line short.
- the resistance value including variations thereof, must be estimated preliminarily in the course of designing.
- Another problem relates to the fact that it is uncertain whether the intermediate level of the memory cell is determined to be either high level or low level by the sense amplifier SA.
- the sense amplifier SA always determines unambiguously whether the level is high or low. In the case of the intermediate level, however, it is ambiguous whether the bit lines are determined to be either high level or low level depending on the offset of the sense amplifier SA and surrounding noises. This makes it difficult to obtain reliable defect detection results. In this manner, the difficulty to produce a difference in potential between adjacent bit lines induces a problem that the detection sensitivity is low.
- the detection sensitivity is low due to the difficulty to produce a difference in potential between adjacent bit lines.
- the prior art is not free of the problem the difficulty in detection of the bit-line to bit-line short.
- the conventional semiconductor memory devices have problems that the bit-line to bit-line short in a memory cell is difficult to detect due to its large resistance value, and a long test time is required.
- a semiconductor memory device employing shared type sense amplifiers, the semiconductor memory device having a test mode for detecting a bit-line to bit-line short by placing in the high impedance state a first bit line connected to a first sense amplifier arranged on a first side of a selected memory array, while placing in the low impedance state a second bit line connected to a second sense amplifier arranged on a second side of the selected memory array opposing the first side.
- the first and second bit lines are controlled programmable by means of addresses and commands which are input externally.
- the first and second bit lines are arranged adjacent to each other, and a memory cell is written such that the first and second bit lines assume opposite logic levels.
- a first transfer gate arranged between the first sense amplifier and the first bit line is turned OFF while a second transfer gate arranged between the second sense amplifier and the second bit line is turned ON, and the first bit line is inverted by the second sense amplifier if there is a short between the first and the second bit lines to enable detection of the bit-line to bit-line short.
- Pre-charge operation and read operation are performed after detection of the bit-line to bit-line short.
- the first sense amplifier may be placed in the OFF state while the second sense amplifier in the ON state, the first bit line being in the pre-charge state, and the second bit line being made to undergo a full amplitude by the second sense amplifier.
- the first bit line is in the high impedance state while the second bit line is made to undergo a full amplitude by the second sense amplifier, and if there is a short between the first and second bit lines, the first bit line is inverted by the second sense amplifier to enable detection of the bit-line to bit-line short.
- the present invention provides a semiconductor memory device comprising a first sense amplifier shared by a first memory array and a second memory array, a second sense amplifier shared by a first memory array and a third memory array, wherein:
- the high impedance state and the low impedance state may be made by setting the first switch non-conductive and the second switch conductive for a predetermined time.
- Cell data is written into memory cells such that the first and second bit lines assume opposite logic levels.
- Cell data is read from the memory cells to see if there is an inversion of a written logic level.
- the present invention provides a method of identifying short in lines in memory arrays of a semiconductor memory device comprising a first sense amplifier shared by a first memory array and a second memory array, a second sense amplifier shared by a first memory array and a third memory array, the first semiconductor memory array comprises a first complementary bit line pair connected to the first sense amplifier via a first switch, a second complementary bit line pair connected to the second sense amplifier via a second switch, a bit line of the second complementary bit line pair being arranged adjacent to a bit line of the first complementary bit line pair,
- an object bit line is placed in the high impedance state.
- the opposing sense amplifier is left active to place the adjacent bit line in the low impedance state. If there is a bit-line to bit-line short, data on the object bit line in the high impedance state is inverted from the adjacent bit line in the low impedance state. The bit-line to bit-line short can be detected by reading the inverted data.
- the programmable control makes it possible to control the defect detection time according to a type of products and thus to appropriately adjust the defect detection sensitivity according to each type of products. This means that the necessity of estimating variation in leak resistance is eliminated. Moreover, advantageous effects can be obtained that the circuit configuration is very simple, the detection speed is high, and the detection sensitivity is high.
- FIG. 1 is a diagram illustrating connections in the periphery of bit lines according to the prior art
- FIGS. 2A and 2B are timing charts of the components shown in FIG. 1 ;
- FIG. 3 is a general configuration diagram of a DRAM
- FIG. 4 is a diagram illustrating configuration in the periphery of memory arrays according to a first embodiment of the present invention
- FIG. 5 is a timing chart illustrating operation in the test mode according to the first embodiment
- FIG. 6 is a diagram illustrating connections in the periphery of bit lines according to the first embodiment
- FIG. 7 is a timing chart illustrating operation in the normal mode of the circuit shown in FIG. 4 ;
- FIG. 8 is a diagram illustrating connections in the periphery of bit lines according to a second embodiment.
- FIG. 9 is an operation in the test mode according to the second embodiment.
- FIG. 3 is a general configuration diagram showing a dynamic random access memory (DRAM) as an example of a semiconductor memory device.
- FIG. 4 is a circuit diagram of the periphery of memory cells according to the first embodiment.
- FIG. 5 is a timing chart in the test mode.
- FIG. 6 is a diagram illustrating connections relating to bit lines.
- FIG. 7 is a timing chart in the normal mode.
- DRAM dynamic random access memory
- the DRAM includes a memory array 8 having a plurality of memory array banks built-in, a row decoder 9 , a colurn decoder 11 , a sense amplifier 10 .
- the DRAM also includes a row address buffer and refresh counter 5 , a column address buffer and burst counter 6 , a data control circuit 12 , a latch circuit 13 , an input and output buffer 14 , a mode register 2 , a command decoder 3 , a control logic circuit 4 , a clock generator 1 and a delayed lock loop (DLL) 7 .
- DLL delayed lock loop
- the DRAM externally receives clock signals CK and /CX, a clock enable signal CKE, address signals A 0 to A 12 , bank address signals BA 0 and BA 1 , a chip select signal /CS, a row address strobe signal /RAS, a column address strobe signal /CAS, a write enable signal /WE, a data signal DQ, data strobe signals DQS and /DQS, an on-die termination signal ODT, and a data mask signal DM.
- the clock generator 1 generates an internal clock and supplies the clock to various internal circuits to synchronize the operation thereof.
- the command decoder 3 receives the chip select signal /CS, row enable /RAS, column enable /CAS and write enable /WE inputs. The command decoder 3 recognizes various commands depending on the inputs thereto. The command decoder outputs the command to the control logic 4 which controls the operation of the other components of the DRAM based on the received command. These commands includes, for example, a write command, a read command, a pre-charge command, an active command and a mode register set command.
- the control logic 6 causes the mode register 2 to latch the address data or address inputs: A 0 -A 12 and BA 0 -BA 1 .
- the data on address inputs A 0 -A 12 and BA 0 -BA 1 do not represent addresses.
- the address inputs and the data thereon will generally be referred to as address inputs.
- the mode register 2 recognizes address input A 7 as a test mode during the mode register set operation.
- the control logic 4 controls the components of the memory device according to this setting. Accordingly, the data supplied on address input during the mode register set operation are also command data.
- control logic circuit 4 In response to the internal clock signal from the clock generator 1 , the control logic circuit 4 generates a control signal on the basis of the outputs from the command decoder 3 and the mode register 2 . This control signal is supplied to the row address buffer and refresh counter 5 , the column address buffer and burst counter 6 , the row decoder 9 , the sense amplifier 10 , the data control circuit 12 , and the latch circuit 13 .
- the row address buffer and refresh counter 5 controls the row decoder 9
- the column address buffer and burst counter 6 controls the column decoder 11
- the DLL 7 generates a clock for data input and output to control the input/output buffer 14 .
- the memory array 8 has the row decoder 9 , the sense amplifier 10 , and the column decoder 11 in the periphery thereof, and exchanges data in a selected memory cell with input/output circuits.
- the memory array 8 has four banks 0 to 3 , and each bank has a plurality of memory sub-arrays (for which simply memory arrays are interchangeably used herein).
- the data control circuit 12 and the latch circuit 13 temporarily store data and control the timing at which data is externally input or output.
- the write or read operation in the overall configuration described above is the same as the prior art operation, and therefore the detailed description thereof is omitted.
- the present invention features the provision of an additional control circuit 15 for a test mode in addition to the control logic circuit 4 to be described later.
- a combination of the additional control circuit 15 and the control logic circuit is hereinafter called a control logic circuit 41 .
- FIG. 4 schematically illustrates a portion of memory arrays, a portion of peripheral circuits, and the control logic circuit 41 .
- the portion of the memory arrays includes a first memory array 410 at the center, a second memory array 412 on the left, and a third memory array 411 on the right.
- the first memory array 410 has a plurality of bit line (column line) pairs and a plurality of word lines (row lines) arranged in a row-column fashion.
- a plurality of memory cells each having a storage capacitor and a MOS transistor are connected to each of bit line pairs, and gates of the transistors are connected to word lines.
- FIG. 4 only part of bit line pairs, word lines and memory cells is illustrated for simplification. That is, a first pair of complementary bit lines BL 1 , /BL 1 , a second pair of complementary bit lines BL 2 , /BL 2 , two word lines and two memory cells are shown.
- the first bit line pairs are connected to a pre-charge circuit of transistors T 5 , T 6 and T 7 which is adapted to pre-charge bit line pair.
- the first bit line pair is also connected to a sense amplifier SAL by way of transfer gate transistors T 1 , T 2 .
- the transfer gate transistors are switched by a gate signal TGL appearing on a line TGL while the pre-charge circuit is controlled by a pre-charge control signal BLEQL on a pre-charge control line BLEQL. It should be noted herein that in the description, the same sign is used to indicate a transfer gate, a gate signal for the transfer gate, and a line on which the gate signal appears. Similar expression is used in other parts.
- the sense amplifier SAL is shared by the second memory array 412 which is connected via transfer gate transistors T 01 , T 02 to the amplifier and is similar in configuration to the center memory array 410 .
- the second bit line pair is connected to a pre-charge circuit of transistors T 8 , T 9 , T 10 for pre-charging the second bit line pair.
- the second bit line pairs is also connected to a sense amplifier SAR by way of transfer gates, or gate transistors, T 3 , T 4 .
- the transfer gates are switched by a gate signal TGR appearing on a line TGR while the pre-charge circuit is controlled by a pre-charge control signal BLEQR on a pre-charge control line BLEQR.
- the sense amplifier SAR is shared by the third (right) memory array 411 which is connected via transfer gates, or transistors, T 03 , T 04 to the amplifier and is also similar in configuration to the center memory array 410 .
- the control logic circuit 41 of FIG. 4 includes a conventional control logic 4 and an additional control logic circuit 15 which provides gate signals on the lines TGL, TGR and the pre-charge control lines BLEQL, BLEQR depending on a normal mode and a test mode.
- the provision of the additional control circuit provides in a test mode a unique switching of connections of bit-line pairs to sense amplifiers by controlling the pre-charge circuit and the transfer gates.
- the additional control logic circuit 15 In the test mode, the additional control logic circuit 15 generates control signals for separately controlling the left-side and right-side transfer gate transistors T 1 , T 2 and T 3 , T 4 and pre-charge circuits 432 , 431 .
- the left-side transfer gate transistors T 1 , T 2 are controlled by a gate signal TGL generated by first and second transfer control signals TGL 1 and TGL 2 .
- the right-side transfer gates T 3 , T 4 are controlled by a gate signal TGR generated by first and second transfer control signals TGR 1 and TGR 2 .
- the left-side pre-charge circuit 432 is controlled by the pre-charge control signal BLEQL generated by a pre-charge control signal BLEQL 1 .
- the right-side pre-charge circuit 431 is controlled by a pre-charge control signal BLEQL generated by a pre-charge control signal BLEQR 1 .
- the suffixes “L” and “R” are used to distinguish the left side and the right of the memory array. No such suffix is added when the memory array is referred to as a whole.
- Each memory array has sense amplifiers SAL and SAR, and pre-charge circuits for pre-charging bit lines on the left and right sides thereof, respectively.
- the memory array further has transfer gates for selecting bit lines of the memory array connected to the sense amplifiers.
- the bit lines are arranged such that the bit lines are alternately connected to the left and right sense amplifiers SAL and SAR arranged on the left and right sides to face each other.
- the bit lines connected to the left-side sense amplifier and the bit lines connected to the right-side sense amplifier are arranged alternately, for example in the sequence of a left-side bit line BL 1 , a right-side bit line BL 2 , a left-side bit line /BL 1 , and a right-side bit line /BL 2 .
- the transfer gate transistors TG select and switch a bit line pair of the memory array connected to the sense amplifiers SA.
- Transfer gate transistors T 1 and T 2 connected to the left-side sense amplifier SAL are controlled by a gate signal TGL.
- Transistors T 5 , T 6 , and T 7 forming the left-side pre-charge circuit are controlled by a pre-charge control signal BLEQL.
- transfer gate transistors T 3 and T 4 connected to the right-side sense amplifier SAR are controlled by a gate signal TGR.
- Transistors T 8 , T 9 , and T 10 forming the right-side pre-charge circuit are controlled by a pre-charge control signal BLEQR.
- the central memory array is the selected memory array.
- the outside gate signals TGL 0 and TGR 0 are inactive, and the left-side and right-side memory arrays are non-selected memory arrays.
- the address signal is input to the control logic 4 via the mode register 2
- the command signal is input to the control logic 4 via the command decoder 3 .
- the control logic 4 logically processes these input signals to generate gate signals TGL and TGR, and pre-charge control signals BLEQL and BLEQR.
- the additional control circuit 15 controls the normal mode and the test mode by means of the logically processed signals.
- the transfer control signals TGL 1 and TGR 1 are test mode entry signals in the test mode, while the transfer control signals TGL 2 and TGR 2 are gate signals in the normal mode.
- FIG. 7 is a timing chart of the normal mode. Shown in FIG. 7 are signal waveforms of (a) a command, (b) a word line, (c) a transfer gate signal, and (d) a bit line.
- a memory array is selected by a command ACT, and one word line in the selected array is selected.
- the transfer control signals TGL 1 and TGR 1 are both at a high level, and the transfer control signals TGL 2 and TGR 2 are both at a low level.
- the gate signals TGL and TGR thus become a high level.
- the transfer gate transistors T 1 , T 2 and T 3 , T 4 are in the ON state.
- the gate signals TGL 0 and TGR 0 change to the low level state to disconnect the neighboring memory arrays from the sense amplifiers.
- the control logic circuit 4 renders the pre-charge control signals BLEQL and BLEQR inactive and the pre-charge transistors are turned off.
- the potential of the bit lines is amplified by the sense amplifiers SA to enable writing or reading of data in response to the Write/Read command.
- the selected word line is rendered inactive.
- the gate signals TGL 0 and TGR 0 are rendered active and the pre-charge control signals BLEQL and BLEQR are also changed to the active state to pre-charge the bit lines.
- Illustrated in FIG. 5 are signal waveforms of (a) the command, (b) the word line, (c) the sense amplifier, (d) the gate signal TGL, (e) the gate signal TGR, (f) the pre-charge signal, (g) the object bit lines, and (h) the adjacent bit lines.
- the waveforms of the bit lines are represented as those of a complementary bit line pair.
- data is written in the memory cells by the same operation as in the normal mode.
- a high level is written in the cell connected to the object bit line /BL 1
- a low level is written in the cell connected to the adjacent bit line BL 2 neighboring to the object bit line /BL 1
- mutually inverted data is written in the bit lines BL 2 and /BL 1 for which the bit-line to bit-line short is to-be detected.
- a pre-charge operation is performed according to a command Pre.
- a word line is selected, and the sense amplifiers amplify the respective cell data, respectively.
- a command MRS mode resister set
- the gate signal TGR is left at a high level in the same manner as in the normal mode.
- the transfer gate control signal TGL 1 is changed to a low level, and the transfer control signal TGL 2 is at a low level.
- the gate control signal TGL is thus changed to a low level. Consequently, the transfer gate transistors T 3 and T 4 are turned ON, while the transfer gate transistors T 1 and T 2 are turned OFF.
- the bit line pair BL 1 and /BL 1 is disconnected from the sense amplifier SAL by the transfer gate transistors T 1 and T 2 being turned OFF, and becomes the floating state (the high impedance state).
- the transfer gate transistors T 3 and T 4 are in the ON state, and the bit line pair BL 2 and /BL 2 remains in the amplified state by the sense amplifier SAR (the low impedance state).
- the state in which the bit line /BL 1 is disconnected from the sense amplifier SAL to become the floating state shall be defined as the high impedance state of the bit line /BL 1 .
- the state in which the bit line BL 2 is connected to the sense amplifier SAR and the sense amplifier is connected to the power supply shall be defined as the low impedance state of the bit line BL 2 .
- the sense amplifier SAR and the bit line pair BL 2 and /BL 2 undergo a full amplitude at low impedance. If there is a bit-line to bit-line short between the bit lines /BL 1 and BL 2 , the charge stored in the bit line /BL 1 in the floating state will be rapidly pulled out by the difference in potential with the adjacent bit line BL 2 .
- the object bit line /BL 1 is changed from a high level to a low level, and thus, the data indicating the low level is restored into the selected memory cell.
- a pre-charge operation is performed in accordance with a command Pre.
- a command ACT is input, and the read operation is performed in response to a subsequent read command.
- an expected high level is read as a low level, which makes it possible to detect a bit-line to bit-line short defect. If there is no bit-line to bit-line short, the original correct data will be restored with no charge being pulled out of the bit line pair BL 1 and /BL 1 . Thus, the correct data is read in the subsequent read cycle.
- bit-line to bit-line short between the object bit line /BL 1 and the adjacent and opposing bit line BL 2 is detected as described above. Further, a short between the object bit line /BL 1 and the non-selected word line (0 V), if any, can be detected simultaneously.
- the non-selected word line is fixed at a low level and hence in the low impedance state. Therefore, if there is a short, the charge in the bit line/BL 1 can be pulled out to a low level, and thus the short can be detected similarly to the bit-line to bit-line short.
- the short can be detected similarly by writing the initial write data at a high level in the object bit line /BL 1 and at a low-level in the bit line /BL 2 .
- the write level of the bit line for which a short is to be detected is set at a different level from neighboring bit lines.
- Transfer gates used in a conventional shared type sense amplifier are operated simultaneously and cannot be operated separately as long as the selected memory array is the same. In the present invention, however, the entry to the test mode enables the programmable control of the gate signals TGR and TGL. That is, the left and right transfer gates are separately controlled by means of the gate signals TGR and TGL.
- the transfer gates on either the left-side or the right-side with respect to the selected memory array are controlled in a different manner from normal operation.
- One pair of bit line pairs respectively connected to opposing sense amplifiers, namely the object bit line pair is rendered high impedance, while the other bit line pair is rendered low impedance by activating the sense amplifier. If there is leakage due to a bit-line to bit-line short, the current will leak from the high impedance to the low impedance, resulting in change in the bit line level.
- the sense amplifier of the other opposing bit line pair is connected to the power supply while remaining active and in the low impedance state, it takes a short time to detect the bit-line to bit-line short. Accordingly, it is possible to substantially reduce the period of time that is conventionally defined by a time constant determined by the resistance value and the bit line capacity, and hence the test time can be shortened.
- the bit lines are connected to the sense amplifiers and caused to undergo a full amplitude at low impedance. This produces a difference in potential between the object bit line and the adjacent bit line, and enhances the short detection sensitivity.
- the time constant is denoted by ⁇ , 0.4 ⁇ will be sufficient to exceed an intermediate level.
- One pair of the transfer gates are turned OFF while the other pair of the transfer gates are left ON, whereby the difference in potential between the object bit line and the adjacent bit line can be increased to improve the sensitivity to detect a bit-line to bit-line short.
- the transfer gates are turned OFF at timing after elapse of a specific time from the falling edge of a write command.
- the transfer gates can be controlled by an external command and hence can be controlled programmably. It is made possible to control the defect detection time according to each type of products by changing the timings of commands MRS, Pre, and ACT to be programmable. Therefore, the defect detection sensitivity also can be adjusted appropriately according to each type of products. This means that the necessity of estimating variation in resistance of the bit-line to bit-line short is eliminated.
- entry is made to the test mode and the transfer gates used in the shared type sense amplifier are controlled individually.
- the transfer gate connected to the object bit line is turned OFF and placed in the floating state (high impedance state).
- the opposing sense amplifier is left active and thereby placed in the low impedance state. If there is a bit-line to bit-line short, the data on the object bit line in the floating state is inverted by the adjacent bit line in the low impedance state. The bit-line to bit-line short can be detected by reading this inverted data.
- a bit-line to bit-line short is detected by turning OFF the sense amplifier on the side of an object bit line during and after a pre-charge period to produce the high impedance state, while placing the opposing sense amplifier in the ON state.
- FIG. 9 is a connection diagram relating to bit lines of the second embodiment and illustrates a portion oflthe center memory array and its related circuitry shown in FIG. 4 , and FIG. 8 shows a timing chart.
- signal waveforms are shown of (a) a command, (b) a word line, (c) a sense amplifier, (d) a transfer gate signal, (e) a pre-charge signal, and (f) an object bit line.
- a high level is written in the object bit line /BL 1 for which a bit-line to bit-line short is to be detected.
- the write level is not limited to a high level, and may be set, similarly to the first embodiment, such that the bit lines to be detected are at different levels from each other.
- entry is made to the test mode in response to a command MRS.
- This command MRS keeps the sense amplifier SAR active until receiving a subsequent pre-charge command Pre.
- the pre-charge signal BLEQR is kept inactive until the subsequent pre-charge period.
- the sense amplifier SAL is turned OFF, putting the bit line pair BL 1 and /BL 1 into the high impedance state.
- the pre-charge operation here is performed only on the left-side bit line pair BL 1 and /BL 1 which are in the floating state with the pre-charge signal BLEQL being at a high level and the pre-charge signal BLEQR being at a low level. Accordingly, the bit line pair BL 1 and /BL 1 is pre-charged to a pre-charge voltage HVDL.
- the opposing bit line pair BL 2 and /BL 2 is not pre-charged but is made to undergo a full amplitude by the sense amplifier SAR.
- the voltage HVDL on the bit line/BL 1 is slightly reduced by the low level (0 V) of the bit line BL 2 .
- the voltage thus reduced depends on the difference in the drive capacity between the pre-charge circuit and the sense amplifier SAR.
- a subsequent command ACT is input, whereby the gate signal TGL is changed to a high level and the pre-charge signal BLEQL is changed to a low level to turn OFF the pre-charge circuit.
- the turning OFF of the pre-charge circuit places the bit line pair BL 1 and /BL 1 in the complete high impedance state.
- the bit line pair BL 1 and /BL 1 is made to undergo a full amplitude by the sense amplifier SAR in the same manner as the bit line pair BL 2 and /BL 2 .
- bit line pair BL 1 and /BL 1 is made to undergo a full amplitude and held in the inverted state by a bit-line to bit-line short.
- the bit-line to bit-line short is detected by fail data being read out by the input of the read command.
- the bit line pair BL 1 and /BL 1 is pre-charged to a pre-charge voltage HVDL. Thus, correct data is read out.
- a bit-line to bit-line short is detected if any in response to the command MRS after the pre-charge.
- the object bit line is pre-charged to the high impedance state, while the sense amplifier of the opposing adjacent bit line is rendered active in the low impedance state.
- the bit-line to bit-line short can be detected efficiently by activating the opposing sense amplifier to place the same in the low impedance state.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Dram (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
Abstract
Description
-
- the first semiconductor memory array comprises a first complementary bit line pair connected to the first sense amplifier via a first switch, a second complementary bit line pair connected to the second sense amplifier via a second switch, a bit line of the second complementary bit line pair being arranged adjacent to a bit line of the first complementary bit line pair,
- word lines for selecting memory cells, and
- control circuit for controlling the first switch and the second switch, and wherein:
- a bit line to bit line short is detected by putting the first bit line pair into a high impedance state and the second bit line pair into a low impedance state in response to a test mode set command.
-
- the method comprising steps of:
- writing cell data into memory cells so that the first and second bit lines assume opposite logic levels,
- putting the first bit line pair into a high impedance state and the second bit line pair into a low impedance state in response to a test mode set command, and
- reading cell data from the memory cells to see if there is an inversion of a written logic level.
Claims (18)
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JP2005376501A JP2007179639A (en) | 2005-12-27 | 2005-12-27 | Semiconductor memory device |
JP2005-376501 | 2005-12-27 |
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US20070183232A1 US20070183232A1 (en) | 2007-08-09 |
US7636267B2 true US7636267B2 (en) | 2009-12-22 |
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US11/645,174 Expired - Fee Related US7636267B2 (en) | 2005-12-27 | 2006-12-26 | Semiconductor memory device |
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JP (1) | JP2007179639A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090262590A1 (en) * | 2002-05-29 | 2009-10-22 | Elpida Memory, Inc. | Semiconductor memory device |
US20110273951A1 (en) * | 2010-05-10 | 2011-11-10 | Hung-Yu Li | Memory circuit and method for controlling memory circuit |
US8947960B2 (en) * | 2013-04-05 | 2015-02-03 | Winbond Electronics Corp. | Semiconductor storage with a floating detection circuitry and floating detection method thereof |
TWI484496B (en) * | 2012-11-29 | 2015-05-11 | Winbond Electronics Corp | Storage medium and floating detection method |
US20220215867A1 (en) * | 2019-12-31 | 2022-07-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit with asymmetric arrangements of memory arrays |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
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US20080235541A1 (en) * | 2007-03-19 | 2008-09-25 | Powerchip Semiconductor Corp. | Method for testing a word line failure |
JP2009099235A (en) * | 2007-10-19 | 2009-05-07 | Toshiba Corp | Semiconductor memory device |
JP5193635B2 (en) * | 2008-03-17 | 2013-05-08 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
KR20100060063A (en) * | 2008-11-27 | 2010-06-07 | 삼성전자주식회사 | Bit line bridge test method in semiconductor memory device |
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US9502089B2 (en) | 2014-09-30 | 2016-11-22 | Everspin Technologies, Inc. | Short detection and inversion |
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Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5500601A (en) * | 1991-02-21 | 1996-03-19 | Sgs-Thomson Microelectronics, S.A. | Device for detecting the logic state of a memory cell |
US5684748A (en) * | 1993-12-31 | 1997-11-04 | Samsung Electronics Co., Ltd. | Circuit for testing reliability of chip and semiconductor memory device having the circuit |
US5748545A (en) * | 1997-04-03 | 1998-05-05 | Aplus Integrated Circuits, Inc. | Memory device with on-chip manufacturing and memory cell defect detection capability |
JP2002074995A (en) | 2000-08-29 | 2002-03-15 | Hitachi Ltd | Semiconductor memory |
US6781902B2 (en) * | 2002-08-28 | 2004-08-24 | Renesas Technology Corp. | Semiconductor memory device and method of testing short circuits between word lines and bit lines |
US6795372B2 (en) * | 2002-09-11 | 2004-09-21 | Samsung Electronics Co. Ltd. | Bit line sense amplifier driving control circuits and methods for synchronous drams that selectively supply and suspend supply of operating voltages |
US20040233706A1 (en) * | 2003-02-19 | 2004-11-25 | Burgan John M. | Variable refresh control for a memory |
US6982920B2 (en) * | 2001-12-12 | 2006-01-03 | Micron Technology, Inc. | Flash array implementation with local and global bit lines |
US7126834B1 (en) * | 2003-09-12 | 2006-10-24 | Netlogic Microsystems, Inc. | Sense amplifier architecture for content addressable memory device |
US20060262589A1 (en) * | 2003-12-18 | 2006-11-23 | Canon Kabushiki Kaisha | Semiconductor integrated circuit, operating method thereof, and ic card including the circuit |
US20070140039A1 (en) * | 2004-08-16 | 2007-06-21 | Fujitsu Limited | Nonvolatile semiconductor memory |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100343143B1 (en) * | 2000-08-01 | 2002-07-05 | 윤종용 | Semiconductor memory device having sense amplifier control circuit for detecting bit line bridge and method thereof |
-
2005
- 2005-12-27 JP JP2005376501A patent/JP2007179639A/en active Pending
-
2006
- 2006-12-26 US US11/645,174 patent/US7636267B2/en not_active Expired - Fee Related
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5500601A (en) * | 1991-02-21 | 1996-03-19 | Sgs-Thomson Microelectronics, S.A. | Device for detecting the logic state of a memory cell |
US5684748A (en) * | 1993-12-31 | 1997-11-04 | Samsung Electronics Co., Ltd. | Circuit for testing reliability of chip and semiconductor memory device having the circuit |
US5748545A (en) * | 1997-04-03 | 1998-05-05 | Aplus Integrated Circuits, Inc. | Memory device with on-chip manufacturing and memory cell defect detection capability |
JP2002074995A (en) | 2000-08-29 | 2002-03-15 | Hitachi Ltd | Semiconductor memory |
US6982920B2 (en) * | 2001-12-12 | 2006-01-03 | Micron Technology, Inc. | Flash array implementation with local and global bit lines |
US6781902B2 (en) * | 2002-08-28 | 2004-08-24 | Renesas Technology Corp. | Semiconductor memory device and method of testing short circuits between word lines and bit lines |
US6795372B2 (en) * | 2002-09-11 | 2004-09-21 | Samsung Electronics Co. Ltd. | Bit line sense amplifier driving control circuits and methods for synchronous drams that selectively supply and suspend supply of operating voltages |
US20040233706A1 (en) * | 2003-02-19 | 2004-11-25 | Burgan John M. | Variable refresh control for a memory |
US7126834B1 (en) * | 2003-09-12 | 2006-10-24 | Netlogic Microsystems, Inc. | Sense amplifier architecture for content addressable memory device |
US20060262589A1 (en) * | 2003-12-18 | 2006-11-23 | Canon Kabushiki Kaisha | Semiconductor integrated circuit, operating method thereof, and ic card including the circuit |
US20070140039A1 (en) * | 2004-08-16 | 2007-06-21 | Fujitsu Limited | Nonvolatile semiconductor memory |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090262590A1 (en) * | 2002-05-29 | 2009-10-22 | Elpida Memory, Inc. | Semiconductor memory device |
US8040751B2 (en) * | 2002-05-29 | 2011-10-18 | Elpida Memory, Inc. | Semiconductor memory device |
US20110273951A1 (en) * | 2010-05-10 | 2011-11-10 | Hung-Yu Li | Memory circuit and method for controlling memory circuit |
US8228752B2 (en) * | 2010-05-10 | 2012-07-24 | Faraday Technology Corp. | Memory circuit and method for controlling memory circuit |
TWI484496B (en) * | 2012-11-29 | 2015-05-11 | Winbond Electronics Corp | Storage medium and floating detection method |
US8947960B2 (en) * | 2013-04-05 | 2015-02-03 | Winbond Electronics Corp. | Semiconductor storage with a floating detection circuitry and floating detection method thereof |
US20220215867A1 (en) * | 2019-12-31 | 2022-07-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit with asymmetric arrangements of memory arrays |
US11705174B2 (en) | 2019-12-31 | 2023-07-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit with asymmetric arrangements of memory arrays |
US11769539B2 (en) * | 2019-12-31 | 2023-09-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit with asymmetric arrangements of memory arrays |
Also Published As
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US20070183232A1 (en) | 2007-08-09 |
JP2007179639A (en) | 2007-07-12 |
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