US7704869B2 - Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias - Google Patents
Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias Download PDFInfo
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- US7704869B2 US7704869B2 US11/853,139 US85313907A US7704869B2 US 7704869 B2 US7704869 B2 US 7704869B2 US 85313907 A US85313907 A US 85313907A US 7704869 B2 US7704869 B2 US 7704869B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (16)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/853,139 US7704869B2 (en) | 2007-09-11 | 2007-09-11 | Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias |
PCT/EP2008/058306 WO2009033837A2 (en) | 2007-09-11 | 2008-06-27 | Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias |
TW097126073A TW200924058A (en) | 2007-09-11 | 2008-07-10 | Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias |
US12/540,457 US7955967B2 (en) | 2007-09-11 | 2009-08-13 | Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/853,139 US7704869B2 (en) | 2007-09-11 | 2007-09-11 | Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/540,457 Division US7955967B2 (en) | 2007-09-11 | 2009-08-13 | Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias |
Publications (2)
Publication Number | Publication Date |
---|---|
US20090068835A1 US20090068835A1 (en) | 2009-03-12 |
US7704869B2 true US7704869B2 (en) | 2010-04-27 |
Family
ID=40432318
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/853,139 Active 2028-01-27 US7704869B2 (en) | 2007-09-11 | 2007-09-11 | Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias |
US12/540,457 Active 2027-12-24 US7955967B2 (en) | 2007-09-11 | 2009-08-13 | Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/540,457 Active 2027-12-24 US7955967B2 (en) | 2007-09-11 | 2009-08-13 | Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias |
Country Status (1)
Country | Link |
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US (2) | US7704869B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080057725A1 (en) * | 2006-08-30 | 2008-03-06 | Sang-Il Hwang | Method of manufacturing semiconductor device |
US20190097039A1 (en) * | 2016-12-29 | 2019-03-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and a method for fabricating the same |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8166651B2 (en) | 2008-07-29 | 2012-05-01 | International Business Machines Corporation | Through wafer vias with dishing correction methods |
US7859114B2 (en) * | 2008-07-29 | 2010-12-28 | International Business Machines Corporation | IC chip and design structure with through wafer vias dishing correction |
JP5304536B2 (en) * | 2009-08-24 | 2013-10-02 | ソニー株式会社 | Semiconductor device |
JP5957840B2 (en) * | 2011-10-04 | 2016-07-27 | ソニー株式会社 | Manufacturing method of semiconductor device |
KR20140059569A (en) * | 2012-11-08 | 2014-05-16 | 삼성전자주식회사 | A semiconductor device having staggered pad wiring structure |
US9287257B2 (en) | 2014-05-30 | 2016-03-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Power gating for three dimensional integrated circuits (3DIC) |
KR102310122B1 (en) | 2014-06-10 | 2021-10-08 | 삼성전자주식회사 | Logic cell, integrated circuit including logic cell, and methods of manufacturing the same |
US9899297B1 (en) * | 2016-09-30 | 2018-02-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device having a through-silicon via and manufacturing method thereof |
CN107665829B (en) * | 2017-08-24 | 2019-12-17 | 长江存储科技有限责任公司 | method for improving metal lead process safety in wafer hybrid bonding |
US11018134B2 (en) | 2017-09-26 | 2021-05-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method for manufacturing the same |
CN107658323B (en) * | 2017-10-25 | 2019-11-01 | 武汉新芯集成电路制造有限公司 | A kind of deep via forming method |
US11004733B2 (en) | 2018-06-29 | 2021-05-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Protection structures for bonded wafers |
US10720580B2 (en) * | 2018-10-22 | 2020-07-21 | Globalfoundries Singapore Pte. Ltd. | RRAM device and method of fabrication thereof |
US11004972B2 (en) * | 2019-06-12 | 2021-05-11 | Globalfoundries Singapore Pte. Ltd. | Semiconductor device having conducting member for electrically coupling gate structure to underlying substrate of SOI structure |
US11296083B2 (en) * | 2020-03-06 | 2022-04-05 | Qualcomm Incorporated | Three-dimensional (3D), vertically-integrated field-effect transistors (FETs) electrically coupled by integrated vertical FET-to-FET interconnects for complementary metal-oxide semiconductor (CMOS) cell circuits |
US11715690B2 (en) * | 2020-09-24 | 2023-08-01 | Nanya Technology Corporation | Semiconductor device having a conductive contact with a tapering profile |
Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5841195A (en) | 1992-02-06 | 1998-11-24 | Stmicroelectronics, Inc. | Semiconductor contact via structure |
US6133144A (en) * | 1999-08-06 | 2000-10-17 | Taiwan Semiconductor Manufacturing Company | Self aligned dual damascene process and structure with low parasitic capacitance |
US6180997B1 (en) * | 1998-02-23 | 2001-01-30 | Winbond Electronics Corp. | Structure for a multi-layered dielectric layer and manufacturing method thereof |
US6232663B1 (en) | 1996-12-13 | 2001-05-15 | Fujitsu Limited | Semiconductor device having interlayer insulator and method for fabricating thereof |
US20020076916A1 (en) | 2000-12-20 | 2002-06-20 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device, and method of manufacturing the same |
US20020142235A1 (en) | 2001-04-02 | 2002-10-03 | Nec Corporation | Photo mask for fabricating semiconductor device having dual damascene structure |
US20030129829A1 (en) | 2002-01-08 | 2003-07-10 | David Greenlaw | Three-dimensional integrated semiconductor devices |
US6727169B1 (en) * | 1999-10-15 | 2004-04-27 | Asm International, N.V. | Method of making conformal lining layers for damascene metallization |
US20040232554A1 (en) | 2003-05-23 | 2004-11-25 | Renesas Technology Corp. | Semiconductor device with effective heat-radiation |
US20040241984A1 (en) | 2003-05-28 | 2004-12-02 | Christoph Schwan | Method of adjusting etch selectivity by adapting aspect ratios in a multi-level etch process |
US20060240652A1 (en) * | 2000-01-18 | 2006-10-26 | Mandal Robert P | Very low dielectric constant plasma-enhanced cvd films |
US20080303169A1 (en) | 2004-09-15 | 2008-12-11 | Infineon Technologies Ag | Integrated Circuit Arrangment Including Vias Having Two Sections, and Method For Producing the Same |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7417321B2 (en) | 2005-12-30 | 2008-08-26 | Taiwan Semiconductor Manufacturing Co., Ltd | Via structure and process for forming the same |
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2007
- 2007-09-11 US US11/853,139 patent/US7704869B2/en active Active
-
2009
- 2009-08-13 US US12/540,457 patent/US7955967B2/en active Active
Patent Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5841195A (en) | 1992-02-06 | 1998-11-24 | Stmicroelectronics, Inc. | Semiconductor contact via structure |
US6232663B1 (en) | 1996-12-13 | 2001-05-15 | Fujitsu Limited | Semiconductor device having interlayer insulator and method for fabricating thereof |
US6180997B1 (en) * | 1998-02-23 | 2001-01-30 | Winbond Electronics Corp. | Structure for a multi-layered dielectric layer and manufacturing method thereof |
US6133144A (en) * | 1999-08-06 | 2000-10-17 | Taiwan Semiconductor Manufacturing Company | Self aligned dual damascene process and structure with low parasitic capacitance |
US6727169B1 (en) * | 1999-10-15 | 2004-04-27 | Asm International, N.V. | Method of making conformal lining layers for damascene metallization |
US20040130029A1 (en) * | 1999-10-15 | 2004-07-08 | Ivo Raaijmakers | Conformal lining layers for damascene metallization |
US20060240652A1 (en) * | 2000-01-18 | 2006-10-26 | Mandal Robert P | Very low dielectric constant plasma-enhanced cvd films |
US7205224B2 (en) * | 2000-01-18 | 2007-04-17 | Applied Materials, Inc. | Very low dielectric constant plasma-enhanced CVD films |
US20020076916A1 (en) | 2000-12-20 | 2002-06-20 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device, and method of manufacturing the same |
US20020142235A1 (en) | 2001-04-02 | 2002-10-03 | Nec Corporation | Photo mask for fabricating semiconductor device having dual damascene structure |
US20030129829A1 (en) | 2002-01-08 | 2003-07-10 | David Greenlaw | Three-dimensional integrated semiconductor devices |
US6943067B2 (en) | 2002-01-08 | 2005-09-13 | Advanced Micro Devices, Inc. | Three-dimensional integrated semiconductor devices |
US20040232554A1 (en) | 2003-05-23 | 2004-11-25 | Renesas Technology Corp. | Semiconductor device with effective heat-radiation |
US20040241984A1 (en) | 2003-05-28 | 2004-12-02 | Christoph Schwan | Method of adjusting etch selectivity by adapting aspect ratios in a multi-level etch process |
US20080303169A1 (en) | 2004-09-15 | 2008-12-11 | Infineon Technologies Ag | Integrated Circuit Arrangment Including Vias Having Two Sections, and Method For Producing the Same |
Non-Patent Citations (1)
Title |
---|
Office Action (Mail Date Jun. 25, 2009) for U.S. Appl. No. 11/853,118, Filing Date Sep. 11, 2007; Confirmation No. 2505. |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080057725A1 (en) * | 2006-08-30 | 2008-03-06 | Sang-Il Hwang | Method of manufacturing semiconductor device |
US20190097039A1 (en) * | 2016-12-29 | 2019-03-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and a method for fabricating the same |
US10727347B2 (en) * | 2016-12-29 | 2020-07-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and a method for fabricating the same |
US11355638B2 (en) | 2016-12-29 | 2022-06-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and a method for fabricating the same |
Also Published As
Publication number | Publication date |
---|---|
US20110097870A1 (en) | 2011-04-28 |
US20090068835A1 (en) | 2009-03-12 |
US7955967B2 (en) | 2011-06-07 |
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