US7788464B2 - Scalability of virtual TLBs for multi-processor virtual machines - Google Patents
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
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US20150006840A1 (en) * | 2009-11-13 | 2015-01-01 | International Business Machines Corporation | Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses |
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US9639476B2 (en) * | 2013-09-26 | 2017-05-02 | Cavium, Inc. | Merged TLB structure for multiple sequential address translations |
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US10248573B2 (en) | 2016-07-18 | 2019-04-02 | International Business Machines Corporation | Managing memory used to back address translation structures |
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US10176111B2 (en) | 2016-07-18 | 2019-01-08 | International Business Machines Corporation | Host page management using active guest page table indicators |
US10282305B2 (en) | 2016-07-18 | 2019-05-07 | International Business Machines Corporation | Selective purging of entries of structures associated with address translation in a virtualized environment |
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US10613990B2 (en) | 2017-12-05 | 2020-04-07 | Red Hat, Inc. | Host address space identifier for non-uniform memory access locality in virtual machines |
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