|Número de publicación||US7808100 B2|
|Tipo de publicación||Concesión|
|Número de solicitud||US 12/106,486|
|Fecha de publicación||5 Oct 2010|
|Fecha de presentación||21 Abr 2008|
|Fecha de prioridad||21 Abr 2008|
|También publicado como||US20090261472|
|Número de publicación||106486, 12106486, US 7808100 B2, US 7808100B2, US-B2-7808100, US7808100 B2, US7808100B2|
|Cesionario original||Infineon Technologies Ag|
|Exportar cita||BiBTeX, EndNote, RefMan|
|Citas de patentes (23), Otras citas (3), Citada por (10), Clasificaciones (81), Eventos legales (2)|
|Enlaces externos: USPTO, Cesión de USPTO, Espacenet|
The invention relates to a power semiconductor module and to a method for fabricating a power semiconductor module.
Conventional semiconductor modules comprise a baseplate on which one or more power semiconductor chips are arranged. To cool the power semiconductor chips, the power semiconductor module's baseplate is pressed against a heat sink. To improve the transfer of heat, a thermally conductive material, for example a thermally conductive paste, may be introduced between the baseplate and the heat sink in order to compensate for irregularities in the baseplate and the heat sink. However, the thermal conductivity of such thermally conductive materials is much lower than the thermal conductivity of both the heat sink and the baseplate. In principle, therefore, optimum cooling of the power semiconductor chips involved is desired for such arrangements. At the same time, it needs to be possible to fabricate such power semiconductor modules easily and efficiently. This also includes the possibility of making electrical contact with the power semiconductor chips on their top sides facing away from the heat sink using one or more bonding wires. In order to avoid short-circuits and/or a damage of the bonding wires, a deformation of the bonding wires after bonding them to the respective electrical connection partners shall be avoided.
A first aspect of the invention relates to a power semiconductor module comprising a support, a power semiconductor chip, a pressure element and a bonding wire. The power semiconductor chip comprises a bottom side, facing the support, and a top side, opposite the bottom side, to which top side the bonding wire is bonded. In a state in which the power semiconductor module has the support fixed to a heat sink, the pressure element, which is arranged distant from the bonding wire, exerts a contact pressure on the top in the direction of the heat sink.
A further aspect of the invention relates to a method for fabricating a power semiconductor module. In this context, a support, a pressure element and a bonding wire are provided. The support comprises a power semiconductor chip arranged on it. A bonding connection is produced between the bonding wire and the top side of the semiconductor chip, which is facing away from the support, and the pressure element is arranged above the top side and distant from the bonding wire.
Yet another aspect of the invention relates to a method for fabricating a power semiconductor arrangement. In this case, a power semiconductor module and a heat sink are provided. The power semiconductor module comprises a support, a power semiconductor chip with a bottom side, facing the support, and with a top side, opposite the bottom side, a bonding wire bonded to the top side, and a pressure element. Fixing the power semiconductor module to the heat sink produces a contact pressure acting on the top side in the direction of the heat sink, the pressure element pushing the power semiconductor chip and the support in the direction of the heat sink with said contact pressure. Thereby, the pressure element is arranged distant from the bonding wire.
The power semiconductor module 1 comprises a support 20 which is provided with a patterned top—i.e. arranged in a vertical direction v—metallization 21 and with a continuous bottom—i.e. arranged in a direction opposite the vertical direction v—metallization 29 and which terminates the package 10 at the bottom side. The bottom metallization 29 thus also forms the bottom side of the power semiconductor module 1. In this context, the vertical direction v is understood to mean a direction which runs perpendicular to the patterned metallization 21 facing the inside of the module and points from the patterned metallization 21 in the direction of the inside of the module. The support 20 is electrically insulating and may be formed from a ceramic, for example from alumina (Al2O3) or from silicon nitride (Si3N4) or from aluminum nitride (AlN), or from plastic. By way of example, the support 20 together with its patterned top metallization 21 and possibly with its optional bottom metallization 29 may be in the form of a DCB (Direct Copper Bonding) substrate, in the form of a DAB (Direct Aluminum Bonding) substrate, or in the form of an AMB (Active Metal Brazing) substrate.
A support 20 which is metallized at least on the top may have (without the metallizations 21, 29) a thickness in the range of 0.1 mm to 2 mm, for example, e.g. less than or equal to 0.635 mm, less than or equal to 0.38 mm, less than or equal to 0.32 mm or less than or equal to 0.25 mm. The thicknesses of the top metallization 21 and—to the extent provided—bottom metallization 29 may be, independently of one another, 50 μm to 1000 μm, for example, e.g. 300 μm, more than 300 μm, more than or equal to 400 μm, more than or equal to 500 μm, or more than or equal to 600 μm.
On account of the patterning, the top metallization 21 comprises a conductor structure which comprises interconnects and also one or more pads for power semiconductor chips 30. The bottom metallization 29 is provided, inter alia, for the purpose of avoiding bending, as would arise when a thin support 20 metallized only on its top is heated, on account of different coefficients of thermal expansion for the support 20 and the metallization 21. In principle, it is also possible to dispense with the bottom metallization 29, however, if this does not result in unacceptable impairment of the heat transfer resistance between the heating 50 and the power semiconductor module 1 fixed thereto. In this regard, to increase mechanical stability, for example, the support 20 metallized only on one side may be of thicker design than a support metallized on two opposite sides—under otherwise identical conditions and with the same cooling success to be attained. If the bottom metallization 29 is dispensed with, the insulating support 20 forms the side of the power semiconductor module 1.
The power semiconductor chips 30, which may be in the form of IGBTs, in the form of MOSFETs, in the form of J-FETs, in the form of thyristors or in the form of diodes, for example, have a respective top metallization 31, forming a load connection for the power semiconductor chip 30, on their top, which is facing away from the support 20. As a further load connection for the power semiconductor chip 30, a respective bottom metallization 39 is provided which is arranged on the side of the power semiconductor chip 30 which faces the support 20. By way of example, the load connections 31, 39 may be source connections, drain connections, collector connections, emitter connections, anode connections or cathode connections. The bottom metallization 39 is electrically conductively connected to a section of the top metallization 21 of the support 20. This electrically conductive connection may be produced using a connecting layer 35 which is arranged between the bottom metallization 39 of the power semiconductor chip 30 and the top metallization 21 of the support 20. The connecting layer 35 may be a solder, for example a eutectic solder, an alloy layer (diffusion solder) comprising metals, a silver-containing layer (e.g. produced using a low temperature connection method) or an electrically conductive adhesive. Regardless of the type of electrical contact connection, it is advantageous to perform this over as large an area as possible in order to minimize the heat transfer resistance between the power semiconductor chip 30 and the support 20.
For the purpose of making electrical contact with the power semiconductor module 1 externally, connection contacts 15 are provided which—as depicted—may be in the form of press fit contacts, for example. As an alternative or in addition, connection contacts 15 may also be provided which are in the form of a resilient contact element or which have a mounting opening. It is equally possible for connection contacts 15 to be in the form of a threaded hole, for example in the form of a screw nut which is embedded in the package 10 of the power semiconductor module 1.
Certain instances of the connection contacts 15 are provided for the purpose of supplying a supply voltage to the power semiconductor module 1. Other instances of the connection contacts 15 may—depending on the function of the power semiconductor module 1—provide one or more, for example frequency-modulated, output voltages. If one or more of the power semiconductor chips 30 are in the form of controllable power semiconductor components, further instances of the connection contacts 15 may also be used to supply a control voltage to the associated control connection. By way of example, the power semiconductor module 1 may have the function of a single switch with one or else more controllable power semiconductor chips 30 connected in parallel with one another. Equally, the power semiconductor chips 30 may also be connected up to form one or more half-bridges, one or more full-bridges, or a “six pack” comprising six power semiconductor chips connected to for three half-bridges, or other assemblies with an arbitrary function. Suitable applications of such power semiconductor modules 1 are frequency converters, engine controllers, switched-mode power supplies, rectifiers and other power circuits, for example.
To connect the connection contacts 15 electrically conductively to the power semiconductor chips 30, to the patterned top metallization 21, or to other electrical components of the power semiconductor module 1, metal connection lugs 16 are provided. In the case of the present example, the connection lugs 16 are of two-part design and comprise a top lug element 16 a and a bottom lug element 16 b which may be pressed, soldered or welded together, for example. In this case, the top lug element 16 a and its connection contact 15 may be made of a material which is harder than the material of the bottom lug element 16 b. The connection contacts 15 are connected to the corresponding top lug elements 16 a and may—as shown in FIG. 1—also be designed as an integral part of the top lug elements 16 a.
Optionally, the top lug elements 16 a may be molded into the package 10, or cast integral, or inserted into guide elements in the package 10. Instead of two-element or multi-element connection lugs 16, a connection lug 16 may in principle also be of integral design.
To connect the power semiconductor chips 30 to the external connection contacts 15 and/or to one another, one or more bonding wires 18 are provided in addition to the patterned top metallization 21 of the support 20 and in addition to the connection lugs 16. The bonding wires 18 are used, inter alia, to connect the top metallization 31 of the power semiconductor chips 30 electrically conductively to sections of the patterned top metallization 21 of the support 20 and/or to connection lugs 16. In this context, one or more bonding wires 18 may be bonded to each top metallization 31 of a power semiconductor chip 30. For operation, the power semiconductor module 1 is fixed to a heat sink 50, so that the bottom side 28 of the power semiconductor module 1 is in good thermal contact with the heat sink 50. The heat to be dissipated from the power semiconductor module 1 is produced predominantly in the power semiconductor chips 30, which means that good heat dissipation is advantageous.
During operation of the power semiconductor module 1, the highest temperatures are reached in the central region of the power semiconductor chips 30. Pressure elements 40 are therefore provided which exert a contact pressure, e.g. more than 5 N, more than 10 N, more than 20 N, more than 100 N or more than 500 N, on the power semiconductor chip 30 in the direction of the heat sink 50 when the power semiconductor module 1 is fixed to the heat sink 50. By way of example, the pressure elements 40 are formed from metal, plastic or ceramic and may have no electrical function, or else—in the case of an electrically conductive material—may take on an electrical function. They may be in electrically conductive or electrically insulating form.
In this context, the contact pressure of such pressure elements 40 is exerted specifically on the power semiconductor chips 30, and not on a point of the metallized support 20 between or next to the power semiconductor chips 30. The advantage resulting from such pressure elements 40 increases with the size of the power semiconductor chips 30, i.e. a pressure element 40 may be provided for a power semiconductor chip 30 when the shortest edge length of the power semiconductor chip 30 is greater than or equal to a prescribed value, e.g. 7 mm, or when the power semiconductor chip 30 (when projected onto the top of the metallized support 20) has a base area of more than 65 mm2, of more than 80 mm2 or of more than 100 mm2.
In the case of the arrangement shown in
A heat conducting element 60 may be electrically conductive or electrically insulating. By way of example, it may be a silicone film without mechanical reinforcement or a silicone film with mechanical reinforcement, for example by virtue of the addition of glass fibers. Equally, technical plastic films, phase change coatings, soft polymer contact coatings, gap fillers made of soft elastomers with or without mechanical reinforcement, for example by virtue of the addition of glass fibers, or adhesive films with electrically insulating supports may be used as the heat conducting element 60. In the case of thermally conductive films or gap fillers, it is possible to use highly crosslinked elastomers, e.g. silicones, mixed with thermally conductive ceramics (e.g. boron nitride, aluminum nitride, or mixtures of boron nitride and aluminum nitride). Examples of suitable electrically and thermally conductive elements 60 are aluminum with a phase change coating or a polymer coating, graphite films (e.g. with a graphite proportion of more than 98%), thermally conductive adhesive films or thermally conductive pastes.
A pressure element 40 is proportioned, at least on its associated power semiconductor chip 30, such that it can only locally exert a pressure of, by way of example, more than 1.25 N/mm2, more than 2.5 N/mm2, more than 5 N/mm2, more than 25 N/mm2 or more than 125 N/mm2 on the top metallization 31, so that there still remains sufficient free area of the top metallization 31 at the side next to the contact area to bond one or more bonding wires 18 to said metallization.
To prevent any damage to a power semiconductor chip 30 by the pressure element 40 pressing against this power semiconductor chip 30, various measures can be taken. An example of one option is to choose the thickness d31 of the top metallization 31 over the entire area of the metallization or at least locally to be thicker than in the case of a comparable conventional power semiconductor chip. In this context, the increased thickness d31 may also be chosen to be greater than the thickness d32 of the bottom metallization 39 of the power semiconductor chip 30. The thickness d31 of the top metallization 31 may be more than 6 μm, more than 10 μm or more than 20 μm, for example. In addition, the top metallization 31 may comprise just one layer, or else a plurality of sublayers. Examples of suitable sublayers are layers made of or containing aluminum and/or copper, made of or containing nickel, and nickel alloys. In addition, the metallizations 31, 39 may also be provided with protective layers to prevent oxidation on the surface.
In the case of a multilayer metallization 31, 39, one or more of the sublayers may be in the form of thin intermediate layers with a thickness of less than 1 μm, for example, which are arranged between other sublayers. By way of example, the intermediate layers may be used as diffusion barriers preventing certain substances, e.g. copper, from diffusing into the semiconductor body of the power semiconductor chip 30. Another function of such intermediate layers may be to prevent the formation of hillocks and/or to improve the metallization's resistance to sudden changes of temperature. To this end, such an intermediate layer may be formed from titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tantalum silicon (TaSi), tantalum silicon nitride (TaSiN) or tungsten (W), for example. In addition, intermediate layers may be used as cohesion layers, e.g. made of titanium nitride (TiN), aluminum (Al), aluminum silicon (AlSi), aluminum copper (AlCu), aluminum silicon copper (AlSiCu), nickel (Ni), palladium (Pd), gold (Au), or made of other materials, which improves the mechanical adhesion of another layer to be applied. An example of a form of the top metallization 31 which may be mentioned is a layer sequence which successively comprises, starting from the semiconductor chip 30, an aluminum layer approximately 3 μm thick, a layer of nickel or nickel alloy approximately 6 μm thick, and a layer of palladium.
As an alternative or in addition to a thicker top metallization 31 for the power semiconductor chip 30, a pressure distribution element 42 may also be provided, as shown in
A pressure distribution element may, in principle, also comprise any materials other than silicone. Suitable examples are also silicon nitride (Si3N4) or polyimide, i.e. materials which are used as a passivation layer when fabricating the power semiconductor chips 30 anyway. For this reason, a pressure distribution element 40 may also be produced easily by producing a passivation layer for the power semiconductor chip 30, at least in the region A of the top side on which a contact pressure is intended to act on the power semiconductor chip 30 provided in the power semiconductor module 1, with a thickness, for example greater than or equal to 6 μm, which is greater than the thickness of the passivation layer of conventional power semiconductor components. It goes without saying that the passivation layer applied to the top metallization 31 may also have a thickness of greater than 6 μm overall, i.e. at any point.
The power semiconductor chip 30 shown in
To compensate for tolerances such as may arise when positioning the pressure distribution element 42 and/or the pressure element 40, the top side section A may be chosen to be larger than the contact area between the top of the power semiconductor chip 30 and the pressure distribution element 42 or—when the pressure element 40 acts directly on the metallization 31—the pressure element 40. By way of example, the top side section A may have an area of less than or equal to 2 mm×2 mm. In addition, the bottom end of a pressure element 40 may extend in any lateral direction, i.e. a lateral direction perpendicular to the vertical direction v, over a range of no more than 2 mm. In addition, the top side section A may have an area greater than or equal to 1 mm×1 mm, for example. Equally, the bottom end of a pressure element 40 may extend in any lateral direction over a range of at least 1 mm.
It is also advantageous if the control connection 32 is arranged outside of the top side section A. In the present exemplary embodiment, the control connection 32 is arranged on the lateral edge of the patterned top metallization 31, 32 of the semiconductor chip 30.
In the case of the semiconductor modules 1 explained with reference to
If, as in the examples shown in
As a further example,
Optionally, the package cover 10 a may comprise depressions 14 on its side facing the interior of the module which correspond to the top ends of the pressure elements 40 shown in
Another possibility for producing an arrangement as shown in
In another example, shown in
In all the examples explained hitherto, the contact pressure has been produced primarily by virtue of the power semiconductor module 1 having been fixed to a heat sink. Another possibility for producing a contact pressure is to use a pressure element 40, as shown in
Yet another possibility for exerting a contact pressure on a power semiconductor chip 30 or for intensifying a contact pressure conveyed by the package 10 is to use a pressure element 40 which heats up and accordingly expands in a direction v perpendicular to it's the top side of the power semiconductor chip 30 as the temperature of the power semiconductor chip 30 increases. Suitable materials for this are not only materials with isotropic thermal length expansion but also those with anisotropic thermal length expansion, the pressure element 40 being oriented such that the direction with the greatest coefficient of length expansion is identical to the direction perpendicular to the top side of the power semiconductor chip 30.
The arrangement shown in
A corresponding view is shown in
A further alternative for producing a contact pressure acting on the contact region A of the power semiconductor chip 30 is to use a pressure element 40 in the form of a helical spring, as is shown in
It is also possible to produce a contact pressure by prestressing the package 10 when the power semiconductor module is screwed onto a heat sink 50 such that this produces a force which pushes the pressure element 40 against the contact region of the power semiconductor chip 20.
As an example in this regard,
Although various examples to realize the invention have been disclosed, it will be apparent to those skilled in the art that various changes and modifications can be made which will achieve some of the advantages of the invention without departing from the spirit and scope of the invention. It will be obvious to those reasonably skilled in the art that other components performing the same functions may be suitably substituted. Such modifications to the inventive concept are intended to be covered by the appended claims.
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|Clasificación de EE.UU.||257/719, 257/675, 257/690, 257/E23.101, 438/117, 257/720, 174/261|
|Clasificación cooperativa||H01L2224/83825, H01L24/73, H01L2924/00014, H01L2924/1301, H01L2224/4846, H01L2224/4945, H01L2924/04941, H01L2224/05552, H01L2924/01028, H01L2924/04953, H01L2224/05624, H01L2224/83851, H01L2224/4813, H01L2924/3511, H01L2924/014, H01L2224/48472, H01L2924/13091, H01L2224/49051, H01L24/28, H01L2224/48227, H01L2224/73265, H01L24/49, H01L2924/01029, H01L2224/29339, H01L2924/01074, H01L2924/01022, H01L2224/05655, H01L23/4006, H01L2224/32225, H01L2224/48091, H01L2924/01005, H01L24/06, H01L24/72, H01L2224/83805, H01L2224/0603, H01L2924/01019, H01L2924/05042, H01L2924/01079, H01L2924/01006, H01L2924/0105, H01L2224/85191, H01L2924/013, H01L2924/01013, H01L2924/01322, H01L2924/0781, H01L2924/13055, H01L2924/01014, H01L2924/01073, H01L2224/49111, H01L2924/01033, H01L2224/32014, H01L2224/04042, H01L2224/83801, H01L24/48, H01L2924/01047, H01L25/072, H01L2924/01046, H01L2224/05647, H01L24/83, H01L2924/01023, H01L2224/4903, H01L23/3735, H01L2224/49175, H01L2224/2919, H01L2224/05554, H01L2224/06051, H01L2224/293, H01L2224/2929|
|Clasificación europea||H01L24/49, H01L24/72, H01L24/06, H01L24/48, H01L25/07N|
|7 May 2008||AS||Assignment|
Owner name: INFINEON TECHNOLOGIES AG, GERMANY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BAYERER, REINHOLD;REEL/FRAME:020911/0889
Effective date: 20080424
|27 Mar 2014||FPAY||Fee payment|
Year of fee payment: 4