US7977241B2 - Method for fabricating highly reliable interconnects - Google Patents
Method for fabricating highly reliable interconnects Download PDFInfo
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- US7977241B2 US7977241B2 US11/961,392 US96139207A US7977241B2 US 7977241 B2 US7977241 B2 US 7977241B2 US 96139207 A US96139207 A US 96139207A US 7977241 B2 US7977241 B2 US 7977241B2
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- wafer
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- hclu
- module
- orifices
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- Expired - Fee Related, expires
Links
- 238000000034 method Methods 0.000 title claims description 55
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims abstract description 94
- 238000004140 cleaning Methods 0.000 claims abstract description 12
- 230000007547 defect Effects 0.000 claims description 56
- 230000001105 regulatory effect Effects 0.000 claims description 30
- 229910052751 metal Inorganic materials 0.000 claims description 27
- 239000002184 metal Substances 0.000 claims description 27
- 230000007797 corrosion Effects 0.000 claims description 21
- 238000005260 corrosion Methods 0.000 claims description 21
- 238000005498 polishing Methods 0.000 claims description 19
- 238000012545 processing Methods 0.000 claims description 15
- 239000007789 gas Substances 0.000 claims description 12
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 10
- 230000003068 static effect Effects 0.000 claims description 10
- 238000010926 purge Methods 0.000 claims description 7
- 230000004044 response Effects 0.000 claims description 6
- 238000012360 testing method Methods 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 238000013022 venting Methods 0.000 claims description 5
- 239000000523 sample Substances 0.000 claims description 3
- 238000007517 polishing process Methods 0.000 claims description 2
- 229910001220 stainless steel Inorganic materials 0.000 claims description 2
- 239000010935 stainless steel Substances 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052721 tungsten Inorganic materials 0.000 abstract description 10
- 239000010937 tungsten Substances 0.000 abstract description 10
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 3
- 235000012431 wafers Nutrition 0.000 description 114
- 238000010586 diagram Methods 0.000 description 12
- 230000008569 process Effects 0.000 description 10
- 230000002028 premature Effects 0.000 description 3
- 239000007921 spray Substances 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000013100 final test Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000012216 screening Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000012913 prioritisation Methods 0.000 description 1
- 238000012552 review Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
Images
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/34—Accessories
- B24B37/345—Feeding, loading or unloading work specially adapted to lapping
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S414/00—Material or article handling
- Y10S414/135—Associated with semiconductor wafer handling
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/906—Cleaning of wafer as interim step
Definitions
- This disclosure relates generally to semiconductor manufacturing and processing, and more specifically, to methods for fabricating highly reliable interconnects.
- Problems in the art include, for example, premature via failures due to tungsten plug corrosion that is not otherwise detectable through in-line, end of line, or final test screening. Problems in the art further include yield decrease due to localized charging that can occur at an inter-layer dielectric (ILD) polish portion of a semiconductor device manufacturing process. Furthermore, prior known processing techniques do not address tungsten corrosion or localized charging resulting from chemical mechanical polishing (CMP) processing.
- CMP chemical mechanical polishing
- FIG. 1 is a block diagram view of a CMP tool according to a current practice in the art
- FIG. 2 is a block diagram view of a CMP polish platen module according to a current practice in the art
- FIG. 3 is a table view of a wafer unload sequence as implemented in a current practice with respect to the CMP tool of FIG. 1 ;
- FIG. 4 is a table view of a wafer load sequence as implemented in a current practice with respect to the CMP tool of FIG. 1 ;
- FIG. 5 is a diagram view of various types of contact via defects, including a notch down wafer map, illustrating problems in the art
- FIG. 6 is a block diagram view of an improved CMP tool according to an embodiment of the present disclosure.
- FIG. 7 is a block diagram view of an improved CMP tool according to another embodiment of the present disclosure.
- FIG. 8 is a graphical representation view of via defects versus rotometer setting as applied to the improved CMP tool according to an embodiment of the present disclosure.
- FIG. 9 is a table diagram view of rotometer settings and DI flow as applied to the improved CMP tool according to an embodiment of the present disclosure and current practice.
- a method for fabricating highly reliable interconnects advantageously addresses the issues of (i) uncontrolled de-ionized (DI) water flow dispensed through small orifices over an inter-layer dielectric (ILD) and (ii) exposed tungsten plugs which undesirably leads to localized charging and subsequent galvanic reactions (for example, in the case of tungsten plugs) or arcing (for example, in the case of bulk ILD).
- the method according to the embodiments of the present disclosure includes reducing water flow to an appropriate level, wherein reducing the water flow to the appropriate level eliminates the undesirable charging and the attendant defects.
- the method according to the embodiments of the present disclosure comprises the installation of a variable pressure input constant flow output regulator to reduce DI water flow contacting the polished wafer surface during CMP processing to the desired appropriate level.
- semiconductor substrate can be any semiconductor material or combinations of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOI), silicon, monocrystalline silicon, the like, and combinations of the above.
- SOI silicon-on-insulator
- FIG. 1 is a block diagram view of a CMP tool according to a current practice in the art.
- the current practice makes use of a CMP tool in which a polish process is carried out.
- a wafer handler is used for loading and unloading a wafer to be processed by the CMP tool.
- HCLU head cleaning load and unload
- FIG. 1 illustrates the head cleaning load and unload (HCLU) module of a current CMP process.
- the HCLU module has a number of inputs, which include DI water, vacuum, and regulated nitrogen.
- the HCLU performs many functions, some of which require vacuum, some of which require DI water spraying out of the head, and others require a nitrogen (N 2 ) purge. All three are inputs to the HCLU.
- Each of the DI water, vacuum, and N 2 are coupled to the HCLU head through orifices located within cut-outs in the HCLU pad. DI water sprays out of the orifices in the form of a water jet. Nitrogen is blown out of the orifices. In addition, vacuum is applied to the orifices, as needed.
- FIG. 2 is a block diagram view of a CMP polish platen module according to a current practice in the art.
- a wafer is transported via a wafer carrier head from one platen to another during wafer processing. That is, the CMP polish platen module includes a wafer being transported between three (3) platens via a wafer carrier head.
- Various elements of the CMP polish platen module are identified directly on the drawing figure.
- a robot arm loads and unloads a wafer onto and off of the HCLU.
- FIG. 3 is a table view of a wafer unloading sequence as implemented in a current practice with respect to the CMP tool of FIG. 1 .
- the wafer unload sequence includes: N2 venting of orifices to clear out the same, prior to the wafer carrier head delivering the wafer to the HCLU, vacuum applied—carrier head unload, high pressure DI water—robot load, and high pressure DI water—empty carrier clean.
- the step of high pressure DI water for the robot unload has been discovered to generate defective interconnects, resulting in premature via failure.
- FIG. 4 is a table view of a wafer load sequence as implemented in a current practice with respect to the CMP tool of FIG. 1 .
- the wafer load sequence includes: N2 venting of orifices, vacuum—robot unload, high pressure DI water—carrier head load, and high pressure DI water—empty carrier clean.
- FIG. 5 is a diagram view of various types of contact via defects, including a notch down wafer map, illustrating problems in the art. Typical defects include fence defects, protruded vias, and dished vias. A composite wafer map signature is shown that illustrates one example of various locations of contact via defects on a wafer.
- FIG. 6 is a block diagram view of an improved CMP tool according to an embodiment of the present disclosure.
- the improved CMP tool includes a flow controller configured for providing a predetermined control of flow for the DI water.
- the flow control comprises a variable pressure input constant flow output in-line controller.
- the predetermined control of flow for the DI water is in the range of 750 ml/min to 1100 ml/min. In another embodiment, the predetermined control of flow for the DI water is on the order of 1000 ml/min.
- Various elements of the improved CMP tool are identified directly on the drawing figure.
- FIG. 7 is a block diagram view of an improved CMP tool according to another embodiment of the present disclosure.
- the embodiment of FIG. 7 is similar to that of FIG. 6 with the following difference.
- Alarmed and regulated DI water flow is passed through a flow restrictor, prior to being fed to the orifaces in the (HCLU) pad/plate that spray the DI water onto the wafer or the membrane of the carrier head.
- HCLU orifaces in the
- FIG. 8 is a graphical representation view of via defects versus rotometer setting as applied to the improved CMP tool according to an embodiment of the present disclosure.
- FIG. 9 is a table diagram view of rotometer settings and DI flow as applied to the improved CMP tool according to an embodiment of the present disclosure and current practice.
- a variable flow rotometer was used to demonstrate that via defects can be modulated by HCLU DI water flow.
- the rotometer setting is selected to be 4.0, corresponding to an flow on the order of approximately 1000 ml/min.
- the desired rotometer setting is used for wafer load/unload and efficient head clean.
- the DI flow is noted to be on the order of 6150 ml/min. From the graph, it is also noted that the via defect counts for unrestricted flow of DI water are on the order of approximately 10.4, corresponding to an approximate order of magnitude more defect counts than the number of defect counts for rotometer flow of 4.0 units.
- the embodiments of the present disclosure resolve problems and/or fulfill needs in the art in a new way, in that, the method takes into consideration the effects of charging within the CMP module due to DI water flow. No prior methods are known that address charging in the CMP module, as discussed herein.
- the method according to the present embodiments provides a variable pressure input constant flow output inline controller to the DI water line on the HCLU. Such a measure eliminates contact via defects, and changes the way a robot loads/unloads a wafer with respect to the CMP process.
- a mechanism for preventing galvanic action including a strap or flow restriction.
- the embodiments apply to a wafer handling tool, as well as, a method of wafer handling.
- the methods and apparatus according to the embodiments of the present disclosure can be applied to various semiconductor products, including, 0.25 ⁇ m, 0.4 ⁇ m, smartMOS, automotive semiconductor, and other type semiconductor products, for example.
- the embodiments of the present disclosure provide for an increased yield over prior known techniques.
- the embodiments of the present disclosure advantageously overcome the problem of premature via failures due to tungsten plug corrosion that previously was not detectable through in-line, end of line, or final test screening.
- the embodiments include DI water flow rate control during a wafer unload portion of a CMP process.
- the method includes the addition of a variable pressure input, constant flow output, in-line controller to the DI water line on HCLU.
- the load cup is the interface for transferring wafers to and from the wafer handling robotics and the polishing module. In the process of transferring wafers, the load cup washes the wafers and aligns them for the polishing head. It also washes the polishing head between wafers.
- via defects can be modulated by HCLU DI water flow.
- a strong statistical difference was observed, in that there was obtained an approximate 84% reduction in contact via defects, 8.8 NKD to 1.4 NKD. (Normalized Killed Die)
- a method of fabricating highly reliable tungsten interconnects includes use of a variable pressure input constant flow output in-line controller for a DI water line to a wafer carrier associated with wafer processing equipment, and a wafer handling apparatus configured to perform the method.
- the embodiments of the present disclosure advantageously address an issue of previously unknown tungsten corrosion which had resulted from the prior known tungsten CMP process.
- a method for fabricating highly reliable interconnects comprising: processing a wafer in a chemical-mechanical polishing apparatus, the chemical-mechanical polishing apparatus including a head cleaning load and unload (HCLU) module, a robotic arm, and a wafer carrier head, wherein the HCLU module includes a padded surface for receiving the wafer during loading and unloading operations, the padded surface including a plurality of orifices disposed in a given arrangement, wherein the processed wafer includes at least one of (i) metal interconnect features and (ii) a processed inter-level dielectric, the metal interconnect features being susceptible to metal corrosion defects and the processed inter-level dielectric being susceptible to arcing defects; transferring the processed wafer from the wafer carrier head to the HCLU module, wherein transferring includes using vacuum supplied to the HCLU module for pulling the wafer away from the wafer carrier head to the HCLU module; and transferring the processed wafer from the HCLU module to the robotic arm, wherein
- the HCLU module receives a regulated gas supply input, a vacuum input, and a DI water input, wherein each of the regulated gas supply input, the vacuum input, and the DI water input are selectively coupled to the plurality of orifices through a manifold, further wherein the variable pressure input DI water is regulated inline to provide a constant flow DI water to the plurality orifices at least during a polished wafer unloading from the HCLU to the robotic arm.
- inline regulating of the variable pressure input DI water comprises using a flow controller, the flow controller being adjusted to provide a given constant DI water flow during a polished wafer unloading from the HCLU to the robotic arm according to the requirements of the wafer being polished via chemical-mechanical polishing.
- the flow controller is adjustable to (i) a first constant DI water flow during the polished wafer unloading from the HCLU to the robotic arm and adjustable to (ii) a second constant DI water flow during a cleaning of the wafer carrier head, wherein the second constant DI water flow is greater than the first constant DI water flow.
- inline regulating of the variable pressure input DI water comprises sharing a regulated supply of DI water with the chemical-mechanical polishing process and further using a flow restrictor on the regulated supply of DI water, the flow restrictor configured to provide a given constant DI water flow, which is less than the regulated supply of DI water, during a polished wafer unloading from the HCLU to the robotic arm according to the requirements of the wafer being polished via chemical-mechanical polishing.
- the constant DI water flow is selected according to the requirements of (i) maximizing an ability to reduce occurrence of defects, while (ii) maintaining a maximum ability for cleaning the wafer carrier head.
- the constant DI water flow is on the order of 1000 ml/min.
- metal corrosion defects further comprise latent defects which are not detectable at wafer level or die level testing, but are activated during actual use of a semiconductor device fabricated from the processed wafer, and wherein the arcing defects are detectable at a wafer probe testing.
- the metal interconnect features are susceptible to metal corrosion defects in response to an unrestricted flow of DI water during a wafer unloading operation from the wafer carrier head to the HCLU, wherein the unrestricted flow of DI water through the orifices creates a build up of static charge which can discharge upon contact with the wafer, the discharge creating a metal corrosion latent defect.
- the metal corrosion latent defect comprises at least one of a fence defect, a protruded via, and a dished via.
- the processed inter-level dielectric is susceptible to arcing defects in response to an unrestricted flow of DI water during a wafer unloading operation from the wafer carrier head to the HCLU, wherein the unrestricted flow of DI water through the orifices creates a build up of static charge which can discharge upon contact with the wafer.
- the method further comprises: transferring the wafer from a robotic arm to the padded surface of the HCLU module of the chemical-mechanical polishing apparatus; and transferring the wafer to the wafer carrier head from the HCLU module.
- the method prior to transferring the processed wafer from the wafer carrier head to the HCLU module, the method further comprises: venting the orifices using a purging gas supplied to the HCLU module.
- the purging gas comprises nitrogen
- the method further comprises: using the regulated constant flow DI water through the orifices of the HCLU module to clean the wafer carrier head.
- the DI water input comprises unregulated flow and variable pressure DI water house supply.
- the DI water is characterized by a given resistivity and further wherein the DI water output through the plurality of orifices is subject to creating a static charge in response to unregulated DI water flow through the plurality of orifices being at a pressure greater than a threshold amount.
- the plurality of orifices comprises orifices formed within stainless steel.
- the plurality of orifices can comprise nine orifices that are arranged in two rows, each row containing five orifices, wherein the central orifice is shared between the two rows, the first and second rows further being perpendicular to one another through the central orifice.
- a method for fabricating highly reliable interconnects and inter-level dielectrics comprises: processing a wafer in a chemical-mechanical polishing apparatus, the chemical-mechanical polishing apparatus including a head cleaning load and unload (HCLU) module, a robotic arm, and a wafer carrier head, wherein the HCLU module includes a padded surface for receiving the wafer during loading and unloading operations, the padded surface including a plurality of orifices disposed in a given arrangement, wherein the processed wafer includes at least one of (i) metal interconnect features and (ii) a processed inter-level dielectric, the metal interconnect features being susceptible to metal corrosion defects and the processed inter-level dielectric being susceptible to arcing defects; transferring the processed wafer from the wafer carrier head to the HCLU module, wherein transferring includes using vacuum supplied to the HCLU module for pulling the wafer away from the wafer carrier head to the HCLU module; and transferring the processed wafer from the HCLU module to the robotic arm, wherein
- a method for fabricating highly reliable interconnects comprises: processing a wafer in a chemical-mechanical polishing apparatus, the chemical-mechanical polishing apparatus including a head cleaning load and unload (HCLU) module, a robotic arm, and a wafer carrier head, wherein the HCLU module includes a padded surface for receiving the wafer during loading and unloading operations, the padded surface including a plurality of orifices disposed in a given arrangement, wherein the processed wafer includes at least one of (i) metal interconnect features and (ii) a processed inter-level dielectric, the metal interconnect features being susceptible to metal corrosion defects and the processed inter-level dielectric being susceptible to arcing defects; transferring the processed wafer from the wafer carrier head to the HCLU module, wherein transferring includes using vacuum supplied to the HCLU module for pulling the wafer away from the wafer carrier head to the HCLU module; and transferring the processed wafer from the HCLU module to the robotic arm, wherein transferring includes using a regulated constant
- Coupled is not intended to be limited to a direct coupling or a mechanical coupling.
Abstract
Description
Claims (16)
Priority Applications (1)
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US11/961,392 US7977241B2 (en) | 2006-12-20 | 2007-12-20 | Method for fabricating highly reliable interconnects |
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US87111606P | 2006-12-20 | 2006-12-20 | |
US11/961,392 US7977241B2 (en) | 2006-12-20 | 2007-12-20 | Method for fabricating highly reliable interconnects |
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US20080153394A1 US20080153394A1 (en) | 2008-06-26 |
US7977241B2 true US7977241B2 (en) | 2011-07-12 |
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US7642105B2 (en) * | 2007-11-23 | 2010-01-05 | Kingston Technology Corp. | Manufacturing method for partially-good memory modules with defect table in EEPROM |
CN103578918B (en) * | 2012-07-24 | 2017-08-29 | 无锡华润上华科技有限公司 | The method for reducing semiconductor wafer surface electric arc defect |
US10832917B2 (en) | 2017-06-09 | 2020-11-10 | International Business Machines Corporation | Low oxygen cleaning for CMP equipment |
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US6517637B1 (en) * | 1997-07-23 | 2003-02-11 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for cleaning wafers with ionized water |
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- 2007-12-20 US US11/961,392 patent/US7977241B2/en not_active Expired - Fee Related
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US5331987A (en) * | 1991-11-14 | 1994-07-26 | Dainippon Screen Mfg. Co. Ltd. | Apparatus and method for rinsing and drying substrate |
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