US8093711B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
US8093711B2
US8093711B2 US12/364,340 US36434009A US8093711B2 US 8093711 B2 US8093711 B2 US 8093711B2 US 36434009 A US36434009 A US 36434009A US 8093711 B2 US8093711 B2 US 8093711B2
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United States
Prior art keywords
semiconductor chip
metal layer
main face
semiconductor
encapsulation material
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US12/364,340
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US20100193928A1 (en
Inventor
Frank Zudock
Thorsten Meyer
Markus Brunnbauer
Andreas Wolter
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Infineon Technologies AG
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Infineon Technologies AG
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Priority to US12/364,340 priority Critical patent/US8093711B2/en
Assigned to INFINEON TECHNOLOGIES AG reassignment INFINEON TECHNOLOGIES AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MEYER, THORSTEN, WOLTER, ANDREAS, BRUNNBAUER, MARKUS, ZUDOCK, FRANK
Priority to DE102010000269.0A priority patent/DE102010000269B4/en
Publication of US20100193928A1 publication Critical patent/US20100193928A1/en
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Publication of US8093711B2 publication Critical patent/US8093711B2/en
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Definitions

  • a semiconductor package provides a protective enclosure for one or more semiconductor chips and includes interconnects to the chip(s).
  • Semiconductor packages are employed in mobile electronic devices, including cellular telephones and other communication devices, automotive electronics, as well as other technology platforms.
  • Some semiconductor packages are configured to be compatible with package-on-package stacking technologies in which a separate electronic component is stacked on a base package.
  • package-on-package stacks include the base package fabricated to include landing pad(s) that receive/connect an upper package with semiconductor chip(s) in the base package. It is desirable to provide package-on-package semiconductor stacks with improved interconnect geometry and in a manner that does not deleteriously increase the base package size.
  • One embodiment provides a semiconductor device including a semiconductor chip having a through-connection extending between a first main face of the semiconductor chip and a second main face of the semiconductor chip opposite the first main face, encapsulation material at least partially encapsulating the semiconductor chip, and a first metal layer disposed over the encapsulation material and connected with the through-connection.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor device according to one embodiment.
  • FIG. 2 is a schematic cross-sectional view of another semiconductor device according to one embodiment.
  • FIG. 3 is a block diagram of a process for manufacturing a semiconductor device according to one embodiment.
  • FIGS. 4A-4D are schematic cross-sectional views of a process for manufacturing a semiconductor device according to one embodiment.
  • FIG. 5 is a schematic cross-sectional view of multiple semiconductor chips encapsulated by material, with each chip including a through-silicon via according to one embodiment.
  • FIG. 6 is a schematic cross-sectional view of an embedded wafer level package including a semiconductor chip formed to include a through-silicon via encapsulated by material, with a through-mold via formed through the encapsulation material according to one embodiment.
  • FIG. 7 is a schematic cross-sectional view of a package-on-package stack according to one embodiment.
  • Embodiments provide an embedded wafer level base package including at least one semiconductor chip formed to include at least one through-connection or through-silicon via extending through the chip.
  • the package is fabricated to include a lower metal layer configured for attachment to an electronic board, for example a lower redistribution layer that is attached to a printed circuit board by a solder ball.
  • the package includes an upper metal layer that forms a landing pad configured to receive another package in a stacked package-on-package configuration.
  • the through-connection enables vertical and three-dimensional interconnection in the embedded wafer level base package.
  • Embodiments provide embedded wafer level packages configured for package-on-package stacking that eliminates the use of expensive substrates common to ball grid array packages.
  • the through-connections formed as through-silicon vias in the semiconductor chip eliminates the use of long metal wires that are employed to connect conventional side-by-side or two-dimensional chips together.
  • the embedded wafer level base package including the through-silicon via provides Z-directional electrical connection through the semiconductor chip for improved radio-frequency performance with lower power consumption.
  • the embedded wafer level package including chips with one or more through-silicon vias provide a reduced package size and reduced package thickness.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor device 20 according to one embodiment.
  • Semiconductor device 20 includes a semiconductor chip 22 formed to include a through-connection 24 , encapsulation material 26 at least partially encapsulating semiconductor chip 22 , and a first metal layer 28 disposed over encapsulation material 26 and connected with through-connection 24 .
  • semiconductor chip 22 includes a first main face 30 opposite a second main face 32 , where through-connection 24 extends between first main face 30 and second main face 32 .
  • first main face 30 includes an active surface of semiconductor chip 22 that is provided with active surface connections.
  • second main face 32 of semiconductor chip 22 provides another active surface of semiconductor chip 22 and includes active surface connections.
  • an opening 34 is formed through encapsulation material 26 and a dielectric layer 36 to enable first metal layer 28 to connect with through-connection 24 .
  • semiconductor chip 22 is a logic chip, or a memory chip, or another form of a suitable semiconductor chip.
  • Suitable semiconductor chips include integrated circuits configured as logic circuits, control circuits, microprocessors or microelectrical-mechanical components, memory chips, power semiconductor chips such as power transistors, power diodes, insulated gate bi-polar transistors, vertical chips configured such that electric current flows in the Z-direction between main faces 30 / 32 , embedded chips, or flip chips.
  • chip 22 is provided as a vertical power transistor having a first electrode connected to one of a source/drain on first main face 30 and a second electrode connected to the other of the source/drain on second main face 32 .
  • though-connection 24 is formed as a through-hole ( 112 in FIG. 4A ) that is filled with metal, such as copper, gold, silver, aluminum, or alloys of these metals, or other electrically conducting metals.
  • Through-connection 24 provides for electrical communication between main faces 30 , 32 of semiconductor chip 22 and is configured to provide enhanced radio-frequency performance with reduced power consumption by shortening the connection length through the thickness (or Z-direction) of device 20 .
  • Suitable processes for forming an opening through the silicon portion of semiconductor chip 22 include deep silicon etching (DRIE) or laser drilling.
  • DRIE deep silicon etching
  • Encapsulation material 26 includes material that is generally non-electrically conducting. Suitable material for encapsulation material 26 includes polymers and/or epoxies. In one embodiment, dielectric 36 is deposited on encapsulation material 26 and suitably patterned (opened) for connection of first metal layer 28 with through-connection 24 . In one embodiment, encapsulation material 26 is disposed around semiconductor chip 22 over second main face 32 , leaving first main face 30 uncovered such that encapsulation material 26 is co-planar with first main face 30 .
  • FIG. 2 is a schematic cross-sectional view of another semiconductor device 40 according to one embodiment.
  • Semiconductor device 40 includes a semiconductor chip 42 formed to include multiple through-silicon vias (TSV) 44 a, 44 b, encapsulation material 46 at least partially encapsulating semiconductor chip 42 , and a metal layer 48 a connected with TSV 44 a and a metal layer 48 b connected with TSV 44 b.
  • TSV through-silicon vias
  • TSV 44 a, 44 b are formed to extend through semiconductor chip 42 between a first main face 50 and a second main face 52 .
  • openings 54 are formed extending through a potion of encapsulation material 46 and an upper dielectric layer 56 a to enable connection of metal layers 48 a, 48 b with a respective one of TSV 44 a, 44 b.
  • device 40 includes a lower dielectric layer 56 b that is patterned to enable metal layer 60 a to connect with TSV 44 a and metal layer 60 b to connect with TSV 44 b .
  • Device 40 thus includes first metal layers 48 a, 48 b connected with a respective one of TSV 44 a, 44 b and second metal layers 60 a, 60 b connected with a respective one of TSV 44 a, 44 b.
  • first metal layers 48 a, 48 b provide landing pads configured to receive and electrically connect with another package placed on device 40 .
  • metal layers 60 a, 60 b are connected with a printed circuit board, for example through connecting elements 70 such as solder balls.
  • TSV 44 a, 44 b provide three-dimensional electrical connection through semiconductor chip 42 with enhanced radio frequency performance and reduced power consumption.
  • device 40 includes one or more through-mold vias 74 that are formed to extend between opposed major surfaces 80 , 82 of encapsulation material 46 .
  • Through-mold vias (TMV) 74 provide vertical electrical connection through device 40 .
  • TSV 44 a is fabricated to include a width W 1 and TMV 74 is fabricated to include a width W 2 , where the width W 1 of TSV 44 a is less than the width W 2 of TMV 74 .
  • device 40 is provided as a logic device configured for use as a base package in a package-on-package system.
  • device 40 is a logic device, a memory device, or other suitable semiconductor package.
  • FIG. 3 is a block diagram 100 of a process for manufacturing a semiconductor device according to one embodiment.
  • Process 100 includes providing a semiconductor chip at 102 .
  • At 104 at least one through-connection is formed to extend between a first main face of the semiconductor chip and an opposing second main face of the semiconductor chip.
  • the first main face of the semiconductor chip is placed on a carrier.
  • encapsulation material is applied over the semiconductor chip and the carrier. In one embodiment, the first main face is not covered by encapsulation material since the first main face is in contact with the carrier.
  • the carrier is removed from the semiconductor chip and the encapsulation material.
  • Embodiments of process 100 provide a manufacturing approach for embedded or fan-out wafer level package assembly, as further described below.
  • FIGS. 4A-4D provide schematic cross-sectional views of the fabrication of semiconductor device 20 ( FIG. 1 ) according to one embodiment.
  • FIG. 4A is a schematic cross-sectional view of semiconductor chip 22 including openings 112 that are filled with electrically conducting material to form though-connection 24 .
  • Through-connection 24 extends between first main face 30 and second main face 32 of chip 22 .
  • FIG. 4B is a schematic cross-sectional view of first main face 30 of chip 22 placed on a carrier 120 .
  • carrier 120 includes a carrier substrate 122 and an adhesive layer 124 disposed on substrate 122 .
  • Carrier substrate 122 includes metal, plastic, paper, laminate or other suitable substrates for carrying chip 22 . Chip 22 is picked and placed in position on adhesive layer 124 of carrier 120 .
  • FIG. 4C is a schematic cross-sectional view of encapsulation material 26 disposed over carrier 120 to at least partially encapsulate chip 22 .
  • encapsulation material 26 is injection molded over chip 22 and onto carrier 120 .
  • encapsulation material 26 is compression molded over chip 22 and onto carrier 120 .
  • encapsulation material 26 is planarized or chemically mechanically polished to achieve a desired thickness of material 26 over chip 22 .
  • FIG. 4D is a schematic cross-sectional view of chip 22 partially encapsulated by encapsulation material 26 .
  • encapsulation material 26 is co-planar with first main face 30 of chip 22 .
  • FIG. 5 is a schematic cross-sectional view of semiconductor package units 130 fabricated according to embodiments described above in FIGS. 4A-4D to include multiple semiconductor chips 22 a, 22 b, 22 c . Each of these multiple semiconductor chips 22 a, 22 b, 22 c include one or more through-connections 24 extending between main faces of the chips. Encapsulation material 26 covers at least a portion of the chips after the carrier 120 ( FIG. 4C ) is removed. In one embodiment, the package units 130 are configured for separation or singulation along saw streets 132 . Sawing or dicing along saw streets 132 separates individual components 130 for subsequent fabrication into package 20 or package 40 , as described above.
  • FIG. 6 is a schematic cross-sectional view of semiconductor device 40 fabricated according to the manufacturing process described above.
  • the embedded chip 22 illustrated in FIG. 4D or the embedded chips 22 a, 22 b, 22 c of the semiconductor units 130 illustrated in FIG. 5 are each suited for subsequent processing to include upper and lower metal layers connected with through-connections 24 / 44 .
  • semiconductor chip 22 / 42 is at least partially embedded in encapsulation material 26 and further processed to include upper metal first layers 28 / 48 electrically connected to through-connections 24 / 44 , and lower or second metal layer 60 electrically connected to through-connections 24 / 44 .
  • the Z-direction electrical connectivity through the semiconductor package 40 is supplemented with TMV 74 formed to extend through encapsulation material 26 between first metal layer 28 / 48 and second metal layer 60 .
  • semiconductor package 40 is configured for use as a base package in a package-on-package system by connecting second metal layer 60 to a printed circuit board, for example with solder balls or other suitable connecting elements.
  • semiconductor package 40 is a memory package or a logic package and configured for mounting to a base package in a package-on-package system.
  • FIG. 7 is a schematic cross-sectional view of a semiconductor package-on-package (POP) stack 140 according to one embodiment.
  • POP stack 140 includes base semiconductor package 40 electrically connected to a printed circuit board 142 , and another package 144 stacked on base semiconductor package 40 .
  • solder balls 70 connect second metal layer 60 of base package 40 to printed circuit board 142 .
  • Second package 144 or top package 144 is electrically connected to landing pads provided by first metal layer 28 / 48 . In this manner, electrical connection is established between second package 144 through landing pads 28 / 48 , TSV 24 / 44 , second metal layer 60 , solder balls 70 , and ultimately to printed circuit board 142 .
  • first metal layer 28 / 48 and second metal layer 60 are patterned redistribution layers patterned over an embedded chip 22 to provide an embedded package-on-package (ePOP) device 140 .
  • ePOP embedded package-on-package
  • base package 40 is provided as a logic device and second package 144 is provided as a memory device.
  • base semiconductor package 40 is provided as a first memory device and second package 144 is provided as a second memory device.
  • Printed circuit board 142 includes electronic boards, printed circuit boards, or other suitable electronic devices which POP 40 / 144 is electrically connected.
  • Embodiments provide a semiconductor package including one or more semiconductor chips provided with one or more through-silicon vias. Forming the via in the silicon portion of the chip provides a very uniform via as compared to through-mold vias.
  • Through-mold vias have openings formed in the encapsulation material, which is typically highly filled with silica particles. The TMV are consequently formed to have a greater width compared to the TSV to account for the undercuts that are formed in the encapsulation material when the opening is formed.
  • Embodiments provide an embedded wafer level semiconductor package including through-silicon vias having three-dimensional interconnect geometry, smaller package sizes as compared to wire bonded packages, and improved radio-frequency with reduced power consumption.

Abstract

A semiconductor device includes a semiconductor chip having a through-connection extending between a first main face of the semiconductor chip and a second main face of the semiconductor chip opposite the first main face, encapsulation material at least partially encapsulating the semiconductor chip, and a first metal layer disposed over the encapsulation material and connected with the through-connection.

Description

BACKGROUND
A semiconductor package provides a protective enclosure for one or more semiconductor chips and includes interconnects to the chip(s). Semiconductor packages are employed in mobile electronic devices, including cellular telephones and other communication devices, automotive electronics, as well as other technology platforms.
Some semiconductor packages are configured to be compatible with package-on-package stacking technologies in which a separate electronic component is stacked on a base package. Such package-on-package stacks include the base package fabricated to include landing pad(s) that receive/connect an upper package with semiconductor chip(s) in the base package. It is desirable to provide package-on-package semiconductor stacks with improved interconnect geometry and in a manner that does not deleteriously increase the base package size.
For these and other reasons there is a need for the present invention.
SUMMARY
One embodiment provides a semiconductor device including a semiconductor chip having a through-connection extending between a first main face of the semiconductor chip and a second main face of the semiconductor chip opposite the first main face, encapsulation material at least partially encapsulating the semiconductor chip, and a first metal layer disposed over the encapsulation material and connected with the through-connection.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are included to provide a further understanding of embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and together with the description serve to explain principles of embodiments. Other embodiments and many of the intended advantages of embodiments will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.
FIG. 1 is a schematic cross-sectional view of a semiconductor device according to one embodiment.
FIG. 2 is a schematic cross-sectional view of another semiconductor device according to one embodiment.
FIG. 3 is a block diagram of a process for manufacturing a semiconductor device according to one embodiment.
FIGS. 4A-4D are schematic cross-sectional views of a process for manufacturing a semiconductor device according to one embodiment.
FIG. 5 is a schematic cross-sectional view of multiple semiconductor chips encapsulated by material, with each chip including a through-silicon via according to one embodiment.
FIG. 6 is a schematic cross-sectional view of an embedded wafer level package including a semiconductor chip formed to include a through-silicon via encapsulated by material, with a through-mold via formed through the encapsulation material according to one embodiment.
FIG. 7 is a schematic cross-sectional view of a package-on-package stack according to one embodiment.
 DETAILED DESCRIPTION
In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
It is to be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically noted otherwise.
Embodiments provide an embedded wafer level base package including at least one semiconductor chip formed to include at least one through-connection or through-silicon via extending through the chip. The package is fabricated to include a lower metal layer configured for attachment to an electronic board, for example a lower redistribution layer that is attached to a printed circuit board by a solder ball. The package includes an upper metal layer that forms a landing pad configured to receive another package in a stacked package-on-package configuration. The through-connection enables vertical and three-dimensional interconnection in the embedded wafer level base package.
Embodiments provide embedded wafer level packages configured for package-on-package stacking that eliminates the use of expensive substrates common to ball grid array packages. The through-connections formed as through-silicon vias in the semiconductor chip eliminates the use of long metal wires that are employed to connect conventional side-by-side or two-dimensional chips together. The embedded wafer level base package including the through-silicon via provides Z-directional electrical connection through the semiconductor chip for improved radio-frequency performance with lower power consumption. The embedded wafer level package including chips with one or more through-silicon vias provide a reduced package size and reduced package thickness.
FIG. 1 is a schematic cross-sectional view of a semiconductor device 20 according to one embodiment. Semiconductor device 20 includes a semiconductor chip 22 formed to include a through-connection 24, encapsulation material 26 at least partially encapsulating semiconductor chip 22, and a first metal layer 28 disposed over encapsulation material 26 and connected with through-connection 24.
In one embodiment, semiconductor chip 22 includes a first main face 30 opposite a second main face 32, where through-connection 24 extends between first main face 30 and second main face 32. In one embodiment, first main face 30 includes an active surface of semiconductor chip 22 that is provided with active surface connections. In one embodiment, second main face 32 of semiconductor chip 22 provides another active surface of semiconductor chip 22 and includes active surface connections.
In one embodiment, an opening 34 is formed through encapsulation material 26 and a dielectric layer 36 to enable first metal layer 28 to connect with through-connection 24.
In one embodiment, semiconductor chip 22 is a logic chip, or a memory chip, or another form of a suitable semiconductor chip. Suitable semiconductor chips include integrated circuits configured as logic circuits, control circuits, microprocessors or microelectrical-mechanical components, memory chips, power semiconductor chips such as power transistors, power diodes, insulated gate bi-polar transistors, vertical chips configured such that electric current flows in the Z-direction between main faces 30/32, embedded chips, or flip chips. In one embodiment, chip 22 is provided as a vertical power transistor having a first electrode connected to one of a source/drain on first main face 30 and a second electrode connected to the other of the source/drain on second main face 32.
In one embodiment, though-connection 24 is formed as a through-hole (112 in FIG. 4A) that is filled with metal, such as copper, gold, silver, aluminum, or alloys of these metals, or other electrically conducting metals. Through-connection 24 provides for electrical communication between main faces 30, 32 of semiconductor chip 22 and is configured to provide enhanced radio-frequency performance with reduced power consumption by shortening the connection length through the thickness (or Z-direction) of device 20. Suitable processes for forming an opening through the silicon portion of semiconductor chip 22 include deep silicon etching (DRIE) or laser drilling.
Encapsulation material 26 includes material that is generally non-electrically conducting. Suitable material for encapsulation material 26 includes polymers and/or epoxies. In one embodiment, dielectric 36 is deposited on encapsulation material 26 and suitably patterned (opened) for connection of first metal layer 28 with through-connection 24. In one embodiment, encapsulation material 26 is disposed around semiconductor chip 22 over second main face 32, leaving first main face 30 uncovered such that encapsulation material 26 is co-planar with first main face 30.
FIG. 2 is a schematic cross-sectional view of another semiconductor device 40 according to one embodiment. Semiconductor device 40 includes a semiconductor chip 42 formed to include multiple through-silicon vias (TSV) 44 a, 44 b, encapsulation material 46 at least partially encapsulating semiconductor chip 42, and a metal layer 48 a connected with TSV 44 a and a metal layer 48 b connected with TSV 44 b.
In one embodiment, TSV 44 a, 44 b are formed to extend through semiconductor chip 42 between a first main face 50 and a second main face 52. In one embodiment, openings 54 are formed extending through a potion of encapsulation material 46 and an upper dielectric layer 56 a to enable connection of metal layers 48 a, 48 b with a respective one of TSV 44 a, 44 b.
In one embodiment, device 40 includes a lower dielectric layer 56 b that is patterned to enable metal layer 60 a to connect with TSV 44 a and metal layer 60 b to connect with TSV 44 b. Device 40 thus includes first metal layers 48 a, 48 b connected with a respective one of TSV 44 a, 44 b and second metal layers 60 a, 60 b connected with a respective one of TSV 44 a, 44 b.
In one embodiment, first metal layers 48 a, 48 b provide landing pads configured to receive and electrically connect with another package placed on device 40. In one embodiment, metal layers 60 a, 60 b are connected with a printed circuit board, for example through connecting elements 70 such as solder balls.
TSV 44 a, 44 b provide three-dimensional electrical connection through semiconductor chip 42 with enhanced radio frequency performance and reduced power consumption. In one embodiment, device 40 includes one or more through-mold vias 74 that are formed to extend between opposed major surfaces 80, 82 of encapsulation material 46. Through-mold vias (TMV) 74 provide vertical electrical connection through device 40.
In one embodiment, TSV 44 a is fabricated to include a width W1 and TMV 74 is fabricated to include a width W2, where the width W1 of TSV 44 a is less than the width W2 of TMV 74.
In one embodiment, device 40 is provided as a logic device configured for use as a base package in a package-on-package system. Depending upon the format of semiconductor chip 42, device 40 is a logic device, a memory device, or other suitable semiconductor package.
FIG. 3 is a block diagram 100 of a process for manufacturing a semiconductor device according to one embodiment. Process 100 includes providing a semiconductor chip at 102. At 104, at least one through-connection is formed to extend between a first main face of the semiconductor chip and an opposing second main face of the semiconductor chip. At 106, the first main face of the semiconductor chip is placed on a carrier. At 108, encapsulation material is applied over the semiconductor chip and the carrier. In one embodiment, the first main face is not covered by encapsulation material since the first main face is in contact with the carrier. At 110, the carrier is removed from the semiconductor chip and the encapsulation material. Embodiments of process 100 provide a manufacturing approach for embedded or fan-out wafer level package assembly, as further described below.
FIGS. 4A-4D provide schematic cross-sectional views of the fabrication of semiconductor device 20 (FIG. 1) according to one embodiment.
FIG. 4A is a schematic cross-sectional view of semiconductor chip 22 including openings 112 that are filled with electrically conducting material to form though-connection 24. Through-connection 24 extends between first main face 30 and second main face 32 of chip 22.
FIG. 4B is a schematic cross-sectional view of first main face 30 of chip 22 placed on a carrier 120. In one embodiment, carrier 120 includes a carrier substrate 122 and an adhesive layer 124 disposed on substrate 122. Carrier substrate 122 includes metal, plastic, paper, laminate or other suitable substrates for carrying chip 22. Chip 22 is picked and placed in position on adhesive layer 124 of carrier 120.
FIG. 4C is a schematic cross-sectional view of encapsulation material 26 disposed over carrier 120 to at least partially encapsulate chip 22. In one embodiment, encapsulation material 26 is injection molded over chip 22 and onto carrier 120. In one embodiment, encapsulation material 26 is compression molded over chip 22 and onto carrier 120. In one embodiment, encapsulation material 26 is planarized or chemically mechanically polished to achieve a desired thickness of material 26 over chip 22.
FIG. 4D is a schematic cross-sectional view of chip 22 partially encapsulated by encapsulation material 26. In one embodiment, after removal of carrier 120 (FIG. 4C), encapsulation material 26 is co-planar with first main face 30 of chip 22.
FIG. 5 is a schematic cross-sectional view of semiconductor package units 130 fabricated according to embodiments described above in FIGS. 4A-4D to include multiple semiconductor chips 22 a, 22 b, 22 c. Each of these multiple semiconductor chips 22 a, 22 b, 22 c include one or more through-connections 24 extending between main faces of the chips. Encapsulation material 26 covers at least a portion of the chips after the carrier 120 (FIG. 4C) is removed. In one embodiment, the package units 130 are configured for separation or singulation along saw streets 132. Sawing or dicing along saw streets 132 separates individual components 130 for subsequent fabrication into package 20 or package 40, as described above.
FIG. 6 is a schematic cross-sectional view of semiconductor device 40 fabricated according to the manufacturing process described above. For example, the embedded chip 22 illustrated in FIG. 4D or the embedded chips 22 a, 22 b, 22 c of the semiconductor units 130 illustrated in FIG. 5 are each suited for subsequent processing to include upper and lower metal layers connected with through-connections 24/44.
In one embodiment, semiconductor chip 22/42 is at least partially embedded in encapsulation material 26 and further processed to include upper metal first layers 28/48 electrically connected to through-connections 24/44, and lower or second metal layer 60 electrically connected to through-connections 24/44. In one embodiment, the Z-direction electrical connectivity through the semiconductor package 40 is supplemented with TMV 74 formed to extend through encapsulation material 26 between first metal layer 28/48 and second metal layer 60.
In one embodiment, semiconductor package 40 is configured for use as a base package in a package-on-package system by connecting second metal layer 60 to a printed circuit board, for example with solder balls or other suitable connecting elements. In one embodiment, semiconductor package 40 is a memory package or a logic package and configured for mounting to a base package in a package-on-package system.
FIG. 7 is a schematic cross-sectional view of a semiconductor package-on-package (POP) stack 140 according to one embodiment. POP stack 140 includes base semiconductor package 40 electrically connected to a printed circuit board 142, and another package 144 stacked on base semiconductor package 40. In one embodiment, solder balls 70 connect second metal layer 60 of base package 40 to printed circuit board 142. Second package 144 or top package 144 is electrically connected to landing pads provided by first metal layer 28/48. In this manner, electrical connection is established between second package 144 through landing pads 28/48, TSV 24/44, second metal layer 60, solder balls 70, and ultimately to printed circuit board 142.
In one embodiment, first metal layer 28/48 and second metal layer 60 are patterned redistribution layers patterned over an embedded chip 22 to provide an embedded package-on-package (ePOP) device 140.
In one embodiment, base package 40 is provided as a logic device and second package 144 is provided as a memory device. In one embodiment, base semiconductor package 40 is provided as a first memory device and second package 144 is provided as a second memory device. Printed circuit board 142 includes electronic boards, printed circuit boards, or other suitable electronic devices which POP 40/144 is electrically connected.
Embodiments provide a semiconductor package including one or more semiconductor chips provided with one or more through-silicon vias. Forming the via in the silicon portion of the chip provides a very uniform via as compared to through-mold vias. Through-mold vias have openings formed in the encapsulation material, which is typically highly filled with silica particles. The TMV are consequently formed to have a greater width compared to the TSV to account for the undercuts that are formed in the encapsulation material when the opening is formed.
Embodiments provide an embedded wafer level semiconductor package including through-silicon vias having three-dimensional interconnect geometry, smaller package sizes as compared to wire bonded packages, and improved radio-frequency with reduced power consumption.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments of packages configured to support package-on-package semiconductor stacking, as discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.

Claims (22)

1. A semiconductor device comprising:
a semiconductor chip comprising a through-connection extending between a first main face of the semiconductor chip and a second main face of the semiconductor chip opposite the first main face;
encapsulation material encapsulating the semiconductor chip and extending beyond lateral dimensions of the semiconductor chip and having a first main surface parallel with and adjacent to the first main face and a second main surface parallel with and adjacent to the second main face ; and
a first metal layer disposed over the first main surface of the encapsulation material and connected with the through-connection;
a second metal layer disposed over the second main surface of the encapsulation material and connected with the through-connection such that the first metal layer is disposed adjacent to the first main face and the second metal layer is disposed adjacent to the second main face; and
at least one through-mold connection extending through the encapsulating material from the first main surface to the second main surface in a region of the encapsulation material beyond the lateral dimensions of the semiconductor chip, the at least one through-mold connection connected between the first and second metal layers.
2. The semiconductor device of claim 1, wherein one of the first main face and the second main face of the semiconductor chip is not encapsulated by the encapsulation material.
3. The semiconductor device of claim 1, wherein the semiconductor chip comprises a first active area on the first main face and a second active area on the second main face.
4. The semiconductor device of claim 1, comprising multiple through-connections extending between the first main face and the second main face of the semiconductor chip.
5. The semiconductor device of claim 4, wherein the first metal layer and the second metal layer are substantially co-planar to the first main face, each connected to a separate one of the multiple through-connections.
6. A semiconductor device comprising:
a semiconductor chip comprising a through-connection extending between a first main face of the semiconductor chip and a second main face of the semiconductor chip opposite the first main face;
encapsulation material at least partially encapsulating the semiconductor chip; and
a first metal layer disposed over the encapsulation material and connected with the through-connection; and
a second metal layer disposed over the encapsulation material and connected with the through-connection, wherein the first metal layer is disposed adjacent to the first main face and the second metal layer is disposed adjacent to the second main face, wherein the first and second metal layers each comprise a redistribution layer patterned in a dielectric layer disposed on the encapsulation material.
7. A semiconductor device comprising:
a semiconductor chip comprising a through-connection extending between a first main face of the semiconductor chip and a second main face of the semiconductor chip opposite the first main face;
encapsulation material at least partially encapsulating the semiconductor chip; and
a first metal layer disposed over the encapsulation material and connected with the through-connection; and
a second metal layer disposed over the encapsulation material and connected with the through-connection, wherein the first metal layer is disposed adjacent to the first main face and the second metal layer is disposed adjacent to the second main face, wherein the encapsulation material comprises a first surface opposite a second surface and a through-mold via extending between the first and second surfaces of the encapsulation material.
8. A method of manufacturing a semiconductor device, the method comprising:
providing a semiconductor chip;
forming at least one through-connection extending between a first main face of the semiconductor chip and an opposing second main face of the semiconductor chip;
placing the first main face of the semiconductor chip on a carrier;
applying encapsulation material over the semiconductor chip and the carrier so as to encase all but the first main surface of the semiconductor chip in the encapsulation material;
removing the carrier from the semiconductor chip and the encapsulation material; and
forming at least one through-connection between opposing first and second major surfaces of the encapsulation material, the first major surface of the encapsulation material being coplanar with the first main face of the semiconductor chip and the second major surface of the encapsulation material being disposed above and substantially parallel with the second main face of the semiconductor chip.
9. The method of claim 8, further comprising:
applying a first metal layer adjacent to the first main face of the semiconductor chip.
10. The method of claim 9, further comprising:
electrically coupling the first metal layer with the at least one through-connection.
11. The method of claim 9, further comprising:
applying external connection elements to the first metal layer.
12. The method of claim 8, further comprising:
applying a second metal layer adjacent to the second main face of the semiconductor chip.
13. The method of claim 12, further comprising:
electrically coupling the second metal layer with the at least one through-connection.
14. The method of claim 8, wherein providing a semiconductor chip comprises providing multiple semiconductor chips, each semiconductor chip comprising at least one through-connection extending between a first main face of the semiconductor chip and an opposing second main face of the semiconductor chip.
15. The method of claim 14, wherein applying encapsulation material over the semiconductor chip and the carrier comprises applying encapsulation material over the multiple semiconductor chips and the carrier.
16. The method of claim 15, further comprising:
cutting through the encapsulation material and singulating semiconductor packages each comprising at least one of the semiconductor chips.
17. A method of connecting a package-on-package stack to a board, the method comprising:
obtaining a base semiconductor package comprising a semiconductor chip comprising a through-silicon connection extending between opposing main faces of the semiconductor chip and connected to a first metal layer disposed on a first surface of the base semiconductor package and a second metal layer disposed on a second surface of the base semiconductor package opposite the first surface, and a through-mold connection connected to the first and second metal layers and extending between opposing surfaces of an encapsulation material encasing all but a main face of the semiconductor chip proximate to the second metal layer;
electrically connecting a second semiconductor package eto the first metal layer; and
connecting the second metal layer to an electronic board.
18. The method of claim 17, comprising quality testing at least one of the base semiconductor package and the second semiconductor package.
19. A semiconductor package-on-package stack comprising:
a base semiconductor package comprising a semiconductor chip comprising a through-silicon connection extending between opposing main faces of the semiconductor chip, encapsulation material encapsulating all but one of the opposing main faces of the semiconductor chip and including a through-mold connection extending between opposing main faces of the encapsulation material, a first metal layer disposed on a first surface of the base semiconductor package and connected with the through-silicon and through-mold connections, and a second metal layer disposed on a second surface of the base semiconductor package opposite the first surface and connected with the through-silicon and through-mold connections, the second metal layer configured for electrical connection to a circuit board; and
a second semiconductor package electrically connected to the first metal layer.
20. A semiconductor package-on-package stack comprising:
a base semiconductor package comprising a semiconductor chip comprising a through-connection extending between opposing main faces of the semiconductor chip, encapsulation material partially encapsulating the semiconductor chip, a first metal layer disposed on a first surface of the base semiconductor package and connected with the through-connection, and a second metal layer disposed on a second surface of the base semiconductor package opposite the first surface and connected with the through-connection, the second metal layer configured for electrical connection to a circuit board; and
a second semiconductor package electrically connected to the first metal layer, wherein at least one of the first and second surfaces of the base semiconductor package comprises a dielectric layer, and at least one of the first and second metal layers is patterned in the dielectric layer.
21. The semiconductor package-on-package stack of claim 19, wherein the through-silicon connection has a first width and the through-mold connection has a second width that is larger than the first width.
22. The semiconductor package-on-package stack of claim 19, comprising multiple connection pads disposed on the first surface of the base semiconductor package, each connection pad connected to at least one of multiple through-connections formed to extend between opposing main faces of the semiconductor chip.
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Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100252934A1 (en) * 2009-04-07 2010-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. Three-Dimensional Semiconductor Architecture
US20110193221A1 (en) * 2010-02-05 2011-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC Architecture with Interposer for Bonding Dies
US20110254160A1 (en) * 2010-04-16 2011-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. TSVs with Different Sizes in Interposers for Bonding Dies
US20120032340A1 (en) * 2010-08-06 2012-02-09 Stats Chippac, Ltd. Semiconductor Die and Method of Forming FO-WLCSP Vertical Interconnect Using TSV and TMV
US20120038044A1 (en) * 2010-08-12 2012-02-16 Siliconware Precision Industries Co., Ltd. Chip scale package and fabrication method thereof
US20130001797A1 (en) * 2011-06-28 2013-01-03 Choi Yun-Seok Package on package using through substrate vias
US20130105970A1 (en) * 2010-05-26 2013-05-02 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Conductive Posts and Heat Sink Over Semiconductor Die Using Leadframe
DE102013109825A1 (en) 2012-09-07 2014-03-13 Infineon Technologies Ag System and method for a coreless transformer
US20140110728A1 (en) * 2011-06-01 2014-04-24 The Hong Kong University Of Science And Technology Submount with cavities and through vias for led packaging
US8928132B2 (en) 2011-02-17 2015-01-06 Samsung Electronics Co., Ltd. Semiconductor package having through silicon via (TSV) interposer and method of manufacturing the semiconductor package
US9269691B2 (en) 2010-05-26 2016-02-23 Stats Chippac, Ltd. Semiconductor device and method of making an embedded wafer level ball grid array (EWLB) package on package (POP) device with a slotted metal carrier interposer
US20170373029A1 (en) * 2016-06-23 2017-12-28 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
US10177115B2 (en) * 2014-09-05 2019-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8822281B2 (en) * 2010-02-23 2014-09-02 Stats Chippac, Ltd. Semiconductor device and method of forming TMV and TSV in WLCSP using same carrier
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8283754B2 (en) 2010-08-13 2012-10-09 Taiwan Semiconductor Manufacturing Company, Ltd. Seal ring structure with metal pad
US8304913B2 (en) 2010-09-24 2012-11-06 Intel Corporation Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby
GB2514032B (en) * 2010-09-24 2015-05-06 Intel Corp Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby
US8883561B2 (en) * 2011-04-30 2014-11-11 Stats Chippac, Ltd. Semiconductor device and method of embedding TSV semiconductor die within encapsulant with TMV for vertical interconnect in POP
US9087701B2 (en) * 2011-04-30 2015-07-21 Stats Chippac, Ltd. Semiconductor device and method of embedding TSV semiconductor die within substrate for vertical interconnect in POP
US8288209B1 (en) 2011-06-03 2012-10-16 Stats Chippac, Ltd. Semiconductor device and method of using leadframe bodies to form openings through encapsulant for vertical interconnect of semiconductor die
US9679863B2 (en) * 2011-09-23 2017-06-13 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming interconnect substrate for FO-WLCSP
US8778733B2 (en) 2012-03-19 2014-07-15 Infineon Technologies Ag Semiconductor package and methods of formation thereof
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US9978654B2 (en) 2012-09-14 2018-05-22 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming dual-sided interconnect structures in Fo-WLCSP
US9818734B2 (en) 2012-09-14 2017-11-14 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming build-up interconnect structures over a temporary substrate
US9385075B2 (en) 2012-10-26 2016-07-05 Infineon Technologies Ag Glass carrier with embedded semiconductor device and metal layers on the top surface
US20140133105A1 (en) * 2012-11-09 2014-05-15 Nvidia Corporation Method of embedding cpu/gpu/logic chip into a substrate of a package-on-package structure
US9320149B2 (en) * 2012-12-21 2016-04-19 Intel Corporation Bumpless build-up layer package including a release layer
US11239138B2 (en) * 2014-06-27 2022-02-01 Taiwan Semiconductor Manufacturing Company Methods of packaging semiconductor devices and packaged semiconductor devices
US10056352B2 (en) 2014-07-11 2018-08-21 Intel IP Corporation High density chip-to-chip connection
US9893017B2 (en) 2015-04-09 2018-02-13 STATS ChipPAC Pte. Ltd. Double-sided semiconductor package and dual-mold method of making same
JP6592948B2 (en) * 2015-04-21 2019-10-23 富士通株式会社 Manufacturing method of semiconductor device
US11342282B2 (en) * 2020-02-21 2022-05-24 Advanced Semiconductor Engineering, Inc. Semiconductor device package including a reinforcement structure on an electronic component and method of manufacturing the same

Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4939568A (en) * 1986-03-20 1990-07-03 Fujitsu Limited Three-dimensional integrated circuit and manufacturing method thereof
US5202754A (en) * 1991-09-13 1993-04-13 International Business Machines Corporation Three-dimensional multichip packages and methods of fabrication
US5424245A (en) 1994-01-04 1995-06-13 Motorola, Inc. Method of forming vias through two-sided substrate
US6569762B2 (en) 2000-06-16 2003-05-27 Chartered Semiconductor Manufacturing Ltd. Three dimensional IC package module
DE10205026C1 (en) 2002-02-07 2003-05-28 Bosch Gmbh Robert Semiconductor substrate used for vertical integration of integrated circuits comprises a first conductor strip on its front side, and a region formed by insulating trenches and electrically insulated from the substrate
US6960837B2 (en) 2002-02-26 2005-11-01 International Business Machines Corporation Method of connecting core I/O pins to backside chip I/O pads
US20060087044A1 (en) 2003-05-07 2006-04-27 Bernd Goller Electronic component, and system carrier and panel for producing an electronic component
US20060131721A1 (en) 2004-12-21 2006-06-22 Seiko Epson Corporation Semiconductor device, method for manufacturing semiconductor device, circuit board, and electronic instrument
US7247518B2 (en) 2001-11-01 2007-07-24 Rohm Co., Ltd. Semiconductor device and method for manufacturing same
US20070222050A1 (en) 2006-03-17 2007-09-27 Seung Hyun Lee Stack package utilizing through vias and re-distribution lines
US20080136004A1 (en) 2006-12-08 2008-06-12 Advanced Chip Engineering Technology Inc. Multi-chip package structure and method of forming the same
US20080272465A1 (en) * 2007-05-04 2008-11-06 Stats Chippac, Ltd. Semiconductor Die with Through-Hole Via on Saw Streets and Through-Hole Via in Active Area of Die
US20080274603A1 (en) * 2007-05-04 2008-11-06 Stats Chippac, Ltd. Semiconductor Package Having Through-Hole Via on Saw Streets Formed with Partial Saw
US20090008793A1 (en) 2007-07-02 2009-01-08 Infineon Technologies Ag Semiconductor device
US7480426B1 (en) * 2008-03-25 2009-01-20 International Business Machines Corporation Method of forming a three-dimensional stacked optical device
US20100133704A1 (en) * 2008-12-01 2010-06-03 Stats Chippac, Ltd. Semiconductor Device and Method of Forming an Interposer Package with Through Silicon Vias

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3772066B2 (en) * 2000-03-09 2006-05-10 沖電気工業株式会社 Semiconductor device
JP3740469B2 (en) * 2003-01-31 2006-02-01 株式会社東芝 Semiconductor device and manufacturing method of semiconductor device
US20090008792A1 (en) * 2004-11-19 2009-01-08 Industrial Technology Research Institute Three-dimensional chip-stack package and active component on a substrate

Patent Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4939568A (en) * 1986-03-20 1990-07-03 Fujitsu Limited Three-dimensional integrated circuit and manufacturing method thereof
US5202754A (en) * 1991-09-13 1993-04-13 International Business Machines Corporation Three-dimensional multichip packages and methods of fabrication
US5424245A (en) 1994-01-04 1995-06-13 Motorola, Inc. Method of forming vias through two-sided substrate
US6569762B2 (en) 2000-06-16 2003-05-27 Chartered Semiconductor Manufacturing Ltd. Three dimensional IC package module
US7247518B2 (en) 2001-11-01 2007-07-24 Rohm Co., Ltd. Semiconductor device and method for manufacturing same
DE10205026C1 (en) 2002-02-07 2003-05-28 Bosch Gmbh Robert Semiconductor substrate used for vertical integration of integrated circuits comprises a first conductor strip on its front side, and a region formed by insulating trenches and electrically insulated from the substrate
US6960837B2 (en) 2002-02-26 2005-11-01 International Business Machines Corporation Method of connecting core I/O pins to backside chip I/O pads
US20060087044A1 (en) 2003-05-07 2006-04-27 Bernd Goller Electronic component, and system carrier and panel for producing an electronic component
US20060131721A1 (en) 2004-12-21 2006-06-22 Seiko Epson Corporation Semiconductor device, method for manufacturing semiconductor device, circuit board, and electronic instrument
US20070222050A1 (en) 2006-03-17 2007-09-27 Seung Hyun Lee Stack package utilizing through vias and re-distribution lines
US20080136004A1 (en) 2006-12-08 2008-06-12 Advanced Chip Engineering Technology Inc. Multi-chip package structure and method of forming the same
US20080272465A1 (en) * 2007-05-04 2008-11-06 Stats Chippac, Ltd. Semiconductor Die with Through-Hole Via on Saw Streets and Through-Hole Via in Active Area of Die
US20080274603A1 (en) * 2007-05-04 2008-11-06 Stats Chippac, Ltd. Semiconductor Package Having Through-Hole Via on Saw Streets Formed with Partial Saw
US20090008793A1 (en) 2007-07-02 2009-01-08 Infineon Technologies Ag Semiconductor device
DE102008028072A1 (en) 2007-07-02 2009-01-22 Infineon Technologies Ag Semiconductor device
US7480426B1 (en) * 2008-03-25 2009-01-20 International Business Machines Corporation Method of forming a three-dimensional stacked optical device
US20100133704A1 (en) * 2008-12-01 2010-06-03 Stats Chippac, Ltd. Semiconductor Device and Method of Forming an Interposer Package with Through Silicon Vias

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Brunnbauer et al., "Embedded Wafer Level Ball Grid Array (eWLB)," 2006 Electronics Packaging Technology Conference, Copyright 2006, 5 pages.

Cited By (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8552563B2 (en) * 2009-04-07 2013-10-08 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional semiconductor architecture
US9111936B2 (en) 2009-04-07 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional semiconductor architecture
US20100252934A1 (en) * 2009-04-07 2010-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. Three-Dimensional Semiconductor Architecture
US8753939B2 (en) 2009-04-07 2014-06-17 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional semiconductor architecture
US9559003B2 (en) 2009-04-07 2017-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional semiconductor architecture
US11854990B2 (en) 2010-02-05 2023-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming a semiconductor device having TSV formed through a silicon interposer and a second silicon substrate with cavity covering a second die
US10923431B2 (en) 2010-02-05 2021-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming a 3D IC architecture including forming a first die on a first side of a first interconnect structure and a second die in an opening formed in a second side
US10297550B2 (en) 2010-02-05 2019-05-21 Taiwan Semiconductor Manufacturing Company, Ltd. 3D IC architecture with interposer and interconnect structure for bonding dies
US20110193221A1 (en) * 2010-02-05 2011-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC Architecture with Interposer for Bonding Dies
US8455995B2 (en) * 2010-04-16 2013-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. TSVs with different sizes in interposers for bonding dies
US20110254160A1 (en) * 2010-04-16 2011-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. TSVs with Different Sizes in Interposers for Bonding Dies
US20130105970A1 (en) * 2010-05-26 2013-05-02 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Conductive Posts and Heat Sink Over Semiconductor Die Using Leadframe
US9269691B2 (en) 2010-05-26 2016-02-23 Stats Chippac, Ltd. Semiconductor device and method of making an embedded wafer level ball grid array (EWLB) package on package (POP) device with a slotted metal carrier interposer
US9064859B2 (en) * 2010-05-26 2015-06-23 Stats Chippac, Ltd. Semiconductor device and method of forming conductive posts and heat sink over semiconductor die using leadframe
US9153494B2 (en) 2010-08-06 2015-10-06 Stats Chippac, Ltd. Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMV
US20120032340A1 (en) * 2010-08-06 2012-02-09 Stats Chippac, Ltd. Semiconductor Die and Method of Forming FO-WLCSP Vertical Interconnect Using TSV and TMV
US8895440B2 (en) * 2010-08-06 2014-11-25 Stats Chippac, Ltd. Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMV
US9040361B2 (en) * 2010-08-12 2015-05-26 Siliconware Precision Industries Co., Ltd. Chip scale package with electronic component received in encapsulant, and fabrication method thereof
US20120038044A1 (en) * 2010-08-12 2012-02-16 Siliconware Precision Industries Co., Ltd. Chip scale package and fabrication method thereof
US8928132B2 (en) 2011-02-17 2015-01-06 Samsung Electronics Co., Ltd. Semiconductor package having through silicon via (TSV) interposer and method of manufacturing the semiconductor package
US9431592B2 (en) * 2011-06-01 2016-08-30 The Hong Kong University Of Science And Technology Submount with cavities and through vias for LED packaging
US20140110728A1 (en) * 2011-06-01 2014-04-24 The Hong Kong University Of Science And Technology Submount with cavities and through vias for led packaging
US20130001797A1 (en) * 2011-06-28 2013-01-03 Choi Yun-Seok Package on package using through substrate vias
DE102013109825A1 (en) 2012-09-07 2014-03-13 Infineon Technologies Ag System and method for a coreless transformer
US10177115B2 (en) * 2014-09-05 2019-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming
US10672738B2 (en) 2014-09-05 2020-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming
US11444057B2 (en) 2014-09-05 2022-09-13 Taiwan Semiconductor Manufacturing Company Ltd Package structures and methods of forming
US20170373029A1 (en) * 2016-06-23 2017-12-28 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
US10229865B2 (en) * 2016-06-23 2019-03-12 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package

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