US8110903B2 - QFN package - Google Patents
QFN package Download PDFInfo
- Publication number
- US8110903B2 US8110903B2 US12/544,468 US54446809A US8110903B2 US 8110903 B2 US8110903 B2 US 8110903B2 US 54446809 A US54446809 A US 54446809A US 8110903 B2 US8110903 B2 US 8110903B2
- Authority
- US
- United States
- Prior art keywords
- die
- leadframe
- package
- apertures
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active, expires
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01076—Osmium [Os]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Definitions
- Quad Flat No-Lead (QFN) packaging technology can be used to produce packaged die which are not significantly bigger than the actual die.
- QFN packages are fabricated by attaching the die to a metal leadframe and forming electrical connections between the leadframe and pads on the die using wirebonds.
- a moulding compound (which may also be referred to as a ‘mould’, ‘mold’ or ‘molding’ compound) is then used to encapsulate the die and the wirebonds and form the package.
- One face of the leadframe is exposed on the base of the QFN package and the exposed areas of metal may be used to attach the QFN package to a printed circuit board (PCB) or other substrate, e.g. using solder paste which may be stencil printed onto the PCB.
- PCB printed circuit board
- Chip-on-Lead is a variant of QFN in which the die is mounted directly onto all or some of the leads (which may also be referred to as ‘terminals’ or ‘electrical terminals’), often in addition to mounting onto a separate die attach region of the leadframe, which may be referred to as the paddle.
- Use of CoL QFNs may enable smaller packages, because there is a reduction in the minimum distance between the edge of the die and the package edge (e.g. a reduction from around 1 mm to around 0.5 mm).
- FIG. 1 shows a comparison of a QFN package 101 and a CoL QFN package 102 .
- Each example shows a cross-section through a portion of a package and shows the leadframe 111 , 112 , die 121 , 122 , adhesive 131 , 132 , wirebonds 141 , 142 and moulding compound 151 , 152 .
- the package is formed by encapsulating a die mounted on a leadframe with a moulding compound using a mould chase.
- the mould chase comprises a number of internal projections which form openings in the mould compound to expose regions of the leadframe. These exposed regions of the leadframe may then be used for soldering the package to a substrate.
- the arrangement of the openings may be designed such that each aperture is the same shape and size and/or that the apertures are arranged in multiple rows on the underside of the package.
- a first aspect provides a packaged die comprising a leadframe and a die attached to the leadframe, wherein the die and the leadframe are encapsulated in a moulding compound and the packaged die further comprising a plurality of apertures in the moulding compound each of which expose a portion of the leadframe.
- Each aperture may be formed by an internal projection in a mould chase used when encapsulating the die and the leadframe.
- Each aperture may form an area for connection of the packaged die to a substrate.
- the area may be used for at least one of a physical connection, an electrical connection and a thermal connection.
- Each of the plurality of apertures may have the same area.
- the leadframe may have a substantially constant thickness.
- the plurality of apertures may be formed on an underside of the packaged die and are arranged in at least two rows of apertures around a portion of the periphery of the underside.
- the leadframe may comprise a lead that fans underneath the die and wherein one of the plurality of apertures exposes a portion of the lead underneath the die.
- the packaged die may further comprise a plurality of solder elements, wherein each solder elements is attached to an exposed portion of the leadframe.
- the package die may be a Quad Flat No-Lead package or a Chip-on-Lead Quad Flat No-Lead package.
- a second aspect provides a method of fabricating a packaged die comprising: attaching a die to a leadframe; wirebonding the die to the leadframe; and encapsulating the die and the leadframe using a mould compound and a mould chase comprising a plurality of projections, wherein each projection forms an aperture in the mould compound that exposes a portion of the leadframe.
- the method may further comprise: separating the encapsulated die to form a plurality of packaged die.
- the method may further comprise: attaching a solder element to each exposed portion of the leadframe.
- Each of the plurality of apertures may have the same area.
- the leadframe may have a substantially constant thickness.
- the package die may be a Quad Flat No-Lead package or a Chip-on-Lead Quad Flat No-Lead package.
- FIGS. 2-6 and 8 - 13 of the drawings Further aspects provide a packaged IC substantially as described with reference to any of FIGS. 2-6 and 8 - 13 of the drawings and a method of packaging an IC substantially as described with reference to FIG. 7 of the drawings.
- FIG. 1 shows a comparison of a QFN package and a CoL QFN package and an example of a package comprising a part-etched leadframe
- FIG. 2 shows a schematic diagram of two improved CoL QFN packages
- FIG. 3 shows a schematic diagram of an improved CoL QFN package bonded to a substrate
- FIG. 4 shows schematic diagrams of bottom views of four example improved CoL QFN packages
- FIG. 5 shows a schematic diagram of a QFN package in which leads fan underneath the die
- FIG. 6 shows a schematic diagram of another two improved CoL QFN packages
- FIG. 7 shows a flow diagram of an example method of manufacture of an improved QFN package
- FIGS. 8-12 show further examples of improved QFN packages.
- FIG. 13 shows a schematic diagram of an improved QFN package which includes an embedded discrete component in addition to a silicon die.
- Embodiments of the present invention are described below by way of example only. These examples represent the best ways of putting the invention into practice that are currently known to the Applicant although they are not the only ways in which this could be achieved.
- the description sets forth the functions of the example and the sequence of steps for constructing and operating the example. However, the same or equivalent functions and sequences may be accomplished by different examples.
- FIG. 1 shows a comparison of a QFN package 101 and a CoL QFN package 102 .
- Use of CoL QFNs may enable smaller packages and can also provide an increase in the number of leads for a given package size, by enabling an area array of leads—some, or all, of which may be located underneath the die. This is typically achieved using half- or part-etched leadframes, where the full thickness areas of leadframe form the exposed leads.
- This is shown in the third example, 103 , in FIG. 1 , which shows a cross-section through a portion of a package including the leadframe 113 , die 123 , adhesive 133 , wirebonds 143 and moulding compound 153 .
- the half- or part-etched regions of the leadframe 113 are indicated by brackets 163 .
- FIG. 2 shows a schematic diagram of two improved CoL QFN packages 201 , 202 .
- the packages are formed using a mould (which may also be referred as a mold, mould chase or mold chase) which has internal projections 203 which create apertures 204 in the moulding compound 205 to expose the leadframe 206 .
- a mould which may also be referred as a mold, mould chase or mold chase
- internal projections 203 which create apertures 204 in the moulding compound 205 to expose the leadframe 206 .
- solder lands i.e. areas to which solder can wet
- FIG. 3 shows a schematic diagram of an improved CoL QFN package 301 bonded to a substrate 302 using a number of solder balls 303 .
- solder balls may alternatively be used, e.g. solder bumps. References to solder balls in the following description are by way of example only.
- FIG. 4 shows schematic diagrams of a bottom views of four examples of improved CoL QFN packages 401 - 404 which each show a number of exposed lands 412 which are all the same size and shape.
- the examples in FIG. 4 also show the outline of the die (or integrated circuit (IC)) 411 and the lands may be outside and/or within the outline of the die.
- the outline of the paddle is shown 413 and some of the exposed lands 412 are underneath the paddle whilst others are outside the paddle area and may be used to provide electrical connections to leads which fan underneath the die (as described in more detail below).
- the fourth example 404 has an exposed paddle 414 .
- the corresponding solder bumps formed on a substrate to which the package is to be bonded can all be the same shape and size. This means that when the solder is reflowed, all the resulting solder bumps should be the same height and this increases the yield and reliability of the solder bonding process.
- the geometry of the apertures may be chosen such that solder balls (solder bumps or other solder elements), could be applied to the QFN package and used to mount the package on a substrate in a similar manner to a BGA (ball grid array) package.
- the leads (within the leadframe 206 ) can fan underneath the die, such that the aperture 204 on the lead is underneath the die, rather than around the periphery of the die (e.g. underneath where a wirebond 207 joins the leadframe 206 ). Routing of leads underneath the die can be used to make better use of the available area on the bottom of the package and/or to create multiple rows of lands. This is shown in FIG. 5 .
- FIG. 5 shows a schematic diagram of a die (indicated by the dotted outline 501 ) and a number of leads 502 - 508 , some of which ( 502 - 505 ) fan underneath the die.
- the positions of the wirebonds on the leads are marked with an ‘X’ 509 and the positions of the apertures in the moulding compound which form the solder lands are shown as shaded circles 510 .
- those leads 502 - 505 which fan underneath the die have solder lands towards their interior (or inboard) end (i.e.
- the spacing of the solder lands is labelled A and B (for each of the two perpendicular directions) and each of these spacings is larger than the spacing of the leads, as labelled C in FIG. 5 .
- the spacing of the lands (A, B) may be restricted by design rules relating to solder bonding, whist the spacing of the leads (C) may instead be dominated by design rules for wirebonding, leadframe manufacture or by the IC design (e.g. the position and number of I/Os).
- the leadframe need not be part-etched (or part-sawn), e.g. as shown in example 103 in FIG. 1 .
- the manufacturing process is simplified and the overall leadframe thickness may be reduced (which may enable a reduced lead pitch) or may stay the same (e.g. 150 ⁇ m thick), which provides a more robust leadframe (and may improve the yield of the wirebonding process).
- the methods described herein may be used to make low cost packaged ICs, where the ICs have too many connections for single row QFNs.
- the two improved CoL QFN packages shown in FIG. 2 are designed to be punched out to separate the packages (e.g. along doffed line 208 ).
- Internal projections 209 in the upper mould chase 210 and corresponding internal projections in the lower mould chase 211 expose a portion of the leadframe on both sides along the punch line 208 .
- These internal projections 209 in the upper mould chase 210 also serve to clamp the leadframe 206 against the lower mould chase 211 which may assist in forming the apertures 203 .
- other techniques may be used to ensure that the leadframe 206 is held in contact with the lower mould chase 211 (e.g. film assisted moulding).
- FIG. 6 shows a schematic diagram of two improved CoL QFN packages 601 , 602 which are designed to be sawn (e.g. along dotted line 603 ) rather than punched.
- the packages are formed using a mould chase which has internal projections 604 which create apertures 605 in the moulding compound 606 to expose the leadframe 607 .
- only one of the mould chases e.g. the bottom mould chase 608
- both mould chases 608 , 609 may comprise projections.
- FIG. 7 shows a flow diagram of an example method of manufacture of an improved QFN package, such as an improved CoL QFN package as described above.
- the die are attached to the leadframe (block 701 ) using any suitable material, such as a film adhesive, which typically is electrically non-conductive, and then the die is wirebonded to the leadframe (block 702 ). These wirebonds form the electrical connection between pads on the die and the leads in the leadframe. This process is typically performed on a leadframe strip or sheet which supports many die (e.g. many hundreds of die) and provides economies of scale in processing.
- the leadframe and die are encapsulated in a moulding compound using a mould chase with internal projections to form solder lands (block 703 ) and then the encapsulated die are separated (block 704 ), for example by punching or sawing (or any other process, e.g. laser ablation, metal etching etc.).
- the moulding process may use any suitable moulding technique which uses a mould chase.
- film assisted moulding may be used (e.g. as developed by Boschman Technologies. b.v.).
- the film provides protection for the die and forms a gasket between the mould chase and the lead frame to prevent bleeding of the moulding compound.
- Moulding techniques which are used for the manufacture of exposed-die packages may also be used.
- FIG. 7 does not show the addition of solder elements (e.g. solder balls, or plated or stencil printed solder); however solder elements may be added prior to separation of the encapsulated die (i.e. prior to block 704 ) or at an alternative stage in the process (e.g. after block 704 ).
- solder elements e.g. solder balls, or plated or stencil printed solder
- FIG. 8 is a schematic diagram of an improved QFN package 801 .
- the die 802 is mounted on a paddle 803 which extends beyond the die.
- the die may be mounted using an adhesive 804 or other material which may be electrically conductive or non-conductive.
- the die 802 and leadframe 805 are encapsulated (after wirebonding) in a moulding compound 806 using a mould chase 807 which has internal projections 808 which create apertures 809 in the moulding compound 806 to expose the leadframe 805 .
- This improved QFN package 801 may, for example, be a sawn or a punched QFN package.
- FIG. 8 shows a number of apertures forming solder lands underneath the paddle 803 . It will be appreciated that the number, shape and configuration of the solder lands may be chosen by the designer and implemented through the design of the internal projections in the mould chase.
- the methods described above enable a very flexible design of a QFN package and of the leadframe and arrangement of solder lands.
- the leadframe can route between wirebond connections to the die and solder lands which enable connections to the substrate.
- the die is mounted on a region of leadframe which is smaller than the die and in the example of FIG. 8 , the die is mounted on a region of leadframe (the paddle 803 ) which is larger than the die.
- FIG. 9 shows schematic diagrams of further examples.
- a portion of the paddle 912 may extend beyond the die, e.g. to enable the paddle and a ground connection on the die to be connected to ground on the substrate (through the solder lands under the paddle and a wirebond 913 ). Additionally, in the second example, a lead 914 may fan underneath the die to provide flexibility in the position of solder lands (as indicated by shaded area 915 ).
- FIGS. 10-12 show further examples 1001 - 1006 of package design which may be considered variants of the examples shown in FIGS. 5 and 9 and described above.
- the first example 1001 shows a number of leads 1014 - 1015 some of which ( 1015 ) fan underneath the die (as indicated by the dotted line 1017 showing the die outline).
- the positions of the wirebonds on the leads are marked with an ‘X’ 1011 and the positions of the apertures in the moulding compound which form the solder lands are shown as shaded regions 1012 (circles in the first example 1001 ).
- the paddle 1013 is also shown and in this example, the paddle includes tie bars 1016 , which connect the paddle to the ring of the leadframe before encapsulation and dicing.
- the lands 1012 are underneath the paddle and all the lands are the same shape and size.
- the second example 1002 shown in FIG. 10 has rectangular lands rather than circular lands. It will be appreciated that other shapes may alternatively be used (e.g. square or oval lands).
- the two examples 1003 - 1004 in FIG. 11 show an exposed paddle (as indicated by the large shaded area 1018 ).
- the first example 1005 in FIG. 12 shows a leadframe 1020 which comprises combined tie bars and leads.
- the second example 1006 shows a leadframe 1021 with both combined tie bars and leads and separate tie bars and also shows wirebonds 1019 to the tie bars.
- the apertures are formed by internal projections within the mould chase
- the apertures may alternatively be formed by an insert which is placed inside a standard (planar) mould chase to form the required internal projections which make contact with the leadframe during the encapsulation process.
- the examples show apertures only being created on a single side of the package (i.e. on the bottom in the examples shown) to expose regions of the leadframe, in other examples, apertures may be created on any one or more sides of the package.
- the improved packages and improved process flow described above may enable one or more of the following:
- An improved QFN package such as described above, with solder balls may be used as a replacement to an existing BGA package.
- the pin-out of the improved QVN can be designed to be the same as an existing BGA package. This may provide a lower cost alternative and also may provide better thermal performance than a similar size BGA because the leadframes are typically made of copper which is more thermally conductive than PCB. Additionally, leadframe manufacture may be considered more environmentally friendly than BGA substrate manufacture. BGA substrates use the same processes as PCBs—which are considered polluting.
- the technology described herein could also provide a way for attaching discrete components within the package, without the need for half etching.
- These discrete components which may for example be soldered decoupling capacitors (e.g. of size 0402), may then be encapsulated within the moulding compound. An example of this is shown in FIG. 13 .
- FIG. 13 shows a schematic diagram of an improved QFN package 1300 in which a discrete component 1301 (e.g. a capacitor or resistor) and a die 1302 are encapsulated in moulding compound 1303 . Projections in the mould chase (as described above) are used to create apertures 1304 in the moulding compound which expose areas of the leadframe 1305 to create lands for connecting to the package (e.g. physically, thermally and/or electrically).
- a discrete component 1301 e.g. a capacitor or resistor
- Projections in the mould chase are used to create apertures 1304 in the moulding compound which expose areas of the leadframe 1305 to create lands for connecting to the package (e.g. physically, thermally and/or electrically).
- the thickness of the leadframe used is substantially constant (e.g. a constant thickness of 150 ⁇ to within manufacturing tolerances).
- the techniques and examples described herein relate to QFN packages, the principles may also be applied to other types of packages. Examples include Dual-Flat No-lead (DFN), Quad Flat Pack (QFP), and Small Outline (SO) packages.
- the techniques may be applied to versions of these packages (e.g. DFN, QFP, SO) with an exposed paddle and the techniques may be used to reduce the paddle area and to stop the package floating during solder reflow (e.g. as described above).
- the techniques may also be applied to other package designs, such as the FusionQuad produced by Amkor.
- the techniques described above may also be used to embed a substrate (PCB) in a package, rather than a leadframe, to form a BGA.
- PCB substrate
- any reference to ‘an’ item refers to one or more of those items.
- the term comprising is used herein to mean including the method blocks or elements identified, but that such blocks or elements do not comprise and exclusive list and a method or apparatus may contain additional blocks or elements.
Abstract
Description
-
- an improved wire-bonding yield of QFN (and in particular CoL QFN) packages, e.g. because wirebonding onto a half-etched leadframe can be avoided whilst still enabling multiple rows of solder lands which form electrical connections between the substrate and I/Os on the die;
- an improved track/gap capability of CoL leadframes, e.g. because of the ability to fan leads underneath the die and to choose the positions of the solder lands (rather than have all of the underneath of the leadframe exposed, as shown in
FIG. 1 ) and/or because of the ability to use thinner leadframes (as leadframes need not be etched to enable multiple rows of connections); - an improved surface-mount yield of QFN packages, e.g. because the solder lands can be designed to be the same shape and size and/or because solder balls may be used instead of solder paste, which overcomes problems associated with open/short circuit pins because of variable collapse during solder reflow resulting from use of different solder volumes/areas;
- improved board-level reliability of QFNs, e.g. because use of solder balls adds to the volume of solder in the joints, increases the stand-off height of the package above the substrate, and provides greater ability to overcome warpage, and thermal expansion, of the package and the substrate (e.g. the PCB).
- simplified PCB rework, e.g. because solder balls can be applied to the QFN package which negates the need to define solder paste on the part-populated PCB being reworked.
Claims (16)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GBGB0815870.1A GB0815870D0 (en) | 2008-09-01 | 2008-09-01 | Improved qfn package |
GB0815870.1 | 2008-09-01 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20100052141A1 US20100052141A1 (en) | 2010-03-04 |
US8110903B2 true US8110903B2 (en) | 2012-02-07 |
Family
ID=39866040
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/544,468 Active 2029-12-18 US8110903B2 (en) | 2008-09-01 | 2009-08-20 | QFN package |
Country Status (2)
Country | Link |
---|---|
US (1) | US8110903B2 (en) |
GB (1) | GB0815870D0 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8703598B2 (en) * | 2008-09-29 | 2014-04-22 | Toppan Printing Co., Ltd. | Manufacturing method of lead frame substrate |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012069764A (en) * | 2010-09-24 | 2012-04-05 | On Semiconductor Trading Ltd | Circuit device and method for manufacturing the same |
CN102376672B (en) * | 2011-11-30 | 2014-10-29 | 江苏长电科技股份有限公司 | Foundation island-free ball grid array packaging structure and manufacturing method thereof |
MY169839A (en) * | 2011-12-29 | 2019-05-16 | Semiconductor Components Ind Llc | Chip-on-lead package and method of forming |
CN108614941B (en) * | 2018-05-08 | 2022-04-12 | 湖南城市学院 | Board-level packaging design optimization method for integrated QFN chip |
CN109119397A (en) * | 2018-10-24 | 2019-01-01 | 扬州扬杰电子科技股份有限公司 | A kind of ultrathin type stamp-mounting-paper diode frame |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6025640A (en) * | 1997-07-16 | 2000-02-15 | Dai Nippon Insatsu Kabushiki Kaisha | Resin-sealed semiconductor device, circuit member for use therein and method of manufacturing resin-sealed semiconductor device |
US6437429B1 (en) * | 2001-05-11 | 2002-08-20 | Walsin Advanced Electronics Ltd | Semiconductor package with metal pads |
US7015591B2 (en) | 2004-04-09 | 2006-03-21 | Airoha Technology Corp. | Exposed pad module integrating a passive device therein |
US7045882B2 (en) * | 2000-12-29 | 2006-05-16 | Amkor Technology, Inc. | Semiconductor package including flip chip |
US7217991B1 (en) * | 2004-10-22 | 2007-05-15 | Amkor Technology, Inc. | Fan-in leadframe semiconductor package |
-
2008
- 2008-09-01 GB GBGB0815870.1A patent/GB0815870D0/en not_active Ceased
-
2009
- 2009-08-20 US US12/544,468 patent/US8110903B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6025640A (en) * | 1997-07-16 | 2000-02-15 | Dai Nippon Insatsu Kabushiki Kaisha | Resin-sealed semiconductor device, circuit member for use therein and method of manufacturing resin-sealed semiconductor device |
US7045882B2 (en) * | 2000-12-29 | 2006-05-16 | Amkor Technology, Inc. | Semiconductor package including flip chip |
US6437429B1 (en) * | 2001-05-11 | 2002-08-20 | Walsin Advanced Electronics Ltd | Semiconductor package with metal pads |
US7015591B2 (en) | 2004-04-09 | 2006-03-21 | Airoha Technology Corp. | Exposed pad module integrating a passive device therein |
US7217991B1 (en) * | 2004-10-22 | 2007-05-15 | Amkor Technology, Inc. | Fan-in leadframe semiconductor package |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8703598B2 (en) * | 2008-09-29 | 2014-04-22 | Toppan Printing Co., Ltd. | Manufacturing method of lead frame substrate |
Also Published As
Publication number | Publication date |
---|---|
GB0815870D0 (en) | 2008-10-08 |
US20100052141A1 (en) | 2010-03-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6420779B1 (en) | Leadframe based chip scale package and method of producing the same | |
KR100294719B1 (en) | Molded semiconductor device and method for manufacturing the same, lead frame | |
US6917097B2 (en) | Dual gauge leadframe | |
US8618641B2 (en) | Leadframe-based semiconductor package | |
US6773961B1 (en) | Singulation method used in leadless packaging process | |
US20160056097A1 (en) | Semiconductor device with inspectable solder joints | |
US11842948B2 (en) | SMDs integration on QFN by 3D stacked solution | |
JP2003243600A (en) | Semiconductor device and method of manufacturing the same | |
JP5232394B2 (en) | Manufacturing method of semiconductor device | |
US8592962B2 (en) | Semiconductor device packages with protective layer and related methods | |
US8110903B2 (en) | QFN package | |
KR20060042872A (en) | A method of surface mounting a semiconductor device | |
US9184118B2 (en) | Micro lead frame structure having reinforcing portions and method | |
JP2003332513A (en) | Semiconductor device and its manufacturing method | |
KR20000048011A (en) | A semiconductor device | |
KR20080029904A (en) | Integrated circuit package system employing bump technology | |
US20080197464A1 (en) | Integrated Circuit Device Package with an Additional Contact Pad, a Lead Frame and an Electronic Device | |
US9673122B2 (en) | Micro lead frame structure having reinforcing portions and method | |
JP2007201324A (en) | Mounting structure of electronic device and mounting method for electronic component | |
US9099363B1 (en) | Substrate with corner cut-outs and semiconductor device assembled therewith | |
JPH11297917A (en) | Semiconductor device and its manufacture | |
US11869831B2 (en) | Semiconductor package with improved board level reliability | |
JP4030363B2 (en) | Semiconductor device | |
US11227820B2 (en) | Through hole side wettable flank | |
KR101120718B1 (en) | Dual gauge leadframe |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: CAMBRIDGE SILICON RADIO LTD.,UNITED KINGDOM Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ROBINSON, PETER JOHN;REEL/FRAME:023141/0652 Effective date: 20090824 Owner name: CAMBRIDGE SILICON RADIO LTD., UNITED KINGDOM Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ROBINSON, PETER JOHN;REEL/FRAME:023141/0652 Effective date: 20090824 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
CC | Certificate of correction | ||
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: QUALCOMM TECHNOLOGIES INTERNATIONAL, LTD., UNITED Free format text: CHANGE OF NAME;ASSIGNOR:CAMBRIDGE SILICON RADIO LIMITED;REEL/FRAME:036663/0211 Effective date: 20150813 |
|
AS | Assignment |
Owner name: CAMBRIDGE SILICON RADIO LIMITED, GREAT BRITAIN Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 023222 FRAME: 0140. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT;ASSIGNOR:ROBINSON, PETER JOHN;REEL/FRAME:038006/0135 Effective date: 20160225 |
|
AS | Assignment |
Owner name: CAMBRIDGE SILICON RADIO LIMITED, GREAT BRITAIN Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE NAME OF ASSIGNEE, PREVIOUSLY RECORDED ON REEL 023141 FRAME 0652. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT;ASSIGNOR:ROBINSON, PETER JOHN;REEL/FRAME:038026/0132 Effective date: 20160307 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 12 |