US8202782B2 - Method of manufacturing transistor - Google Patents
Method of manufacturing transistor Download PDFInfo
- Publication number
- US8202782B2 US8202782B2 US12/676,017 US67601708A US8202782B2 US 8202782 B2 US8202782 B2 US 8202782B2 US 67601708 A US67601708 A US 67601708A US 8202782 B2 US8202782 B2 US 8202782B2
- Authority
- US
- United States
- Prior art keywords
- spacer
- gate
- source
- substrate
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related, expires
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 125000006850 spacer group Chemical group 0.000 claims abstract description 114
- 239000000463 material Substances 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 238000000034 method Methods 0.000 claims abstract description 37
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 13
- 238000000137 annealing Methods 0.000 claims description 13
- 229910052739 hydrogen Inorganic materials 0.000 claims description 13
- 239000001257 hydrogen Substances 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 8
- 239000010410 layer Substances 0.000 description 91
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 29
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 25
- 229910052581 Si3N4 Inorganic materials 0.000 description 19
- 229910052710 silicon Inorganic materials 0.000 description 18
- 239000010703 silicon Substances 0.000 description 18
- 229910052814 silicon oxide Inorganic materials 0.000 description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 16
- 239000004065 semiconductor Substances 0.000 description 11
- 229910021417 amorphous silicon Inorganic materials 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 9
- 235000012431 wafers Nutrition 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 239000007943 implant Substances 0.000 description 7
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- 238000002513 implantation Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 239000002019 doping agent Substances 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 238000000407 epitaxy Methods 0.000 description 4
- 238000011065 in-situ storage Methods 0.000 description 4
- 238000001459 lithography Methods 0.000 description 4
- 230000008707 rearrangement Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 229910021419 crystalline silicon Inorganic materials 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 3
- 230000005012 migration Effects 0.000 description 3
- 238000013508 migration Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 238000005334 plasma enhanced chemical vapour deposition Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- IAOZJIPTCAWIRG-QWRGUYRKSA-N aspartame Chemical compound OC(=O)C[C@H](N)C(=O)N[C@H](C(=O)OC)CC1=CC=CC=C1 IAOZJIPTCAWIRG-QWRGUYRKSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000010561 standard procedure Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
- H01L29/41783—Raised source or drain electrodes self aligned with the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/90—MOSFET type gate sidewall insulating spacer
Definitions
- the invention relates to a transistor.
- the invention relates to a method of manufacturing a transistor.
- CMOS technology for logical applications may allow that a CMOS transistor could now reach a frequency domain, which was previously reserved for bipolar transistors.
- a MOSFET device may be considered to be short when the channel length is in the same order of magnitude as the depletion layer width of the source and drain junction. As the channel length may be reduced to increase both the operation speed and the number of components per chips, so-called short channel effects may arise which implied that the transistors are becoming more and more leaky.
- Curvature of junctions includes high electric fields at these curved junctions: The lower the radius the higher the field. With decreasing dimensions, the radius goes down so the field goes up. If one could avoid or reduce the junction curvature (this lower curvature results in a larger effective radius), the electric field would go up less with the ever increasing doping levels.
- Shaping a gradually increasing source/drain extension depth by using a number of implants with varying implant tilts or growing elevated source/drains may remedy the excessive increase of the electric field due to the scaling, but may be expensive.
- Such a multiple implant method is not only expensive, but may also implant part of the extension through the gate oxide. This may harm the gate oxide integrity.
- the elevated source/drain by epitaxial growth is not only expensive but also induces extra source/gate, drain/gate and source/drain capacitances which may be problematic for high frequency operation.
- U.S. Pat. No. 5,953,615 discloses MOSFETs with deep source/drain junctions and shallow source/drain extensions, and provides on a semiconductor wafer a gate stack with side spacers. The side spacers are etched so that a known thickness of the side spacers is left. An ion beam is used to implant Si+ or Ge+ or Xe+ to amorphize the silicon region, creating an amorphous region with two different depths. A high dose ion beam is then used to implant a dopant. An oxide layer is then deposited as a barrier layer, and then a metal layer is deposited to improve laser energy absorption.
- Laser annealing is used to melt the amorphous silicon region which causes the dopant to diffuse in and into the amorphous silicon region creating deep source/drain junctions and shallow source/drain extensions. Standard techniques are then used to complete the transistor, which includes silicidation of the source/drain junctions.
- a method of manufacturing a transistor comprising forming a gate on a substrate, forming a spacer on lateral side walls of the gate (that is walls of the gate being perpendicular to a main surface of the substrate) and on an adjacent portion of the substrate (more precisely on a surface portion of the substrate which surface portion is directly neighboured to the gate), modifying material of the spacer (that is modifying a spatial distribution of material of the spacer and/or removing part of the spacer, for instance by etching) so that the modified spacer covers only a lower portion of the lateral side walls of the gate (that is a portion of the lateral side wall which is closer or adjacent to the substrate), and providing source/drain regions in the modified spacer.
- a transistor comprising a substrate, a gate on the substrate, a spacer (for instance rearranged in accordance with the above described method) which covers only a lower portion of lateral side walls of the gate and a portion of the substrate, and source/drain regions in the spacer.
- substrate may denote any suitable material, such as a semiconductor, glass, plastic, etc. According to an exemplary embodiment, the term “substrate” may be used to define generally the elements for layers that underlie and/or overlie a layer or portions of interest. Also, the substrate may be any other base on which a layer is formed, for example a semiconductor wafer such as a silicon wafer or silicon chip.
- the transistor may be a field effect transistor.
- MOSFET MOS structure
- JFET p-n junction
- MESFET metal-semiconductor contact
- a FET is a unipolar transistor, that is current is controlled by majority carriers only.
- source/drain region may particularly denote a source region or a drain region. Since the functionality of a source region and a drain region may depend on the operation mode of a (memory or logic) transistor, for instance voltages applied thereto, the term source/drain region may denote a structure which can act as a source region or as a drain region.
- gate may denote an electrically conductive structure to which an electric voltage may be applied to control a conductivity of a channel region of a semiconductor substrate.
- the term gate may cover such an electrically conductive structure individually, or the electrically conductive structure with at least one electrically insulating component connected thereto.
- a gate stack may be covered by the term “gate”.
- modifying may particularly denote any treatment by which the configuration of spacer material is altered along the lateral walls of the gate stack. Such a modification may be performed with or without adding material to the spacer and with (for instance etching) or without (for instance annealing SiGe material in hydrogen atmosphere) removing material from the spacer.
- rearranging may particularly denote any treatment by which spacer material is migrated, moved or transferred along the lateral walls of the gate stack. Such a rearrangement may be performed essentially without adding material to the spacer and essentially without removing material from the spacer.
- concave may particularly denote curved downwards, when seen from the top of the layer sequence.
- convex may particularly denote curved upwards, when seen from the top of a layer sequence.
- a spacer is provided on a side wall of a gate stack for the purpose to obtain a slanted source/drain region by first forming a spacer conventionally on a lateral sidewall of a gate stack, and by subsequently migrating material of this spacer to thereby move part of the material to a lower portion of the substrate, thereby forcing it to cover a larger area on the substrate and a smaller area on the lateral walls of the gate stack.
- an elevated source/drain may be provided which suffers less from problems occurring when scaling devices down, especially the high source/drain resistances are remedied.
- an elevated source/drain formation without selective epitaxy may be provided.
- Making a raised source/drain MOSFET without the use of selective epitaxy may allow a better source/drain engineering that improves the short channel effects and especially the punch through effect and the breakdown voltage and still have a low source and drain series resistance.
- the breakdown voltage can also be improved because a low curvature of the junction may result from the processing according to an exemplary embodiment of the invention. This allows the fabrication of transistors for high frequency applications (comparable to the mainstream CMOS) and allows to improve breakdown voltage (higher than the mainstream CMOS) to make the transistor suitable for “RF power” applications.
- the combination of a shallow junction depth at the channel edge gradually going deeper induces a good breakdown voltage, a good (that is low) source/drain resistance and good gate length scaling characteristics.
- the higher breakdown voltage can be exploited for higher reliability or for higher operating voltages, for instance in analog applications.
- a MOSFET gate length downscaling may enhance the high frequency operation but may also increase short channel effects.
- RF power applications may require transistors able to deliver high frequency and a decent power output (or breakdown).
- the raised source/drain structures reduce the short channel effects and punch through without degrading (too much) the frequency operations of the transistors.
- embodiments of the invention allow to make an elevated source/drain structure in a standard mainstream CMOS without the use of selective epitaxy and still having the benefit of the lower series resistance.
- the spacer layer is an amorphous Si(Ge) layer, which is reshaped and used as well as elevated source drain after solid phase epitaxial regrowth (which is a cheap flexible method of manufacturing). The latter combines the advantage of elevated source/drain with an attractive shape of the source/drain junction.
- the method may comprise implanting the source/drain regions in the modified (for instance rearranged) spacer.
- the rearranged spacer itself may be used as raised source/drain regions which then may make it necessary to implant dopant into the spacer.
- the spacer remains on the layer sequence.
- the method may comprise forming the source/drain regions in the modified (for instance rearranged) spacer which may be made of an already doped material.
- the implantation may become dispensable, since in situ doped material may be used for manufacturing the spacer, or implantation may be performed during manufacture (for example deposition) of the spacer.
- the modifying may comprise rearranging the material of the spacer so that the rearranged spacer covers only a lower portion of the lateral side walls of the gate and an increased portion of the substrate. In such an embodiment, essentially without loss of material, the material may simply be migrated towards the substrate and away from a center of the gate stack.
- the method may further comprise rearranging the material of the spacer by annealing, particularly by hydrogen annealing (that is annealing in hydrogen atmosphere).
- annealing particularly by hydrogen annealing (that is annealing in hydrogen atmosphere).
- Such a procedure may be performed at a temperature in a range of, for example, 600° C. to 1000° C., at a pressure in a range of, for example, 1 Torr to 100 Torr, and for a time in a range of, for instance, 10 seconds to 10 minutes. This may allow to force the material of the spacer to migrate or to sink towards the surface of the substrate, thereby allowing to control an extent to which an upper portion of the lateral sidewall of the gate stack is free of the spacer after the rearranging procedure.
- the thickness variation of the source/drain region is not too extreme, yielding a smooth transition of the depth of the source/drain regions.
- the modifying may comprise etching back part of the material of the spacer. By such a back etch, the thickness of the spacer may be reduced in a vertical direction, thereby allowing to obtain a back etched source/drain structure having advantageous properties for the transistor performance (see FIG. 4 ).
- the method may comprise modifying (for instance rearranging) the material of the spacer with a thickness which gradually increases towards the gate. Therefore, an essentially stepless doping profile may be obtained in the source/drain regions.
- the method may comprise forming a protection structure, particularly an essentially L-shaped protection structure (see reference numeral 901 ), between the gate and the spacer.
- L-shaped may denote a shape of the protection structure in a cross-sectional view of the layer sequence which may result in an appearance of the protection structure to have the shape of two letters “L” at the two lateral sidewalls of the gate stack visible in such a cross-sectional view.
- Such a protection structure may protect the gate stack against possibly chemically aggressive material of the spacer, thereby ensuring a high quality of the manufactured transistor.
- the method may comprise forming the spacer on the lateral sidewalls of the gate and on the adjacent portion of the substrate by (for instance conformally) depositing spacer material over the gate and the substrate, and subsequently removing (for instance by etching) part of the spacer material so that the spacer remains only on lateral sidewalls of the gate and on the adjacent portions of the substrate.
- a conformal deposition of the spacer material for instance SiGe
- the spacer material for instance SiGe
- the rearrangement may convert this convex structure into a concave structure, for example by annealing.
- the spacer may have a concave shape.
- the shape of the spacer may be concave in a similar manner as an avalanche which has slipped down or glided down a hill.
- the extent to which the material has been rearranged then also has an impact on the curvature of the concave spacer.
- the spacer may comprise a material of the group consisting of silicon-germanium (SiGe) and silicon. Silicon-germanium may be a preferred choice since this may be rearranged efficiently by hydrogen annealing.
- the transistor may comprise a further spacer on a lateral wall of the gate, essentially (that is at least to a main part) above the spacer, and having a thickness smaller than the thickness of the spacer.
- This additional spacer may prevent silicidation bridging between the source/drain regions and a polysilicon gate.
- the further spacer may be a convex spacer.
- the transistor may comprise a concave spacer used as a source/drain region or for defining a design of the source/drain regions in the substrate, and may comprise a further concave spacer for protection purposes.
- the further spacer may have a height which is higher than the height of the spacer, but may have a width which is smaller than the width of the spacer.
- a raised source/drain structure according to an exemplary embodiment of the invention may be obtained by the formation of a SiGe spacer and the use of silicon migration. Such a concept may involve the following measures:
- an amorphous silicon etch (as shown for instance in FIG. 10 ) may be omitted, since it is not mandatory.
- Embodiments of the invention are applicable to crystalline silicon wafers. Other embodiments are applicable on SOI (Silicon On Insulator) wafers. However, the silicon migration may also occur on the top silicon or on top of the box oxide.
- a hydrogen anneal of 800° C. may be applied to SOI wafers with silicon layers as thin as 8 nm. Lower hydrogen anneal temperatures may be used by increasing the Ge concentration and decreasing the oxide thickness under the SiGe layer.
- the SiGe spacer may be replaced by a dummy gate.
- Exemplary embodiments of the invention may be applied to any CMOS application allowing low source/drain resistance with shallow junctions at the channel edge allowing proper length scaling and also in CMOS applications requiring higher operating voltages such as in RF power CMOS.
- a vertical thickness of the rearranged spacer is smaller than a vertical thickness of the gate stack. Since after rearranging, only a portion of the lateral sidewall of the gate stack is covered with the rearranged material of the spacer, it is possible to allow for tuning of the absorption thickness at the gate edge and tuning of its width.
- the device may be manufactured in CMOS technology. Any CMOS technology generation may be used. When using CMOS technology, a known and cheap method may be used for manufacturing the transistor.
- the substrate may be a semiconductor substrate.
- the transistor device may be monolithically integrated in the semiconductor substrate, particularly comprising one of the group consisting of a group IV semiconductor (such as silicon or germanium), and a group III-group V semiconductor (such as gallium arsenide).
- Forming layers or components may include deposition techniques like CVD (chemical vapour deposition), PECVD (plasma enhanced chemical vapour deposition), ALD (atomic layer deposition), or sputtering.
- Removing layers or components may include etching techniques like wet etching, plasma etching, etc., as well as patterning techniques like optical lithography, UV lithography, electron beam lithography, etc.
- Embodiments of the invention are not bound to specific materials, so that many different materials may be used.
- conductive structures it may be possible to use metallization structures, silicide structures or polysilicon structures.
- semiconductor regions or components crystalline silicon may be used.
- insulating portions silicon oxide or silicon nitride may be used.
- the transistor may be formed on a purely crystalline silicon wafer or on an SOI wafer (Silicon On Insulator).
- CMOS complementary metal-oxide-semiconductor
- BIPOLAR BIPOLAR
- BICMOS BICMOS
- FIG. 1 to FIG. 3 show layer sequences obtained during a method of manufacturing a transistor according to an exemplary embodiment of the invention.
- FIG. 1 , FIG. 2 and FIG. 4 show layer sequences obtained during a method of manufacturing a transistor according to an exemplary embodiment of the invention.
- FIG. 5 to FIG. 22 show layer sequences obtained during another method of manufacturing a transistor according to an exemplary embodiment of the invention.
- FIG. 1 to FIG. 3 a method of manufacturing a transistor 400 according to an exemplary embodiment of the invention will be explained.
- a gate stack 101 is formed on a silicon substrate 102 .
- the gate stack 101 comprises a poly silicon gate 103 and a gate oxide layer 104 .
- the gate oxide layer 104 may be deposited as a silicon oxide layer on the silicon substrate 102 or may be formed by thermally oxidizing the silicon material at the surface of the silicon substrate 102 .
- a poly silicon layer may be deposited on top of the gate oxide layer 104 and may be patterned using a lithography to obtain the laterally confined gate 103 .
- a spacer 201 is formed on entire lateral sidewalls of the gate stack 101 and on an adjacent portion 202 of the substrate 102 .
- the spacer 201 may be made of silicon-germanium material (as will be described in more detail referring to the embodiment shown in FIG. 5 to FIG. 22 ).
- material of the spacer 201 is rearranged by thermally annealing the layer sequence 200 in hydrogen atmosphere, so that the rearranged spacer 301 covers only a lower sub-portion 303 of the lateral sidewalls of the gate stack 101 and an increased portion 302 of the substrate 102 , as compared to the layer sequence 200 . Furthermore, a convex geometry of the spacer 201 is converted into a concave geometry of the rearranged spacer 301 .
- FIG. 3 shows a transistor 300 according to an exemplary embodiment of the invention, in which the rearranged spacers 301 form raised source-/drain regions.
- the rearranged spacers 301 are directly used as source/drain regions, which may then require that they are doped (for instance in situ or by implantation).
- a transistor 400 shown in FIG. 4 can be manufactured based on the layer sequence 200 shown in FIG. 2 by etching back part of the material of the spacer 201 .
- the back etched spacers 301 are directly used as source/drain regions, which may then require that they are doped (for instance in situ or by implantation).
- STI shallow trench isolation
- Gate stacks 101 are formed comprising a gate insulation layer 104 and a poly silicon gate 103 .
- a silicon oxide layer 601 for instance having a thickness of 3 nm, a silicon nitride layer 602 having a thickness of 5 nm, and an amorphous silicon layer 603 having a thickness of 5 nm are deposited on the layer sequence 500 .
- a photoresist layer 701 is spun over the layer sequence 600 , and a lithography is performed in order to expose the portion of the layer sequence 600 on which a transistor according to an exemplary embodiment of the invention shall be formed.
- an a-Si spacer formation is performed by removing an exposed portion of the silicon layer 603 resulting in the formation of silicon spacers 801 .
- the resist 701 is stripped and a silicon nitride etch is performed. This removes exposed surface portions of the silicon nitride layer 602 . As can be taken from FIG. 9 , the remaining portions of the silicon nitride layer 602 on the gate stack on the right-hand side of FIG. 9 form essentially L-shaped spacers 901 .
- an a-Si etch is performed thereby removing remaining portions of the silicon material 603 , 801 exposed in FIG. 9 .
- a silicon oxide etch is performed to remove exposed portions of the layer 601 .
- a silicon oxide layer 1201 having a thickness of for instance 5 nm is deposited over the layer sequence 1100 .
- a-SiGe is deposited over the layer sequence 1200 , thereby forming a conformal SiGe layer 1301 .
- the SiGe layer 1301 is etched to form a-SiGe spacers 201 .
- a photoresist 1502 is spun, and a lithography is performed to maintain only a portion of the layer sequence 1400 covered with photoresist 1502 on which portion the transistor according to an exemplary embodiment of the invention shall be formed. Subsequently, an a-SiGe etch is performed in order to remove the spacer 201 on the gate stack on the left-hand side of FIG. 15 .
- the resist 1502 is stripped, and a silicon oxide etch is performed to remove exposed portions of layer 1201 .
- the layer sequence 1600 is made subject to a hydrogen anneal procedure to thereby rearrange the material of the convex spacer 201 to form a rearranged concave spacer 301 .
- a silicon nitride etch and a silicon oxide etch may be performed to remove layers 602 , 601 and portions of the remaining structures 901 , 1201 .
- a silicon oxide deposition is performed to form a conformally deposited silicon oxide layer 1901 .
- a silicon nitride deposition is performed in order to produce a silicon nitride layer 2001 .
- a silicon nitride etch is performed to produce the silicon nitride spacers 2101 .
- a layer sequence 2200 as shown in FIG. 22 is obtained including, on the right-hand side, a transistor according to an exemplary embodiment of the invention.
- the process integration starts with the deposition of silicon oxide 601 , silicon nitride 602 and amorphous silicon layer 603 , as shown in FIG. 6 .
- the silicon nitride layer 602 is used as a protective layer for mainstream CMOS, and the silicon nitride layer 602 is also used for the formation of the L-shaped spacer 901 for the dedicated transistors with an elevated source/drain.
- a mask 701 is used (see FIG. 7 ) in order to create a silicon spacer 801 (see FIG. 8 ).
- the resist 701 is stripped and silicon nitride 602 is etched (see FIG. 9 ). Only the silicon nitride 602 on the poly gate 103 and on the source/drain area is removed.
- the a-Si 603 is removed selectively to silicon nitride 602 and silicon oxide 601 (see FIG. 10 ).
- the remaining protective silicon oxide 601 on the source/drain and poly gate is removed (see FIG. 11 ), and a further silicon oxide layer 1201 (with accurate thickness) is deposited (see FIG. 12 ).
- the thickness of this silicon oxide layer 1201 may be rather important because it may determine the silicon oxide etch rate undercut in FIG. 16 and the sealing of the layer in FIG. 17 .
- An amorphous SiGe layer 1301 is deposited (see FIG. 13 ), and SiGe spacers 201 are formed (see FIG. 14 ).
- SiGe spacers 201 may be etched away using a mask (see FIG. 15 ).
- An HF dip may be used in order to remove the silicon oxide layer 1201 underneath the SiGe spacer 201 (see FIG. 16 ).
- the SiGe spacers 201 are spread out using a hydrogen anneal (see FIG. 17 ).
- a typical hydrogen anneal is performed at 800° C., 10 Torr and one minute for a SiGe layer with a Germanium concentration around 30 at. %.
- the silicon-germanium layer 301 will recrystallize or have epitaxial realignment such that the interface is defect free.
- the silicon nitride spacer 2101 prevents the merging and/or the deformation of the poly gate 103 .
- the protective silicon nitride layer 602 and silicon oxide layer 601 are removed (see FIG. 18 ), and CMOS processing is continued.
- the CMOS spacer formation is illustrated between FIG. 19 and FIG. 22 .
- the source/drain dopant engineering (not shown in FIG. 5 to FIG. 22 ) may be performed in different ways:
Abstract
Description
-
- make a silicon nitride L-shaped spacer after the gate patterning to protect the poly gate
- make a SiGe spacer
- promote a SiGe migration during a hydrogen annealing in order to “spread” the SiGe layer on the source/drain regions
- use a standard CMOS spacer in order to prevent silicidation bridging between the source/drain and the poly gate.
-
- The silicon-germanium layer may be already doped before the silicon-germanium spacer formation. This can be done in situ or with implantation (in both cases a dedicated mask for the n- and p-type MOS devices may be required).
- The silicon-germanium layer may be undoped and the source/drain regions are implanted after the raised source/drain formation.
- A combination of the above two concepts is possible.
Claims (9)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP07115714 | 2007-09-05 | ||
EP07115714.3 | 2007-09-05 | ||
EP07115714 | 2007-09-05 | ||
PCT/IB2008/053496 WO2009031085A1 (en) | 2007-09-05 | 2008-08-29 | A transistor and a method of manufacturing the same |
Publications (2)
Publication Number | Publication Date |
---|---|
US20100176426A1 US20100176426A1 (en) | 2010-07-15 |
US8202782B2 true US8202782B2 (en) | 2012-06-19 |
Family
ID=40093041
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/676,017 Expired - Fee Related US8202782B2 (en) | 2007-09-05 | 2008-08-29 | Method of manufacturing transistor |
Country Status (4)
Country | Link |
---|---|
US (1) | US8202782B2 (en) |
EP (1) | EP2191505A1 (en) |
CN (1) | CN101796632A (en) |
WO (1) | WO2009031085A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8697529B2 (en) * | 2010-12-30 | 2014-04-15 | Fudan University | Schottky junction source/drain transistor and method of making |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20100103302A (en) * | 2009-03-13 | 2010-09-27 | 삼성전자주식회사 | Method of fabricating semiconductor devices |
CN102185575A (en) * | 2010-12-31 | 2011-09-14 | 苏州普锐晶科技有限公司 | Method for removing frequency chip protective glass |
US9087741B2 (en) | 2011-07-11 | 2015-07-21 | International Business Machines Corporation | CMOS with dual raised source and drain for NMOS and PMOS |
JP5956809B2 (en) | 2012-04-09 | 2016-07-27 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
US8927406B2 (en) * | 2013-01-10 | 2015-01-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dual damascene metal gate |
US9716142B2 (en) | 2015-10-12 | 2017-07-25 | International Business Machines Corporation | Stacked nanowires |
Citations (39)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2460967A1 (en) | 1974-12-21 | 1976-07-01 | Philips Patentverwaltung | MOS transistor with lateral dislocation gradient in channel - with higher doping at source zone end, avoiding punch-through effect |
JPS59208784A (en) | 1983-05-12 | 1984-11-27 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
JPS6059777A (en) | 1983-09-13 | 1985-04-06 | Nec Corp | Manufacture of semiconductor device |
JPS61267368A (en) | 1985-05-21 | 1986-11-26 | Fujitsu Ltd | Manufacture of misfet |
US4713356A (en) | 1985-02-28 | 1987-12-15 | Kabushiki Kaisha Toshiba | Manufacturing MOS semiconductor device with planarized conductive layer |
US4755479A (en) * | 1986-02-17 | 1988-07-05 | Fujitsu Limited | Manufacturing method of insulated gate field effect transistor using reflowable sidewall spacers |
EP0422824A1 (en) | 1989-10-12 | 1991-04-17 | AT&T Corp. | Field-effect transistor with polysilicon window pad |
JPH04142747A (en) | 1990-10-03 | 1992-05-15 | Fujitsu Ltd | Manufacture of semiconductor device |
US5424571A (en) | 1992-03-30 | 1995-06-13 | Sgs-Thomson Microelectronics, Inc. | Sloped spacer for mos field effect devices |
EP0671760A2 (en) | 1994-03-07 | 1995-09-13 | Oki Electric Industry Co., Ltd. | A method of fabricating a semiconductor device using high dose implantation |
US5501997A (en) * | 1994-05-03 | 1996-03-26 | United Microelectronics Corp. | Process of fabricating semiconductor devices having lightly-doped drain |
US5518944A (en) | 1991-02-05 | 1996-05-21 | Matsushita Electric Industrial Co., Ltd. | MOS transistor and its fabricating method |
US5631174A (en) * | 1995-12-21 | 1997-05-20 | Micron Technology, Inc. | Method for forming a spacer with a prograde profile |
US5652159A (en) | 1994-10-27 | 1997-07-29 | Nec Corporation | Thin film transistor having improved switching characteristic |
US5656556A (en) | 1996-07-22 | 1997-08-12 | Vanguard International Semiconductor | Method for fabricating planarized borophosphosilicate glass films having low anneal temperatures |
US5663591A (en) * | 1995-02-14 | 1997-09-02 | Crosspoint Solutions, Inc. | Antifuse with double via, spacer-defined contact |
US5763301A (en) * | 1993-05-20 | 1998-06-09 | Lg Semicon Co., Ltd. | Method for fabricating thin film transistors |
US5811342A (en) | 1998-01-26 | 1998-09-22 | Texas Instruments - Acer Incorporated | Method for forming a semiconductor device with a graded lightly-doped drain structure |
JPH10270375A (en) | 1997-03-25 | 1998-10-09 | Toshiba Corp | Ion implantation method and method for forming mos type transistor using it |
WO1999030361A1 (en) | 1997-12-09 | 1999-06-17 | Advanced Micro Devices, Inc. | Spacer formation for precise salicide formation |
US5915175A (en) | 1997-06-27 | 1999-06-22 | Siemens Aktiengesellschaft | Mitigation of CMP-induced BPSG surface damage by an integrated anneal and silicon dioxide deposition |
US5953615A (en) | 1999-01-27 | 1999-09-14 | Advance Micro Devices | Pre-amorphization process for source/drain junction |
US5960315A (en) * | 1997-07-10 | 1999-09-28 | International Business Machines Corporation | Tapered via using sidewall spacer reflow |
JP2000049332A (en) | 1998-07-27 | 2000-02-18 | Matsushita Electric Works Ltd | Semiconductor device and fabrication thereof |
US6054356A (en) | 1996-12-10 | 2000-04-25 | Advanced Micro Devices, Inc. | Transistor and process of making a transistor having an improved LDD masking material |
US6063676A (en) | 1997-06-09 | 2000-05-16 | Integrated Device Technology, Inc. | Mosfet with raised source and drain regions |
US6187642B1 (en) | 1999-06-15 | 2001-02-13 | Advanced Micro Devices Inc. | Method and apparatus for making mosfet's with elevated source/drain extensions |
US6208008B1 (en) * | 1998-01-06 | 2001-03-27 | International Business Machines Corporation | Integrated circuits having reduced stress in metallization |
US6238988B1 (en) | 1999-12-09 | 2001-05-29 | United Microelectronics Corp. | Method of forming a MOS transistor |
US20020009897A1 (en) * | 1998-08-21 | 2002-01-24 | Micron Technology, Inc. | Flowable germanium doped silicate glass for use as a spacer oxide |
US6351013B1 (en) * | 1999-07-13 | 2002-02-26 | Advanced Micro Devices, Inc. | Low-K sub spacer pocket formation for gate capacitance reduction |
US6492665B1 (en) | 1998-07-28 | 2002-12-10 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
US20030194851A1 (en) * | 2002-04-16 | 2003-10-16 | Johnson F. Scott | Methods for transistor gate formation using gate sidewall implantation |
EP1478029A1 (en) | 2003-05-14 | 2004-11-17 | Samsung Electronics Co., Ltd. | Mos transistor and method of fabricating the same |
US20040262650A1 (en) | 2000-01-07 | 2004-12-30 | Sharp Kabushiki Kaisha | Semiconductor device, method for producing the same, and information processing apparatus |
KR20050059633A (en) | 2003-12-15 | 2005-06-21 | 한국전자통신연구원 | Method for fabricating a soi mosfet device having elevated source/drain formed by using a reflow process |
US20050167765A1 (en) * | 2000-12-27 | 2005-08-04 | Kabushiki Kaisha Toshiba | Semiconductor device with an L-shaped/reversed L-shaped gate side-wall insulating film and method of manufacturing same |
US20060194398A1 (en) | 2005-02-28 | 2006-08-31 | Kabushiki Kaisha Toshiba | Semiconductor device and its manufacturing method |
US20070298549A1 (en) * | 2006-06-23 | 2007-12-27 | Interuniversitair Microelektronica Centrum Vzw (Imec) | Method of fabricating a strained multi-gate transistor and devices obtained thereof |
-
2008
- 2008-08-29 EP EP08807491A patent/EP2191505A1/en not_active Withdrawn
- 2008-08-29 US US12/676,017 patent/US8202782B2/en not_active Expired - Fee Related
- 2008-08-29 WO PCT/IB2008/053496 patent/WO2009031085A1/en active Application Filing
- 2008-08-29 CN CN200880105448A patent/CN101796632A/en active Pending
Patent Citations (39)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2460967A1 (en) | 1974-12-21 | 1976-07-01 | Philips Patentverwaltung | MOS transistor with lateral dislocation gradient in channel - with higher doping at source zone end, avoiding punch-through effect |
JPS59208784A (en) | 1983-05-12 | 1984-11-27 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
JPS6059777A (en) | 1983-09-13 | 1985-04-06 | Nec Corp | Manufacture of semiconductor device |
US4713356A (en) | 1985-02-28 | 1987-12-15 | Kabushiki Kaisha Toshiba | Manufacturing MOS semiconductor device with planarized conductive layer |
JPS61267368A (en) | 1985-05-21 | 1986-11-26 | Fujitsu Ltd | Manufacture of misfet |
US4755479A (en) * | 1986-02-17 | 1988-07-05 | Fujitsu Limited | Manufacturing method of insulated gate field effect transistor using reflowable sidewall spacers |
EP0422824A1 (en) | 1989-10-12 | 1991-04-17 | AT&T Corp. | Field-effect transistor with polysilicon window pad |
JPH04142747A (en) | 1990-10-03 | 1992-05-15 | Fujitsu Ltd | Manufacture of semiconductor device |
US5518944A (en) | 1991-02-05 | 1996-05-21 | Matsushita Electric Industrial Co., Ltd. | MOS transistor and its fabricating method |
US5424571A (en) | 1992-03-30 | 1995-06-13 | Sgs-Thomson Microelectronics, Inc. | Sloped spacer for mos field effect devices |
US5763301A (en) * | 1993-05-20 | 1998-06-09 | Lg Semicon Co., Ltd. | Method for fabricating thin film transistors |
EP0671760A2 (en) | 1994-03-07 | 1995-09-13 | Oki Electric Industry Co., Ltd. | A method of fabricating a semiconductor device using high dose implantation |
US5501997A (en) * | 1994-05-03 | 1996-03-26 | United Microelectronics Corp. | Process of fabricating semiconductor devices having lightly-doped drain |
US5652159A (en) | 1994-10-27 | 1997-07-29 | Nec Corporation | Thin film transistor having improved switching characteristic |
US5663591A (en) * | 1995-02-14 | 1997-09-02 | Crosspoint Solutions, Inc. | Antifuse with double via, spacer-defined contact |
US5631174A (en) * | 1995-12-21 | 1997-05-20 | Micron Technology, Inc. | Method for forming a spacer with a prograde profile |
US5656556A (en) | 1996-07-22 | 1997-08-12 | Vanguard International Semiconductor | Method for fabricating planarized borophosphosilicate glass films having low anneal temperatures |
US6054356A (en) | 1996-12-10 | 2000-04-25 | Advanced Micro Devices, Inc. | Transistor and process of making a transistor having an improved LDD masking material |
JPH10270375A (en) | 1997-03-25 | 1998-10-09 | Toshiba Corp | Ion implantation method and method for forming mos type transistor using it |
US6063676A (en) | 1997-06-09 | 2000-05-16 | Integrated Device Technology, Inc. | Mosfet with raised source and drain regions |
US5915175A (en) | 1997-06-27 | 1999-06-22 | Siemens Aktiengesellschaft | Mitigation of CMP-induced BPSG surface damage by an integrated anneal and silicon dioxide deposition |
US5960315A (en) * | 1997-07-10 | 1999-09-28 | International Business Machines Corporation | Tapered via using sidewall spacer reflow |
WO1999030361A1 (en) | 1997-12-09 | 1999-06-17 | Advanced Micro Devices, Inc. | Spacer formation for precise salicide formation |
US6208008B1 (en) * | 1998-01-06 | 2001-03-27 | International Business Machines Corporation | Integrated circuits having reduced stress in metallization |
US5811342A (en) | 1998-01-26 | 1998-09-22 | Texas Instruments - Acer Incorporated | Method for forming a semiconductor device with a graded lightly-doped drain structure |
JP2000049332A (en) | 1998-07-27 | 2000-02-18 | Matsushita Electric Works Ltd | Semiconductor device and fabrication thereof |
US6492665B1 (en) | 1998-07-28 | 2002-12-10 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
US20020009897A1 (en) * | 1998-08-21 | 2002-01-24 | Micron Technology, Inc. | Flowable germanium doped silicate glass for use as a spacer oxide |
US5953615A (en) | 1999-01-27 | 1999-09-14 | Advance Micro Devices | Pre-amorphization process for source/drain junction |
US6187642B1 (en) | 1999-06-15 | 2001-02-13 | Advanced Micro Devices Inc. | Method and apparatus for making mosfet's with elevated source/drain extensions |
US6351013B1 (en) * | 1999-07-13 | 2002-02-26 | Advanced Micro Devices, Inc. | Low-K sub spacer pocket formation for gate capacitance reduction |
US6238988B1 (en) | 1999-12-09 | 2001-05-29 | United Microelectronics Corp. | Method of forming a MOS transistor |
US20040262650A1 (en) | 2000-01-07 | 2004-12-30 | Sharp Kabushiki Kaisha | Semiconductor device, method for producing the same, and information processing apparatus |
US20050167765A1 (en) * | 2000-12-27 | 2005-08-04 | Kabushiki Kaisha Toshiba | Semiconductor device with an L-shaped/reversed L-shaped gate side-wall insulating film and method of manufacturing same |
US20030194851A1 (en) * | 2002-04-16 | 2003-10-16 | Johnson F. Scott | Methods for transistor gate formation using gate sidewall implantation |
EP1478029A1 (en) | 2003-05-14 | 2004-11-17 | Samsung Electronics Co., Ltd. | Mos transistor and method of fabricating the same |
KR20050059633A (en) | 2003-12-15 | 2005-06-21 | 한국전자통신연구원 | Method for fabricating a soi mosfet device having elevated source/drain formed by using a reflow process |
US20060194398A1 (en) | 2005-02-28 | 2006-08-31 | Kabushiki Kaisha Toshiba | Semiconductor device and its manufacturing method |
US20070298549A1 (en) * | 2006-06-23 | 2007-12-27 | Interuniversitair Microelektronica Centrum Vzw (Imec) | Method of fabricating a strained multi-gate transistor and devices obtained thereof |
Non-Patent Citations (1)
Title |
---|
Kang-Kyu Choi, et al; "Untrathin-body SOI MOSFET for Deep-Sub-Tenth Micron Era"; IEEE Electron Device Letters; IEEE Service Center, New York, NY, US; vol. 21, No. 5; May 1, 2005. |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8697529B2 (en) * | 2010-12-30 | 2014-04-15 | Fudan University | Schottky junction source/drain transistor and method of making |
Also Published As
Publication number | Publication date |
---|---|
US20100176426A1 (en) | 2010-07-15 |
CN101796632A (en) | 2010-08-04 |
EP2191505A1 (en) | 2010-06-02 |
WO2009031085A1 (en) | 2009-03-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR101510029B1 (en) | Transistors with high concentration of boron doped germanium | |
US7923782B2 (en) | Hybrid SOI/bulk semiconductor transistors | |
US6372559B1 (en) | Method for self-aligned vertical double-gate MOSFET | |
US7648868B2 (en) | Metal-gated MOSFET devices having scaled gate stack thickness | |
JP4777987B2 (en) | Semiconductor transistor having components made of different materials and method of forming the same | |
US8198673B2 (en) | Asymmetric epitaxy and application thereof | |
US7208397B2 (en) | Transistor having an asymmetric source/drain and halo implantation region and a method of forming the same | |
US6537885B1 (en) | Transistor and method of manufacturing a transistor having a shallow junction formation using a two step EPI layer | |
US20100200897A1 (en) | Transistor and method of manufacturing the same | |
US8084305B2 (en) | Isolation spacer for thin SOI devices | |
US8202782B2 (en) | Method of manufacturing transistor | |
US8735237B2 (en) | Method for increasing penetration depth of drain and source implantation species for a given gate height | |
US20150228777A1 (en) | Silicon on insulator device with partially recessed gate | |
JP2006121074A (en) | Semiconductor device and manufacturing method of the same | |
US20110027954A1 (en) | Method to improve transistor tox using si recessing with no additional masking steps | |
US7176110B2 (en) | Technique for forming transistors having raised drain and source regions with different heights | |
US7442612B2 (en) | Nitride-encapsulated FET (NNCFET) | |
US20050224896A1 (en) | High voltage semiconductor device utilizing a deep trench structure | |
JP2008500721A (en) | Planar dual gate semiconductor device | |
KR100593452B1 (en) | Method of forming a mos transistor having fully silicided metal gate electrode | |
US20070069309A1 (en) | Buried well for semiconductor devices | |
US20130302954A1 (en) | Methods of forming fins for a finfet device without performing a cmp process | |
US6897114B2 (en) | Methods of forming a transistor having a recessed gate electrode structure | |
US20060068542A1 (en) | Isolation trench perimeter implant for threshold voltage control | |
US6097060A (en) | Insulated gate semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: NXP, B.V., NETHERLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MEUNIER-BEILLARD, PHILIPPE;HERINGA, ANCO;DONKERS, JOHANNES;SIGNING DATES FROM 20080829 TO 20080901;REEL/FRAME:024011/0750 |
|
REMI | Maintenance fee reminder mailed | ||
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:038017/0058 Effective date: 20160218 |
|
LAPS | Lapse for failure to pay maintenance fees | ||
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:039361/0212 Effective date: 20160218 |
|
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20160619 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:042762/0145 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:042985/0001 Effective date: 20160218 |
|
AS | Assignment |
Owner name: NXP B.V., NETHERLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:050745/0001 Effective date: 20190903 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051145/0184 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051029/0387 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051029/0001 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051030/0001 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051029/0001 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051029/0387 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051145/0184 Effective date: 20160218 |