US8216902B2 - Nanomesh SRAM cell - Google Patents
Nanomesh SRAM cell Download PDFInfo
- Publication number
- US8216902B2 US8216902B2 US12/536,741 US53674109A US8216902B2 US 8216902 B2 US8216902 B2 US 8216902B2 US 53674109 A US53674109 A US 53674109A US 8216902 B2 US8216902 B2 US 8216902B2
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- US
- United States
- Prior art keywords
- layers
- layer
- gate
- nanowire
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related, expires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/902—Specified use of nanostructure
- Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
- Y10S977/936—Specified use of nanostructure for electronic or optoelectronic application in a transistor or 3-terminal device
- Y10S977/938—Field effect transistors, FETS, with nanowire- or nanotube-channel region
Abstract
Description
Claims (5)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/536,741 US8216902B2 (en) | 2009-08-06 | 2009-08-06 | Nanomesh SRAM cell |
PCT/EP2010/060244 WO2011015440A1 (en) | 2009-08-06 | 2010-07-15 | A nanomesh sram cell |
TW099125382A TW201123429A (en) | 2009-08-06 | 2010-07-30 | A nanomesh SRAM cell |
US13/417,829 US8395220B2 (en) | 2009-08-06 | 2012-03-12 | Nanomesh SRAM cell |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/536,741 US8216902B2 (en) | 2009-08-06 | 2009-08-06 | Nanomesh SRAM cell |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/417,829 Division US8395220B2 (en) | 2009-08-06 | 2012-03-12 | Nanomesh SRAM cell |
Publications (2)
Publication Number | Publication Date |
---|---|
US20110031473A1 US20110031473A1 (en) | 2011-02-10 |
US8216902B2 true US8216902B2 (en) | 2012-07-10 |
Family
ID=42738877
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/536,741 Expired - Fee Related US8216902B2 (en) | 2009-08-06 | 2009-08-06 | Nanomesh SRAM cell |
US13/417,829 Active US8395220B2 (en) | 2009-08-06 | 2012-03-12 | Nanomesh SRAM cell |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/417,829 Active US8395220B2 (en) | 2009-08-06 | 2012-03-12 | Nanomesh SRAM cell |
Country Status (3)
Country | Link |
---|---|
US (2) | US8216902B2 (en) |
TW (1) | TW201123429A (en) |
WO (1) | WO2011015440A1 (en) |
Cited By (24)
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US20110108804A1 (en) * | 2009-02-04 | 2011-05-12 | International Business Machines Corporation | Maskless Process for Suspending and Thinning Nanowires |
EP2384094A2 (en) | 2008-09-05 | 2011-11-02 | Lutron Electronics Co., Inc. | Hybrid light source |
US8587068B2 (en) * | 2012-01-26 | 2013-11-19 | International Business Machines Corporation | SRAM with hybrid FinFET and planar transistors |
US20140339611A1 (en) * | 2013-05-14 | 2014-11-20 | International Business Machines Corporation | Stacked semiconductor nanowires with tunnel spacers |
US9224811B2 (en) | 2014-03-17 | 2015-12-29 | Globalfoundries Inc | Stacked semiconductor device |
US20160012169A1 (en) * | 2014-07-14 | 2016-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gate pad layout patterns of standard cell having different gate pad pitches |
US9536885B2 (en) | 2015-03-30 | 2017-01-03 | International Business Machines Corporation | Hybrid FINFET/nanowire SRAM cell using selective germanium condensation |
US20170141112A1 (en) * | 2015-11-16 | 2017-05-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-Gate Device and Method of Fabrication Thereof |
US20170162583A1 (en) * | 2015-12-03 | 2017-06-08 | Samsung Electronics Co., Ltd. | Static random access memory (sram) device for improving electrical characteristics and logic device including the same |
US9685539B1 (en) * | 2016-03-14 | 2017-06-20 | International Business Machines Corporation | Nanowire isolation scheme to reduce parasitic capacitance |
US9825143B1 (en) * | 2017-01-09 | 2017-11-21 | International Business Machines Corporation | Single spacer tunnel on stack nanowire |
US9997496B2 (en) | 2015-04-01 | 2018-06-12 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit |
US20180350800A1 (en) * | 2016-11-29 | 2018-12-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US10388569B1 (en) | 2018-06-26 | 2019-08-20 | International Business Machines Corporation | Formation of stacked nanosheet semiconductor devices |
US10483166B1 (en) | 2018-06-26 | 2019-11-19 | International Business Machines Corporation | Vertically stacked transistors |
US10490559B1 (en) | 2018-06-27 | 2019-11-26 | International Business Machines Corporation | Gate formation scheme for nanosheet transistors having different work function metals and different nanosheet width dimensions |
US10741564B2 (en) | 2016-01-04 | 2020-08-11 | Samsung Electronics Co., Ltd. | SRAM device provided with a plurality of sheets serving as a channel region |
US10741456B2 (en) | 2018-10-10 | 2020-08-11 | International Business Machines Corporation | Vertically stacked nanosheet CMOS transistor |
US10818751B2 (en) * | 2019-03-01 | 2020-10-27 | International Business Machines Corporation | Nanosheet transistor barrier for electrically isolating the substrate from the source or drain regions |
US10868193B2 (en) | 2018-11-09 | 2020-12-15 | Samsung Electronics Co., Ltd. | Nanosheet field effect transistor cell architecture |
US10892331B2 (en) | 2019-06-05 | 2021-01-12 | International Business Machines Corporation | Channel orientation of CMOS gate-all-around field-effect transistor devices for enhanced carrier mobility |
US11101367B2 (en) * | 2015-06-19 | 2021-08-24 | International Business Machines Corporation | Contact-first field-effect transistors |
US11257681B2 (en) | 2019-07-17 | 2022-02-22 | International Business Machines Corporation | Using a same mask for direct print and self-aligned double patterning of nanosheets |
US11798992B2 (en) | 2018-09-25 | 2023-10-24 | Socionext Inc. | Semiconductor device and method of producing the same |
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US8901537B2 (en) * | 2010-12-21 | 2014-12-02 | Intel Corporation | Transistors with high concentration of boron doped germanium |
US9099388B2 (en) * | 2011-10-21 | 2015-08-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | III-V multi-channel FinFETs |
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US9087863B2 (en) | 2011-12-23 | 2015-07-21 | Intel Corporation | Nanowire structures having non-discrete source and drain regions |
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US9012284B2 (en) | 2011-12-23 | 2015-04-21 | Intel Corporation | Nanowire transistor devices and forming techniques |
US10424580B2 (en) | 2011-12-23 | 2019-09-24 | Intel Corporation | Semiconductor devices having modulated nanowire counts |
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US9400862B2 (en) | 2014-06-23 | 2016-07-26 | Synopsys, Inc. | Cells having transistors and interconnects including nanowires or 2D material strips |
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- 2010-07-30 TW TW099125382A patent/TW201123429A/en unknown
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2012
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Cited By (46)
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EP2384094A2 (en) | 2008-09-05 | 2011-11-02 | Lutron Electronics Co., Inc. | Hybrid light source |
US20110108804A1 (en) * | 2009-02-04 | 2011-05-12 | International Business Machines Corporation | Maskless Process for Suspending and Thinning Nanowires |
US8441043B2 (en) * | 2009-02-04 | 2013-05-14 | International Business Machines Corporation | Maskless process for suspending and thinning nanowires |
US8587068B2 (en) * | 2012-01-26 | 2013-11-19 | International Business Machines Corporation | SRAM with hybrid FinFET and planar transistors |
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WO2011015440A1 (en) | 2011-02-10 |
TW201123429A (en) | 2011-07-01 |
US20110031473A1 (en) | 2011-02-10 |
US8395220B2 (en) | 2013-03-12 |
US20120168872A1 (en) | 2012-07-05 |
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