|Número de publicación||US8405196 B2|
|Tipo de publicación||Concesión|
|Número de solicitud||US 12/072,508|
|Fecha de publicación||26 Mar 2013|
|Fecha de presentación||26 Feb 2008|
|Fecha de prioridad||5 Mar 2007|
|También publicado como||CN101675516A, CN101675516B, EP2135280A2, EP2575166A2, EP2575166A3, US8310036, US8735205, US20080246136, US20100225006, US20130065390, WO2008108970A2, WO2008108970A3|
|Número de publicación||072508, 12072508, US 8405196 B2, US 8405196B2, US-B2-8405196, US8405196 B2, US8405196B2|
|Inventores||Belgacem Haba, Kenneth Allen Honer, David B. Tuckerman, Vage Oganesian|
|Cesionario original||DigitalOptics Corporation Europe Limited|
|Exportar cita||BiBTeX, EndNote, RefMan|
|Citas de patentes (196), Otras citas (20), Citada por (28), Clasificaciones (57), Eventos legales (8)|
|Enlaces externos: USPTO, Cesión de USPTO, Espacenet|
This application claims the benefit of the filing date of U.S. Provisional Patent Application No. 60/905,096 filed Mar. 5, 2007, the disclosure of which is hereby incorporated herein by reference.
The present invention relates to packaging of microelectronic devices, especially the packaging of semiconductor devices.
Certain types of microelectronic devices and semiconductor chips include devices such as acoustic transducers, radio frequency emitters, radio frequency detectors or optoelectronic devices or a combination of such devices. Such devices typically require packaging which permits the passage of energy, e.g., acoustic, radio frequency or optical wavelength energy to and from devices at a face of a semiconductor chip.
Because such devices are often exposed at a front face of the microelectronic devices, they usually require protection from the elements, such as dust, other particles, contaminants or humidity. For this reason, it is advantageous to assemble the microelectronic device with a lid or other element covering the front face of such microelectronic device at an early stage of processing.
It is desirable in some types of microelectronic systems to mount chips and packaged chips having very small, i.e., chip-scale packages, to circuit panels. In some cases it is desirable to stack and interconnect chips to each other one on top of another to increase the circuit density of the assembly.
Some types of mass-produced chips also require packaging costs to be tightly controlled. Processing used to package such semiconductor chips can be performed on many chips simultaneously while the chips remain attached to each other in form of a wafer or portion of a wafer. Such “wafer-level” processing typically is performed by a sequence of processes applied to an entire wafer, after which the wafer is diced into individual chips. Advantageously, wafer-level packaging processes produce packaged chips which have the same area dimensions as the original semiconductor chips, making their interconnection compact on circuit panels and the like.
In accordance with an aspect of the invention, a microelectronic unit is provided in which a semiconductor element has a front surface and a rear surface remote from the front surface. The front and rear surfaces may define a thin region which has a first thickness and a thicker region having a second thickness being at least about twice the first thickness. In such microelectronic unit, the semiconductor element may include a semiconductor device at the front surface and a plurality of first conductive contacts at the front surface connected to the device. A plurality of conductive vias may extend from the rear surface through the thin region of the semiconductor element to the first conductive contacts. A plurality of second conductive contacts can be exposed at an exterior of the semiconductor element, and a plurality of conductive traces may connect the second conductive contacts to the conductive vias.
A microelectronic unit is provided in accordance with another aspect of the invention. In such microelectronic unit, a semiconductor element has a front surface, a semiconductor device at the front surface and a rear surface remote from the front surface. First conductive contacts may be provided at the front surface. The semiconductor element may also have first holes having a first depth extending from the rear surface partially through the semiconductor element towards the front surface. Such second holes may have a second depth which extends from the first holes to the first conductive contacts. A plurality of first conductive vias may extend along walls of the second holes to contact the first conductive contacts. A plurality of conductive interconnects may be connected to the first conductive vias. In one embodiment, such conductive interconnects may extend along walls of the first holes. A plurality of second conductive contacts may be connected to the conductive interconnects. In one example, the second contacts may be exposed at an exterior of the semiconductor element.
In accordance with an aspect of the invention, a microelectronic unit is provided which may includes a semiconductor element having a front surface, a semiconductor device at the front surface and a plurality of first conductive contacts at the front surface connected to the device. A lid may be provided which has an inner surface confronting the front surface of the semiconductor element and an outer surface remote from the inner surface. First holes having a first depth may extend from the outer surface at least partially through the lid towards the inner surface. A support structure may be provided which supports the inner surface of the lid above the front surface of the semiconductor element. In one example, the support structure has second holes which are aligned with the first holes. The second holes may extend through the support structure to the first conductive contacts. A plurality of first conductive vias may extend along walls of the second holes to contact the first conductive contacts. A plurality of second conductive vias may extend along walls of the first holes. A plurality of second conductive contacts may be exposed at an exterior of the lid. In one example, a plurality of conductive traces connect such second conductive contacts to the conductive vias.
In accordance with an aspect of the invention, a microelectronic unit is provided which includes a semiconductor element having a front surface and a semiconductor device at the front surface of the semiconductor element. A plurality of first conductive contacts may be provided at the front surface which are connected to the device. The microelectronic unit may additionally include a lid having an inner surface confronting the front surface of the semiconductor element and an outer surface remote from the inner surface. The inner and outer surfaces of the lid may define a thin region having a first thickness and a thicker region having a second thickness being at least about twice the first thickness. Such lid may further include a plurality of conductive vias extending from the outer surface through the thin region of the lid to connect to the first conductive contacts. Such microelectronic unit may further include a plurality of second conductive contacts. A plurality of conductive traces may also connect the second conductive contacts to the conductive vias.
In accordance with an aspect of the invention, a microelectronic unit is provided which may include a lid having an inner surface confronting the front surface of a semiconductor element and an outer surface remote from the front surface. A plurality of conductive vias may extend through the lid to contact the first conductive contacts. Such microelectronic unit may additionally include a plurality of second conductive contacts overlying the outer surface of the lid. A plurality of conductive traces may connect the second conductive contacts to the conductive vias.
In accordance with an aspect of the invention, a microelectronic unit is provided which includes a semiconductor element having a front surface, a semiconductor device at the front surface and a rear surface remote from the front surface. Front conductive contacts may be exposed at the front surface. Rear conductive contacts may be exposed at the rear surface. A plurality of conductive vias may be connected to the front conductive contacts, the conductive vias extending downwardly from the front surface. An opening may extend downwardly from the rear surface in registration with at least one of the conductive vias. A conductive trace may extend upwardly from at least one of the conductive vias along a wall of the opening. Such conductive trace may be connected to at least one of the rear conductive contacts.
In accordance with an aspect of the invention, a microelectronic unit is provided which includes a semiconductor element having a front surface, a semiconductor device at the front surface and a rear surface remote from the front surface. Rear conductive contacts may be exposed at the rear surface. In such microelectronic unit, a plurality of conductive vias may extend downwardly from the front surface. An opening may extend downwardly from the rear surface in registration with at least one of the conductive vias. A conductive bump can be joined to one of the conductive vias within the opening. In such case, the conductive bump may extend from the conductive via to a position above a plane defined by the rear surface.
In accordance with an aspect of the invention, a microelectronic unit is provided which includes a semiconductor element having a front surface, a semiconductor device at the front surface and a rear surface remote from the front surface. Rear conductive contacts may be exposed at the rear surface. A plurality of conductive vias may extend downwardly from the front surface. An opening can extend downwardly from the rear surface in registration with at least one of the conductive vias. A conductive bump can be joined to one of the conductive vias at the front surface. The conductive bump may extend upwardly from the front surface, for example.
A method of fabricating a microelectronic unit is provided in accordance with another aspect of the invention. Such method may include providing a semiconductor element having a front surface, a rear surface remote from the front surface and a semiconductor device at the front surface. First conductive contacts may be provided at the front surface of the semiconductor element which are connected to the device. A plurality of conductive vias may extend from the rear surface through the semiconductor element to the first conductive contacts. Such method may further include forming a plurality of second conductive contacts overlying the rear surface and a plurality of conductive traces, the conductive traces connecting the second conductive contacts to the conductive vias.
A method of fabricating a microelectronic unit is provided in accordance with another aspect of the invention in which a semiconductor element is provided which includes a front surface and a semiconductor device at the front surface. First conductive contacts at the front surface may be connected to the semiconductor device. The semiconductor element may further include a rear surface remote from the front surface and semiconductor material exposed at the rear surface. A plurality of through holes may extend from the rear surface through the semiconductor element to the first conductive contacts. A rear dielectric layer may be electrodeposited onto the exposed semiconductor material at the rear surface, along walls of the through holes or both. Second conductive contacts may overlie the rear surface. A plurality of conductive vias may be formed within the through holes which contact the first conductive contacts. A plurality of conductive traces may be formed which connect the second conductive contacts to the conductive vias.
A method of fabricating a microelectronic unit is provided in accordance with another embodiment of the invention. Such method may include assembling a semiconductor element with a cover element overlying a front surface of the semiconductor element to form a unit. The semiconductor element may have first conductive contacts at the front surface connected to the semiconductor device. A rear surface may be provided which is remote from the front surface. A plurality of through holes may extend from the rear surface through the semiconductor element to the first conductive contacts. In one embodiment, the semiconductor material is exposed at the rear surface and at walls of the through holes.
A dielectric layer can be electrodeposited to overlie the exposed semiconductor material at the rear surface and along walls of the through holes. The dielectric layer can also be electrodeposited over the dielectric layer such that conductive vias are formed are formed within the through which contact the first conductive contacts. A plurality of second conductive contacts may overlie the rear surface and a plurality of conductive traces may connect the conductive vias to the second conductive contacts.
The semiconductor chip 100 typically is connected to the lid 104 through one or more standoff structures 124, which may include an adhesive, an inorganic or organic material and/or a joining metal. Structures for supporting a lid at a constant spacing from a chip are described in the commonly owned U.S. Provisional Application No. 60/761,171 filed on Jan. 23, 2006, and U.S. Provisional Application No. 60/775,086 filed on Feb. 21, 2006, the disclosures of which are hereby incorporated herein by reference. The packaged chip may include an interior cavity 106 between the front face 102 of the chip and the inner surface 105 of the lid 104, as illustrated in
The semiconductor devices 112 in the semiconductor chip 100 typically include electromagnetic transducer devices such as electromagnetic or electro-optic devices which either detect or output electromagnetic radiation. The semiconductor devices may be designed to emit or receive radio frequency and/or optical wavelengths of infrared, visible and/or ultraviolet or higher wavelength spectra including but not limited to x-ray wavelengths. Alternatively, the semiconductor devices 112 can include acoustic transducer devices, such devices being designed to convert sound pressure waves received through a medium, e.g., air and/or other fluid medium (gas or liquid) to one or more electrical signals, or to convert one or more electrical signals into sound pressure waves.
In a particular embodiment, the packaged chip is a sensor unit in which the semiconductor devices 112 of the chip 100 include an imaging area 107 for capturing an image. Electronic circuits (not shown) in chip 100 are connected to the semiconductor devices in the imaging area 107 for generating one or more electrical signals representing an image captured by the imaging area 107. Numerous electrical circuits are well known in the imaging art for this purpose. For example, the semiconductor chip 100 may be a generally conventional charge-coupled device (CCD) imaging chip with conventional circuits such as clocking and charge-to-voltage conversion circuits.
As seen in
The semiconductor chip has surfaces 120 which are set at an angle away from the rear surface. As illustrated in
Conductive vias 125 extend between the front face 102 of the chip 100 and the lowered rear surfaces 115. The conductive vias provide conductive interconnection between the front contact pads 116 and conductive traces 126 overlying the lowered rear surfaces 115 and surfaces 120. The conductive vias 125 include a conductive layer overlying a dielectric layer 122 disposed within holes 127 extending between the front face and the lowered rear surfaces. Between the front face 102 and the lowered rear surface, the walls of the holes 127 can extend vertically, i.e., at right angles relative to the front face. Alternatively, the holes 127 can be tapered in a direction from the lowered rear surface towards the front face such that the holes become smaller with increasing distance from the lowered rear surface. In yet another alternative, the holes 127 can be tapered in a direction from the front face towards the lowered rear surface such that the holes become smaller with increasing depth from the front face. Each of the embodiments described below can include holes having any one of these available hole geometries.
In the example shown in
The dielectric layer 122 preferably includes a conformally coated dielectric material. Preferably, there are no breaks in the conformal coating and the dielectric layer 122 provides good dielectric isolation with respect to the semiconductor chip 100. Desirably, the dielectric layer 122 is a compliant layer, having sufficiently low modulus of elasticity and sufficient thickness such that the product of the modulus and the thickness provide compliancy. Specifically, such compliant layer can allow the contacts 128 and traces 126 attached thereto to flex somewhat. In that way, the bond between external conductive bumps 134 of the packaged chip 10 and terminals of a circuit panel (not shown) can better withstand thermal strain due to mismatch of the coefficient of thermal expansion (“CTE”) between the packaged chip 10 and a circuit panel (not shown). Desirably, the degree of compliancy provided by the product of the thickness of the dielectric layer 122 and its modulus are sufficient to compensate for strain applied to the conductive bumps due to thermal expansion mismatch between the chip 100 and the circuit panel. An underfill (not shown) can be provided between the exposed surface of the dielectric layer 130 and such circuit panel to enhance resistance to thermal strain due to CTE mismatch.
With further reference to
As further shown in
In a particular embodiment, a metal structure 132 including a metal layer or stack of metal layers including a wettable metal layer overlies the package contact pads 128, and conductive bumps 134 overlie the metal structure 132. Typically, the conductive bumps 134 include a fusible metal having a relatively low melting temperature such as solder, tin, or a eutectic mixture including a plurality of metals. Alternatively, the bumps 134 include a wettable metal, e.g., copper or other noble metal or non-noble metal having a melting temperature higher than that of solder or other fusible metal. Such wettable metal can be joined with a corresponding feature, e.g., a fusible metal feature of an interconnect element such as a circuit panel to externally interconnect the packaged chip 10 to such interconnect element. In another alternative, the bumps 134 include a conductive material interspersed in a medium, e.g., a % conductive paste, e.g., metal-filled paste, solder-filled paste or isotropic conductive adhesive or anisotropic conductive adhesive.
A method of simultaneously fabricating a plurality of packaged chips 10 (
As further illustrated in
After joining the device wafer 101 to the lid element 111 as illustrated in
Thereafter, the resulting device wafer has a reduced thickness 274, as shown in
As particularly shown in
Thereafter, as illustrated in
Thereafter, in the stage of fabrication illustrated in
In still another example, the assembly including the device wafer with the lid element attached thereto is immersed in a dielectric deposition bath to form a conformal dielectric coating or layer 820. Preferably, an electrophoretic deposition technique is utilized to form the conformal dielectric coating, such that the conformal dielectric coating is only deposited onto exposed conductive and semiconductive surfaces of the assembly. During deposition, the semiconductor device wafer is held at a desired electric potential and an electrode is immersed into the bath to hold the bath at a different desired potential. The assembly is then held in the bath under appropriate conditions for a sufficient time to form an electrodeposited conformal dielectric coating 820 on exposed surfaces of the device wafer which are conductive or semiconductive, including but not limited to along the rear faces 114, walls 504 of the recess, the lowered surface 502 and walls 806 of the vias 708. Electrophoretic deposition occurs so long as a sufficiently strong electric field is maintained between the surface to be coated thereby and the bath. As the electrophoretically deposited coating is self-limiting in that after it reaches a certain thickness governed by parameters, e.g., voltage, concentration, etc. of its deposition, deposition stops. Electrophoretic deposition forms a continuous and uniformly thick conformal coating on conductive and/or semiconductive exterior surfaces of the assembly. In addition, the electrophoretically deposited coating preferably does not form on the remaining dielectric layer 710 overlying the contacts 116, due to its dielectric (nonconductive) property. Stated another way, a property of electrophoretic deposition is that is does not form on a layer of dielectric material overlying a conductor provided that the layer of dielectric material has sufficient thickness, given its dielectric properties. Typically, electrophoretic deposition will not occur on dielectric layers having thicknesses greater than about 10 microns to a few tens of microns.
Preferably, the conformal dielectric layer 820 is formed from a cathodic epoxy deposition precursor. Alternatively, a polyurethane or acrylic deposition precursor could be used. A variety of electrophoretic coating precursor compositions and sources of supply are listed in Table 1 below.
Pb or Pf-free
VOC, g/L (MINUS WATER)
20 min/175 C.
20 min/175 C.
SOLIDS, % wt.
pH (25 C)
CONDUCTIVITY (25 C) μS
OPERATION TEMP., C.
VOC, g/L (MINUS WATER)
20 min/149 C.
20 min/175 C.
20 min/175 C.
SOLIDS, % wt.
pH (25 C)
CONDUCTIVITY (25 C) μS
OPERATION TEMP., C.
Next, referring to
The conductive traces 126 and lands 128 are now formed to overlie the conformal dielectric coating 820. An exemplary method of forming the traces and lands involves depositing a metal layer to overlie the conformal dielectric coating 220. Alternatively, the deposition can be conducted while portions of those surfaces are protected by a masking layer. The metal layer preferably is deposited by sputtering a primary metal layer onto exposed surfaces of the assembly, or by electroless deposition. This step can be performed by blanket deposition onto the rear face, walls and lowered surface of the device wafer, for example. In one embodiment, the primary metal layer includes or consists essentially of aluminum. In another particular embodiment, the primary metal layer includes or consists essentially of copper. In yet another embodiment, the primary metal layer includes or consists essentially of titanium. One or more other exemplary metals can be used in a process to form the primary metal layer.
A photoimageable layer then is deposited to overlie the primary metal layer and a three-dimensional photolithographic patterning process is utilized to pattern the primary metal layer, such as the process described in U.S. Pat. No. 5,716,759 to Badehi, the disclosure of which is hereby incorporated by reference herein. Thereafter, remaining portions of the photoimageable layer are removed. As a result, individual conductive patterns are formed which correspond to the dimensions of conductive traces to be formed thereon. Following patterning of the primary metal layer into individual lines, the photoimageable layer is removed from the device wafer and an electroplating process is used to plate a secondary metal layer onto the primary metal layer to form individual conductive traces 126 extending from the front contact pads 116 along the walls 120 and onto the rear faces 114 of the semiconductor chips. The secondary metal may include nickel or other noble metal. In one embodiment, the electroplated second metal on the primary metal layer completes the conductive traces. Alternatively, an optional third metal layer such as gold, platinum or palladium may be plated onto the secondary metal for providing corrosion resistance to complete the conductive traces.
Subsequently, an exemplary process, an additional dielectric layer 230 is deposited to overlie each of the conductive traces 226 extending along the rear surface 114 and walls 120. Desirably, the additional dielectric layer 230 is deposited by an electrophoretic deposition process such as described above with reference to
Alternatively, instead of depositing the dielectric layer 230 by electrophoretic deposition, the dielectric layer can be formed by spin-coating or spray coating a photoimageable dielectric such as an encapsulant or a solder mask material towards the rear face 114 and walls 120 of the device wafer to form a relatively uniformly thick coating. Thereafter, openings can be formed in the conformal dielectric layer 230 in registration with the contacts 128 by photolithographic process. One or more processes, e.g., heating etc. may be performed to cause the dielectric layer 230 to harden after the initial deposition of the photoimageable material.
Next, a wettable metal layer 132, e.g., an “under bump metallization” or (“UBM”) is formed within the openings in the dielectric layer 230, the wettable layer being in contact with each of the contacts 128. In one exemplary process, a diffusion barrier layer, e.g., a conductive layer including titanium, tungsten, tantalum, or other similar metal is formed in contact with the contacts 128. Thereafter, a layer including a first wettable metal can be deposited to overlie the barrier layer, such layer including a metal such as nickel, copper or other metal which desirably includes a noble metal. For enhanced corrosion resistance, a layer of gold, usually very thin, e.g., 0.1 micron, can be deposited as a final layer of wettable metal. After forming the wettable metal layer, conductive bumps 134 can be formed in contact with the wettable metal layer over each contact. Conductive bumps can be formed which include a fusible metal such as a solder, tin or eutectic composition, or which include a conductive paste, e.g., solder-filled or silver-filled paste, among others. The conductive bumps can include one or more conductive materials. In a particular example, the conductive bumps can include one or more noble metals, for example, copper, nickel, etc. In one example, the conductive bumps may be formed by placing spheres including a fusible metal such as solder, tin or eutectic onto the wettable metal layer 232 and then heating the conductive bumps thereto to fuse them to the wettable metal layer 232.
Finally, the packaged chips are severed from each other along dicing lane 12 by sawing or other dicing method to form individual packaged chips 10 as illustrated in
A camera module 1030 according to an embodiment of the invention (
The optical unit 1050 in this arrangement includes a turret or support structure 1051 having a mounting portion 1052 arranged to hold one or more lenses or other optical elements 1058. The support structure 1051 also includes a plurality of rear elements 1062 in the form of elongated posts 1062 projecting rearward from the mounting portion 1052. These posts have rear surfaces 1054 which abut or mechanically engage a reference plane in the sensor unit to position the optical unit relative to the sensor unit. In the example illustrated in
It is desirable to make the connection between the rear surfaces of the posts 1062 and the front surface 1034 level and uniform in thickness. In another way to achieve this purpose, metallic attachment features or pads 1055 can be provided at the outer surface 1036 of the cover 1034, which are metallurgically bonded, e.g., via diffusion bonding, to metallic features at the rear surfaces 1054 of the posts 1062. Alternatively, a somewhat thin adhesive can be used to bond the rear surfaces of the posts to the cover.
In another embodiment, in place of posts, the turret or support structure 1051 includes a rear element which encloses or substantially encloses a volume having a cylindrical or polyhedral shape. Such rear element can be provided which has a cylindrical wall or polyhedral shaped (e.g., box-shaped) wall, in which the rear surface of the rear element abuts against a reference plane of the sensor unit such as provided at the outer surface 1036 of the cover 1034.
In a variation of the above embodiment shown in
A camera module in accordance with a further embodiment of the invention (
A module or assembly in accordance with the embodiment of
In a method according to a further embodiment of the invention, the sensor unit may include a sacrificial layer overlying the front of the sensor unit as, for example, a sacrificial layer overlying the outer surface of the cover in a sensor unit which includes a cover, or a sacrificial layer overlying the imaging area of the chip in a sensor unit which does not include a cover. The assembly is fabricated with the sacrificial layer in place. The completed assembly is then subjected to an operation in which the sacrificial layer, or at least that portion of the sacrificial layer aligned with the imaging area of the sensor unit, is removed through hole 972 and through the one or more of the gaps 963 in the support structure 952. For example, the sacrificial layer may be removed by dissolving it, or by mechanically engaging it and peeling it away from the sensor unit. Removal of the sacrificial layer removes any contaminants which may have accumulated on that layer.
Other operations also may be performed through the gap or gaps. For example, a tool may be inserted into the gap or gaps to engage the conductors of the circuit panel and bond them to the contacts of the sensor unit. Alternatively, a wire-bonding tool may be used to provide wire bonds extending between the conductors and the sensor unit through hole 972, or through one or more of the additional apertures 974, or through other apertures (not shown) provided in the circuit panel for this purpose.
It is not essential to provide post-like rear elements in order to provide large gaps as discussed above. For example, the rear elements may be in the form of plates or ribs. Also, it is not essential to provide multiple gaps; only one gap may be sufficient for some operations.
As in the example shown and described above with reference to
In the embodiments discussed above, the circuit panel has a hole extending through the panel in alignment with the imaging area of the sensor unit. Such a hole forms a transparent region in the circuit panel. In other embodiments, the circuit panel includes a solid but transparent region in alignment with the imaging area of the sensor unit. For example, the circuit panel may be formed from a transparent dielectric material, in which case the transparent region of the circuit panel may be provided simply by routing the conductors of the circuit panel so that no conductors cross the transparent region.
In the example shown in
Alternatively, when each large opening 1604 has only one via within, the via 1608 and the large opening 1604 can be filled with a conductive material overlying a dielectric layer 1620 disposed on walls of the via 1608 and opening 1604.
Referring again to
A dielectric fill material 1940 desirably overlies the traces 1924 within the large opening 1904 for providing electrical isolation between traces as well as mechanical support to the packaged chip 1901. Desirably, a dielectric layer 1942, e.g., a solder mask, overlies the traces 1924. Openings 1944 in the dielectric layer expose rear face contacts 1946 of the chip.
By providing both front face contacts 1936 and rear face contacts 1946, several packaged chips can be stacked one on top of the other to form a stacked assembly 1950 of packaged chips (
An advantage of the stacked assembly 1950 is that the front face and rear face contacts are offset from the large openings 1904 in the packaged chip. Therefore, pressure exerted upon the stacked assembly when interconnecting the packaged chips is felt primarily at those contacts at locations away from the large openings. Such arrangement helps to avoid applying pressure to the packaged chip at the large opening where the semiconductor chip may possibly be weakened by the removal of semiconductor material to form the large opening.
One potential benefit of having offset contacts is the ability to provide redistribution traces between the actual bond pads of the chip and the front and rear face contacts. Chip select features of certain types of memories, e.g., DRAMs, may require that certain bond pads of chips not be connected to the bond pads of other chips which directly overlie them.
Interconnection between the conductive vias and traces in the large opening can be achieved in different ways.
In another variation of the packaged chip 1910 described above with reference to
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.
For example, in a particular embodiment of the invention, conductive traces extend from conductive features at the front face of a semiconductor chip along edges of a lid or along walls of openings formed in a lid covering the semiconductor chip and onto an outer surface of the cover element.
|Patente citada||Fecha de presentación||Fecha de publicación||Solicitante||Título|
|US4682074||1 Nov 1985||21 Jul 1987||U.S. Philips Corporation||Electron-beam device and semiconductor device for use in such an electron-beam device|
|US4765864||15 Jul 1987||23 Ago 1988||Sri International||Etching method for producing an electrochemical cell in a crystalline substrate|
|US5322816||19 Ene 1993||21 Jun 1994||Hughes Aircraft Company||Method for forming deep conductive feedthroughs|
|US5481133||29 Dic 1994||2 Ene 1996||United Microelectronics Corporation||Three-dimensional multichip package|
|US5686762||21 Dic 1995||11 Nov 1997||Micron Technology, Inc.||Semiconductor device with improved bond pads|
|US5700735||22 Ago 1996||23 Dic 1997||Taiwan Semiconductor Manufacturing Company, Ltd.||Method of forming bond pad structure for the via plug process|
|US5703408||10 Abr 1995||30 Dic 1997||United Microelectronics Corporation||Bonding pad structure and method thereof|
|US5808874||2 May 1996||15 Sep 1998||Tessera, Inc.||Microelectronic connections with liquid conductive elements|
|US6005466||24 Jul 1995||21 Dic 1999||Mitel Semiconductor Limited||Trimmable inductor structure|
|US6013948||1 Abr 1998||11 Ene 2000||Micron Technology, Inc.||Stackable chip scale semiconductor package with mating contacts on opposed surfaces|
|US6022758||7 Jul 1995||8 Feb 2000||Shellcase Ltd.||Process for manufacturing solder leads on a semiconductor device package|
|US6031274||10 Oct 1997||29 Feb 2000||Hamamatsu Photonics K.K.||Back irradiation type light-receiving device and method of making the same|
|US6103552||10 Ago 1998||15 Ago 2000||Lin; Mou-Shiung||Wafer scale packaging scheme|
|US6143369||30 Dic 1996||7 Nov 2000||Matsushita Electric Works, Ltd.||Process of impregnating substrate and impregnated substrate|
|US6143396||1 May 1997||7 Nov 2000||Texas Instruments Incorporated||System and method for reinforcing a bond pad|
|US6169319||17 Nov 1999||2 Ene 2001||Tower Semiconductor Ltd.||Backside illuminated image sensor|
|US6181016||8 Jun 1999||30 Ene 2001||Winbond Electronics Corp||Bond-pad with a single anchoring structure|
|US6261865||6 Oct 1998||17 Jul 2001||Micron Technology, Inc.||Multi chip semiconductor package and method of construction|
|US6277669||15 Sep 1999||21 Ago 2001||Industrial Technology Research Institute||Wafer level packaging method and packages formed|
|US6284563||1 May 1998||4 Sep 2001||Tessera, Inc.||Method of making compliant microelectronic assemblies|
|US6313540||22 Dic 1999||6 Nov 2001||Nec Corporation||Electrode structure of semiconductor element|
|US6362529||22 Sep 2000||26 Mar 2002||Sharp Kabushiki Kaisha||Stacked semiconductor device|
|US6368410||28 Jun 1999||9 Abr 2002||General Electric Company||Semiconductor processing article|
|US6472247||25 Jun 2001||29 Oct 2002||Ricoh Company, Ltd.||Solid-state imaging device and method of production of the same|
|US6492201||10 Jul 1998||10 Dic 2002||Tessera, Inc.||Forming microelectronic connection components by electrophoretic deposition|
|US6498387||15 Feb 2000||24 Dic 2002||Wen-Ken Yang||Wafer level package and the process of the same|
|US6507113||19 Nov 1999||14 Ene 2003||General Electric Company||Electronic interface structures and methods of fabrication|
|US6586955||27 Feb 2001||1 Jul 2003||Tessera, Inc.||Methods and structures for electronic probing arrays|
|US6608377||4 Dic 2001||19 Ago 2003||Samsung Electronics Co., Ltd.||Wafer level package including ground metal layer|
|US6693358||10 Oct 2001||17 Feb 2004||Matsushita Electric Industrial Co., Ltd.||Semiconductor chip, wiring board and manufacturing process thereof as well as semiconductor device|
|US6727576||31 Oct 2001||27 Abr 2004||Infineon Technologies Ag||Transfer wafer level packaging|
|US6737300||21 May 2002||18 May 2004||Advanced Semiconductor Engineering, Inc.||Chip scale package and manufacturing method|
|US6743660||12 Ene 2002||1 Jun 2004||Taiwan Semiconductor Manufacturing Co., Ltd||Method of making a wafer level chip scale package|
|US6812549||21 Oct 2002||2 Nov 2004||Seiko Epson Corporation||Wiring board and fabricating method thereof, semiconductor device and fabricating method thereof, circuit board and electronic instrument|
|US6828175||10 Jun 2003||7 Dic 2004||Micron Technology, Inc.||Semiconductor component with backside contacts and method of fabrication|
|US6864172||17 Jun 2003||8 Mar 2005||Sanyo Electric Co., Ltd.||Manufacturing method of semiconductor device|
|US6867123||30 Nov 2001||15 Mar 2005||Renesas Technology Corp.||Semiconductor integrated circuit device and its manufacturing method|
|US6873054||17 Abr 2003||29 Mar 2005||Seiko Epson Corporation||Semiconductor device and a method of manufacturing the same, a circuit board and an electronic apparatus|
|US6879049||22 Ene 1999||12 Abr 2005||Rohm Co., Ltd.||Damascene interconnection and semiconductor device|
|US6927156||18 Jun 2003||9 Ago 2005||Intel Corporation||Apparatus and method extending flip-chip pad structures for wirebonding on low-k dielectric silicon|
|US6982475||3 Jul 2002||3 Ene 2006||Mcsp, Llc||Hermetic wafer scale integrated circuit structure|
|US7026175||29 Mar 2004||11 Abr 2006||Applied Materials, Inc.||High throughput measurement of via defects in interconnects|
|US7068139||29 Sep 2004||27 Jun 2006||Agere Systems Inc.||Inductor formed in an integrated circuit|
|US7091062||15 Oct 2004||15 Ago 2006||Infineon Technologies Ag||Wafer level packages for chips with sawn edge protection|
|US7271033||28 Oct 2004||18 Sep 2007||Megica Corporation||Method for fabricating chip package|
|US7329563||21 Jun 2005||12 Feb 2008||Industrial Technology Research Institute||Method for fabrication of wafer level package incorporating dual compliant layers|
|US7413929||22 Ene 2002||19 Ago 2008||Megica Corporation||Integrated chip package structure using organic substrate and method of manufacturing the same|
|US7420257||22 Jul 2004||2 Sep 2008||Hamamatsu Photonics K.K.||Backside-illuminated photodetector|
|US7436069||1 Dic 2005||14 Oct 2008||Nec Electronics Corporation||Semiconductor device, having a through electrode semiconductor module employing thereof and method for manufacturing semiconductor device having a through electrode|
|US7446036||18 Dic 2007||4 Nov 2008||International Business Machines Corporation||Gap free anchored conductor and dielectric structure and method for fabrication thereof|
|US7456479||15 Dic 2005||25 Nov 2008||United Microelectronics Corp.||Method for fabricating a probing pad of an integrated circuit chip|
|US7531445||31 Ene 2007||12 May 2009||Hymite A/S||Formation of through-wafer electrical interconnections and other structures using a thin dielectric membrane|
|US7531453 *||6 Feb 2008||12 May 2009||Micron Technology, Inc.||Microelectronic devices and methods for forming interconnects in microelectronic devices|
|US7719121 *||17 Oct 2006||18 May 2010||Tessera, Inc.||Microelectronic packages and methods therefor|
|US7750487 *||11 Ago 2004||6 Jul 2010||Intel Corporation||Metal-metal bonding of compliant interconnect|
|US7754531 *||15 Nov 2006||13 Jul 2010||Micron Technology, Inc.||Method for packaging microelectronic devices|
|US7767497 *||12 Jul 2007||3 Ago 2010||Tessera, Inc.||Microelectronic package element and method of fabricating thereof|
|US7781781||17 Nov 2006||24 Ago 2010||International Business Machines Corporation||CMOS imager array with recessed dielectric|
|US7791199||22 Nov 2006||7 Sep 2010||Tessera, Inc.||Packaged semiconductor chips|
|US8008192||23 Ago 2010||30 Ago 2011||Micron Technology, Inc.||Conductive interconnect structures and formation methods using supercritical fluids|
|US20010048591 *||26 Ene 2001||6 Dic 2001||Joseph Fjelstad||Microelectronics component with rigid interposer|
|US20020061723||13 Dic 2001||23 May 2002||Duescher Wayne O.||Raised island abrasive and process of manufacture|
|US20020096787||27 Mar 2002||25 Jul 2002||Tessera, Inc.||Connection components with posts|
|US20020109236||28 Ene 2002||15 Ago 2002||Samsung Electronics Co., Ltd.||Three-dimensional multi-chip package having chip selection pads and manufacturing method thereof|
|US20030059976||12 Mar 2002||27 Mar 2003||Nathan Richard J.||Integrated package and methods for making same|
|US20030071331||17 Oct 2002||17 Abr 2003||Yoshihide Yamaguchi||Semiconductor device and structure for mounting the same|
|US20040016942||17 Abr 2003||29 Ene 2004||Seiko Epson Corporation||Semiconductor device and a method of manufacturing the same, a circuit board and an electronic apparatus|
|US20040017012||11 Jul 2003||29 Ene 2004||Yuichiro Yamada||Semiconductor chip, wiring board and manufacturing process thereof as well as semiconductor device|
|US20040043607||29 Ago 2002||4 Mar 2004||Farnworth Warren M.||Methods for creating electrophoretically insulated vias in semiconductive substrates and resulting structures|
|US20040051173||10 Dic 2001||18 Mar 2004||Koh Philip Joseph||High frequency interconnect system using micromachined plugs and sockets|
|US20040104454||10 Oct 2003||3 Jun 2004||Rohm Co., Ltd.||Semiconductor device and method of producing the same|
|US20040155354||2 Feb 2004||12 Ago 2004||Seiko Epson Corporation||Semiconductor device, method of fabricating the same, stack-type semiconductor device, circuit board and electronic instrument|
|US20040178495 *||28 Ago 2003||16 Sep 2004||Yean Tay Wuu||Microelectronic devices and methods for packaging microelectronic devices|
|US20040188819||8 Dic 2003||30 Sep 2004||Farnworth Warren M.||Wafer level methods for fabricating multi-dice chip scale semiconductor components|
|US20040188822||14 Ene 2004||30 Sep 2004||Kazumi Hara||Semiconductor chip, semiconductor wafer, semiconductor device and method of manufacturing the same, circuit board, and electronic instrument|
|US20040217483||30 Abr 2004||4 Nov 2004||Infineon Technologies Ag||Semiconductor device and method for fabricating the semiconductor device|
|US20040222508||16 Mar 2004||11 Nov 2004||Akiyoshi Aoyagi||Semiconductor device, electronic device, electronic apparatus, method of manufacturing semiconductor device, and method of manufacturing electronic device|
|US20040251525||16 Jun 2003||16 Dic 2004||Shellcase Ltd.||Methods and apparatus for packaging integrated circuit devices|
|US20040259292||2 Abr 2004||23 Dic 2004||Eric Beyne||Method for producing electrical through hole interconnects and devices made thereof|
|US20050012225||24 May 2004||20 Ene 2005||Choi Seung-Yong||Wafer-level chip scale package and method for fabricating and using the same|
|US20050046002||15 Jul 2004||3 Mar 2005||Kang-Wook Lee||Chip stack package and manufacturing method thereof|
|US20050051883||8 Jun 2004||10 Mar 2005||Seiko Epson Corporation||Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument|
|US20050056903||24 Ago 2004||17 Mar 2005||Satoshi Yamamoto||Semiconductor package and method of manufacturing same|
|US20050106845||16 Dic 2004||19 May 2005||Halahan Patrick B.||Semiconductor structures having multiple conductive layers in an opening, and methods for fabricating same|
|US20050156330||21 Ene 2004||21 Jul 2005||Harris James M.||Through-wafer contact to bonding pad|
|US20050248002||7 May 2004||10 Nov 2005||Michael Newman||Fill for large volume vias|
|US20050260794||21 Jun 2005||24 Nov 2005||Industrial Technology Research Institute||Method for fabrication of wafer level package incorporating dual compliant layers|
|US20050279916||3 May 2005||22 Dic 2005||Tessera, Inc.||Image sensor package and fabrication method|
|US20050282374||2 Jun 2005||22 Dic 2005||Samsung Electronics Co., Ltd.||Method of forming a thin wafer stack for a wafer level package|
|US20050287783||29 Jun 2004||29 Dic 2005||Kirby Kyle K||Microelectronic devices and methods for forming interconnects in microelectronic devices|
|US20060001174||29 Jun 2005||5 Ene 2006||Nec Electronics Corporation||Semiconductor device and method for manufacturing the same|
|US20060017161||22 Jul 2005||26 Ene 2006||Jae-Sik Chung||Semiconductor package having protective layer for re-routing lines and method of manufacturing the same|
|US20060043598||31 Ago 2004||2 Mar 2006||Kirby Kyle K||Methods of manufacture of a via structure comprising a plurality of conductive elements, semiconductor die, multichip module, and system including same|
|US20060046348||29 Dic 2004||2 Mar 2006||Kang Byoung Y||Semiconductor chip packages and methods for fabricating the same|
|US20060046463||27 May 2005||2 Mar 2006||Watkins Charles M||Method of forming vias in semiconductor substrates without damaging active regions thereof and resulting structures|
|US20060046471||27 Ago 2004||2 Mar 2006||Kirby Kyle K||Methods for forming vias of varying lateral dimensions and semiconductor components and assemblies including same|
|US20060068580||16 Sep 2005||30 Mar 2006||Sharp Kabushiki Kaisha||Semiconductor device and fabrication method thereof|
|US20060071347||28 Sep 2005||6 Abr 2006||Sharp Kabushiki Kaisha||Semiconductor device and fabrication method thereof|
|US20060076019||4 Oct 2005||13 Abr 2006||Ric Investments, Llc.||User interface having a pivotable coupling|
|US20060079019||7 Oct 2005||13 Abr 2006||Easetech Korea Co., Ltd.||Method for manufacturing wafer level chip scale package using redistribution substrate|
|US20060094231||28 Oct 2004||4 May 2006||Lane Ralph L||Method of creating a tapered via using a receding mask and resulting structure|
|US20060115932||17 Ene 2006||1 Jun 2006||Farnworth Warren M||Method for fabricating semiconductor components with conductive vias|
|US20060175697||1 Feb 2006||10 Ago 2006||Tetsuya Kurosawa||Semiconductor device having semiconductor chips stacked and mounted thereon and manufacturing method thereof|
|US20060197216||6 Dic 2005||7 Sep 2006||Advanced Semiconductor Engineering, Inc.||Semiconductor package structure and method for manufacturing the same|
|US20060197217||6 Dic 2005||7 Sep 2006||Advanced Semiconductor Engineering, Inc.||Semiconductor package structure and method for manufacturing the same|
|US20060264029||23 May 2005||23 Nov 2006||Intel Corporation||Low inductance via structures|
|US20060278898||23 Jul 2004||14 Dic 2006||Katusmi Shibayama||Backside-illuminated photodetector and method for manufacturing same|
|US20060278997||21 Nov 2005||14 Dic 2006||Tessera, Inc.||Soldered assemblies and methods of making the same|
|US20060292866||23 Jun 2005||28 Dic 2006||Borwick Robert L||Low temperature method for fabricating high-aspect ratio vias and devices fabricated by said method|
|US20070035020||16 Dic 2005||15 Feb 2007||Sanyo Electric Co., Ltd.||Semiconductor Apparatus and Semiconductor Module|
|US20070052050||7 Sep 2005||8 Mar 2007||Bart Dierickx||Backside thinned image sensor with integrated lens stack|
|US20070096295 *||19 Dic 2006||3 May 2007||Tessera, Inc.||Back-face and edge interconnects for lidded package|
|US20070126085||21 Nov 2006||7 Jun 2007||Nec Electronics Corporation||Semiconductor device and method of manufacturing the same|
|US20070194427||3 Oct 2006||23 Ago 2007||Choi Yun-Seok||Semiconductor package including transformer or antenna|
|US20070231966||20 Mar 2007||4 Oct 2007||Yoshimi Egawa||Semiconductor device fabricating method|
|US20070249095||27 Jun 2007||25 Oct 2007||Samsung Electro-Mechanics Co., Ltd.||Semiconductor package and method of manufacturing the same|
|US20070262464||20 Jul 2007||15 Nov 2007||Micron Technology, Inc.||Method of forming vias in semiconductor substrates and resulting structures|
|US20070269931||22 May 2007||22 Nov 2007||Samsung Electronics Co., Ltd.||Wafer level package and method of fabricating the same|
|US20070290300||2 Abr 2007||20 Dic 2007||Sony Corporation||Semiconductor device and method for manufacturing same|
|US20080002460||27 Feb 2007||3 Ene 2008||Tessera, Inc.||Structure and method of making lidded chips|
|US20080020898 *||29 Ago 2007||24 Ene 2008||Johnson Health Tech Co., Ltd.||Rapid circuit training machine with dual resistance|
|US20080076195||31 Ene 2007||27 Mar 2008||Hymite A/S||Formation of through-wafer electrical interconnections and other structures using a thin dielectric membrane|
|US20080090333||17 Oct 2006||17 Abr 2008||Tessera, Inc.||Microelectronic packages fabricated at the wafer level and methods therefor|
|US20080099900 *||31 Oct 2006||1 May 2008||Tessera Technologies Hungary Kft.||Wafer-level fabrication of lidded chips with electrodeposited dielectric coating|
|US20080099907 *||25 Abr 2007||1 May 2008||Tessera Technologies Hungary Kft.||Wafer-level fabrication of lidded chips with electrodeposited dielectric coating|
|US20080111213||26 Oct 2007||15 May 2008||Micron Technology, Inc.||Through-wafer interconnects for photoimager and memory wafers|
|US20080116544||22 Nov 2006||22 May 2008||Tessera, Inc.||Packaged semiconductor chips with array|
|US20080136038 *||6 Dic 2006||12 Jun 2008||Sergey Savastiouk||Integrated circuits with conductive features in through holes passing through other conductive features and through a semiconductor substrate|
|US20080150089||6 Nov 2007||26 Jun 2008||Yong-Chai Kwon||Semiconductor device having through vias and method of manufacturing the same|
|US20080157273||27 Dic 2007||3 Jul 2008||Stmicroelectronics Sa||Integrated electronic circuit chip comprising an inductor|
|US20080164574||19 Mar 2008||10 Jul 2008||Sergey Savastiouk||Integrated circuits with conductive features in through holes passing through other conductive features and through a semiconductor substrate|
|US20080274589||4 May 2007||6 Nov 2008||Chien-Hsiun Lee||Wafer-level flip-chip assembly methods|
|US20080284041||11 Mar 2008||20 Nov 2008||Samsung Electronics Co., Ltd.||Semiconductor package with through silicon via and related method of fabrication|
|US20090014843||5 Jun 2008||15 Ene 2009||Kawashita Michihiro||Manufacturing process and structure of through silicon via|
|US20090026566||27 Jul 2007||29 Ene 2009||Micron Technology, Inc.||Semiconductor device having backside redistribution layers and method for fabricating the same|
|US20090032951||2 Ago 2007||5 Feb 2009||International Business Machines Corporation||Small Area, Robust Silicon Via Structure and Process|
|US20090032966||31 Jul 2008||5 Feb 2009||Jong Ho Lee||Method of fabricating a 3-D device and device made thereby|
|US20090039491||16 Abr 2008||12 Feb 2009||Samsung Electronics Co., Ltd.||Semiconductor package having buried post in encapsulant and method of manufacturing the same|
|US20090065907||31 Jul 2008||12 Mar 2009||Tessera, Inc.||Semiconductor packaging process using through silicon vias|
|US20090085208||25 Sep 2008||2 Abr 2009||Nec Electronics Corporation||Semiconductor device|
|US20090133254 *||16 Ene 2009||28 May 2009||Tessera, Inc.||Components with posts and pads|
|US20090212381||26 Feb 2009||27 Ago 2009||Tessera, Inc.||Wafer level packages for rear-face illuminated solid state image sensors|
|US20090224372||20 Mar 2008||10 Sep 2009||Advanced Inquiry Systems, Inc.||Wafer translator having a silicon core isolated from signal paths by a ground plane|
|US20090263214||22 Abr 2008||22 Oct 2009||Taiwan Semiconductor Manufacturing Co., Ltd.||Fixture for p-through silicon via assembly|
|US20090267183||28 Abr 2008||29 Oct 2009||Research Triangle Institute||Through-substrate power-conducting via with embedded capacitance|
|US20090309235||11 Jun 2008||17 Dic 2009||Stats Chippac, Ltd.||Method and Apparatus for Wafer Level Integration Using Tapered Vias|
|US20100013060||22 Jul 2009||21 Ene 2010||Taiwan Semiconductor Manufacturing Company, Ltd.||Method of forming a conductive trench in a silicon wafer and silicon wafer comprising such trench|
|US20100127346||21 Nov 2008||27 May 2010||Denatale Jeffrey F||Power distribution for cmos circuits using in-substrate decoupling capacitors and back side metal layers|
|US20100148371||12 Dic 2008||17 Jun 2010||Qualcomm Incorporated||Via First Plus Via Last Technique for IC Interconnects|
|US20100155940||17 Dic 2009||24 Jun 2010||Renesas Technology Corp.||Semiconductor device and method of manufacturing the same|
|US20100159699||17 Dic 2009||24 Jun 2010||Yoshimi Takahashi||Sandblast etching for through semiconductor vias|
|US20100164062||9 Jun 2009||1 Jul 2010||Industrial Technology Research Institute||Method of manufacturing through-silicon-via and through-silicon-via structure|
|US20100167534||11 Mar 2010||1 Jul 2010||Ronald Takao Iwata||Method for fabricating a semiconductor chip device having through-silicon-via (tsv)|
|US20100230795 *||12 Mar 2010||16 Sep 2010||Tessera Technologies Hungary Kft.||Stacked microelectronic assemblies having vias extending through bond pads|
|US20120018895||23 Jul 2010||26 Ene 2012||Tessera Research Llc||Active chip on carrier or laminated chip having microelectronic element embedded therein|
|US20120068352||16 Sep 2010||22 Mar 2012||Tessera Research Llc||Stacked chip assembly having vertical vias|
|EP0316799A1||11 Nov 1988||24 May 1989||Nissan Motor Co., Ltd.||Semiconductor device|
|EP0926723B1||26 Nov 1997||17 Ene 2007||SGS-THOMSON MICROELECTRONICS S.r.l.||Process for forming front-back through contacts in micro-integrated electronic devices|
|EP1482553A2||26 May 2004||1 Dic 2004||Sanyo Electric Co., Ltd.||Semiconductor device and manufacturing method thereof|
|EP1519410A1||25 Sep 2003||30 Mar 2005||Interuniversitair Microelektronica Centrum vzw ( IMEC)||Method for producing electrical through hole interconnects and devices made thereof|
|EP1551060A1||24 Sep 2003||6 Jul 2005||Hamamatsu Photonics K. K.||Photodiode array and method for manufacturing same|
|EP1619722B1||14 Abr 2004||13 Ago 2008||Hamamatsu Photonics K. K.||Method for manufacturing backside-illuminated optical sensor|
|EP1653510A2||28 Oct 2005||3 May 2006||Sanyo Electric Co., Ltd.||Semiconductor device and manufacturing method of the same|
|EP1653521A1||23 Jul 2004||3 May 2006||Hamamatsu Photonics K.K.||Backside-illuminated photodetector and method for manufacturing same|
|EP1686627A1||8 Dic 2005||2 Ago 2006||Samsung Electro-Mechanics Co., Ltd.||Semiconductor package and method of manufacturing the same|
|JP60160645U||Título no disponible|
|JP2001085559A||Título no disponible|
|JP2001217386A||Título no disponible|
|JP2002217331A||Título no disponible|
|JP2004200547A||Título no disponible|
|JP2005026405A||Título no disponible|
|JP2005093486A||Título no disponible|
|JP2005101268A||Título no disponible|
|JP2007053149A||Título no disponible|
|JP2007157844A||Título no disponible|
|JP2007317887A||Título no disponible|
|JP2008091632A||Título no disponible|
|JP2008177249A||Título no disponible|
|JP2008258258A||Título no disponible|
|JP2010028601A||Título no disponible|
|JPH1116949A||Título no disponible|
|JPH11195706A||Título no disponible|
|KR100750741B1||Título no disponible|
|KR19990088037A||Título no disponible|
|KR20040066018A||Título no disponible|
|KR20060009407A||Título no disponible|
|KR20060020822A||Título no disponible|
|KR20070065241A||Título no disponible|
|KR20100087566A||Título no disponible|
|TW200406884A||Título no disponible|
|TW200522274A||Título no disponible|
|TW200535435A||Título no disponible|
|WO2004114397A1||11 Jun 2004||29 Dic 2004||Koninklijke Philips Electronics N.V.||Electronic device, assembly and methods of manufacturing an electronic device|
|WO2008054660A2||23 Oct 2007||8 May 2008||Tessera Technologies Hungary Kft.||Wafer-level fabrication of lidded chips with electrodeposited dielectric coating|
|WO2009023462A1||4 Ago 2008||19 Feb 2009||Spansion Llc||Semiconductor device and method for manufacturing thereof|
|WO2009104668A1||19 Feb 2009||27 Ago 2009||日本電気株式会社||Wiring board and semiconductor device|
|1||International Search Report and Written Opinion for Application No. PCT/US2011/029394 dated Jun. 6, 2012.|
|2||International Search Report and Written Opinion for PCT/US2011/051552 dated Apr. 11, 2012.|
|3||International Search Report and Written Opinion for PCT/US2011/051556 dated Feb. 13, 2012.|
|4||International Search Report and Written Opinion, PCT/US2010/052458, dated Jan. 31, 2011.|
|5||International Search Report and Written Opinion, PCT/US2010/052785, Dated Dec. 20, 2010.|
|6||International Search Report, PCT/US10/52783, Dated Dec. 10, 2010.|
|7||International Search Report, PCT/US2008/002659, filed Oct. 9, 2008.|
|8||International Search Report, PCT/US2008/002659, Oct. 9, 2008.|
|9||International Searching Authority, Search Report for Application No. PCT/US2011/060553 dated Jun. 27, 2012.|
|10||Japanese Office Action for Application No. 2009-552696 dated Aug. 14, 2012.|
|11||Partial International Search Report for Application No. PCT/US2011/063653 dated Jul. 9, 2012.|
|12||Supplementary European Search Report, EP 08795005 dated Jul. 5, 2010.|
|13||Taiwan Office Action for Application No. 100113585 dated Jun. 5, 2012.|
|14||U.S. Appl. No. 11/590,616, filed Oct. 31, 2006.|
|15||U.S. Appl. No. 11/789,694, filed Apr. 25, 2007.|
|16||U.S. Appl. No. 12/143,743, "Recontituted Wafer Level Stacking", filed Jun. 20, 2008.|
|17||U.S. Appl. No. 12/842,612, filed Jul. 23, 2010.|
|18||U.S. Appl. No. 12/842,717, filed Jul. 23, 2010.|
|19||U.S. Application No. 12/784,841, filed May 21, 2010.|
|20||U.S. Application No. 12/842,651, filed Jul. 23, 2010.|
|Patente citante||Fecha de presentación||Fecha de publicación||Solicitante||Título|
|US8604576 *||19 Jul 2011||10 Dic 2013||Opitz, Inc.||Low stress cavity package for back side illuminated image sensor, and method of making same|
|US8735205 *||8 Nov 2012||27 May 2014||Invensas Corporation||Chips having rear contacts connected by through vias to front contacts|
|US8735287||5 Jun 2012||27 May 2014||Invensas Corp.||Semiconductor packaging process using through silicon vias|
|US8796135||23 Jul 2010||5 Ago 2014||Tessera, Inc.||Microelectronic elements with rear contacts connected with via first or via middle structures|
|US8796828||12 Dic 2013||5 Ago 2014||Tessera, Inc.||Compliant interconnects in wafers|
|US8809190||12 Dic 2013||19 Ago 2014||Tessera, Inc.||Multi-function and shielded 3D interconnects|
|US8847380||17 Sep 2010||30 Sep 2014||Tessera, Inc.||Staged via formation from both sides of chip|
|US8895344 *||14 Nov 2013||25 Nov 2014||Optiz, Inc.||Method of making a low stress cavity package for back side illuminated image sensor|
|US8952519 *||15 Jun 2010||10 Feb 2015||Chia-Sheng Lin||Chip package and fabrication method thereof|
|US8975751||22 Abr 2011||10 Mar 2015||Tessera, Inc.||Vias in porous substrates|
|US9070678||11 Feb 2014||30 Jun 2015||Tessera, Inc.||Packaged semiconductor chips with array|
|US9099296||23 Oct 2013||4 Ago 2015||Tessera, Inc.||Stacked microelectronic assembly with TSVS formed in stages with plural active chips|
|US9224649||4 Ago 2014||29 Dic 2015||Tessera, Inc.||Compliant interconnects in wafers|
|US9269692||25 Mar 2014||23 Feb 2016||Tessera, Inc.||Stacked microelectronic assembly with TSVS formed in stages and carrier above chip|
|US9355948||24 Jul 2014||31 May 2016||Tessera, Inc.||Multi-function and shielded 3D interconnects|
|US9362203||27 Sep 2014||7 Jun 2016||Tessera, Inc.||Staged via formation from both sides of chip|
|US9368476||28 Jul 2015||14 Jun 2016||Tessera, Inc.||Stacked microelectronic assembly with TSVs formed in stages with plural active chips|
|US9433100||19 Mar 2014||30 Ago 2016||Tessera, Inc.||Low-stress TSV design using conductive particles|
|US9455181||30 Ene 2015||27 Sep 2016||Tessera, Inc.||Vias in porous substrates|
|US9548254||29 Jun 2015||17 Ene 2017||Tessera, Inc.||Packaged semiconductor chips with array|
|US9620437||18 Feb 2016||11 Abr 2017||Tessera, Inc.||Stacked microelectronic assembly with TSVS formed in stages and carrier above chip|
|US9640437||23 Jul 2010||2 May 2017||Tessera, Inc.||Methods of forming semiconductor elements using micro-abrasive particle stream|
|US9667900||26 Nov 2014||30 May 2017||Optiz, Inc.||Three dimensional system-on-chip image sensor package|
|US20110169159 *||15 Jun 2010||14 Jul 2011||Chia-Sheng Lin||Chip package and fabrication method thereof|
|US20130020665 *||19 Jul 2011||24 Ene 2013||Vage Oganesian||Low Stress Cavity Package For Back Side Illuminated Image Sensor, And Method Of Making Same|
|US20130065390 *||8 Nov 2012||14 Mar 2013||DigitalOptics Corporation Europe Limited||Chips having rear contacts connected by through vias to front contacts|
|US20140065755 *||14 Nov 2013||6 Mar 2014||Optiz, Inc.||Method Of Making A Low Stress Cavity Package For Back Side Illuminated Image Sensor|
|US20170110641 *||29 Dic 2016||20 Abr 2017||Xintec Inc.||Semiconductor package and manufacturing method thereof|
|Clasificación de EE.UU.||257/686, 257/723, 257/E21.597, 257/E23.167, 257/E23.021, 257/E21.506|
|Clasificación cooperativa||H01L2224/05571, H01L2224/05169, H01L2224/05655, H01L2224/05647, H01L2224/05644, H01L2224/05164, H01L2224/05166, H01L2224/05155, H01L2224/05184, H01L2224/05124, H01L2224/05147, H01L2224/05181, H01L2224/05001, H01L2224/0557, H01L2224/05026, H01L2224/05022, H01L2224/05008, H01L2224/13, H01L2924/12042, H01L2924/07811, H01L2924/01029, H01L2924/01082, H01L2924/19041, H01L2924/014, H04N5/2257, H01L2924/01073, H01L23/3128, H01L2924/01047, H01L2924/01005, H01L2924/01322, H01L2924/01079, H01L2924/01015, H01L2924/30107, H01L2924/01078, H01L2924/01074, H01L2924/01006, H01L2924/01046, H01L2924/01033, H01L27/14618, H01L27/14683, H01L24/10, H01L2224/13099, H01L2924/01013, H01L2924/3025, H01L2924/01022, H01L2924/12044, H01L2924/01027, H01L29/0657, H01L23/481, H01L24/13|
|10 Sep 2008||AS||Assignment|
Owner name: TESSERA, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HABA, BELGACEM;HONER, KENNETH ALLEN;TUCKERMAN, DAVID B.;AND OTHERS;REEL/FRAME:021513/0144;SIGNING DATES FROM 20080424 TO 20080909
Owner name: TESSERA, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HABA, BELGACEM;HONER, KENNETH ALLEN;TUCKERMAN, DAVID B.;AND OTHERS;SIGNING DATES FROM 20080424 TO 20080909;REEL/FRAME:021513/0144
|31 Mar 2011||AS||Assignment|
Owner name: TESSERA TECHNOLOGIES IRELAND LIMITED, IRELAND
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TESSERA, INC.;REEL/FRAME:026110/0370
Effective date: 20110325
|4 May 2012||AS||Assignment|
Owner name: DIGITALOPTICS CORPORATION EUROPE LIMITED, IRELAND
Free format text: CHANGE OF NAME;ASSIGNOR:TESSERA TECHNOLOGIES IRELAND LIMITED;REEL/FRAME:028170/0196
Effective date: 20110713
|20 Mar 2013||AS||Assignment|
Owner name: INVENSAS CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:DIGITAL OPTICS CORPORATION EUROPE LIMITED;REEL/FRAME:030065/0817
Effective date: 20130318
Owner name: INVENSAS CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:DIGITALOPTICS CORPORATION EUROPE LIMITED;REEL/FRAME:030065/0817
Effective date: 20130318
|4 Nov 2016||REMI||Maintenance fee reminder mailed|
|2 Dic 2016||AS||Assignment|
Owner name: ROYAL BANK OF CANADA, AS COLLATERAL AGENT, CANADA
Free format text: SECURITY INTEREST;ASSIGNORS:INVENSAS CORPORATION;TESSERA, INC.;TESSERA ADVANCED TECHNOLOGIES, INC.;AND OTHERS;REEL/FRAME:040797/0001
Effective date: 20161201
|26 Mar 2017||LAPS||Lapse for failure to pay maintenance fees|
|16 May 2017||FP||Expired due to failure to pay maintenance fee|
Effective date: 20170326