US8524398B2 - All-electron battery having area-enhanced electrodes - Google Patents

All-electron battery having area-enhanced electrodes Download PDF

Info

Publication number
US8524398B2
US8524398B2 US12/798,102 US79810210A US8524398B2 US 8524398 B2 US8524398 B2 US 8524398B2 US 79810210 A US79810210 A US 79810210A US 8524398 B2 US8524398 B2 US 8524398B2
Authority
US
United States
Prior art keywords
inclusions
electrodes
dielectric structure
area
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US12/798,102
Other versions
US20100255381A1 (en
Inventor
Timothy P. Holme
Friedrich B. Prinz
Takane Usui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Leland Stanford Junior University
Original Assignee
Leland Stanford Junior University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Leland Stanford Junior University filed Critical Leland Stanford Junior University
Priority to US12/798,102 priority Critical patent/US8524398B2/en
Assigned to BOARD OF TRUSTEES OF THE LELAND STANFORD JUNIOR UNIVERSITY, THE reassignment BOARD OF TRUSTEES OF THE LELAND STANFORD JUNIOR UNIVERSITY, THE ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HOLME, TIMOTHY P., PRINZ, FRIEDRICH B., USUI, TAKANE
Publication of US20100255381A1 publication Critical patent/US20100255381A1/en
Priority to US12/928,346 priority patent/US8877367B2/en
Application granted granted Critical
Publication of US8524398B2 publication Critical patent/US8524398B2/en
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/33Thin- or thick-film capacitors 
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G11/00Hybrid capacitors, i.e. capacitors having different positive and negative electrodes; Electric double-layer [EDL] capacitors; Processes for the manufacture thereof or of parts thereof
    • H01G11/22Electrodes
    • H01G11/26Electrodes characterised by their structure, e.g. multi-layered, porosity or surface features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G9/00Electrolytic capacitors, rectifiers, detectors, switching devices, light-sensitive or temperature-sensitive devices; Processes of their manufacture
    • H01G9/004Details
    • H01G9/04Electrodes or formation of dielectric layers thereon
    • H01G9/048Electrodes or formation of dielectric layers thereon characterised by their structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G9/00Electrolytic capacitors, rectifiers, detectors, switching devices, light-sensitive or temperature-sensitive devices; Processes of their manufacture
    • H01G9/004Details
    • H01G9/04Electrodes or formation of dielectric layers thereon
    • H01G9/048Electrodes or formation of dielectric layers thereon characterised by their structure
    • H01G9/055Etched foil electrodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/82Electrodes with an enlarged surface, e.g. formed by texturisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/82Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/13Energy storage using capacitors

Definitions

  • This invention relates to energy storage.
  • Energy storage is a crucial component of a large number and variety of electronic devices, particularly for mobile devices and vehicles.
  • Energy storage devices have been based on a wide variety of physical effects. For example, electric fields can be employed to store energy in capacitors, and chemical reactions (involving ion motion) can be employed to store energy in batteries.
  • energy storage in a capacitor can be limited by the device geometry (e.g., 2-D capacitor plates having limited area), and batteries can have a slow response time due to the ion motion inherent in electrochemical reactions.
  • Battery powered devices such as hybrid or electric vehicles are often limited in performance by the low energy stored per weight in batteries. Batteries have low storage density due to the large size and weight of the ions stored in the batteries. Slow ion transport in batteries also causes slow charge and discharge performance. Furthermore, the reliance of existing batteries on ionic transport causes high degradation rates of the batteries.
  • the first effect can be referred to as the All-Electron Battery (AEB) effect, and relates to the use of inclusions embedded in a dielectric structure between two electrodes of a capacitor. Electrons can tunnel through the dielectric between the electrodes and the inclusions, thereby increasing the charge storage density relative to a conventional capacitor.
  • the second effect can be referred to as an area enhancement effect, and relates to the use of micro-structuring or nano-structuring on one or both of the electrodes to provide an enhanced interface area relative to the electrode geometrical area. Area enhancement is advantageous for reducing the self-discharge rate of the device.
  • Applications include electric vehicle energy storage (EV or PHEV battery), portable electronics (laptop, cell phone, etc.), and troop gear/weapons, where the advantages include high energy density storage (possibly greater than 250 Whr/kg), high power density storage ( ⁇ 10 8 W/kg), fast charge/discharge rate, and low degradation over time because there are no chemical reactions. Further advantages include no moving atoms/ions, and no risk of catastrophic, unsafe failure.
  • EV electric vehicle energy storage
  • portable electronics laptop, cell phone, etc.
  • troop gear/weapons where the advantages include high energy density storage (possibly greater than 250 Whr/kg), high power density storage ( ⁇ 10 8 W/kg), fast charge/discharge rate, and low degradation over time because there are no chemical reactions. Further advantages include no moving atoms/ions, and no risk of catastrophic, unsafe failure.
  • the present approach relates to a capacitor and an electron battery having very high storage density. Because the present approach relies on electrical energy stored as electrons instead of ions, small and light devices with high storage capacities are provided. Furthermore, electron transport allows for fast charge and discharge. The present solid-state devices can also have improved lifetime relative to existing energy storage devices. In this approach, energy storage is via electrons in bulk, as opposed to surface charges (e.g., conventional capacitors) or ions (e.g., batteries).
  • FIG. 1 shows an embodiment of the invention.
  • FIG. 2 shows another embodiment of the invention.
  • FIG. 3 shows a further embodiment of the invention.
  • FIG. 4 shows a detail view of an embodiment of the invention.
  • FIG. 5 shows several kinds of inclusion suitable for use in embodiments of the invention.
  • FIGS. 6 a - b shows examples of the use of inclusions of different size in connection with embodiments of the invention.
  • FIGS. 7 a - e show a first fabrication sequence for an embodiment of the invention.
  • FIGS. 8 a - b show final steps of a second fabrication sequence for an embodiment of the invention.
  • FIG. 9 shows the final step of a third fabrication sequence for an embodiment of the invention.
  • FIG. 10 a shows a control structure for experiments relating to principles of the invention.
  • FIG. 10 b shows I-V data for the control structure of FIG. 10 a.
  • FIG. 11 a shows a test structure relating to principles of the invention.
  • FIGS. 11 b - f show experimental data from the test structure of FIG. 11 a.
  • FIG. 1 shows an embodiment of the invention.
  • an electrode 106 includes micro-structured or nano-structured features, one of which is referenced as 108 . These electrode features provide an increased interfacial area (i.e., active area) relative to the electrode geometrical area.
  • An insulating layer 104 is disposed on top of electrode 106 . Inclusions are disposed on top of insulating layers 104 . One of these inclusions is referenced as 110 . The inclusions are surrounded by insulating layers, one of which is referenced as 112 .
  • a second electrode 102 is disposed such that a dielectric structure is disposed between the electrodes. In this example, the dielectric structure includes layers 104 and 112 . The inclusions are disposed in this dielectric structure.
  • the inclusions are capable of transferring electrons to or from at least one of the electrodes by tunneling through the dielectric structure.
  • Energy can be stored by establishing a charge separation between the inclusions, and energy can be provided by using this charge separation as an energy source.
  • FIGS. 2 and 3 show some alternative geometrical possibilities. More specifically, the example of FIG. 2 is like the example of FIG. 1 , except that the interdigitated electrode 102 of FIG. 1 is replaced with a planar electrode 204 on FIG. 2 , and the dielectric structure of FIG. 2 includes a dielectric filler region 202 .
  • the example of FIG. 3 is like the example of FIG. 2 , except that the top electrode 302 on FIG. 3 is nanostructured and there are also inclusions near this electrode. Several layers of inclusions surrounded by dielectric layers may be disposed on top of one or both electrodes.
  • the point of micro-structuring or nano-structuring one or both electrodes of the device is to provide an electrode area enhancement.
  • NiSi nanowires on the electrodes to increase the interfacial area, although it is understood that any conductive material would suffice.
  • the NiSi nanowire growth process is well understood and can produce an area enhancement factor of a ⁇ 50-100.
  • nanostructured electrodes An advantage of nanostructured electrodes is that it will bring down cost, since the cost of fabricating the AEB scales with the geometric area deposited, but with nanostructured electrodes, the energy density per geometric area will be higher by a factor of a.
  • the area enhancement factor is 1.5 or more. More preferably, this factor is 5 or more, and still more preferably, this factor is 10 or more.
  • Another advantage of using nanostructured electrodes is that the self-discharge rate will be lower by a factor that scales exponentially with a.
  • the AEB is inherently suited for delivering high power density, since thin tunneling layers permit fast charge/discharge.
  • a naively engineered AEB would suffer from unreasonably high rates of self-discharge for the same reason.
  • the product a ⁇ must be greater than 10 18 ⁇ m.
  • the resistivity of insulators such as SiO 2 is approximately 10 14 ⁇ m, we conclude that ac must be greater than 10000.
  • must be at least 10 2 . Permittivity values this high or higher are readily attainable, whereas a permittivity of 10 4 or more is difficult to obtain and tends to occur only in materials with other disadvantageous properties such as low breakdown strength, low temperature tolerance, and low energy density.
  • Atomic layer deposition is well suited to coat high aspect ratio structures and complex geometries, whereas PVD techniques tend to be limited by line-of-sight deposition. Therefore, chemical vapor deposition techniques such as ALD are the preferred deposition mechanism for the layer of dielectric that interfaces with microstructured electrodes.
  • a noteworthy feature of the present device is that it tends to be large compared to microelectronic switching devices, such as transistors, although still small relative to conventional batteries. Such size follows from its purpose of storing energy.
  • the electrodes each have a geometrical area of 1 ⁇ m 2 or greater.
  • Another typical feature of embodiments of the invention is operation at relatively high voltages.
  • charge separation between the inclusions is established by application of a voltage of 5V or more between the electrodes.
  • AEBs are preferably two terminal devices, where the only external device terminals are the electrodes on either side of the dielectric structure.
  • Embodiments of the invention can provide high charge storage density. To quantify this point, it is convenient to define the volume averaged charge separation density as follows: In a charged device having N extra electrons near one of its terminals and N missing electrons (e.g. holes) near the other terminal, and a volume between the terminals of V, the volume averaged charge separation density is N/V. Preferably, the volume averaged charge separation density can be 10 ⁇ 4 e ⁇ /nm 3 or greater when a charge separation is present between the inclusions (i.e., when the AEB is in an energy storing state).
  • Important design parameters for AEBs include some or all of the following parameters: electrode area enhancement factors, the spacing between electrodes and inclusions, the spacing between inclusions, the size, shape, and number density of inclusions, the tunneling energy barrier between electrodes and inclusions, the tunneling energy barrier between inclusions, dielectric constants, and work functions.
  • the charge and discharge rates and storage capacities of the devices can be selected by appropriate geometrical design and material choice. Charge and discharge rates depend on the gaps between inclusions and the dielectric constant of the dielectric material, therefore the rates can be altered by changing the distances between inclusions, and/or the dielectric constant. Charge and discharge rates further depend upon the electron affinity of the dielectric material and of the inclusions.
  • FIG. 4 shows a detail view of an embodiment of the invention.
  • the inclusions are organized as functional layers disposed in or on the dielectric structure. More specifically, functional layers 402 and 406 are disposed near a micro-structured electrode 106 , and functional layers 424 and 428 are disposed near a planar electrode 204 . Insulating layers 422 and 104 separate functional layers 424 and 402 from electrodes 204 and 106 respectively. An insulating barrier layer 426 is disposed between functional layers 424 and 428 . An insulating barrier layer 404 is disposed between functional layers 402 and 406 .
  • the dielectric structure in this example includes multiple dielectric layers (i.e., layers 104 , 404 , 202 , 422 , and 426 ).
  • Functional layers can be metallic or be semiconductors and can contain embedded inclusions having an electron affinity that is higher than the electron affinity of the dielectric structure.
  • the inclusions can be arranged to provide a work function gradient for the inclusions, e.g., by providing an inclusion size and/or material composition gradient.
  • the functional layers can include different materials having different work functions, and can be disposed to form a Fermi level gradient.
  • the functional layers can include one or more materials having an electron affinity that is lower than an electron affinity of part or all of the dielectric structure.
  • This example includes, as a preferred feature, vertical stacking of inclusions.
  • Each of the functional layers is capable of storing an amount of charge by itself, therefore the device with functional layers is capable of storing a larger amount of charge. Since the voltage of these functional layers stacked in series is additive, and the energy density scales with the square of the voltage, a substantially higher energy density can be achieved.
  • an energy storage device has inclusions of varying sizes.
  • large inclusions are placed near one electrode and smaller inclusions are placed near an opposing electrode.
  • Charge is preferentially stored in the larger inclusions.
  • the gradient in the size distribution allows polarization of the inclusions, even when the cell is neutral (e.g., a larger inclusion can be polarized due to its proximity to a smaller inclusion).
  • the excess charge is preferentially contained in the larger inclusion, thereby increasing the stored charge.
  • the inclusions can have a wide range of sizes.
  • the larger inclusions can be nanowires, quantum wells, and/or bulk inclusions, while the smaller inclusions can be as small as an individual atom.
  • the inclusions are made of different materials.
  • a first inclusion can be made from a material with a greater work function than a second inclusion. Electron transfer results from the Fermi level difference between materials in proximity, so a greater polarization can be achieved with a greater difference in Fermi level.
  • a size gradient is employed. Inclusions in functional layer 402 , one of which is referenced as 412 , are larger than inclusions in functional layer 406 (one of which is referenced as 416 ). Similarly, inclusions in functional layer 428 , one of which is referenced as 438 , are larger than inclusions in functional layer 424 (one of which is referenced as 434 ). These size gradients provide a continuous change in work function across functional layers 424 and 428 , and across functional layers 402 and 406 because work function decreases as size decreases for quantum-confined inclusions.
  • the thickness of functional layers 402 , 406 , 428 and 424 is preferably in a range from 0.3 nm to 300 ⁇ m.
  • Dielectric filler layer 202 preferably has a thickness in a range of 1 nm to 500 ⁇ m and having a relatively high electron affinity, relatively high bandgap and relatively high breakdown voltage.
  • the bandgap of layer 202 may be above 1 eV and is preferably above 4 eV.
  • the breakdown field for layer 202 is preferably above 1 MV/cm and more preferably above 3 MV/cm.
  • Electrode 204 preferably has a relatively small work function ⁇ s (i.e., ⁇ s below 4 eV and more preferably below 3 eV).
  • Some exemplary materials useful for electrode 204 include but are not limited to: Zn, Li, Na, Mg, K, Ca, Rb, Sr, Ba, Cs, doped diamond and Y.
  • Electrode 106 is micro-structured as described above and has a relatively large work function ⁇ l (i.e., ⁇ l above 4.5 eV and more preferably above 5.5 eV).
  • Some exemplary materials useful for electrode 106 include but are not limited to: Au, Pt, W, Al, Cu, Ag, Ti, Se, Ge, Pd, Ni, Co, Rh, Ir and Os.
  • Inclusion size gradients are highly polarizable using high density of state (DOS) materials including but not limited to: Ni, Pt, Cu, Ag, Au and Ir as inclusion materials. Inclusions are preferably chemically stable in the dielectric structure material (e.g. doesn't oxidize if the matrix material is an oxide).
  • DOS high density of state
  • Some examples of materials useful for the dielectric layers include, but are not limited to: Al 2 O 3 , Si, TiO 2 , Ti-nitride, Ti-oxynitride, Ge, ZnO, ZrO 2 , HfO 2 , SiO 2 , Si 3 N 4 , Y 2 O 3 , BaTiO 3 , SrO, SrTiO 3 , and mixtures or combinations thereof.
  • Materials useful for the inclusions include metals such as Pt, Au, Ni, Ag, W, Ti, Al, Cu, Pd, Cs, Li, Na, K, Y, Sr and Ba. Further examples of materials useful for the inclusions include low bandgap semiconductors such as PbSe, PbS, ZnS, CdSe, CdS, ZnSe, Ge, Si, Sn and conductive oxides such as RuO 2 .
  • Insulating layer 202 can be made from materials including but not limited to: ZnS, TiO 2 , Al 2 O 3 , ZrO 2 , Y 2 O 3 , HfO 2 , Si 3 N 4 , SiO 2 , other oxides, nitrides, sulfides, and selenides.
  • FIG. 5 shows several kinds of inclusion suitable for use in embodiments of the invention. More specifically, inclusions can be bulk materials, or they can be quantum confined in one dimension (quantum well 506 ), two dimensions (quantum wire 504 ), and/or three dimensions (quantum dot 502 ).
  • the size below which quantum confinement effects become significant depends on the material, but it is typically about 2-10 nm in metals and about 5-40 nm in semiconductors. Thus metallic inclusions having size greater than 10 nm in all three dimensions are likely to effectively have bulk material properties. Similarly, semiconductor inclusions having size greater than 40 nm in all three dimensions are likely to effectively have bulk material properties.
  • quantum dot inclusions e.g., metal dots having all dimensions 10 nm or less and/or semiconductor dots having all dimensions 40 nm or less, as in the preceding examples, is preferred but not required.
  • FIGS. 6 a - b shows examples of the use of inclusions of different size in connection with embodiments of the invention.
  • a relatively large inclusion 604 is surrounded by smaller inclusions 602 .
  • a relatively small inclusion 606 is surrounded by larger inclusions 602 .
  • size gradients allow for the creation of helpful work function gradients in AEBs.
  • FIGS. 7 a - e show a first fabrication sequence for an embodiment of the invention.
  • FIG. 7 a shows the results of the first step of this example, which is formation of vertical metal nanowires (one of which is referenced as 108 ) on electrode 106 .
  • Suitable fabrication methods include, but are not limited to: Vapor-Liquid-Solid (VLS) growth techniques, optical and/or e-beam lithography, nanosphere lithography, and electroplating through a porous membrane (e.g., a polycarbonate track-etched membrane).
  • VLS techniques start with a solid catalyst particle and a vapor reactant. The vapor lands on the solid, diffuses through it, and forms a solid beneath the catalyst particle, resulting in a wire of diameter approximately equal to the catalyst diameter.
  • FIG. 7 b shows the result of the second step of this example, which is deposition of an insulating layer 104 .
  • Any insulator deposition method can be employed, although chemical vapor deposition is preferred as indicated above.
  • FIG. 7 c shows the result of the third step of this example, which is deposition of quantum dots, one of which is referenced as 110 .
  • Any quantum dot deposition technique can be employed, including but not limited to vapor deposition, self-assembly, and processing of colloidal quantum dots.
  • the second and third steps can be repeated one or more times to form a multi-layered structure (e.g., as in the example of FIG. 4 ).
  • FIG. 7 d shows the result of the fourth step of this example, which is deposition of an insulating passivation layer on top of the quantum dots, part of which is referenced as 112 .
  • Any insulator deposition method can be employed, although chemical vapor deposition is preferred as indicated above.
  • FIG. 7 e shows the result of the fifth step of this example, which is deposition of metal to form an interdigitated top electrode 102 .
  • Any metal deposition method can be employed, including but not limited to: vapor phase deposition and electroless plating.
  • FIGS. 8 a - b show final steps of a second fabrication sequence for an embodiment of the invention.
  • the first four steps are as described in connection with FIGS. 7 a - d .
  • FIG. 8 a shows the result of the fifth step of this example, which is deposition of a dielectric filler region 202 on the structure of FIG. 7 d .
  • Any insulator deposition method can be employed, although chemical vapor deposition is preferred as indicated above.
  • the steps of FIGS. 7 d and 8 a can be combined into a single insulator deposition step.
  • FIG. 8 b shows the result of the sixth step of this example, which is deposition of an electrode 204 on top of the dielectric filler region 202 . Any method for depositing metal electrodes on an insulator can be employed.
  • FIG. 9 shows the final step of a third fabrication sequence for an embodiment of the invention.
  • the first five steps are as described in connection with FIGS. 7 a - d and 8 a .
  • FIG. 9 shows the result of the sixth step of this example, which is performing insulator to insulator bonding of two structures as in FIG. 8 a along a bond line 902 to provide an AEB having two nano-structured electrodes.
  • Suitable bonding methods include but are not limited to: sintering, heat treatment with a low melting point metal (which can be regarded as analogous to low temperature soldering), and vapor phase deposition.
  • FIG. 10 a shows a control structure for experiments relating to principles of the invention.
  • a voltage source 1002 provides input to a control sample via a Pt/Ir Atomic Force Microscope (AFM) tip 1004 .
  • the control sample includes a quartz substrate 1018 , a Cr layer 1016 and a Pt layer 1014 which together form the bottom electrode of this sample, a 10 nm thick ZrO 2 insulating layer 1012 , a 10 nm thick conductive Pt layer 1010 , a 10 nm thick ZrO 2 insulating layer 1008 , and a Pt top electrode 1006 .
  • This control structure is basically two capacitors in series.
  • FIG. 10 b shows I-V data for the control structure of FIG. 10 a .
  • the solid line shows results for a voltage sweep rate of 7.8 V/s, and the dotted line shows results for a voltage sweep rate of 8.8 V/s.
  • FIG. 11 a shows a test structure relating to principles of the invention.
  • a voltage source 1101 provides input to a test sample via a Pt/Ir AFM tip (not shown).
  • the test sample includes a quartz substrate 1126 , a Cr layer 1124 and a Pt layer 1122 which together form the bottom electrode of this sample, a 10 nm thick ZrO 2 insulating layer 1120 , a 10 nm thick conductive Pt layer 1118 , a 2 nm thick ZrO 2 insulating layer 1116 , a 10 ⁇ Pt quantum dot layer 1114 , a 10 nm thick ZrO 2 insulating layer 1112 , a 10 nm thick conductive Pt layer 1110 , a 2 nm thick ZrO 2 insulating layer 1108 , a 10 ⁇ Pt quantum dot layer 1106 , a 10 nm thick ZrO 2 insulating layer 1104 , and a Pt top electrode 1102 .
  • the experimental signature of the AEB effect is a peak in the I-V curve obtained during a sweep of applied voltage.
  • FIG. 11 b shows a representative example. In this example, a substantial I-V peak is seen as the voltage is swept from 10 V to ⁇ 10 V at a sweep rate of 3906 V/s. This peak is attributed to the release of charge that was stored in the device as a result of bringing it to the initial condition of 10 V bias. Quantitative analysis of such I-V peaks provides the basis for experimental estimates of power and energy storage density. More specifically, FIG. 11 c shows raw peak data for the structure of FIG. 11 a , and FIG. 11 d shows corresponding energy density results.
  • FIGS. 11 e and 11 f show comparative energy and power density results for the control structure of FIG. 10 a and the test structure of FIG. 11 a .
  • the “charging voltage” on these plots is defined as follows. Voltage sweeps were performed from X volts to 10 volts, where X is the charging voltage and is negative. The voltage range from X to 0 volts acts to charge the device, while the voltage range from 0 to 10 V is the discharge range. Stored energy/power is seen to increase on these plots as the charging voltage is made more negative (i.e., the device is more completely charged).
  • the preceding description has been by way of example as opposed to limitation, and many variations of the given examples can be employed to practice the invention.
  • practice of the invention does not depend critically on the fabrication sequences and/or methods employed.
  • the size gradient of inclusions may be combined with a material gradient of inclusions, and they may be arranged in any fashion.
  • the inclusions may have any shape such as a sphere, cone, pyramid, or approximately two-dimensional shape such as a triangle or circle.
  • many layers of inclusions, each inclusion being surrounded by a dielectric layer may be included on one or both electrodes.
  • a nanostructured template can be used to provide the conductive nanostructured electrode(s) rather than directly making the electrode nanostructured by nanowire growth.
  • an insulating nanostructured material such as anodic alumina can be used as a template, and electrodes can be formed by depositing a conductive electrode layer on such a micro- or nano-structured template.

Abstract

Improved energy storage is provided by exploiting two physical effects in combination. The first effect can be referred to as the All-Electron Battery (AEB) effect, and relates to the use of inclusions embedded in a dielectric structure between two electrodes of a capacitor. Electrons can tunnel through the dielectric between the electrodes and the inclusions, thereby increasing the charge storage density relative to a conventional capacitor. The second effect can be referred to as an area enhancement effect, and relates to the use of micro-structuring or nano-structuring on one or both of the electrodes to provide an enhanced interface area relative to the electrode geometrical area. Area enhancement is advantageous for reducing the self-discharge rate of the device.

Description

CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of U.S. provisional patent application 61/211,746, filed on Apr. 1, 2009, entitled “Architecture of high-performance all-electron battery”, and hereby incorporated by reference in its entirety.
This application also claims the benefit of U.S. provisional patent application 61/211,745, filed on Apr. 1, 2009, entitled “Energy storage in materials of different bandgaps”, and hereby incorporated by reference in its entirety.
This application also claims the benefit of U.S. provisional patent application 61/274,866, filed on Aug. 20, 2009, entitled “Nanowire architecture all-electron battery”, and hereby incorporated by reference in its entirety.
GOVERNMENT SPONSORSHIP
This invention was made with Government support under contract number W911NF-07-2-0027 awarded by the US Army Research Office. The Government has certain rights in this invention.
FIELD OF THE INVENTION
This invention relates to energy storage.
BACKGROUND
Energy storage is a crucial component of a large number and variety of electronic devices, particularly for mobile devices and vehicles. Energy storage devices have been based on a wide variety of physical effects. For example, electric fields can be employed to store energy in capacitors, and chemical reactions (involving ion motion) can be employed to store energy in batteries. However, energy storage in a capacitor can be limited by the device geometry (e.g., 2-D capacitor plates having limited area), and batteries can have a slow response time due to the ion motion inherent in electrochemical reactions.
Battery powered devices such as hybrid or electric vehicles are often limited in performance by the low energy stored per weight in batteries. Batteries have low storage density due to the large size and weight of the ions stored in the batteries. Slow ion transport in batteries also causes slow charge and discharge performance. Furthermore, the reliance of existing batteries on ionic transport causes high degradation rates of the batteries.
Accordingly, it would be an advance in the art to provide energy storage having higher energy density than a capacitor, faster charge/discharge than a battery and/or much longer lifetime than a battery.
SUMMARY
Improved energy storage is provided by exploiting two physical effects in combination. The first effect can be referred to as the All-Electron Battery (AEB) effect, and relates to the use of inclusions embedded in a dielectric structure between two electrodes of a capacitor. Electrons can tunnel through the dielectric between the electrodes and the inclusions, thereby increasing the charge storage density relative to a conventional capacitor. The second effect can be referred to as an area enhancement effect, and relates to the use of micro-structuring or nano-structuring on one or both of the electrodes to provide an enhanced interface area relative to the electrode geometrical area. Area enhancement is advantageous for reducing the self-discharge rate of the device.
Applications include electric vehicle energy storage (EV or PHEV battery), portable electronics (laptop, cell phone, etc.), and troop gear/weapons, where the advantages include high energy density storage (possibly greater than 250 Whr/kg), high power density storage (˜108 W/kg), fast charge/discharge rate, and low degradation over time because there are no chemical reactions. Further advantages include no moving atoms/ions, and no risk of catastrophic, unsafe failure.
The present approach relates to a capacitor and an electron battery having very high storage density. Because the present approach relies on electrical energy stored as electrons instead of ions, small and light devices with high storage capacities are provided. Furthermore, electron transport allows for fast charge and discharge. The present solid-state devices can also have improved lifetime relative to existing energy storage devices. In this approach, energy storage is via electrons in bulk, as opposed to surface charges (e.g., conventional capacitors) or ions (e.g., batteries).
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows an embodiment of the invention.
FIG. 2 shows another embodiment of the invention.
FIG. 3 shows a further embodiment of the invention.
FIG. 4 shows a detail view of an embodiment of the invention.
FIG. 5 shows several kinds of inclusion suitable for use in embodiments of the invention.
FIGS. 6 a-b shows examples of the use of inclusions of different size in connection with embodiments of the invention.
FIGS. 7 a-e show a first fabrication sequence for an embodiment of the invention.
FIGS. 8 a-b show final steps of a second fabrication sequence for an embodiment of the invention.
FIG. 9 shows the final step of a third fabrication sequence for an embodiment of the invention.
FIG. 10 a shows a control structure for experiments relating to principles of the invention.
FIG. 10 b shows I-V data for the control structure of FIG. 10 a.
FIG. 11 a shows a test structure relating to principles of the invention.
FIGS. 11 b-f show experimental data from the test structure of FIG. 11 a.
DETAILED DESCRIPTION
FIG. 1 shows an embodiment of the invention. In this example, an electrode 106 includes micro-structured or nano-structured features, one of which is referenced as 108. These electrode features provide an increased interfacial area (i.e., active area) relative to the electrode geometrical area. An insulating layer 104 is disposed on top of electrode 106. Inclusions are disposed on top of insulating layers 104. One of these inclusions is referenced as 110. The inclusions are surrounded by insulating layers, one of which is referenced as 112. A second electrode 102 is disposed such that a dielectric structure is disposed between the electrodes. In this example, the dielectric structure includes layers 104 and 112. The inclusions are disposed in this dielectric structure.
The inclusions are capable of transferring electrons to or from at least one of the electrodes by tunneling through the dielectric structure. Energy can be stored by establishing a charge separation between the inclusions, and energy can be provided by using this charge separation as an energy source.
FIGS. 2 and 3 show some alternative geometrical possibilities. More specifically, the example of FIG. 2 is like the example of FIG. 1, except that the interdigitated electrode 102 of FIG. 1 is replaced with a planar electrode 204 on FIG. 2, and the dielectric structure of FIG. 2 includes a dielectric filler region 202. The example of FIG. 3 is like the example of FIG. 2, except that the top electrode 302 on FIG. 3 is nanostructured and there are also inclusions near this electrode. Several layers of inclusions surrounded by dielectric layers may be disposed on top of one or both electrodes.
As indicated above, the point of micro-structuring or nano-structuring one or both electrodes of the device is to provide an electrode area enhancement. The purely geometric effect can be parameterized by the area enhancement ratio a=Ai/Ag, where Ai is the interfacial area (i.e. active area) and Ag is the geometrical area. The capacitance will increase proportionally to the area enhancement factor:
C=∈∈ 0 A i /d∈∈ 0 αA g /d  (1)
One possible embodiment of a nanowire electrode all electron battery uses conductive NiSi nanowires on the electrodes to increase the interfacial area, although it is understood that any conductive material would suffice. The NiSi nanowire growth process is well understood and can produce an area enhancement factor of a˜50-100.
An advantage of nanostructured electrodes is that it will bring down cost, since the cost of fabricating the AEB scales with the geometric area deposited, but with nanostructured electrodes, the energy density per geometric area will be higher by a factor of a. Preferably, the area enhancement factor is 1.5 or more. More preferably, this factor is 5 or more, and still more preferably, this factor is 10 or more.
Another advantage of using nanostructured electrodes is that the self-discharge rate will be lower by a factor that scales exponentially with a. The AEB is inherently suited for delivering high power density, since thin tunneling layers permit fast charge/discharge. A naively engineered AEB would suffer from unreasonably high rates of self-discharge for the same reason.
Assuming there are no deleterious side reactions and self-discharge occurs only by leakage current by discharge through the shunt resistance of the capacitor, the leakage current can be calculated given the resistivity of the material. The result is that the amount of charge stored on a parallel plate capacitor decays exponentially with time according to:
Q ( t ) = Q 0 - t / RC = Q 0 exp [ - t ρ ɛɛ 0 ] ( 2 )
where Q0 is the initial charge, t is the time, C is the capacitance, and R is the resistance of the dielectric of resistivity ρ and permittivity ∈. If we nanostructure the electrode, we can attain an area enhancement factor of up to a=Ai/Ag˜102 as discussed above. In this case, the product RC becomes
RC = [ ρ d A g ] [ ɛɛ 0 A i d ] = a ρ ɛɛ 0 ( 3 )
where d is the thickness separating the electrodes. Therefore, the charge loss in terms of a is given by:
Q ( t ) = Q 0 - t / RC = Q 0 exp [ - t a ρ ɛ ɛ 0 ] ( 4 )
To meet a specification of no more than 15% self-discharge per month, the product aρ∈ must be greater than 1018 Ω·m. As the resistivity of insulators such as SiO2 is approximately 1014 Ω·m, we conclude that ac must be greater than 10000. As discussed above, nanowire electrodes allow an area enhancement of a˜102. Therefore, the self-discharge requirement implies ∈ must be at least 102. Permittivity values this high or higher are readily attainable, whereas a permittivity of 104 or more is difficult to obtain and tends to occur only in materials with other disadvantageous properties such as low breakdown strength, low temperature tolerance, and low energy density.
Atomic layer deposition (ALD) is well suited to coat high aspect ratio structures and complex geometries, whereas PVD techniques tend to be limited by line-of-sight deposition. Therefore, chemical vapor deposition techniques such as ALD are the preferred deposition mechanism for the layer of dielectric that interfaces with microstructured electrodes.
A noteworthy feature of the present device is that it tends to be large compared to microelectronic switching devices, such as transistors, although still small relative to conventional batteries. Such size follows from its purpose of storing energy. Preferably, the electrodes each have a geometrical area of 1 μm2 or greater. Another typical feature of embodiments of the invention is operation at relatively high voltages. Preferably, charge separation between the inclusions is established by application of a voltage of 5V or more between the electrodes. Another noteworthy feature of some embodiments of the invention is that AEBs are preferably two terminal devices, where the only external device terminals are the electrodes on either side of the dielectric structure.
Embodiments of the invention can provide high charge storage density. To quantify this point, it is convenient to define the volume averaged charge separation density as follows: In a charged device having N extra electrons near one of its terminals and N missing electrons (e.g. holes) near the other terminal, and a volume between the terminals of V, the volume averaged charge separation density is N/V. Preferably, the volume averaged charge separation density can be 10−4 e/nm3 or greater when a charge separation is present between the inclusions (i.e., when the AEB is in an energy storing state).
Important design parameters for AEBs include some or all of the following parameters: electrode area enhancement factors, the spacing between electrodes and inclusions, the spacing between inclusions, the size, shape, and number density of inclusions, the tunneling energy barrier between electrodes and inclusions, the tunneling energy barrier between inclusions, dielectric constants, and work functions. The charge and discharge rates and storage capacities of the devices can be selected by appropriate geometrical design and material choice. Charge and discharge rates depend on the gaps between inclusions and the dielectric constant of the dielectric material, therefore the rates can be altered by changing the distances between inclusions, and/or the dielectric constant. Charge and discharge rates further depend upon the electron affinity of the dielectric material and of the inclusions.
FIG. 4 shows a detail view of an embodiment of the invention. In this example, the inclusions are organized as functional layers disposed in or on the dielectric structure. More specifically, functional layers 402 and 406 are disposed near a micro-structured electrode 106, and functional layers 424 and 428 are disposed near a planar electrode 204. Insulating layers 422 and 104 separate functional layers 424 and 402 from electrodes 204 and 106 respectively. An insulating barrier layer 426 is disposed between functional layers 424 and 428. An insulating barrier layer 404 is disposed between functional layers 402 and 406. Thus, the dielectric structure in this example includes multiple dielectric layers (i.e., layers 104, 404, 202, 422, and 426). Functional layers can be metallic or be semiconductors and can contain embedded inclusions having an electron affinity that is higher than the electron affinity of the dielectric structure.
The inclusions can be arranged to provide a work function gradient for the inclusions, e.g., by providing an inclusion size and/or material composition gradient. The functional layers can include different materials having different work functions, and can be disposed to form a Fermi level gradient. The functional layers can include one or more materials having an electron affinity that is lower than an electron affinity of part or all of the dielectric structure.
This example includes, as a preferred feature, vertical stacking of inclusions. Each of the functional layers is capable of storing an amount of charge by itself, therefore the device with functional layers is capable of storing a larger amount of charge. Since the voltage of these functional layers stacked in series is additive, and the energy density scales with the square of the voltage, a substantially higher energy density can be achieved.
In one embodiment, an energy storage device has inclusions of varying sizes. Preferably, large inclusions are placed near one electrode and smaller inclusions are placed near an opposing electrode. Charge is preferentially stored in the larger inclusions. The gradient in the size distribution allows polarization of the inclusions, even when the cell is neutral (e.g., a larger inclusion can be polarized due to its proximity to a smaller inclusion). When the device is charged, the excess charge is preferentially contained in the larger inclusion, thereby increasing the stored charge. It is noted that the inclusions can have a wide range of sizes. In particular, the larger inclusions can be nanowires, quantum wells, and/or bulk inclusions, while the smaller inclusions can be as small as an individual atom.
In another embodiment, the inclusions are made of different materials. Additionally, a first inclusion can be made from a material with a greater work function than a second inclusion. Electron transfer results from the Fermi level difference between materials in proximity, so a greater polarization can be achieved with a greater difference in Fermi level.
These principles can be better appreciated in view of the following more detailed example relating to FIG. 4. In this specific example, a size gradient is employed. Inclusions in functional layer 402, one of which is referenced as 412, are larger than inclusions in functional layer 406 (one of which is referenced as 416). Similarly, inclusions in functional layer 428, one of which is referenced as 438, are larger than inclusions in functional layer 424 (one of which is referenced as 434). These size gradients provide a continuous change in work function across functional layers 424 and 428, and across functional layers 402 and 406 because work function decreases as size decreases for quantum-confined inclusions.
In this example, the thickness of functional layers 402, 406, 428 and 424 is preferably in a range from 0.3 nm to 300 μm. Dielectric filler layer 202 preferably has a thickness in a range of 1 nm to 500 μm and having a relatively high electron affinity, relatively high bandgap and relatively high breakdown voltage. The bandgap of layer 202 may be above 1 eV and is preferably above 4 eV. The breakdown field for layer 202 is preferably above 1 MV/cm and more preferably above 3 MV/cm.
Electrode 204 preferably has a relatively small work function φs (i.e., φs below 4 eV and more preferably below 3 eV). Some exemplary materials useful for electrode 204 include but are not limited to: Zn, Li, Na, Mg, K, Ca, Rb, Sr, Ba, Cs, doped diamond and Y. Electrode 106 is micro-structured as described above and has a relatively large work function φl (i.e., φl above 4.5 eV and more preferably above 5.5 eV). Some exemplary materials useful for electrode 106 include but are not limited to: Au, Pt, W, Al, Cu, Ag, Ti, Se, Ge, Pd, Ni, Co, Rh, Ir and Os.
Inclusion size gradients are highly polarizable using high density of state (DOS) materials including but not limited to: Ni, Pt, Cu, Ag, Au and Ir as inclusion materials. Inclusions are preferably chemically stable in the dielectric structure material (e.g. doesn't oxidize if the matrix material is an oxide). Some examples of materials useful for the dielectric layers include, but are not limited to: Al2O3, Si, TiO2, Ti-nitride, Ti-oxynitride, Ge, ZnO, ZrO2, HfO2, SiO2, Si3N4, Y2O3, BaTiO3, SrO, SrTiO3, and mixtures or combinations thereof. Materials useful for the inclusions include metals such as Pt, Au, Ni, Ag, W, Ti, Al, Cu, Pd, Cs, Li, Na, K, Y, Sr and Ba. Further examples of materials useful for the inclusions include low bandgap semiconductors such as PbSe, PbS, ZnS, CdSe, CdS, ZnSe, Ge, Si, Sn and conductive oxides such as RuO2. Insulating layer 202 can be made from materials including but not limited to: ZnS, TiO2, Al2O3, ZrO2, Y2O3, HfO2, Si3N4, SiO2, other oxides, nitrides, sulfides, and selenides.
FIG. 5 shows several kinds of inclusion suitable for use in embodiments of the invention. More specifically, inclusions can be bulk materials, or they can be quantum confined in one dimension (quantum well 506), two dimensions (quantum wire 504), and/or three dimensions (quantum dot 502). The size below which quantum confinement effects become significant depends on the material, but it is typically about 2-10 nm in metals and about 5-40 nm in semiconductors. Thus metallic inclusions having size greater than 10 nm in all three dimensions are likely to effectively have bulk material properties. Similarly, semiconductor inclusions having size greater than 40 nm in all three dimensions are likely to effectively have bulk material properties. The use of quantum dot inclusions (e.g., metal dots having all dimensions 10 nm or less and/or semiconductor dots having all dimensions 40 nm or less), as in the preceding examples, is preferred but not required.
FIGS. 6 a-b shows examples of the use of inclusions of different size in connection with embodiments of the invention. In the example of FIG. 6 a, a relatively large inclusion 604 is surrounded by smaller inclusions 602. In the example of FIG. 6 b, a relatively small inclusion 606 is surrounded by larger inclusions 602. As indicated above, such size gradients allow for the creation of helpful work function gradients in AEBs.
FIGS. 7 a-e show a first fabrication sequence for an embodiment of the invention. FIG. 7 a shows the results of the first step of this example, which is formation of vertical metal nanowires (one of which is referenced as 108) on electrode 106. Suitable fabrication methods include, but are not limited to: Vapor-Liquid-Solid (VLS) growth techniques, optical and/or e-beam lithography, nanosphere lithography, and electroplating through a porous membrane (e.g., a polycarbonate track-etched membrane). VLS techniques start with a solid catalyst particle and a vapor reactant. The vapor lands on the solid, diffuses through it, and forms a solid beneath the catalyst particle, resulting in a wire of diameter approximately equal to the catalyst diameter.
FIG. 7 b shows the result of the second step of this example, which is deposition of an insulating layer 104. Any insulator deposition method can be employed, although chemical vapor deposition is preferred as indicated above.
FIG. 7 c shows the result of the third step of this example, which is deposition of quantum dots, one of which is referenced as 110. Any quantum dot deposition technique can be employed, including but not limited to vapor deposition, self-assembly, and processing of colloidal quantum dots. Optionally, the second and third steps can be repeated one or more times to form a multi-layered structure (e.g., as in the example of FIG. 4).
FIG. 7 d shows the result of the fourth step of this example, which is deposition of an insulating passivation layer on top of the quantum dots, part of which is referenced as 112. Any insulator deposition method can be employed, although chemical vapor deposition is preferred as indicated above.
FIG. 7 e shows the result of the fifth step of this example, which is deposition of metal to form an interdigitated top electrode 102. Any metal deposition method can be employed, including but not limited to: vapor phase deposition and electroless plating.
FIGS. 8 a-b show final steps of a second fabrication sequence for an embodiment of the invention. In this second sequence, the first four steps are as described in connection with FIGS. 7 a-d. FIG. 8 a shows the result of the fifth step of this example, which is deposition of a dielectric filler region 202 on the structure of FIG. 7 d. Any insulator deposition method can be employed, although chemical vapor deposition is preferred as indicated above. Optionally, the steps of FIGS. 7 d and 8 a can be combined into a single insulator deposition step. FIG. 8 b shows the result of the sixth step of this example, which is deposition of an electrode 204 on top of the dielectric filler region 202. Any method for depositing metal electrodes on an insulator can be employed.
FIG. 9 shows the final step of a third fabrication sequence for an embodiment of the invention. In this third sequence, the first five steps are as described in connection with FIGS. 7 a-d and 8 a. FIG. 9 shows the result of the sixth step of this example, which is performing insulator to insulator bonding of two structures as in FIG. 8 a along a bond line 902 to provide an AEB having two nano-structured electrodes. Suitable bonding methods include but are not limited to: sintering, heat treatment with a low melting point metal (which can be regarded as analogous to low temperature soldering), and vapor phase deposition.
FIG. 10 a shows a control structure for experiments relating to principles of the invention. In this example, a voltage source 1002 provides input to a control sample via a Pt/Ir Atomic Force Microscope (AFM) tip 1004. The control sample includes a quartz substrate 1018, a Cr layer 1016 and a Pt layer 1014 which together form the bottom electrode of this sample, a 10 nm thick ZrO2 insulating layer 1012, a 10 nm thick conductive Pt layer 1010, a 10 nm thick ZrO2 insulating layer 1008, and a Pt top electrode 1006. This control structure is basically two capacitors in series.
FIG. 10 b shows I-V data for the control structure of FIG. 10 a. The solid line shows results for a voltage sweep rate of 7.8 V/s, and the dotted line shows results for a voltage sweep rate of 8.8 V/s. As expected, more current flows at the higher sweep rate, because capacitor current I is given by I=CdV/dt, where C is the capacitance.
FIG. 11 a shows a test structure relating to principles of the invention. In this example, a voltage source 1101 provides input to a test sample via a Pt/Ir AFM tip (not shown). The test sample includes a quartz substrate 1126, a Cr layer 1124 and a Pt layer 1122 which together form the bottom electrode of this sample, a 10 nm thick ZrO2 insulating layer 1120, a 10 nm thick conductive Pt layer 1118, a 2 nm thick ZrO2 insulating layer 1116, a 10× Pt quantum dot layer 1114, a 10 nm thick ZrO2 insulating layer 1112, a 10 nm thick conductive Pt layer 1110, a 2 nm thick ZrO2 insulating layer 1108, a 10× Pt quantum dot layer 1106, a 10 nm thick ZrO2 insulating layer 1104, and a Pt top electrode 1102. Here, “10×” indicates that 10 ALD cycles of Pt were performed to form Pt islands of on average 1.7 nm in diameter with a number density of 3.2×1012 particles per cm2. This experiment demonstrates AEB behavior that is relevant here, even though the electrodes of this test structure are planar as opposed to be being micro-structured or nano-structured.
The experimental signature of the AEB effect is a peak in the I-V curve obtained during a sweep of applied voltage. FIG. 11 b shows a representative example. In this example, a substantial I-V peak is seen as the voltage is swept from 10 V to −10 V at a sweep rate of 3906 V/s. This peak is attributed to the release of charge that was stored in the device as a result of bringing it to the initial condition of 10 V bias. Quantitative analysis of such I-V peaks provides the basis for experimental estimates of power and energy storage density. More specifically, FIG. 11 c shows raw peak data for the structure of FIG. 11 a, and FIG. 11 d shows corresponding energy density results.
FIGS. 11 e and 11 f show comparative energy and power density results for the control structure of FIG. 10 a and the test structure of FIG. 11 a. The “charging voltage” on these plots is defined as follows. Voltage sweeps were performed from X volts to 10 volts, where X is the charging voltage and is negative. The voltage range from X to 0 volts acts to charge the device, while the voltage range from 0 to 10 V is the discharge range. Stored energy/power is seen to increase on these plots as the charging voltage is made more negative (i.e., the device is more completely charged).
The preceding description has been by way of example as opposed to limitation, and many variations of the given examples can be employed to practice the invention. For example, practice of the invention does not depend critically on the fabrication sequences and/or methods employed. As another example, the size gradient of inclusions may be combined with a material gradient of inclusions, and they may be arranged in any fashion. As a further example, the inclusions may have any shape such as a sphere, cone, pyramid, or approximately two-dimensional shape such as a triangle or circle. As yet another example, many layers of inclusions, each inclusion being surrounded by a dielectric layer, may be included on one or both electrodes. In another example, a nanostructured template can be used to provide the conductive nanostructured electrode(s) rather than directly making the electrode nanostructured by nanowire growth. For example, an insulating nanostructured material such as anodic alumina can be used as a template, and electrodes can be formed by depositing a conductive electrode layer on such a micro- or nano-structured template.

Claims (15)

The invention claimed is:
1. An electrostatic solid-state energy storage device comprising:
a first electrode;
a second electrode;
a dielectric structure disposed between said first and second electrodes; and
two or more inclusions disposed in said dielectric structure and capable of transferring electrons to or from at least one of said electrodes by tunneling through said dielectric structure;
wherein at least one of said first and second electrodes is vertically micro-structured to provide a greater active area than geometrical area;
wherein said device is capable of storing energy by establishing a charge separation between said inclusions, and wherein said device is capable of providing energy by using said charge separation as an energy source.
2. The device of claim 1, wherein at least one of said first and second electrodes has an active area to geometrical area ratio of 1.5 or more.
3. The device of claim 1, wherein said device is a two-terminal device having only said first and second electrodes as external terminals.
4. The device of claim 1, wherein said first and second electrodes each have a geometrical area of 1 μm2 or greater.
5. The device of claim 1, wherein said charge separation between said inclusions is established by application of a voltage of 5V or more between said first and second electrodes.
6. The device of claim 1, wherein a volume averaged charge separation density of said device when said charge separation is present is 10−4 e/nm3 or greater.
7. The device of claim 1, wherein said inclusions are selected from the group consisting of: quantum well, quantum wire, quantum dot, and bulk material.
8. The device of claim 1, wherein said inclusions are arranged according to size to provide a smooth work function gradient of said inclusions.
9. The device of claim 1, wherein a first of said inclusions is surrounded by several others of said inclusions each having a smaller size than said first inclusion.
10. The device of claim 1, wherein a first of said inclusions is surrounded by several others of said inclusions each having a larger size than said first inclusion.
11. The device of claim 1, wherein some or all of said inclusions are organized as functional layers disposed in or on said dielectric structure.
12. The device of claim 11, wherein said functional layers comprise different materials having different work functions, and wherein said functional layers are disposed to form a Fermi level gradient.
13. The device of claim 11, wherein said functional layers comprise a material having an electron affinity that is lower than an electron affinity of part or all of said dielectric structure.
14. The device of claim 11, wherein two or more of said functional layers are arranged in a multi-layer stack and separated from each other by one or more barrier layers.
15. The device of claim 1, wherein said dielectric structure comprises two or more dielectric layers.
US12/798,102 2009-01-16 2010-03-29 All-electron battery having area-enhanced electrodes Active 2031-09-04 US8524398B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/798,102 US8524398B2 (en) 2009-04-01 2010-03-29 All-electron battery having area-enhanced electrodes
US12/928,346 US8877367B2 (en) 2009-01-16 2010-12-09 High energy storage capacitor by embedding tunneling nano-structures

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US21174609P 2009-04-01 2009-04-01
US21174509P 2009-04-01 2009-04-01
US27486609P 2009-08-20 2009-08-20
US12/798,102 US8524398B2 (en) 2009-04-01 2010-03-29 All-electron battery having area-enhanced electrodes

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/657,198 Continuation-In-Part US8802287B2 (en) 2009-01-16 2010-01-15 Quantum dot ultracapacitor and electron battery

Publications (2)

Publication Number Publication Date
US20100255381A1 US20100255381A1 (en) 2010-10-07
US8524398B2 true US8524398B2 (en) 2013-09-03

Family

ID=42288783

Family Applications (1)

Application Number Title Priority Date Filing Date
US12/798,102 Active 2031-09-04 US8524398B2 (en) 2009-01-16 2010-03-29 All-electron battery having area-enhanced electrodes

Country Status (5)

Country Link
US (1) US8524398B2 (en)
EP (1) EP2415069A1 (en)
JP (1) JP2012523117A (en)
CN (1) CN102439694A (en)
WO (1) WO2010114600A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11705571B2 (en) 2018-09-05 2023-07-18 Nikolai M. Kocherginsky Foil-based redox flow battery

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7057881B2 (en) 2004-03-18 2006-06-06 Nanosys, Inc Nanofiber surface based capacitors
WO2012009010A2 (en) 2010-07-13 2012-01-19 The Board Of Trustees Of The Leland Stanford Junior University Energy storage device with large charge separation
DE102010051754A1 (en) 2010-11-17 2012-05-24 Hans-Josef Sterzel Electrical energy store for storing electrical energy generated from e.g. wind turbine, has positive and negative electrodes that are in contact with high and low work function arresters respectively
DE102011007988A1 (en) 2011-01-04 2012-07-05 Hans-Josef Sterzel Electrical energy storage device of high energy density for e.g. vehicles, produces electric field effects by valency change one of components of compound semiconductors under influence of loading process
DE102011101304A1 (en) 2011-05-12 2012-11-15 Hans-Josef Sterzel High energy density exhibiting electrical energy storage unit i.e. capacitor, for use in electrical vehicle, has electrodes separated from each other by semiconductor layers exhibiting type of conductivity different from that of electrodes
DE102011104749A1 (en) 2011-06-17 2012-12-20 Hans-Josef Sterzel Reversible electric energy accumulator of high energy density useful for storing electric charges in volume of two compact semiconductor electrodes of equal conductivity, comprises flat and compact semiconductors
FR2981509B1 (en) * 2011-10-18 2013-12-20 Thales Sa COLLECTOR-ELECTRODE ASSEMBLY FOR INTEGRATING AN ELECTRIC ENERGY STORAGE DEVICE
KR20140038884A (en) * 2012-09-21 2014-03-31 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Electrode material for power storage device, electrode for power storage device, and power storage device
FR3011671A1 (en) * 2013-10-04 2015-04-10 Thales Sa CURRENT COLLECTOR FOR SUPERCAPACITY
TW201618139A (en) 2014-05-12 2016-05-16 柯帕瑟特科學有限責任公司 Capacitor and method of production thereof
US10340082B2 (en) 2015-05-12 2019-07-02 Capacitor Sciences Incorporated Capacitor and method of production thereof
US10347423B2 (en) 2014-05-12 2019-07-09 Capacitor Sciences Incorporated Solid multilayer structure as semiproduct for meta-capacitor
CN110085424B (en) 2014-05-12 2021-05-18 柯帕瑟特科学有限责任公司 Energy storage device and method of manufacturing the same
KR102461254B1 (en) 2014-11-04 2022-10-31 캐패시터 사이언시스 인코포레이티드 Energy storage devices and methods of production thereof
US9852846B2 (en) 2015-02-26 2017-12-26 Capacitor Sciences Incorporated Self-healing capacitor and methods of production thereof
JP2016207994A (en) * 2015-04-23 2016-12-08 清水 幹治 High capacity capacitor device
US9932358B2 (en) 2015-05-21 2018-04-03 Capacitor Science Incorporated Energy storage molecular material, crystal dielectric layer and capacitor
US9941051B2 (en) 2015-06-26 2018-04-10 Capactor Sciences Incorporated Coiled capacitor
US10026553B2 (en) 2015-10-21 2018-07-17 Capacitor Sciences Incorporated Organic compound, crystal dielectric layer and capacitor
US10305295B2 (en) 2016-02-12 2019-05-28 Capacitor Sciences Incorporated Energy storage cell, capacitive energy storage module, and capacitive energy storage system
US9978517B2 (en) 2016-04-04 2018-05-22 Capacitor Sciences Incorporated Electro-polarizable compound and capacitor
US10153087B2 (en) 2016-04-04 2018-12-11 Capacitor Sciences Incorporated Electro-polarizable compound and capacitor
US10395841B2 (en) 2016-12-02 2019-08-27 Capacitor Sciences Incorporated Multilayered electrode and film energy storage device

Citations (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5414588A (en) 1993-09-20 1995-05-09 The Regents Of The University Of California High performance capacitors using nano-structure multilayer materials fabrication
US5906670A (en) 1993-11-15 1999-05-25 Isis Innovation Limited Making particles of uniform size
US6060743A (en) 1997-05-21 2000-05-09 Kabushiki Kaisha Toshiba Semiconductor memory device having multilayer group IV nanocrystal quantum dot floating gate and method of manufacturing the same
US6137671A (en) 1998-01-29 2000-10-24 Energenius, Inc. Embedded energy storage device
US6137192A (en) 1998-05-15 2000-10-24 Energenius, Inc. Embedded backup energy storage unit
DE10053276C1 (en) 2000-10-27 2002-01-10 Dornier Gmbh Electrochemical capacitor used as double-layer capacitor or super-capacitor comprises single cell(s) having electrode made from nano-structured film, counter electrode, and thin film electrolyte covering electrode
US6477035B1 (en) 2001-10-10 2002-11-05 Lockheed Martin Corporation Integrally formed energy storage device and method of fabrication
US6830971B2 (en) 2002-11-02 2004-12-14 Chartered Semiconductor Manufacturing Ltd High K artificial lattices for capacitor applications to use in CU or AL BEOL
US6867449B2 (en) 2000-08-30 2005-03-15 Micron Technology, Inc. Capacitor having RuSixOy-containing adhesion layers
US20060007633A1 (en) 2001-08-30 2006-01-12 Micron Technology, Inc. Decoupling capacitor for high frequency noise immunity
US7057881B2 (en) 2004-03-18 2006-06-06 Nanosys, Inc Nanofiber surface based capacitors
US20060164788A1 (en) 2002-07-01 2006-07-27 Rolf Eisenring Method for storing electricity in quantum batteries
US20060243655A1 (en) * 2005-04-29 2006-11-02 University Of Rochester Ultrathin nanoscale membranes, methods of making, and uses thereof
US20070007576A1 (en) 2005-07-07 2007-01-11 Samsung Electronics Co., Ltd. Multi-bit storageable non-volatile memory device
US7193261B2 (en) 2001-06-29 2007-03-20 Alexandr Mikhailovich Ilyanok Quantum supercapacitor
US7208802B2 (en) 2002-09-30 2007-04-24 Kabushiki Kaisha Toshiba Insulating film and electronic device
US20070121274A1 (en) 2005-07-12 2007-05-31 Talvacchio John J Small volume thin film and high energy density crystal capacitors
US7265406B2 (en) 2002-09-20 2007-09-04 Intel Corporation Capacitor with conducting nanostructure
US7323398B2 (en) 2004-09-21 2008-01-29 S.O.I.Tec Silicon On Insulator Technologies Method of layer transfer comprising sequential implantations of atomic species
US20080062614A1 (en) 2005-03-15 2008-03-13 Nanodynamics, Inc. Devices with ultrathin structures and method of making same
US20080094775A1 (en) 2004-07-23 2008-04-24 Sundew Technologies, Llc Capacitors With High Energy Storage Density And Low Esr
US7365395B2 (en) 2004-09-16 2008-04-29 Nanosys, Inc. Artificial dielectrics using nanostructures
WO2008071369A1 (en) 2006-12-11 2008-06-19 Westfälische Wilhelms-Universität Münster Condensed materials
US20080180883A1 (en) 2006-11-01 2008-07-31 The Az Board Regents On Behalf Of The Univ. Of Az Nano scale digitated capacitor
WO2008100304A2 (en) 2006-11-15 2008-08-21 The University Of North Carolina At Chapel Hill Polymer particle composite having high fidelity order, size, and shape particles
US7428137B2 (en) 2004-12-03 2008-09-23 Dowgiallo Jr Edward J High performance capacitor with high dielectric constant material
WO2008118422A1 (en) 2007-03-26 2008-10-02 The Trustees Of Columbia University In The City Of New York Metal oxide nanocrystals: preparation and uses
US7466536B1 (en) 2004-08-13 2008-12-16 Eestor, Inc. Utilization of poly(ethylene terephthalate) plastic and composition-modified barium titanate powders in a matrix that allows polarization and the use of integrated-circuit technologies for the production of lightweight ultrahigh electrical energy storage units (EESU)
US20090047453A1 (en) 2007-08-13 2009-02-19 Smart Nanomaterials, Llc Nano-enhanced smart panel
US20090090999A1 (en) 2007-10-05 2009-04-09 Carver David R High permittivity low leakage capacitor and energy storing device and method for forming the same
US20090096004A1 (en) 2007-10-05 2009-04-16 Kenji Kawabata Semiconductor storage device and manufacturing method thereof
US20090103235A1 (en) 2007-10-19 2009-04-23 Oh Young Joo Metal capacitor and manufacturing method thereof
US20090124483A1 (en) 2006-07-12 2009-05-14 Industrial Technology Research Institute Metal compound dots dielectric piece
US20090195961A1 (en) 2002-07-01 2009-08-06 Rolf Eisenring Method and device for storing electricity in quantum batteries
US7575978B2 (en) 2005-08-04 2009-08-18 Micron Technology, Inc. Method for making conductive nanoparticle charge storage element
US7662731B2 (en) * 2004-03-12 2010-02-16 Japan Science And Technology Agency Quantum dot manipulating method and quantum dot production/manipulation apparatus
WO2010023575A1 (en) 2008-08-26 2010-03-04 Nxp B.V. A capacitor and a method of manufacturing the same
US7687876B2 (en) 2005-04-25 2010-03-30 Smoltek Ab Controlled growth of a nanostructure on a substrate
US20100090663A1 (en) 2008-10-10 2010-04-15 Pappas Alexander N Energy storage module
US7750869B2 (en) 2007-07-24 2010-07-06 Northeastern University Dielectric and magnetic particles based metamaterials
US20100178543A1 (en) * 2007-04-10 2010-07-15 The Regents Of The University Of California Charge storage devices containing carbon nanotube films as electrodes and charge collectors
US7763511B2 (en) 2006-12-29 2010-07-27 Intel Corporation Dielectric barrier for nanocrystals
US20100226066A1 (en) 2009-02-02 2010-09-09 Space Charge, LLC Capacitors using preformed dielectric
US20110275005A1 (en) * 2008-10-24 2011-11-10 Nanosys, Inc Membrane Electrode Assemblies With Interfacial Layer

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001168353A (en) * 1999-09-28 2001-06-22 Toshiba Corp Optical element
JP2003249417A (en) * 2002-02-25 2003-09-05 Tdk Corp Capacitor structure and manufacturing method of the same
JP2008288346A (en) * 2007-05-16 2008-11-27 Hiroshima Univ Semiconductor element

Patent Citations (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5414588A (en) 1993-09-20 1995-05-09 The Regents Of The University Of California High performance capacitors using nano-structure multilayer materials fabrication
US5906670A (en) 1993-11-15 1999-05-25 Isis Innovation Limited Making particles of uniform size
US6060743A (en) 1997-05-21 2000-05-09 Kabushiki Kaisha Toshiba Semiconductor memory device having multilayer group IV nanocrystal quantum dot floating gate and method of manufacturing the same
US6137671A (en) 1998-01-29 2000-10-24 Energenius, Inc. Embedded energy storage device
US6137192A (en) 1998-05-15 2000-10-24 Energenius, Inc. Embedded backup energy storage unit
US6867449B2 (en) 2000-08-30 2005-03-15 Micron Technology, Inc. Capacitor having RuSixOy-containing adhesion layers
DE10053276C1 (en) 2000-10-27 2002-01-10 Dornier Gmbh Electrochemical capacitor used as double-layer capacitor or super-capacitor comprises single cell(s) having electrode made from nano-structured film, counter electrode, and thin film electrolyte covering electrode
EP1414078B1 (en) 2001-06-29 2009-04-08 Alexander Mikhailovich Ilyanok Using an electronic device as a quantum supercapacitor
US7193261B2 (en) 2001-06-29 2007-03-20 Alexandr Mikhailovich Ilyanok Quantum supercapacitor
US20060007633A1 (en) 2001-08-30 2006-01-12 Micron Technology, Inc. Decoupling capacitor for high frequency noise immunity
US6477035B1 (en) 2001-10-10 2002-11-05 Lockheed Martin Corporation Integrally formed energy storage device and method of fabrication
US20090195961A1 (en) 2002-07-01 2009-08-06 Rolf Eisenring Method and device for storing electricity in quantum batteries
US20060164788A1 (en) 2002-07-01 2006-07-27 Rolf Eisenring Method for storing electricity in quantum batteries
US7265406B2 (en) 2002-09-20 2007-09-04 Intel Corporation Capacitor with conducting nanostructure
US7268411B2 (en) 2002-09-30 2007-09-11 Kabushiki Kaisha Toshiba Insulating film and electronic device
US7208802B2 (en) 2002-09-30 2007-04-24 Kabushiki Kaisha Toshiba Insulating film and electronic device
US6830971B2 (en) 2002-11-02 2004-12-14 Chartered Semiconductor Manufacturing Ltd High K artificial lattices for capacitor applications to use in CU or AL BEOL
US7662731B2 (en) * 2004-03-12 2010-02-16 Japan Science And Technology Agency Quantum dot manipulating method and quantum dot production/manipulation apparatus
US7295419B2 (en) 2004-03-18 2007-11-13 Nanosys, Inc. Nanofiber surface based capacitors
US20060279905A1 (en) 2004-03-18 2006-12-14 Nanosys, Inc. Nanofiber surface based capacitors
US7057881B2 (en) 2004-03-18 2006-06-06 Nanosys, Inc Nanofiber surface based capacitors
US20080094775A1 (en) 2004-07-23 2008-04-24 Sundew Technologies, Llc Capacitors With High Energy Storage Density And Low Esr
US7466536B1 (en) 2004-08-13 2008-12-16 Eestor, Inc. Utilization of poly(ethylene terephthalate) plastic and composition-modified barium titanate powders in a matrix that allows polarization and the use of integrated-circuit technologies for the production of lightweight ultrahigh electrical energy storage units (EESU)
US7365395B2 (en) 2004-09-16 2008-04-29 Nanosys, Inc. Artificial dielectrics using nanostructures
US7323398B2 (en) 2004-09-21 2008-01-29 S.O.I.Tec Silicon On Insulator Technologies Method of layer transfer comprising sequential implantations of atomic species
US7428137B2 (en) 2004-12-03 2008-09-23 Dowgiallo Jr Edward J High performance capacitor with high dielectric constant material
US20080062614A1 (en) 2005-03-15 2008-03-13 Nanodynamics, Inc. Devices with ultrathin structures and method of making same
US7687876B2 (en) 2005-04-25 2010-03-30 Smoltek Ab Controlled growth of a nanostructure on a substrate
US20060243655A1 (en) * 2005-04-29 2006-11-02 University Of Rochester Ultrathin nanoscale membranes, methods of making, and uses thereof
US20070007576A1 (en) 2005-07-07 2007-01-11 Samsung Electronics Co., Ltd. Multi-bit storageable non-volatile memory device
US20070121274A1 (en) 2005-07-12 2007-05-31 Talvacchio John J Small volume thin film and high energy density crystal capacitors
US7575978B2 (en) 2005-08-04 2009-08-18 Micron Technology, Inc. Method for making conductive nanoparticle charge storage element
US20090124483A1 (en) 2006-07-12 2009-05-14 Industrial Technology Research Institute Metal compound dots dielectric piece
US20080180883A1 (en) 2006-11-01 2008-07-31 The Az Board Regents On Behalf Of The Univ. Of Az Nano scale digitated capacitor
WO2008100304A2 (en) 2006-11-15 2008-08-21 The University Of North Carolina At Chapel Hill Polymer particle composite having high fidelity order, size, and shape particles
US20100068505A1 (en) 2006-12-11 2010-03-18 Bracht Hartmut Condensed materials
WO2008071369A1 (en) 2006-12-11 2008-06-19 Westfälische Wilhelms-Universität Münster Condensed materials
US7763511B2 (en) 2006-12-29 2010-07-27 Intel Corporation Dielectric barrier for nanocrystals
WO2008118422A1 (en) 2007-03-26 2008-10-02 The Trustees Of Columbia University In The City Of New York Metal oxide nanocrystals: preparation and uses
US20100178543A1 (en) * 2007-04-10 2010-07-15 The Regents Of The University Of California Charge storage devices containing carbon nanotube films as electrodes and charge collectors
US7750869B2 (en) 2007-07-24 2010-07-06 Northeastern University Dielectric and magnetic particles based metamaterials
US20090047453A1 (en) 2007-08-13 2009-02-19 Smart Nanomaterials, Llc Nano-enhanced smart panel
US20090096004A1 (en) 2007-10-05 2009-04-16 Kenji Kawabata Semiconductor storage device and manufacturing method thereof
US20090090999A1 (en) 2007-10-05 2009-04-09 Carver David R High permittivity low leakage capacitor and energy storing device and method for forming the same
US20090103235A1 (en) 2007-10-19 2009-04-23 Oh Young Joo Metal capacitor and manufacturing method thereof
WO2010023575A1 (en) 2008-08-26 2010-03-04 Nxp B.V. A capacitor and a method of manufacturing the same
US20100090663A1 (en) 2008-10-10 2010-04-15 Pappas Alexander N Energy storage module
US20110275005A1 (en) * 2008-10-24 2011-11-10 Nanosys, Inc Membrane Electrode Assemblies With Interfacial Layer
US20100226066A1 (en) 2009-02-02 2010-09-09 Space Charge, LLC Capacitors using preformed dielectric

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
Dunn et al., "Rethinking Multifunction in Three Dimensions for Miniaturizing Electrical Energy Storage", Fall 2008, The Electrochemical Society Interface.
Dupree et al., "The electronic properties of small metal particles: The electric polarizabllity", 1972, pp. 408-414, J. Phys. C: Solid State Physics, v5.
Garcia Del Muro et al., "Metallic nanoparticies embedded in a dielectric matrix: growth mechanisms and percolation", 2008, Art. ID 475168, Journal of Nanomaterials.
Merrill et al., "Effective medium theories for artificial materials composed of multiple sizes of spherical Inclusions in a host continuum", 1999, pp. 142-148, IEEE Trans. Antennas and Propagation v47n1.

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11705571B2 (en) 2018-09-05 2023-07-18 Nikolai M. Kocherginsky Foil-based redox flow battery

Also Published As

Publication number Publication date
WO2010114600A1 (en) 2010-10-07
EP2415069A1 (en) 2012-02-08
US20100255381A1 (en) 2010-10-07
CN102439694A (en) 2012-05-02
JP2012523117A (en) 2012-09-27

Similar Documents

Publication Publication Date Title
US8524398B2 (en) All-electron battery having area-enhanced electrodes
US8802287B2 (en) Quantum dot ultracapacitor and electron battery
US8877367B2 (en) High energy storage capacitor by embedding tunneling nano-structures
US10056609B2 (en) Solid state energy storage devices
JP5743353B2 (en) Charge storage device, method of manufacturing charge storage device, mobile electronic device, and microelectronic device
US7297975B2 (en) Non-volatile, resistive memory cell based on metal oxide nanoparticles, process for manufacturing the same and memory cell arrangement of the same
CN104995763B (en) For manufacturing the method and electroplated components of electroplated components
US20130078510A1 (en) Core-shell nanoparticles in electronic battery applications
EP3086385B1 (en) Electrode material, secondary battery including the same, and manufacturing methods thereof
US10044042B2 (en) Rechargeable battery with wafer current collector and assembly method
US10644324B2 (en) Electrode material and energy storage apparatus
Wei et al. Low-cost and high-productivity three-dimensional nanocapacitors based on stand-up ZnO nanowires for energy storage
US11037737B2 (en) Energy storage technology with extreme high energy density capability
EP2662337A1 (en) Core-shell nanoparticles in electronic capacitor applications
EP3193394B1 (en) Electrode, method for manufacturing same, electrode manufactured by same, and secondary battery comprising same
US20230420193A1 (en) Pseudocapacitive battery
WO2023211975A2 (en) Embedded electrode assembly (emela)
TWI505534B (en) Charge storage device, method of making same, method of making an electrically conductive structure for same, mobile electronic device using same, and microelectronic device containing same
CN113496821A (en) Micro battery of chip process technology

Legal Events

Date Code Title Description
AS Assignment

Owner name: BOARD OF TRUSTEES OF THE LELAND STANFORD JUNIOR UN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HOLME, TIMOTHY P.;PRINZ, FRIEDRICH B.;USUI, TAKANE;REEL/FRAME:024420/0437

Effective date: 20100511

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO SMALL (ORIGINAL EVENT CODE: SMAL); ENTITY STATUS OF PATENT OWNER: SMALL ENTITY

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YR, SMALL ENTITY (ORIGINAL EVENT CODE: M2552); ENTITY STATUS OF PATENT OWNER: SMALL ENTITY

Year of fee payment: 8