US8531022B2 - Routable array metal integrated circuit package - Google Patents

Routable array metal integrated circuit package Download PDF

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Publication number
US8531022B2
US8531022B2 US12/399,200 US39920009A US8531022B2 US 8531022 B2 US8531022 B2 US 8531022B2 US 39920009 A US39920009 A US 39920009A US 8531022 B2 US8531022 B2 US 8531022B2
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metal
integrated circuit
die
routable
layer
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US20100224981A1 (en
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Ken M. Lam
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Atmel Corp
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Atmel Corp
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Assigned to ATMEL CORPORATION reassignment ATMEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LAM, KEN M.
Priority to PCT/US2010/026394 priority patent/WO2010102229A1/en
Priority to TW099106499A priority patent/TWI491001B/en
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Definitions

  • the invention relates generally to integrated circuit packaging, and more specifically to a routable array metal integrated circuit package.
  • circuits that include one or more integrated circuits, often called “chips”. These integrated circuits are usually relatively large or complex circuits such as computer processors, memory arrays, or other such devices.
  • the actual circuits in the integrated circuit are typically formed using semiconductor devices formed on a substrate, such as doped silicon transistors, resistors, and capacitors formed on a silicon substrate.
  • the combination of a substrate and circuitry formed on the substrate is often referred to as a “die”, and usually has circuitry that is so small that it is impossible to see the individual electronic components or circuit traces with the naked eye. Due to the small size of the circuit elements formed on the substrate, the die is also relatively fragile and can be easily damaged by scratching. Some circuits that operate at high power, such as high performance processors or controllers, also produce more heat than the integrated circuit die can dissipate, and so are not usable without some means of dissipating generated heat.
  • Integrated circuit packages typically include pins, solder balls, or other electrical conductors that are coupled via small lead wires to various parts of the die's electrical circuits, enabling easy and reliable electrical connection from the package's exterior to the die's circuitry.
  • These packages provide a variety functions not related to electrical connection, including carrying heat away from the die to the exterior of the circuit package and perhaps to an external heat sink, and protecting the relatively fragile die from environmental factors such as abrasion, moisture, and shock.
  • packaging an integrated circuit die has several challenges itself. Although a typical integrated circuit die is too small to form connections to without specialized equipment, it is still desirable to keep the size of the packaged die small so that it can be easily integrated into compact or portable electronic devices.
  • the cost of the package is a significant concern, as complex packages that provide good heat management, good protection of the die, and easy connectivity to external circuitry can be a significant part of the cost of a packaged integrated circuit.
  • One example embodiment of the invention comprises an integrated circuit assembly including an integrated circuit die, and a routable metal layer comprising metal traces linking a plurality of wire bond pads to a plurality of external connection pads such that the metal traces are routable under the die area.
  • An electrically nonconductive adhesive layer couples the integrated circuit die to the routable metal layer, and a plurality of wire bonds link circuitry on the integrated circuit die to the wire bond pads in the routable metal layer.
  • An overfill material encapsulates the integrated circuit die, the plurality of wire bonds, and one side of the package's external connection pads. A plurality of solder balls are formed on the plurality of external connection pads.
  • FIGS. 1 a - 1 g show an example integrated circuit assembly fabricated using a sacrificial metal base substrate carrier, consistent with a prior art example.
  • FIG. 2 a shows a side view of an integrated circuit assembly having a routable metal layer, consistent with some embodiments of the invention.
  • FIG. 2 b is a bottom view of the integrated circuit assembly having a routable metal layer of FIG. 2 a , consistent with an example embodiment of the invention.
  • FIGS. 3 a - 3 f illustrate an example method of forming an integrated circuit assembly having a routable metal layer using a sacrificial base layer and localized solder stop, consistent with an example embodiment of the invention.
  • FIGS. 4 a - 4 b illustrate an alternate method of forming an integrated circuit assembly having a routable metal layer using a sacrificial base layer using a full solder mask, consistent with an example embodiment of the invention.
  • FIG. 5 is a top view of a series of integrated circuit assemblies formed on a sacrificial metal strip base layer, consistent with an example embodiment of the invention.
  • the invention disclosed herein comprises in one example embodiment an integrated circuit assembly comprising an integrated circuit die, and a routable metal layer comprising metal traces linking a plurality of wire bond pads to a plurality of external connection pads such that the metal traces are routable under the die area.
  • An electrically nonconductive adhesive layer couples the integrated circuit die to the routable metal layer, and a plurality of wire bonds link circuitry on the integrated circuit die to the wire bond pads in the routable metal layer.
  • An overfill material encapsulates at least the integrated circuit die and the plurality of wire bonds, and one side of the package's external connection pads.
  • a plurality of solder balls are formed on the plurality of external connection pads.
  • Packaging for integrated circuits is typically designed to protect a relatively fragile integrated circuit die from its environment, to provide reliable electrical connection between the die and external circuitry, and in many cases to carry heat away from the die. Designing the packaging takes into consideration not only physical constraints such as these, but also the cost and complexity of the packaging process and the equipment required to package the dice.
  • FIGS. 1 a - 1 g show a sacrificial metal base strip packaging process. This example process starts by using a metal base strip onto which a package is formed, and from which the completed package is eventually separated.
  • a copper base strip 101 has a plating resist pattern applied to the surface of the copper base strip, as shown at 102 .
  • the bottom side of the copper base strip also has an unpatterned, solid layer of plating resist coating to prevent any plating metal deposition onto the bottom surface.
  • the resist pattern on the top side allows a plating step shown in FIG. 1 b to deposit plating material in the patterned resist openings to form wire-bond metal pads 103 and die attach pad 104 .
  • the plating material is one or more metal layers, such as gold, palladium, nickel, and copper.
  • Palladium and gold work well for surfaces of metal layers to which wires will later be bonded, while metals such as nickel or copper are often used for the body of a plating step due to their high conductivity and relatively low cost. Gold is also resistant to oxidation, and so is often used for external plating of metal layers to prevent oxidation of the underlying solderable metal.
  • the resist material 102 applied in FIG. 1 a is removed in FIG. 1 c , leaving only the metal pads 103 and 104 formed in FIG. 1 b on the copper strip 101 .
  • region 104 forms a base for attachment of the integrated circuit die, as shown in FIG. 1 d .
  • the die 105 is attached to the metal plating region 104 , such as by use of an epoxy or other adhesive.
  • the various circuits on the integrated circuit die are then connected to metal pads 103 formed during the plating process by using fine wire in what is known as a wirebond process.
  • the wires 106 connect various electrical contact points on the integrated circuit die to the metal pads 103 , such that the metal pads 103 can be eventually coupled to electrical connections external to the completed package to couple the integrated circuit to external circuitry.
  • the assembly is covered with an over-mold material as shown at 107 in FIG. 1 f to encapsulate and protect the die and the wiring and metal pads.
  • This over-mold material is an electrically nonconductive material, such as epoxy or another suitable material.
  • the encapsulated assembly is then processed to remove the sacrificial metal base strip 101 from the assembly, resulting in the die assembly shown in FIG. 1 g .
  • the copper base strip in this example is removed from the die assembly by a chemical etch that removes copper efficiently but does not attach to or react with the exposed metal used in the plated metal pads 103 and 104 .
  • the metal pads 103 and 104 in the assembly shown in FIG. 1 g can then be coupled to the next level board assembly using solder or conductive adhesive compound, or through other means.
  • the metal pad 104 that supports the die is the same metal that is used to form the pads 103 , but no metal pad formed in the plating process of FIG. 1 b is connected to any other metal pad.
  • the bond wires shown at 106 of FIG. 1 e couple the die's circuits to the metal pads 103 , enabling connection to external circuitry. Because the bond wires cannot cross one another without risking electrically coupling one wire to the other due to accidental contact, this packaging system does not provide the ability to cross or route wires to different pads.
  • One example embodiment of the invention addresses some problems with the assembly of FIG. 1 by providing a sacrificial metal base strip packaging process that includes a routable layer that is formed by pattern plating. This provides improved flexibility in routing circuit traces to facilitate external connections
  • FIGS. 2 a and 2 b show a pattern-plated sacrificial metal strip die package including a Ball Grid Array (BGA) format, consistent with an example embodiment of the invention. Other package formats without solder balls are also commonly used.
  • BGA Ball Grid Array
  • FIG. 2 a the die package is inverted from the example die package shown in FIG. 1 g , and includes a routable metal layer in place of the large pad 104 onto which the die is mounted in FIG. 1 .
  • a routable metal layer of conductive traces 204 is formed on the sacrificial metal layer, including in the area in which the die is mounted.
  • the traces are coupled to the die via wire bond connections to metal wirebond pads 203 , which are coupled via the metal layer conductive traces 204 to package pads 201 .
  • Solder balls 202 are here formed on package pads 201 in openings in solder mask layer 206 , for connection to external circuitry.
  • an electrically non-conductive die-attach adhesive material 205 such as epoxy compound, is used for die-attach. This provides a compact, efficient package, with enhanced flexibility in configuration due to the routable metal traces in the metal layer.
  • FIG. 2 b A bottom view of the example package of FIG. 2 a is shown in FIG. 2 b .
  • conductive traces 204 are shown to link various solder balls 202 to various metal wirebond pads 203 , such that a wirebond connection from the die to the wirebond pad 203 is electrically coupled via conductive traces 204 to the solder balls 202 .
  • Some solder balls, such as power and ground connections, may be connected to multiple pads on the routable metal layer so that multiple power and ground connections can be made between the various circuits on the die and the external power source.
  • An example is shown in FIG. 2 b at pads 207 , which are coupled to one another and to a single solder ball via metal traces on the routable metal layer.
  • FIGS. 3 a - 3 f illustrate a method of forming a die package having a routable metal layer using a sacrificial metal strip integrated circuit packaging process, consistent with an example embodiment of the invention.
  • the sacrificial metal strip is a copper metal base 301
  • a routable or patterned metal circuit layer 302 is formed on the strip, such as by using a photo-definable plating resist material and photo-mask as described in greater detail with respect to the example of FIG. 1 .
  • the metal layer here has one or more layers of metal in a metal-stack, where different types of metal may be used in different layers to provide different properties.
  • the metal routable layer 302 which comprises wirebonding pad features 203 , package pad features 201 , and routing trace features 204 as illustrated in FIGS. 2 a and 2 b , includes in one embodiment a wire-bondable metal on the top surface, such as palladium, silver, or gold.
  • a diffusion barrier metal layer such as nickel is immediately below the wire-bondable metal layer, and a conductive metal such as copper is next.
  • a solder diffusion barrier metal such as nickel is formed, and the bottom layer is an oxidation prevention metal such as silver, gold, or palladium.
  • more layers, other layers, or only select layers from the above example are included in the routable metal layer 302 .
  • the die is attached to the routable metal layer in FIG. 3 b via an electrically nonconductive epoxy layer 303 , or via another nonconductive adhesive material.
  • the die is therefore not directly electrically connected to any routable metal traces routed under the die, but is instead coupled to the routable metal layer via bond wires 304 .
  • the bond wires 304 are attached to various pads 305 , which are coupled via the routable metal layer to external circuit connections.
  • the assembly is then encased as shown in FIG. 3 c with an overmold material 306 , which protects the die and the bond wires from abrasion, moisture, and other environmental factors.
  • the sacrificial metal strip copper base is then removed as shown in FIG. 3 d (shown upside-down), such as by chemical etching. This leaves the routable metal layer and the die-attach epoxy exposed from the overmold applied in FIG. 3 c .
  • the sacrificial metal strip is in some examples a long or continuous metal strip that is cut into individual die packages near the end of the packaging process, such as by sawing the metal strip or the die package, as shown in FIG. 5 .
  • solder balls are applied to the exposed solder ball regions 309 of the routable metal layer as shown in FIG. 3 d .
  • solder stop 307 is applied at various points to constrain solder from flowing onto metal traces 204 during solder ball attachment to the pad areas as shown at 308 in FIG. 3 f.
  • FIGS. 4 a and 4 b present an alternate method of applying solder balls, using a full solder mask layer instead of solder stop as employed in FIGS. 3 e and 3 f .
  • a permanent solder mask 401 is applied to the entire bottom side of the integrated circuit package except for the area over the package metal pads that will receive solder balls, as shown at 402 in FIG. 4 b .
  • This solder mask layer can be of a photo-definable or non-photo-definable characteristic, in ink or dry-film form, and can be applied using screening or lamination process in various embodiments.
  • a series of integrated circuit assemblies can be formed on a long or continuous sacrificial metal strip base layer, such as is shown in FIG. 5 .
  • the individual integrated circuit packages 501 are then separated from one another, such as by sawing, in the final stages of integrated circuit package production.
  • the routable metal layer integrated circuit assembly technology described herein therefore provides a variety of advantages over prior art integrated circuit mounting technologies such as the example illustrated in FIG. 1 , including providing the advantage of full layer routing capability.
  • a typical BGA package uses an organic substrate for routing. Eliminating an organic substrate in the routable metal layer integrated circuit examples illustrated in FIGS. 2-4 makes these examples significantly less expensive than prior technologies, and substantially reduces the height of the finished integrated circuit assembly which allows for thinner devices such as cell phones, personal digital assistant devices, global positioning systems, and other portable or handheld electronic devices.

Abstract

An integrated circuit assembly comprises an integrated circuit die, and a routable metal layer comprising metal traces linking a plurality of wire bond pads to a plurality of external connection pads such that the metal traces are routable under the die area. An electrically nonconductive adhesive layer couples the integrated circuit die to the routable metal layer, and a plurality of wire bonds link circuitry on the integrated circuit die to the wire bond pads in the routable metal layer. An overfill material encapsulates at least the integrated circuit die and the plurality of wire bonds, and a plurality of solder balls are formed on the plurality of external connection pads.

Description

FIELD OF THE INVENTION
The invention relates generally to integrated circuit packaging, and more specifically to a routable array metal integrated circuit package.
BACKGROUND
Most electronic or computerized devices have electronic circuits that include one or more integrated circuits, often called “chips”. These integrated circuits are usually relatively large or complex circuits such as computer processors, memory arrays, or other such devices. The actual circuits in the integrated circuit are typically formed using semiconductor devices formed on a substrate, such as doped silicon transistors, resistors, and capacitors formed on a silicon substrate.
The combination of a substrate and circuitry formed on the substrate is often referred to as a “die”, and usually has circuitry that is so small that it is impossible to see the individual electronic components or circuit traces with the naked eye. Due to the small size of the circuit elements formed on the substrate, the die is also relatively fragile and can be easily damaged by scratching. Some circuits that operate at high power, such as high performance processors or controllers, also produce more heat than the integrated circuit die can dissipate, and so are not usable without some means of dissipating generated heat.
For these and other reasons, almost all integrated circuit dice are provided to the manufacturers of devices such as computers or cell phones in packages that are designed to protect the integrated circuit while making it easy to connect to other circuitry. Integrated circuit packages typically include pins, solder balls, or other electrical conductors that are coupled via small lead wires to various parts of the die's electrical circuits, enabling easy and reliable electrical connection from the package's exterior to the die's circuitry. These packages provide a variety functions not related to electrical connection, including carrying heat away from the die to the exterior of the circuit package and perhaps to an external heat sink, and protecting the relatively fragile die from environmental factors such as abrasion, moisture, and shock.
But, packaging an integrated circuit die has several challenges itself. Although a typical integrated circuit die is too small to form connections to without specialized equipment, it is still desirable to keep the size of the packaged die small so that it can be easily integrated into compact or portable electronic devices. The cost of the package is a significant concern, as complex packages that provide good heat management, good protection of the die, and easy connectivity to external circuitry can be a significant part of the cost of a packaged integrated circuit.
It is therefore desired to package integrated circuit dice in a manner that addresses such commercial needs.
SUMMARY
One example embodiment of the invention comprises an integrated circuit assembly including an integrated circuit die, and a routable metal layer comprising metal traces linking a plurality of wire bond pads to a plurality of external connection pads such that the metal traces are routable under the die area. An electrically nonconductive adhesive layer couples the integrated circuit die to the routable metal layer, and a plurality of wire bonds link circuitry on the integrated circuit die to the wire bond pads in the routable metal layer. An overfill material encapsulates the integrated circuit die, the plurality of wire bonds, and one side of the package's external connection pads. A plurality of solder balls are formed on the plurality of external connection pads.
BRIEF DESCRIPTION OF THE FIGURES
FIGS. 1 a-1 g show an example integrated circuit assembly fabricated using a sacrificial metal base substrate carrier, consistent with a prior art example.
FIG. 2 a shows a side view of an integrated circuit assembly having a routable metal layer, consistent with some embodiments of the invention.
FIG. 2 b is a bottom view of the integrated circuit assembly having a routable metal layer of FIG. 2 a, consistent with an example embodiment of the invention.
FIGS. 3 a-3 f illustrate an example method of forming an integrated circuit assembly having a routable metal layer using a sacrificial base layer and localized solder stop, consistent with an example embodiment of the invention.
FIGS. 4 a-4 b illustrate an alternate method of forming an integrated circuit assembly having a routable metal layer using a sacrificial base layer using a full solder mask, consistent with an example embodiment of the invention.
FIG. 5 is a top view of a series of integrated circuit assemblies formed on a sacrificial metal strip base layer, consistent with an example embodiment of the invention.
 DETAILED DESCRIPTION
In the following detailed description of example embodiments of the invention, reference is made to specific example embodiments of the invention by way of drawings and illustrations. These examples are described in sufficient detail to enable those skilled in the art to practice the invention, and serve to illustrate how the invention may be applied to various purposes or embodiments. Other embodiments of the invention exist and are within the scope of the invention, and logical, mechanical, electrical, and other changes may be made without departing from the subject or scope of the present invention.
Features or limitations of various embodiments of the invention described herein, however essential to the example embodiments in which they are incorporated, do not limit other embodiments of the invention or the invention as a whole, and any reference to the invention, its elements, operation, and application do not limit the invention as a whole but serve only to define these example embodiments. The following detailed description does not, therefore, limit the scope of the invention, which is defined only by the appended claims.
The invention disclosed herein comprises in one example embodiment an integrated circuit assembly comprising an integrated circuit die, and a routable metal layer comprising metal traces linking a plurality of wire bond pads to a plurality of external connection pads such that the metal traces are routable under the die area. An electrically nonconductive adhesive layer couples the integrated circuit die to the routable metal layer, and a plurality of wire bonds link circuitry on the integrated circuit die to the wire bond pads in the routable metal layer. An overfill material encapsulates at least the integrated circuit die and the plurality of wire bonds, and one side of the package's external connection pads. In a further example, a plurality of solder balls are formed on the plurality of external connection pads.
Packaging for integrated circuits is typically designed to protect a relatively fragile integrated circuit die from its environment, to provide reliable electrical connection between the die and external circuitry, and in many cases to carry heat away from the die. Designing the packaging takes into consideration not only physical constraints such as these, but also the cost and complexity of the packaging process and the equipment required to package the dice.
One solution to packaging a die is illustrated in FIGS. 1 a-1 g, which show a sacrificial metal base strip packaging process. This example process starts by using a metal base strip onto which a package is formed, and from which the completed package is eventually separated.
In FIG. 1 a, a copper base strip 101 has a plating resist pattern applied to the surface of the copper base strip, as shown at 102. The bottom side of the copper base strip also has an unpatterned, solid layer of plating resist coating to prevent any plating metal deposition onto the bottom surface. The resist pattern on the top side allows a plating step shown in FIG. 1 b to deposit plating material in the patterned resist openings to form wire-bond metal pads 103 and die attach pad 104. In various embodiments, the plating material is one or more metal layers, such as gold, palladium, nickel, and copper. Palladium and gold work well for surfaces of metal layers to which wires will later be bonded, while metals such as nickel or copper are often used for the body of a plating step due to their high conductivity and relatively low cost. Gold is also resistant to oxidation, and so is often used for external plating of metal layers to prevent oxidation of the underlying solderable metal.
Once the metal plating process is completed, the resist material 102 applied in FIG. 1 a is removed in FIG. 1 c, leaving only the metal pads 103 and 104 formed in FIG. 1 b on the copper strip 101. Here, region 104 forms a base for attachment of the integrated circuit die, as shown in FIG. 1 d. The die 105 is attached to the metal plating region 104, such as by use of an epoxy or other adhesive.
The various circuits on the integrated circuit die are then connected to metal pads 103 formed during the plating process by using fine wire in what is known as a wirebond process. As shown in FIG. 1 e, the wires 106 connect various electrical contact points on the integrated circuit die to the metal pads 103, such that the metal pads 103 can be eventually coupled to electrical connections external to the completed package to couple the integrated circuit to external circuitry.
After the die is coupled via the wirebond wires to the metal pads formed in the plating process, the assembly is covered with an over-mold material as shown at 107 in FIG. 1 f to encapsulate and protect the die and the wiring and metal pads. This over-mold material is an electrically nonconductive material, such as epoxy or another suitable material.
The encapsulated assembly is then processed to remove the sacrificial metal base strip 101 from the assembly, resulting in the die assembly shown in FIG. 1 g. The copper base strip in this example is removed from the die assembly by a chemical etch that removes copper efficiently but does not attach to or react with the exposed metal used in the plated metal pads 103 and 104. The metal pads 103 and 104 in the assembly shown in FIG. 1 g can then be coupled to the next level board assembly using solder or conductive adhesive compound, or through other means.
The metal pad 104 that supports the die is the same metal that is used to form the pads 103, but no metal pad formed in the plating process of FIG. 1 b is connected to any other metal pad. The bond wires shown at 106 of FIG. 1 e couple the die's circuits to the metal pads 103, enabling connection to external circuitry. Because the bond wires cannot cross one another without risking electrically coupling one wire to the other due to accidental contact, this packaging system does not provide the ability to cross or route wires to different pads.
One example embodiment of the invention addresses some problems with the assembly of FIG. 1 by providing a sacrificial metal base strip packaging process that includes a routable layer that is formed by pattern plating. This provides improved flexibility in routing circuit traces to facilitate external connections
FIGS. 2 a and 2 b show a pattern-plated sacrificial metal strip die package including a Ball Grid Array (BGA) format, consistent with an example embodiment of the invention. Other package formats without solder balls are also commonly used. In FIG. 2 a, the die package is inverted from the example die package shown in FIG. 1 g, and includes a routable metal layer in place of the large pad 104 onto which the die is mounted in FIG. 1.
Here, a routable metal layer of conductive traces 204 is formed on the sacrificial metal layer, including in the area in which the die is mounted. The traces are coupled to the die via wire bond connections to metal wirebond pads 203, which are coupled via the metal layer conductive traces 204 to package pads 201. Solder balls 202 are here formed on package pads 201 in openings in solder mask layer 206, for connection to external circuitry. To prevent the die, which is typically silicon material, from electrically shorting to the package pad metal 201 and metal traces 204, an electrically non-conductive die-attach adhesive material 205, such as epoxy compound, is used for die-attach. This provides a compact, efficient package, with enhanced flexibility in configuration due to the routable metal traces in the metal layer.
A bottom view of the example package of FIG. 2 a is shown in FIG. 2 b. Here, conductive traces 204 are shown to link various solder balls 202 to various metal wirebond pads 203, such that a wirebond connection from the die to the wirebond pad 203 is electrically coupled via conductive traces 204 to the solder balls 202. Some solder balls, such as power and ground connections, may be connected to multiple pads on the routable metal layer so that multiple power and ground connections can be made between the various circuits on the die and the external power source. An example is shown in FIG. 2 b at pads 207, which are coupled to one another and to a single solder ball via metal traces on the routable metal layer.
FIGS. 3 a-3 f illustrate a method of forming a die package having a routable metal layer using a sacrificial metal strip integrated circuit packaging process, consistent with an example embodiment of the invention. In FIG. 3 a, the sacrificial metal strip is a copper metal base 301, and a routable or patterned metal circuit layer 302 is formed on the strip, such as by using a photo-definable plating resist material and photo-mask as described in greater detail with respect to the example of FIG. 1. The metal layer here has one or more layers of metal in a metal-stack, where different types of metal may be used in different layers to provide different properties.
For example, the metal routable layer 302, which comprises wirebonding pad features 203, package pad features 201, and routing trace features 204 as illustrated in FIGS. 2 a and 2 b, includes in one embodiment a wire-bondable metal on the top surface, such as palladium, silver, or gold. A diffusion barrier metal layer such as nickel is immediately below the wire-bondable metal layer, and a conductive metal such as copper is next. Below that a solder diffusion barrier metal such as nickel is formed, and the bottom layer is an oxidation prevention metal such as silver, gold, or palladium. In alternate embodiments, more layers, other layers, or only select layers from the above example are included in the routable metal layer 302.
The die is attached to the routable metal layer in FIG. 3 b via an electrically nonconductive epoxy layer 303, or via another nonconductive adhesive material. The die is therefore not directly electrically connected to any routable metal traces routed under the die, but is instead coupled to the routable metal layer via bond wires 304. The bond wires 304 are attached to various pads 305, which are coupled via the routable metal layer to external circuit connections.
The assembly is then encased as shown in FIG. 3 c with an overmold material 306, which protects the die and the bond wires from abrasion, moisture, and other environmental factors. The sacrificial metal strip copper base is then removed as shown in FIG. 3 d (shown upside-down), such as by chemical etching. This leaves the routable metal layer and the die-attach epoxy exposed from the overmold applied in FIG. 3 c. The sacrificial metal strip is in some examples a long or continuous metal strip that is cut into individual die packages near the end of the packaging process, such as by sawing the metal strip or the die package, as shown in FIG. 5.
Solder balls are applied to the exposed solder ball regions 309 of the routable metal layer as shown in FIG. 3 d. In FIG. 3 e, solder stop 307 is applied at various points to constrain solder from flowing onto metal traces 204 during solder ball attachment to the pad areas as shown at 308 in FIG. 3 f.
FIGS. 4 a and 4 b present an alternate method of applying solder balls, using a full solder mask layer instead of solder stop as employed in FIGS. 3 e and 3 f. In FIG. 4 a, a permanent solder mask 401 is applied to the entire bottom side of the integrated circuit package except for the area over the package metal pads that will receive solder balls, as shown at 402 in FIG. 4 b. This solder mask layer can be of a photo-definable or non-photo-definable characteristic, in ink or dry-film form, and can be applied using screening or lamination process in various embodiments.
As previously discussed in the example presented in FIG. 3, a series of integrated circuit assemblies can be formed on a long or continuous sacrificial metal strip base layer, such as is shown in FIG. 5. The individual integrated circuit packages 501 are then separated from one another, such as by sawing, in the final stages of integrated circuit package production.
The routable metal layer integrated circuit assembly technology described herein therefore provides a variety of advantages over prior art integrated circuit mounting technologies such as the example illustrated in FIG. 1, including providing the advantage of full layer routing capability. A typical BGA package uses an organic substrate for routing. Eliminating an organic substrate in the routable metal layer integrated circuit examples illustrated in FIGS. 2-4 makes these examples significantly less expensive than prior technologies, and substantially reduces the height of the finished integrated circuit assembly which allows for thinner devices such as cell phones, personal digital assistant devices, global positioning systems, and other portable or handheld electronic devices.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that achieve the same purpose, structure, or function may be substituted for the specific embodiments shown. This application is intended to cover any adaptations or variations of the example embodiments of the invention described herein. It is intended that this invention be limited only by the claims, and the full scope of equivalents thereof.

Claims (19)

The invention claimed is:
1. An integrated circuit assembly, comprising:
an integrated circuit die;
a routable metal layer comprising routable metal traces configured for coupling wire bond pads to package pads that are configured as a mount for the die, the routable metal layer including at least a pair of metal traces that directly couple a pair of wire bond pads to one another without an intervening package pad under an area on which the die is mounted;
an electrically nonconductive adhesive layer coupling the integrated circuit die to the routable metal layer such that the integrated circuit die is not directly electrically connected to the metal traces routed under the area on which the die is mounted; and
a plurality of bond wires linking circuitry on the integrated circuit die to the wire bond pads in the routable metal layer, forming electrical connections between the integrated circuit die and the routable metal layer.
2. The integrated circuit assembly of claim 1, further comprising a continuous sacrificial metal strip upon which a plurality of die packages are formed, each die package including an integrated circuit die and a routable metal layer.
3. The integrated circuit assembly of claim 1, further comprising an overfill material encapsulating at least the integrated circuit die and the plurality of bond wires.
4. The integrated circuit assembly of claim 3, wherein the overfill material further fills at least some gaps between the metal traces in the routable metal layer.
5. The integrated circuit assembly of claim 1, wherein a plurality of solder balls are formed on exposed solder ball regions of the routable metal layer.
6. The integrated circuit assembly of claim 5, wherein at least one of solder stop or a solder mask are used to constrain solder from flowing onto the metal traces during attaching the solder balls to the exposed solder ball regions of the routable metal layer.
7. The integrated circuit assembly of claim 1, wherein the metal traces are routed under the area on which the die is adhesively attached to the routable metal layer.
8. The integrated circuit assembly of claim 7, wherein the electrically nonconductive adhesive layer fills gaps between two or more metal traces routed in the routable metal layer under the area on which the die is adhesively attached to the routable metal layer.
9. The integrated circuit assembly of claim 1, wherein the routable metal layer comprises layers of metal in a metal stack, the layers of metal comprising:
a top surface including a wire-bondable metal that is selected from the group consisting of palladium and silver,
a layer of diffusion barrier metal including nickel immediately below the top surface,
a layer of conductive metal including copper immediately below the layer of diffusion barrier metal,
a layer of solder diffusion barrier metal including nickel below the layer of conductive metal, and
a bottom layer including a layer of oxidation prevention metal that is selected from the group consisting of palladium and silver.
10. The integrated circuit assembly of claim 5, wherein the exposed solder ball regions of the routable metal layer include a package pad.
11. The integrated circuit assembly of claim 1, wherein the metal traces are configured for coupling a subset of the wire bond pads to one another and to a package pad connected to an external power source such that a plurality of power and ground connections are provided between circuitry on the die and the external power source.
12. An integrated circuit assembly, comprising:
an integrated circuit die;
a routable metal layer comprising metal traces configured for coupling wire bond pads to package pads, the routable metal layer including at least a pair of metal traces that directly couple a pair of wire bond pads to one another without an intervening package pad under an area on which the die is mounted, the package pads configured for mounting the die;
a plurality of solder balls formed on exposed solder ball regions of the routable metal layer; and
a ceramic encasing configured for encasing the integrated circuit assembly.
13. The integrated circuit assembly of claim 12, wherein the plurality of solder balls electrically couple the integrated circuit assembly to a printed circuit board.
14. The integrated circuit assembly of claim 12, wherein the routable metal layer includes layers of metal, the layers of metal comprising:
a top surface including a wire-bondable metal, the wire-bondable metal being selected from a group including palladium and silver,
a layer of diffusion barrier metal immediately below the top surface, the diffusion barrier metal including nickel,
a layer of conductive metal immediately below the layer of diffusion barrier metal, the conductive metal including copper,
a layer of solder diffusion barrier metal below the layer of conductive metal, the solder the diffusion barrier metal including nickel, and
a layer of oxidation prevention metal as a bottom layer, the oxidation prevention metal being selected from a group including palladium and silver.
15. The integrated circuit assembly of claim 12, wherein the exposed solder ball regions of the routable metal layer include a package pad.
16. The integrated circuit assembly of claim 12, wherein the metal traces are configured for coupling a subset of the wire bond pads to one another and to a package pad connected to an external power source such that a plurality of power and ground connections are provided between circuitry on the die and the external power source.
17. The integrated circuit assembly of claim 16, wherein one or more solder balls are connected to the external power source and to the wire bond pads coupled to one another such that the plurality of power and ground connections are provided between circuitry on the integrated circuit die and the external power source.
18. An integrated circuit assembly, comprising:
an integrated circuit die; and
a routable metal layer including metal traces configured for coupling wire bond pads to package pads, the package pads being configured as a mount for the integrated circuit die, the routable metal layer including at least a pair of metal traces that directly couple a pair of wire bond pads to one another without an intervening package pad under an area on which the integrated circuit die is mounted.
19. The integrated circuit assembly of claim 18, comprising:
a plurality of solder balls formed on exposed solder ball regions on the package pads, the plurality of solder balls including a solder ball that is connected to an external power source and attached to a package pad that is coupled to a subset of the wire bond pads using the metal traces such that electrical and ground connections are provided to circuitry on the integrated circuit die that are connected to the subset of the wire bond pads.
US12/399,200 2009-03-06 2009-03-06 Routable array metal integrated circuit package Active 2029-09-19 US8531022B2 (en)

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US12/399,200 US8531022B2 (en) 2009-03-06 2009-03-06 Routable array metal integrated circuit package
PCT/US2010/026394 WO2010102229A1 (en) 2009-03-06 2010-03-05 Wire-bonded integrated circuit package without package substrate and including metal traces linking to external connection pads routed under integrated circuit die.
TW099106499A TWI491001B (en) 2009-03-06 2010-03-05 Integrated circuit assembly

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US9324641B2 (en) * 2012-03-20 2016-04-26 Stats Chippac Ltd. Integrated circuit packaging system with external interconnect and method of manufacture thereof

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TW201044535A (en) 2010-12-16
TWI491001B (en) 2015-07-01

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