US8667211B2 - System and method for managing a non-volatile memory - Google Patents
System and method for managing a non-volatile memory Download PDFInfo
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- US8667211B2 US8667211B2 US13/300,312 US201113300312A US8667211B2 US 8667211 B2 US8667211 B2 US 8667211B2 US 201113300312 A US201113300312 A US 201113300312A US 8667211 B2 US8667211 B2 US 8667211B2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7203—Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
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- the embodiments of the invention relate generally to the field of memory storage. More particularly, the disclosed embodiments relate to a system and method of managing flash memory.
- Flash memory devices store information with high density on Flash cells with ever smaller dimensions.
- Multi-Level Cells store several bits per cell by setting the amount of charge in a cell. Flash memory devices are organized into (physical) pages. Each page includes a section allocated for data (512 bytes-8 Kbytes and expected larger in the future) and a small amount of spare bytes (64-512 or more bytes for every page) for storing redundancy and metadata. The redundancy bytes are used to store error correcting information, for correcting errors which may have occurred during flash lifetime and the page Read process.
- Each Program operation is performed on an entire page. A number of pages are grouped together to form an Erase Block (erase block). A page cannot be erased unless the entire erase block which contains it is erased.
- SD cards One common application of flash memory devices is Secure Digital (SD) cards.
- An SD card may typically contain flash memory devices and a flash memory controller.
- the controller translates commands arriving through the SD interface into actions (Read/Write/Erase) on the flash memory devices.
- the most common SD commands may be Read and Write commands of one or more sectors, where a sector may be, but is not limited to, a sequence of 512 bytes.
- the Read or Write commands may be directed to a single sector or multiple sectors. These commands may refer to logical addresses. These addresses may then be redirected to new addresses on the flash memory which need not directly correspond to the logical addresses that might be referenced by the Read or Write commands.
- the erase function is performed on an entire erase block. Because of this functionality, before the data of a certain block may be replaced such as during a write function, the new data must be written in an alternative location before an erase can occur, to preserve the integrity of the stored data.
- the controller may typically have only a small RAM available for storage.
- the small size of the RAM memory limits the type of memory management which may be carried out by the controller with regard to the data stored in the flash memory device and received from the interface.
- the controller may typically manage the memory at the erase block level, because managing data of small particle sizes becomes difficult. That is, the logical memory space may be divided into units of memory contained within a single erase block or some constant. multiple of erase blocks, such that all logical sector addresses within each said unit of memory may be mapped to the same erase block or some constant multiple thereof.
- This type of management has the drawback that for writing random access data sectors to memory or other memory units smaller than an erase block, erase blocks must be frequently rewritten. Because of the characteristics of flash memory, each new piece of information is written into an empty page. In flash memory a page may not be rewritten before the entire erase block is erased first.
- an erase block If a portion of the memory unit contained within an erase block may need to be rewritten, it is first written into a freshly allocated erased erase block. The remaining, unmodified, contents of the erase block may then be copied into the new erase block and the former erase-block may be declared as free and may be further erased. This operation may be referred to as “sealing” or “merging”. The operation involves collecting the most recent data of a logical block and then merging it with the rest of the block data in a single erase block. Thus, even if a single sector from an erase block is rewritten, a complete erase block would be rewritten.
- the controller is used to manage the overhead described above, and must always keep track of the data associated with each logical address and the actual memory location. This is usually achieved by implementing a mapping method between the logical address space assigned to the data and the actual memory storage location of the data.
- mapping systems that rely on block mapping and page mapping, respectively.
- LBA data size
- a merge may be an operation where the original content of a logical block is merged with the new data to form a new up to date copy of the block. This up to date copy is the data block that is associated with a logical data block assigned to the data contained within.
- each logical page of a logical block is mapped to an arbitrary physical page where two pages belonging to the same logical block can reside in different physical blocks of the flash memory.
- the second approach requires additional complexity in terms of the amount of management data and memory overhead required for the physical memory to logical address mapping tables. For memory applications where severe limitations exist on available control memory, this approach is less appropriate. Flash memories such as SD have limited amount of memory overhead and the first mapping approach, or variants thereof are more practical.
- Embodiments of the invention may provide a device and method for reducing peak to average ratio of write throughput in non-volatile based storage systems.
- Non-volatile technologies can include flash or any other non-volatile technology that mandates erasing in erase blocks.
- a method may include receiving data sectors from an interface; writing each data sector into a data block of a buffer such as an extended random sector buffer (ERSB) of the flash memory; creating pointers in a data management structure, for each data sector corresponding to an associated logical block and a storage location of the data sector in the non-volatile extended random sequence buffer; and upon a fulfillment of a predetermined criterion (which is fulfilled before the buffer is full) then determining a number of logical blocks to be merged; and writing the data sectors corresponding to said number of logical blocks from the extended random sequence buffer to the primary non-volatile data storage memory.
- the predefined criteria can be fulfilled, for example, if during the writing of the data sectors a data block in the extended random sequence buffer in the non-volatile memory becomes full.
- the method may further comprise determining an instantaneous number of logical blocks which have at least one associated page in extended random sequence buffer, wherein determining said number of logical blocks comprises of determining said number of logical blocks based on said instantaneous number of logical blocks.
- the method may include determining the number of logical blocks to be merged in response to a difference between (i) the instantaneous number of logical blocks which have at least one associated data page in the buffer and (ii) a product of a multiplication of the number of transaction timeout durations required to complete a single merge operation by a ratio between the number of data blocks in the buffer and the number of memory pages in a data block of the buffer.
- writing the data sectors corresponding to said number of logical blocks from the extended random sequence buffer to the primary non-volatile data storage memory may comprise, selecting a set of logical blocks corresponding to said determined number of logical blocks based on a predetermined algorithm; and writing the data sectors corresponding to the selected logical blocks from the extended random sequence buffer to the primary non-volatile data storage memory.
- selecting said number of logical blocks based on a predetermined algorithm may comprise, determining a set of indices based on an ordering permutation which is defined for a plurality of indices corresponding to a number of logical blocks associated with the flash memory unit; and selecting a set of logical blocks corresponding to said determined number of logical blocks based on the determined set of indices.
- writing the data sectors from the buffer to primary non-volatile data storage memory may comprise, merging the data sectors into erase block sections of data; writing the plurality of erase block sections of data to a plurality of erase blocks in the primary non-volatile data storage memory; and creating for each data sector a pointer in a data management structure, corresponding to an associated logical block and a storage location of the erase blocks in the primary non-volatile data storage memory.
- FIG. 1 is a schematic diagram of instantaneous data throughput in IOPS versus a range of time in accordance with an embodiment of the invention
- FIG. 2 is a schematic diagram of number of logical blocks versus a range of transactions in accordance with an embodiment of the invention
- FIG. 3 is a schematic diagram of instantaneous data throughput in IOPS versus a range of time in accordance with an embodiment of the invention
- FIG. 4 schematically illustrates a system according to an embodiment of the invention
- FIG. 5 is a schematic flow chart diagram of a method according to an embodiment of the invention.
- FIG. 6 is a schematic flow chart diagram of a method according to an embodiment of the invention.
- the terms “plurality” and “a plurality” as used herein may include, for example, “multiple” or “two or more”.
- the terms “plurality” or “a plurality” may be used throughout the specification to describe two or more components, devices, elements, units, parameters, or the like.
- the method embodiments described herein are not constrained to a particular order or sequence. Additionally, some of the described method embodiments or elements thereof can occur or be performed simultaneously, at the same point in time, or concurrently.
- predefined criterions that once fulfilled may trigger stages such as determining a number of logical blocks to be merged and writing data sectors. It is noted that for simplicity of explanation alone there is provided an example of such a predefined criterion where a data block of the extended random sequence buffer becomes full. It is noted that other predefined criterions can be enforced. Some predefined criteria are listed in various parts of the specification and claims. Any reference to the fullness of the data block should be interpreted as being applied to any other predefined criterion.
- Embodiments of the invention may provide for a method and system for managing flash memory to reduce peak to average ratio of write throughput in flash based storage systems.
- Embodiments of the invention may interact with an interface and may receive an input of a plurality of data sectors. The data sectors may then be stored in an extended random sequence buffer contained in non-volatile memory. For each data sector received from the interface a pointer may be created corresponding to an associated logical block and a storage location of the data sector in the non-volatile extended random sequence buffer. The pointer may be written to a data management structure. Once one of a plurality of data blocks in the extended random sequence buffer in the non-volatile memory may become full, then a number of logical blocks may be merged. The data sectors associated with the said number of logical blocks may be written from the extended random sequence buffer to the primary non-volatile data storage memory.
- the merge operation may be initiated when any fixed portion of a data block may become full or the like.
- flash memory controller may be contained within the flash memory unit.
- a flash memory unit may include any or all of a volatile memory module, a non-volatile memory module, an interface module and may include additional modules.
- the flash memory controller may be contained in a control unit, separate from the flash memory unit.
- the flash memory controller may be contained on a logical device, such as a computer.
- the interaction with an interface may be an interaction with an interface of a logic device, such as a computer.
- a logic device such as a computer.
- Such logical device may be capable of sending and receiving sectors of data and may further be capable of sending and receiving data that contains information including commands corresponding to actions performed on the data by the flash memory controller and address information for the data sectors assigned by the logic device.
- Logic may refer to hardware, software, other logic, or any suitable combination of the preceding. Certain logic may manage the operation of a device, and may comprise, for example, a processor.
- An interface may refer to logic of a device operable to receive input for the device, send output from the device, perform suitable processing of the input or output or both, or any combination of the preceding, and may comprise one or more ports, conversion software, or both
- a data sector may refer to a packet of data which may be limited to a single data size, may vary in sizes or both in different embodiments of the invention.
- a data sector is a packet of data that may be smaller in size than the size of a single erase block of the corresponding flash memory unit.
- the input of a stream of data sectors may occur in response to an action or command executed by the flash controller.
- the input consisting of a stream of data sectors may occur when the data sectors are present on the interface.
- the extended random sequence buffer contained in the volatile memory may be an allocated portion of the flash memory containing the primary non-volatile data storage of the flash memory unit.
- the extended random sequence buffer may be contained in a memory module in the non-volatile memory separate from the flash memory module containing the primary non-volatile data storage of the flash memory unit.
- the extended random sequence buffer may be a collection of auxiliary data blocks which may hold short write transactions until a later stage when the data of these transactions may be merged.
- Embodiments of the invention may refer to a pointer as a logic data type whose value refers directly or otherwise, using its address, to another value or segment of data stored elsewhere in a memory of a logic device.
- logic devices include, but are not limited to a flash memory unit.
- it may be cheaper in time and space to copy and dereference pointers than it is to copy and access the data to which the pointers point.
- a pointer may be used in data structures to implement and control the data structures.
- the data structures include one or more of lists, queues and trees.
- the pointers may be absolute such that the actual physical or virtual address is used in the pointer.
- the pointers may be relative, such that the pointer addresses represent a set offset from an absolute start or nominal address.
- pointers are not limited to a specific data size or format.
- Embodiments of the invention may provide for a data management structure arrangement that may include a data management structure stored in the volatile memory portion of the flash memory unit and may also include a data management structure stored in a non-volatile memory module of the flash memory unit.
- the data management structure may be implemented in one or more forms of storing data. These may include an array, a link list, a hash table, a heap, a tree, a stack or a queue.
- the data management structure may store information including data, metadata, pointers or other data types which can be implemented to store address and location information.
- a method may be provided.
- the method may include (i) receiving a plurality of data sectors, wherein each received data sector may be associated with an erase block out of a plurality of erase blocks; (ii) writing the data sectors into data blocks of the extended random sequence buffer in the non-volatile memory; (iii) creating pointers in a data management structure, for each data sector corresponding to an associated logical block and a storage location of the data sector in the non-volatile extended random sequence buffer; (iv) if during said writing of the data sectors a data block in the extended random sequence buffer in the non-volatile memory becomes full, then determining a set of logical blocks to be merged and writing the data sectors corresponding to said set of logical blocks from the extended random sequence buffer to the primary non-volatile data storage memory
- the plurality of data sectors may be received or become available at the interface from a logical device.
- logical device may be a computer.
- the erase block may refer to a set size portion of memory corresponding to the smallest block of data that may be erased by the flash controller or as a response to an erase request by the flash controller, without affecting the data contained in any other portion of the memory.
- the plurality of erase blocks may refer to some or all of the erase blocks which may be stored in the primary non-volatile data storage, the extended random sequence buffer or both.
- the extended random sequence buffer in the non-volatile memory may contain a plurality of data blocks among other elements.
- data blocks of the extended random sequence buffer may have the same data storage size as the erase blocks of the primary non-volatile data storage memory.
- the data blocks of the extended random sequence buffer may contain a plurality of data pages.
- the data blocks and data pages of the sequence memory may have the same write, read and erase properties as the erase blocks and pages of the primary non-volatile data storage memory.
- writing incoming data sectors to the data blocks in the extended random sequence buffer may be accomplished by writing one or a set plurality of incoming data sectors to one of the plurality of data blocks, wherein the data block to be written to may be selected from a plurality of data blocks using various available processes.
- the data block to be written may be determined by utilizing a random function to choose a data block from a plurality of data blocks which may be all or some of the data blocks contained in the extended random sequence buffer.
- the data block to be written may be determined by executing a hashing function which produces a hash value which may be associated with one of a plurality of data blocks of the extended random sequence buffer.
- a pointer or a plurality of pointers may be created in a data management structure for each data sector write or erase operation, which may include write and erase operations performed on the extended random sequence buffer and/or the primary non-volatile data storage memory.
- a single pointer or a plurality of pointers may contain information associated with the corresponding logical block of the data sector and the address location of the data sector.
- the address location of the data sector may refer to a data block or page in the extended random sequence buffer and/or the primary non-volatile data storage memory.
- one or more additional pointers may be required for each data sector, Pointers may be implemented to point to or between the pointers associated with the logical block and data address, as well as point to data management structures and the like.
- a logical block may refer to a variable or other parameter which may be associated with a plurality of data sectors, wherein the data sectors may be stored in the primary non-volatile data storage memory, in the extended random sequence buffer or not yet received at the interface by the flash memory unit.
- a logical block parameter may be assigned to data sectors by the logical device during or before the data sectors are received by the flash memory controller.
- data sectors may be assigned one of a plurality of logical blocks by the flash controller when the data sectors are received at the interface or at another time.
- the total plurality of logical blocks may correspond to the number of available data blocks in the primary non-volatile data storage memory.
- the maximum number of data sectors which may be associated with any one logical block may be such that the total data size of the data sectors assigned to a logical block does not exceed the size of a single erase block of the flash memory unit.
- data sectors may be merged.
- Merging may refer to a process that may include collecting the most recent data sectors or pages associated with a logical block in the extended random sequence buffer, which may be appended with other data associated with the logical block contained in the primary non-volatile data storage memory.
- the merged data may then be written to an available erase block and the former erase block may be declared as free and may be further erased.
- the total size of the data merged block may be equal or less than the size of a single erase block.
- Merging may refer to a process that may include collecting the most recent data of a logical block, which may be merged with other data contained in a single erase block. The block of data may then be written to a new erase block and the former erase block may be declared as free and may be further erased.
- a merge operation may be initiated once every time a fixed portion of a data block may become full. For example every half of a data block.
- each new sector to be written to the flash memory unit may be assessed regarding its write target.
- the write target may refer to a choice of one of a plurality of memory modules contained in the non-volatile memory of the flash memory unit.
- the memory modules may include, but are not restricted to, a random access memory module and a sequential access memory module.
- the amount of merge operations may become more than desired by the flash memory design. For example, when a sequence of writes is performed to the memory system such that each write belongs to a different data block, each write operation may require an independent merge operation.
- a single merge operation may take an amount of time which may be of the order of the timeout permitted to complete the write operation which may include the merge operation in its allotted time. This may cause the system to fail to perform all requested write operations in time.
- the use of the extended random sequence buffer may be able to overcome the excess time required by write operations.
- each write operation may consist of writing a data sector of 4 KB and where the address of each write operation may be randomly chosen from the primary non-volatile data storage memory
- all data transaction may be performed initially to the extended random sequence buffer. This may allow the throughput of data for these write operations to be relatively high and may be primarily determined by the write speed that may be supported by the flash memory unit.
- the extended random sequence buffer may become close to full, it may be necessary to vacate some of the data blocks of the information written in them.
- Each data block of the extended random sequence buffer may contain pages which have been written with incoming data sectors associated with a large portion or all of the plurality of logical block corresponding to the data blocks in the primary non-volatile data storage memory.
- the flash memory controller may be required to merge a very large number of data sectors associated with the logical blocks involved.
- Each merge operation may require a substantial amount of time, which may decrease the possible throughput of the flash memory device for the duration of the merge operations. The duration of the merge operation may continue until at least one or a defined number of data blocks in the extended random sequence buffer are freed.
- a data block being freed may refer to a condition including when the data block does not contain information which has not been written to the primary non-volatile data storage memory, when the data block is actually free of written data and when a variable associated with the data block has been set to represent that the data block is available for writing data sectors. When at least one block may be freed the high rate of throughput may be restored.
- FIG. 1 is a schematic diagram of instantaneous data throughput in Input/Output Operations Per Second (IOPS) versus a range of time in accordance with an embodiment of the invention.
- IOPS Input/Output Operations Per Second
- FIG. 1 illustrates a data block mapping system implementing an extended random sequence buffer according to an embodiment of the invention which implements no further algorithms with the block mapping process.
- Curve 11 of FIG. 1 illustrates that without further algorithms in addition to the block mapping process, a non-stable throughput behavior may result when random writes are performed to the flash memory system.
- FIG. 1 compares instantaneous IOPS (curve 11 ) with a theoretical IOPS over a time range (curve 12 ).
- the instantaneous throughput in FIG. 1 represents a measurement in IOPS.
- IOPS may refer to a measurement of the number of 4 KB write transactions per second.
- the theoretical IOPS may represent an average theoretically computed for the IOPS illustrated IOPS measurement.
- FIG. 1 shows that due to the nature of the flash memory unit and the block mapping process the theoretical average throughput of data to the flash memory is a steady mean over the long term, but can drop much lower than the long term average for a substantially long period of time.
- N ERSB may refer to the number of data blocks in the extended random sequence buffer
- N pgs may refer to the number of pages in one data block in the extended random sequence buffer
- f may refer to the number of transaction timeout durations required to complete a merge operation
- a transaction timeout may refer to a period of time which may be required by the flash memory unit specification as the maximum period of time permitted to complete a single write operation. If a write transaction may have not completed by this time, the memory system is not compliant with the specification.
- the extended random sequence buffer was designed to cope with this limitation, which if not handled appropriately, may lead to violations of the timeout in cases where random access data sectors are written.
- the peaky behavior illustrated in curve 11 may result from the following policy: A writing operation of such data sectors that may reside in different logical blocks may each require a full data block merge. A merge operation may take a period of time longer than one timeout duration (e.g., f such timeouts). Therefore, a random access sector write may be problematic.
- the extended random sequence buffer may solve this issue by writing all such sectors to a special buffer (which represents the peaks in curve 11 ), and may use the remaining time of the transaction timeout for performing merges (this remaining time is represented in the lower values of the IOPS—between said peaks).
- the extended random sequence buffer when the extended random sequence buffer may become close to full, more sectors may be stored into the extended random sequence buffer as they arrive to the interface and also a merge process may be initiated.
- a merge operation When a writing operation of a data sector to the extended random sequence buffer may be complete, in the remaining time until the timeout, a merge operation may be performed.
- the sharp transitions from low IOPS values and to high IOPS values occur each 300 seconds.
- the transitions between high IOPS values to low IOPS values occur at the same cycle but at a delay of about 200 seconds.
- a single merge operation may be complete. This method may permit the merge operations to be performed within the spare time allotted for write operations without violating the transaction timeout specification.
- each merge operation may free more than one data sector in the extended random sequence buffer. This may permit freeing data sectors with less than one merge operation for each data sector.
- N LB N LB may refer to the number of logical blocks associated to the data blocks of the primary non-volatile data storage memory
- SI T may refer to the time duration for writing a single page to a data block in the primary non-volatile data storage memory and/or the extended random sequence buffer
- M T may refer the time duration for performing one merge operation.
- the time duration during which the throughput of the flash memory unit may be low may be for example over an hour.
- a method may be implemented for managing the memory system in a way which may circumvent severe fluctuations in the IOPS performance.
- the method may also be capable of an average performance range which may be the same or similar to the throughput range of the standard flash memory unit utilizing the extended random sequence buffer to implement a block mapping process.
- a method may be implemented which may be capable of performing at an equivalent long term average IOPS throughput rate as a flash memory unit which implements no further algorithms with the block mapping process and the extended random sequence buffer, but with nearly no fluctuations with respect to the average IOPS throughput.
- the impulsive behavior of the write IOPS may be mitigated by performing periodic merges.
- Periodic merges may be performed before the extended random sequence buffer becomes almost full.
- the extended random sequence buffer being full may refer to a condition when data blocks in the extended random sequence buffer are not able to accept additional data sector writes.
- periodic merges of the data in the extended random sequence buffer may be initiated at periodic time intervals or number of data writes.
- merges of the data may be initiated every time one of the data blocks of the extended random sequence buffer may become fully written.
- a data block becoming fully written may refer to a condition when there are no pages in the data block which are able to accept a data sector write without being erased.
- every time one of a plurality of data block of the extended random sequence buffer may become full a defined number of logical blocks may be merged.
- the data sectors associated with a logical block are written to a single data block in the primary non-volatile data storage memory.
- the number of logical blocks to be merged out of the total logical blocks which are associated with data sectors stored in the extended random sequence buffer may be determined according to an algorithm which may determine a number based on one or more inputs and one or more predefined factors.
- Function g(*) may refer to some integer valued function. According to some embodiments of the invention, A(t)*Nelb(t)) need not be an integer. It may be desired for simplicity of implementation that merges of an integer number of logical blocks are performed. According to embodiment of the invention, it may be necessary to transform the number A(t)*Nelb(t)) to an integer.
- a ceil(x) function may be implemented to determine a corresponding integer value of A(t)*Nelb(t)).
- a ceil(x) function may refer to a function which may output the smallest integer not smaller than the input x.
- a ceil(x) function may implement two functions, namely, floor(x), which may return the largest integer not larger than x, and (x ⁇ floor(x)).
- the outcome of floor(x) may be used to determine the number of merge operations to perform.
- the outcome of (x ⁇ floor(x)) may be stored in an accumulator. If the total value of the accumulator exceeds unity, then an extra merge operation may be performed.
- Nelb(t)) may refer to the instantaneous number of logical blocks which may have at least one page in the extended random sequence buffer at a time t
- A(t) may refer to a predefined time variable function which may be based on one or more inputs in addition to time.
- Nersb may refer to the number of data blocks in the extended random sequence buffer
- Npgs may refer to the number of pages in one data block in the extended random sequence buffer
- f may refer to the number of transaction timeout durations required to complete a merge operation.
- the particular logical blocks which may be merged when at least one data block becomes full may be selected through various processes, including random functions, hash function and algorithms which may require one or more inputs.
- a round robin procedure may refer to a method which may be implemented for choosing a resource from a list of a plurality of available resources and which may result in load balancing among the plurality of available resources.
- a simple round robin procedure may include a scheduler selecting one resource out of a plurality of resources which may be pointed to by a counter or the like from a list of available resources. The counter or the like may then be incremented and if the end of the list or predefined condition occurs the counter may be set to a predefined position in the list which may include the beginning of the list.
- a round robin procedure may result in reducing overuse of resources and prevent resource starvation.
- an ordering permutation ⁇ (•) is defined over all the block indices in the memory system.
- the index of a data block which may be associated with the kth merge may be determined by the formula pi(k molulo Nlb). For example, if a flash memory unit contains 4096 logical blocks, a permutation array of size 4096 may be defined, where each entry may hold an index to a logical block and where each logical block index may appear once in the array.
- a variable array index may then be defined which may be initialized to 0.
- a logical block is determined corresponding to the logical block index pointed to by the array at the location array index.
- the array index may then be incremented by 1 modulus 4096 . If a logical block whose index may have been determined by the logical block index does not have any pages in the extended random sequence buffer, a subsequent logical block may be determined by the above process. This process may be repeated until a logical block is found which is mapped to at least on data page in the extended random sequence buffer. The selected logical block may be then used in a merge operation.
- the benefit of implementing an additional algorithm which may initiate a merge of the data associated with a determined plurality of logical blocks may be to prevent a situation where the extended random sequence buffer becomes almost full and may need to devote a substantial amount of time to merging data sectors to the primary non-volatile data storage memory when throughput of the flash memory unit is greatly reduced.
- This method may be referred to as ERSB shaping or just shaping algorithm.
- each time a data block in the extended random sequence buffer may become full some of the logical blocks which may have associated pages in the extended random sequence buffer are merged.
- the number of logical blocks to be merged in such a condition may be set so that by the time one block in the extended random sequence buffer may become full another data block in the extended random sequence buffer may be declared vacated.
- Vacated may refer to a condition where the data block may accept directly or after a further erase operation a maximum number of data sector writes for the data block size and data sector writing method.
- FIG. 2 is a schematic diagram of number of logical blocks versus a range of transactions in accordance with an embodiment of the invention.
- the buffer includes twenty different data blocks and seventeen curves 14 ( 1 )- 14 ( 17 ) represent the fullness level of these seventeen data blocks. These curves illustrate a gradual decrement in the number of logical blocks that have data sectors in each of the data blocks of the buffer due to gradual merging operations. It is assumed that different data blocks are filled at different times and that the fullness level of one block resembles that of another block but with a time shift.
- FIG. 2 may depict an example number of logical blocks with pages mapped to each data block in the extended random sequence buffer.
- FIG. 2 illustrates twenty extended random sequence buffer blocks and two hundred and thirty six logical blocks.
- the number of extended random sequence buffer data blocks and the number of associated logical blocks illustrated in FIG. 2 are solely provided as an example and in no way limit the number of extended random sequence buffer or the number of logical blocks in the embodiments of the invention.
- FIG. 2 illustrates that each block may become occupied with pages, with data sectors written to them, from all or most of the logical blocks. It is shown that once a data block becomes fully written or full, another extended random sequence buffer data block may be used as the destination for data sector write transactions and may become more populated with each transaction. When an extended random sequence buffer data block becomes full all other blocks which have stored data sectors can be seen to decrease the amount of stored pages as a merge is performed.
- FIG. 2 shows that when the last extended random sequence buffer data block is about to become filled with data sectors, another data block in the extended random sequence buffer may become empty. This may allow writing transactions to continue without stopping to perform merges of the data sectors.
- each instant of the writing transaction processes there may be an occupancy distribution of the logical blocks among all the extended random sequence buffer data blocks such that some blocks may have more logical blocks associated with them while some data blocks may have less.
- a uniform distribution of merge operation may be achieved and the throughput of the instantaneous write throughput may be maintained at a relatively constant rate compared to a system implementing block mapping process and utilizing extended random sequence buffer without further algorithms.
- FIG. 3 is a schematic diagram of instantaneous data throughput in IOPS versus a range of time in accordance with an embodiment of the invention.
- FIG. 3 illustrates the effect of implementing the shaping algorithm together with the block mapping process utilizing the extended random sequence buffer.
- Curve 13 of FIG. 3 shows that the throughput of embodiments of the invention implementing the shaping algorithm experience much less variation in instantaneous throughput rates over time as may be compared to FIG. 1 .
- Curve 13 is much closer to the theoretical IOPS curve 12 ′ than curve 11 of FIG. 1 is close to curve 12 of FIG. 1
- FIG. 4 schematically illustrates a system 10 according to embodiments of the invention.
- the system includes an interface ( 20 ) that may be linked to a memory controller ( 30 ) and may be also linked to a non-volatile memory module ( 60 ) and a volatile memory module ( 80 ).
- the non-volatile memory module ( 60 ) may contain a primary non-volatile data storage memory ( 50 ) and an extended random sequence buffer ( 70 ). Some data structures such as the extended random sequence buffer ( 70 ) may be illustrated as being contained outside the primary non-volatile data storage memory ( 50 ), although these structures may be a single module which may be partitioned logical or by another non-physical partition.
- the extended random sequence buffer ( 70 ) may store incoming data sectors received from the interface ( 20 ) in a plurality of data blocks.
- the memory controller may write to the extended random sequence buffer ( 70 ) the incoming data sectors from the interface ( 20 ).
- One or more data management structures which may store pointers associated with written data sectors may be stored in one or more of the extended random sequence buffer ( 70 ), the primary non-volatile data storage memory ( 50 ) and the volatile memory ( 80 ).
- Data sectors that may be associated with the same logical block may be written in the extended random sequence buffer ( 70 ) until being merged.
- the merged blocks may be written to the primary non-volatile data storage memory ( 50 ).
- FIG. 5 is a schematic flow chart diagram of a method 500 in accordance with an embodiment of the invention.
- a flash memory controller may receive data sectors from an interface ( 505 ). Each data sector may then be written into an extended random sequence buffer in the non-volatile memory ( 510 ).
- the write action ( 510 ) may be automatic in response to data sectors being received at the interface ( 505 ).
- the method may wait until a preset plurality of data sectors are received at the interface ( 505 ) or some further action triggers the write action ( 510 ).
- the extended random sequence buffer ( 510 ) may reference a memory section which may be a part of the non-volatile memory module of the flash memory unit. In one embodiment of the invention, the extended random sequence buffer may be located in the same module as the primary non-volatile data storage memory.
- the method may create a pointer in a data management structure ( 515 ).
- the data management structure may be contained in one or both of a volatile memory and a non-volatile memory of the flash memory unit.
- the method may perform an additional process, otherwise the method will continue to perform steps 505 , 510 and 515 .
- the method may determine the instantaneous number of logical blocks with at least one associated page in a data block contained in the extended random sequence buffer ( 525 ). According to one embodiment of the invention determining the instantaneous number of logical blocks with at least one associated page in a data block contained in the extended random sequence buffer may be accomplished by requesting or reading a measurement of the state of the data blocks contained in the extended random sequence buffer.
- the instantaneous number of logical blocks with at least one associated page in a data block contained in the extended random sequence buffer may be determined as a result of a function which may look at historical measurements of the state of the data blocks or other measurements associated with one or more previous states of the data blocks in the extended random sequence buffer.
- a binary array may be used to hold for every logical block in the system an indication to whether or not there is at least one page of this block located in the extended random sequence buffer. Such an array may be modified, if necessary, after each page write operation and after each merge operation.
- the method may then determine a set of logical blocks to be merged based on the instantaneous number of logical blocks with at least one associate page in a data block contained in the extended random sequence buffer ( 530 ).
- the set of blocks to be merged may be directly proportional to the instantaneous number of logical blocks with at least one associated page in a data block contained in the extended random sequence buffer.
- the number of blocks to be merged may be a result of an algorithm that may take into account one or more inputs, measurements and the like, including the instantaneous number of logical blocks with at least one associated page in a data block contained in the extended random sequence buffer.
- An ordering permutation may be executed to select from a plurality of logical blocks which may be associated with data sectors stored in pages in the extended random sequence buffer a set of logical block determined in 530 ( 540 ). According to embodiments of the invention various ordering permutations may be used, including permutations which may be modified by one or more inputs as the method proceeds.
- the method may then write the data sectors corresponding to said number of logical blocks from the extended random sequence buffer to the primary non-volatile data storage memory ( 550 ).
- According to embodiments of the invention 550 may be done by merging data sectors associated with a logical block stored in the extended random sequence buffer with data sectors associated with the logical block stored in the primary non-volatile data storage memory. The merged data sectors may then be written to an available data block in the primary non-volatile data storage memory. According to one embodiment of the invention the primary non-volatile data storage memory data block may then or after a further erase process be declared as available.
- the ERSB may typically be empty.
- the above smoothing algorithm may not be used until the ERSB is full for the first time. This initially permits very high IOPs at first at the expense of lower ones later on. After the first time the ERSB has been filled, the above smoothing algorithm may be applied for subsequent transactions.
- some merge operation may be initiated even when there are no transactions at all, and thus, over time, emptying the ERSB.
- a sort burst of random transactions may appear to have very high IOPs, and during rest time, merge operations may be performed to empty the ERSB.
- the above smoothing algorithm may be used, and a stable and sustained IOPs performance will be observed.
- the algorithm may not be applied until the device is filled to a fraction of its capacity, e.g., half, two-thirds, three-quarters, four-fifths, etc.
- the above smoothing algorithm may be applied with an adapted value for alpha, such that the IOPs drops will not be as severe as before, thereby shaping the IOPs performance over time.
- a computer readable medium can be provided that is non-transitory.
- the computer readable medium can store instructions that once executed by a computer may result in the implementation of any of the mentioned above methods.
- FIG. 6 is a schematic flow chart diagram of a method 600 in accordance with an embodiment of the invention.
- Method 600 differs from method 500 by including stage 620 instead of stage 520 . While stage 520 of method 500 is illustrated as including checking whether a data block in the extended random sequence buffer if full, stage 620 includes checking if a predefined condition is fulfilled. The predetermined condition is fulfilled before the buffer is full.
- Stage 620 may include performing stage 520 but it may also include one or more other predefined criteria, some of which illustrated in the specification.
- a predefined criterion may include: (i) at least two data blocks out of multiple data blocks of the buffer become full; (ii) a predefined fraction of the buffer becomes full, wherein the predefined fraction does not exceed a half of the buffer; (iii) the predefined criterion may change during a lifespan of the non-volatile memory device; (iv) a first portion of the buffer is full for a first time or when a second portion of the buffer is full after the first portion was full for the first time; wherein a size of the first portion differs from a size of the second portion, the first portion may be bigger than the second portion; (v) at least one data block of the buffer becomes empty and at least one data block of the buffer becomes full.
Abstract
Description
IOPS=N ERSB *N pgs −f*N LB/(N ERSB *N pgs −f*N LB)*SI T +N LB *M T
A(t)=1/{Nersb−(f*Nelb(t)/Npgs)}.
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