US8884427B2 - Low CTE interposer without TSV structure - Google Patents
Low CTE interposer without TSV structure Download PDFInfo
- Publication number
- US8884427B2 US8884427B2 US13/828,938 US201313828938A US8884427B2 US 8884427 B2 US8884427 B2 US 8884427B2 US 201313828938 A US201313828938 A US 201313828938A US 8884427 B2 US8884427 B2 US 8884427B2
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- United States
- Prior art keywords
- encapsulant
- microelectronic
- dielectric region
- conductive elements
- microelectronic assembly
- Prior art date
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- 238000004377 microelectronic Methods 0.000 claims abstract description 76
- 239000008393 encapsulating agent Substances 0.000 claims abstract description 67
- 238000000034 method Methods 0.000 claims description 28
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 22
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 12
- 229910052802 copper Inorganic materials 0.000 claims description 12
- 239000010949 copper Substances 0.000 claims description 12
- 230000005496 eutectics Effects 0.000 claims description 11
- 239000000203 mixture Substances 0.000 claims description 11
- 229910000679 solder Inorganic materials 0.000 claims description 10
- 239000003989 dielectric material Substances 0.000 claims description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 7
- 238000002844 melting Methods 0.000 claims description 7
- 230000008018 melting Effects 0.000 claims description 7
- 229910052718 tin Inorganic materials 0.000 claims description 7
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 6
- 229910000570 Cupronickel Inorganic materials 0.000 claims description 6
- 229910000990 Ni alloy Inorganic materials 0.000 claims description 6
- 239000011159 matrix material Substances 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
- 229910052738 indium Inorganic materials 0.000 claims description 5
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 43
- 238000004519 manufacturing process Methods 0.000 description 12
- 239000004065 semiconductor Substances 0.000 description 12
- 238000005304 joining Methods 0.000 description 8
- 239000000758 substrate Substances 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000000227 grinding Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 230000001413 cellular effect Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000005299 abrasion Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000002923 metal particle Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000003351 stiffener Substances 0.000 description 1
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- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
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- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
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- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
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- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Electromagnetism (AREA)
- Ceramic Engineering (AREA)
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
Claims (19)
Priority Applications (7)
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US13/828,938 US8884427B2 (en) | 2013-03-14 | 2013-03-14 | Low CTE interposer without TSV structure |
TW103108845A TWI559474B (en) | 2013-03-14 | 2014-03-12 | Low cte interposer without tsv structure and method |
PCT/US2014/027699 WO2014152756A1 (en) | 2013-03-14 | 2014-03-14 | Low cte interposer without tsv structure and method |
CN201480022444.3A CN105122445B (en) | 2013-03-14 | 2014-03-14 | Low CTE mediplates without TSV structure and method |
KR1020157027609A KR102037114B1 (en) | 2013-03-14 | 2014-03-14 | Low CTE interposer without TSV structure and method |
US14/524,280 US9558964B2 (en) | 2013-03-14 | 2014-10-27 | Method of fabricating low CTE interposer without TSV structure |
US15/407,842 US10396114B2 (en) | 2013-03-14 | 2017-01-17 | Method of fabricating low CTE interposer without TSV structure |
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US13/828,938 US8884427B2 (en) | 2013-03-14 | 2013-03-14 | Low CTE interposer without TSV structure |
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US14/524,280 Division US9558964B2 (en) | 2013-03-14 | 2014-10-27 | Method of fabricating low CTE interposer without TSV structure |
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US14/524,280 Active US9558964B2 (en) | 2013-03-14 | 2014-10-27 | Method of fabricating low CTE interposer without TSV structure |
US15/407,842 Active 2033-06-12 US10396114B2 (en) | 2013-03-14 | 2017-01-17 | Method of fabricating low CTE interposer without TSV structure |
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US15/407,842 Active 2033-06-12 US10396114B2 (en) | 2013-03-14 | 2017-01-17 | Method of fabricating low CTE interposer without TSV structure |
Country Status (5)
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US (3) | US8884427B2 (en) |
KR (1) | KR102037114B1 (en) |
CN (1) | CN105122445B (en) |
TW (1) | TWI559474B (en) |
WO (1) | WO2014152756A1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10181447B2 (en) * | 2017-04-21 | 2019-01-15 | Invensas Corporation | 3D-interconnect |
US10748840B2 (en) | 2008-05-09 | 2020-08-18 | Invensas Corporation | Chip-size, double side connection package and method for manufacturing the same |
US11749586B2 (en) | 2021-03-24 | 2023-09-05 | Samsung Electronics Co., Ltd. | Semiconductor device including through via structure |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8884427B2 (en) * | 2013-03-14 | 2014-11-11 | Invensas Corporation | Low CTE interposer without TSV structure |
US9213361B1 (en) * | 2013-09-18 | 2015-12-15 | Amazon Technologies, Inc. | Temperature sensor in flex circuit |
US9916999B2 (en) | 2015-06-04 | 2018-03-13 | Micron Technology, Inc. | Methods of fabricating a semiconductor package structure including at least one redistribution layer |
KR102450580B1 (en) | 2017-12-22 | 2022-10-07 | 삼성전자주식회사 | Semiconductor Device having a Structure for Insulating Layer under Metal Line |
Citations (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4829403A (en) * | 1987-01-20 | 1989-05-09 | Harding Ade Yemi S K | Packaging arrangement for energy dissipating devices |
US4855868A (en) * | 1987-01-20 | 1989-08-08 | Harding Ade Yemi S K | Preformed packaging arrangement for energy dissipating devices |
US5030796A (en) * | 1989-08-11 | 1991-07-09 | Rockwell International Corporation | Reverse-engineering resistant encapsulant for microelectric device |
US5406117A (en) * | 1993-12-09 | 1995-04-11 | Dlugokecki; Joseph J. | Radiation shielding for integrated circuit devices using reconstructed plastic packages |
US5932254A (en) * | 1995-09-22 | 1999-08-03 | Tessera, Inc. | System for encapsulating microelectronic devices |
US5990418A (en) * | 1997-07-29 | 1999-11-23 | International Business Machines Corporation | Hermetic CBGA/CCGA structure with thermal paste cooling |
US6046910A (en) * | 1998-03-18 | 2000-04-04 | Motorola, Inc. | Microelectronic assembly having slidable contacts and method for manufacturing the assembly |
US6126428A (en) * | 1994-12-29 | 2000-10-03 | Tessera, Inc. | Vacuum dispense apparatus for dispensing an encapsulant |
US6127724A (en) * | 1996-10-31 | 2000-10-03 | Tessera, Inc. | Packaged microelectronic elements with enhanced thermal conduction |
US6255738B1 (en) * | 1996-09-30 | 2001-07-03 | Tessera, Inc. | Encapsulant for microelectronic devices |
US6365975B1 (en) * | 1997-04-02 | 2002-04-02 | Tessera, Inc. | Chip with internal signal routing in external element |
US6373273B2 (en) * | 1999-02-16 | 2002-04-16 | Micron Technology, Inc. | Test insert containing vias for interfacing a device containing contact bumps with a test substrate |
US6602740B1 (en) * | 1999-11-24 | 2003-08-05 | Tessera, Inc. | Encapsulation of microelectronic assemblies |
US6873039B2 (en) * | 2002-06-27 | 2005-03-29 | Tessera, Inc. | Methods of making microelectronic packages including electrically and/or thermally conductive element |
WO2005059993A2 (en) | 2003-12-17 | 2005-06-30 | Tru-Si Technologies, Inc. | Packaging substrates for integrated circuits and soldering methods |
US7501839B2 (en) * | 2005-04-21 | 2009-03-10 | Endicott Interconnect Technologies, Inc. | Interposer and test assembly for testing electronic devices |
US7510912B2 (en) * | 2005-06-15 | 2009-03-31 | Endicott Interconnect Technologies, Inc. | Method of making wirebond electronic package with enhanced chip pad design |
US7749882B2 (en) * | 2006-08-23 | 2010-07-06 | Micron Technology, Inc. | Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices |
US20100327421A1 (en) * | 2009-06-30 | 2010-12-30 | Stmicroelectronics Asia Pacific Pte. Ltd. | Ic package design with stress relief feature |
US20110080713A1 (en) | 2009-10-06 | 2011-04-07 | Shinko Electric Industries Co., Ltd. | Interposer mounted wiring board and electronic component device |
US20120187584A1 (en) | 2011-01-21 | 2012-07-26 | Stats Chippac, Ltd. | Semiconductor Device and Method for Forming Semiconductor Package Having Build-Up Interconnect Structure Over Semiconductor Die with Different CTE Insulating Layers |
US20120211885A1 (en) | 2011-02-17 | 2012-08-23 | Choi Yunseok | Semiconductor package having through silicon via (tsv) interposer and method of manufacturing the semiconductor package |
US20120267777A1 (en) * | 2011-04-22 | 2012-10-25 | Tessera Research Llc | Multi-chip module with stacked face-down connected dies |
US20120267751A1 (en) * | 2011-04-21 | 2012-10-25 | Tessera Research Llc | Interposer having molded low cte dielectric |
EP2555240A1 (en) | 2011-08-05 | 2013-02-06 | Unimicron Technology Corp. | Packaging substrate having embedded interposer and fabrication method thereof |
US20130050972A1 (en) * | 2011-08-23 | 2013-02-28 | Tessera, Inc. | Interconnection elements with encased interconnects |
US20130093097A1 (en) * | 2011-10-12 | 2013-04-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package-On-Package (PoP) Structure and Method |
US20130161833A1 (en) * | 2011-12-23 | 2013-06-27 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Extended Semiconductor Device with Fan-Out Interconnect Structure to Reduce Complexity of Substrate |
US20130214431A1 (en) * | 2012-02-16 | 2013-08-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fine-Pitch Package-on-Package Structures and Methods for Forming the Same |
US20130295727A1 (en) * | 2007-05-29 | 2013-11-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Programmable Semiconductor Interposer for Electronic Package and Method of Forming |
US20140048951A1 (en) * | 2012-08-14 | 2014-02-20 | Bridge Semiconductor Corporation | Semiconductor assembly with dual connecting channels between interposer and coreless substrate |
Family Cites Families (46)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0376255A (en) * | 1989-08-18 | 1991-04-02 | Fujitsu Ltd | Semiconductor device mounting structure |
JPH0372655A (en) | 1990-08-03 | 1991-03-27 | Hitachi Ltd | Semiconductor integrated circuit device |
US5483421A (en) | 1992-03-09 | 1996-01-09 | International Business Machines Corporation | IC chip attachment |
US5454161A (en) | 1993-04-29 | 1995-10-03 | Fujitsu Limited | Through hole interconnect substrate fabrication process |
US5455390A (en) | 1994-02-01 | 1995-10-03 | Tessera, Inc. | Microelectronics unit mounting with multiple lead bonding |
US6465743B1 (en) * | 1994-12-05 | 2002-10-15 | Motorola, Inc. | Multi-strand substrate for ball-grid array assemblies and method |
US5629241A (en) | 1995-07-07 | 1997-05-13 | Hughes Aircraft Company | Microwave/millimeter wave circuit structure with discrete flip-chip mounted elements, and method of fabricating the same |
US5884396A (en) * | 1997-05-01 | 1999-03-23 | Compeq Manufacturing Company, Limited | Transfer flat type ball grid array method for manufacturing packaging substrate |
TW460927B (en) * | 1999-01-18 | 2001-10-21 | Toshiba Corp | Semiconductor device, mounting method for semiconductor device and manufacturing method for semiconductor device |
TW512467B (en) | 1999-10-12 | 2002-12-01 | North Kk | Wiring circuit substrate and manufacturing method therefor |
KR20010094893A (en) | 2000-04-07 | 2001-11-03 | 정보영 | Loss protection device of valuables in bag |
TW512567B (en) | 2001-11-04 | 2002-12-01 | Uis Abler Electronics Co Ltd | Electricity resonance protection module |
US7535100B2 (en) * | 2002-07-12 | 2009-05-19 | The United States Of America As Represented By The Secretary Of The Navy | Wafer bonding of thinned electronic materials and circuits to high performance substrates |
JP3874108B2 (en) | 2002-08-13 | 2007-01-31 | 信越化学工業株式会社 | Epoxy resin composition |
US6734039B2 (en) * | 2002-09-06 | 2004-05-11 | Advanpack Solutions Pte Ltd. | Semiconductor chip grid array package design and method of manufacture |
US7166491B2 (en) | 2003-06-11 | 2007-01-23 | Fry's Metals, Inc. | Thermoplastic fluxing underfill composition and method |
US8641913B2 (en) | 2003-10-06 | 2014-02-04 | Tessera, Inc. | Fine pitch microcontacts and method for forming thereof |
US7622309B2 (en) * | 2005-06-28 | 2009-11-24 | Freescale Semiconductor, Inc. | Mechanical integrity evaluation of low-k devices with bump shear |
US7759782B2 (en) | 2006-04-07 | 2010-07-20 | Tessera, Inc. | Substrate for a microelectronic package and method of fabricating thereof |
TWI402017B (en) | 2008-07-23 | 2013-07-11 | Nec Corp | Semiconductor device and method for manufacturing the same |
JPWO2010024233A1 (en) | 2008-08-27 | 2012-01-26 | 日本電気株式会社 | Wiring board capable of incorporating functional elements and method for manufacturing the same |
US7776649B1 (en) * | 2009-05-01 | 2010-08-17 | Powertech Technology Inc. | Method for fabricating wafer level chip scale packages |
US8039304B2 (en) * | 2009-08-12 | 2011-10-18 | Stats Chippac, Ltd. | Semiconductor device and method of dual-molding die formed on opposite sides of build-up interconnect structures |
US8164158B2 (en) | 2009-09-11 | 2012-04-24 | Stats Chippac, Ltd. | Semiconductor device and method of forming integrated passive device |
US8368232B2 (en) * | 2010-03-25 | 2013-02-05 | Qualcomm Incorporated | Sacrificial material to facilitate thin die attach |
US8535989B2 (en) * | 2010-04-02 | 2013-09-17 | Intel Corporation | Embedded semiconductive chips in reconstituted wafers, and systems containing same |
US8278690B2 (en) * | 2010-04-27 | 2012-10-02 | Omnivision Technologies, Inc. | Laser anneal for image sensors |
US8896136B2 (en) * | 2010-06-30 | 2014-11-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Alignment mark and method of formation |
US8482111B2 (en) | 2010-07-19 | 2013-07-09 | Tessera, Inc. | Stackable molded microelectronic packages |
US8587126B2 (en) * | 2010-12-02 | 2013-11-19 | Tessera, Inc. | Stacked microelectronic assembly with TSVs formed in stages with plural active chips |
US8736066B2 (en) | 2010-12-02 | 2014-05-27 | Tessera, Inc. | Stacked microelectronic assemby with TSVS formed in stages and carrier above chip |
KR101870476B1 (en) * | 2011-03-16 | 2018-06-22 | 썬에디슨, 인크. | Silicon on insulator structures having high resistivity regions in the handle wafer and methods for producing such structures |
US8525321B2 (en) * | 2011-07-06 | 2013-09-03 | Fairchild Semiconductor Corporation | Conductive chip disposed on lead semiconductor package |
TWI503935B (en) * | 2011-10-17 | 2015-10-11 | 矽品精密工業股份有限公司 | Semiconductor package and fabrication method thereof |
US9401308B2 (en) * | 2013-03-12 | 2016-07-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging devices, methods of manufacture thereof, and packaging methods |
US8372741B1 (en) * | 2012-02-24 | 2013-02-12 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
TWI517274B (en) * | 2012-03-21 | 2016-01-11 | 矽品精密工業股份有限公司 | Fabrication method of wafer-scaled semiconductor package and fabrication method of wafer-scaled package substrate thereof |
US8978247B2 (en) | 2012-05-22 | 2015-03-17 | Invensas Corporation | TSV fabrication using a removable handling structure |
US8946884B2 (en) | 2013-03-08 | 2015-02-03 | Xilinx, Inc. | Substrate-less interposer technology for a stacked silicon interconnect technology (SSIT) product |
TWI496270B (en) * | 2013-03-12 | 2015-08-11 | 矽品精密工業股份有限公司 | Semiconductor package and method of manufacture |
US8884427B2 (en) * | 2013-03-14 | 2014-11-11 | Invensas Corporation | Low CTE interposer without TSV structure |
US9318452B2 (en) * | 2014-03-21 | 2016-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor packages and methods of forming the same |
JP2016048729A (en) * | 2014-08-27 | 2016-04-07 | 株式会社東芝 | Support substrate for temporary adhesive and manufacturing method of semiconductor device |
TWI559488B (en) * | 2014-12-27 | 2016-11-21 | 矽品精密工業股份有限公司 | Package structure and fabrication method thereof |
JP6313251B2 (en) * | 2015-03-12 | 2018-04-18 | 東芝メモリ株式会社 | Manufacturing method of semiconductor device |
US9818684B2 (en) * | 2016-03-10 | 2017-11-14 | Amkor Technology, Inc. | Electronic device with a plurality of redistribution structures having different respective sizes |
-
2013
- 2013-03-14 US US13/828,938 patent/US8884427B2/en active Active
-
2014
- 2014-03-12 TW TW103108845A patent/TWI559474B/en active
- 2014-03-14 CN CN201480022444.3A patent/CN105122445B/en active Active
- 2014-03-14 KR KR1020157027609A patent/KR102037114B1/en active IP Right Grant
- 2014-03-14 WO PCT/US2014/027699 patent/WO2014152756A1/en active Application Filing
- 2014-10-27 US US14/524,280 patent/US9558964B2/en active Active
-
2017
- 2017-01-17 US US15/407,842 patent/US10396114B2/en active Active
Patent Citations (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4855868A (en) * | 1987-01-20 | 1989-08-08 | Harding Ade Yemi S K | Preformed packaging arrangement for energy dissipating devices |
US4829403A (en) * | 1987-01-20 | 1989-05-09 | Harding Ade Yemi S K | Packaging arrangement for energy dissipating devices |
US5030796A (en) * | 1989-08-11 | 1991-07-09 | Rockwell International Corporation | Reverse-engineering resistant encapsulant for microelectric device |
US5406117A (en) * | 1993-12-09 | 1995-04-11 | Dlugokecki; Joseph J. | Radiation shielding for integrated circuit devices using reconstructed plastic packages |
US6126428A (en) * | 1994-12-29 | 2000-10-03 | Tessera, Inc. | Vacuum dispense apparatus for dispensing an encapsulant |
US5932254A (en) * | 1995-09-22 | 1999-08-03 | Tessera, Inc. | System for encapsulating microelectronic devices |
US6255738B1 (en) * | 1996-09-30 | 2001-07-03 | Tessera, Inc. | Encapsulant for microelectronic devices |
US6127724A (en) * | 1996-10-31 | 2000-10-03 | Tessera, Inc. | Packaged microelectronic elements with enhanced thermal conduction |
US6365975B1 (en) * | 1997-04-02 | 2002-04-02 | Tessera, Inc. | Chip with internal signal routing in external element |
US5990418A (en) * | 1997-07-29 | 1999-11-23 | International Business Machines Corporation | Hermetic CBGA/CCGA structure with thermal paste cooling |
US6046910A (en) * | 1998-03-18 | 2000-04-04 | Motorola, Inc. | Microelectronic assembly having slidable contacts and method for manufacturing the assembly |
US6373273B2 (en) * | 1999-02-16 | 2002-04-16 | Micron Technology, Inc. | Test insert containing vias for interfacing a device containing contact bumps with a test substrate |
US6602740B1 (en) * | 1999-11-24 | 2003-08-05 | Tessera, Inc. | Encapsulation of microelectronic assemblies |
US6873039B2 (en) * | 2002-06-27 | 2005-03-29 | Tessera, Inc. | Methods of making microelectronic packages including electrically and/or thermally conductive element |
WO2005059993A2 (en) | 2003-12-17 | 2005-06-30 | Tru-Si Technologies, Inc. | Packaging substrates for integrated circuits and soldering methods |
US7501839B2 (en) * | 2005-04-21 | 2009-03-10 | Endicott Interconnect Technologies, Inc. | Interposer and test assembly for testing electronic devices |
US7510912B2 (en) * | 2005-06-15 | 2009-03-31 | Endicott Interconnect Technologies, Inc. | Method of making wirebond electronic package with enhanced chip pad design |
US7749882B2 (en) * | 2006-08-23 | 2010-07-06 | Micron Technology, Inc. | Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices |
US20130295727A1 (en) * | 2007-05-29 | 2013-11-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Programmable Semiconductor Interposer for Electronic Package and Method of Forming |
US20100327421A1 (en) * | 2009-06-30 | 2010-12-30 | Stmicroelectronics Asia Pacific Pte. Ltd. | Ic package design with stress relief feature |
US20110080713A1 (en) | 2009-10-06 | 2011-04-07 | Shinko Electric Industries Co., Ltd. | Interposer mounted wiring board and electronic component device |
US20120187584A1 (en) | 2011-01-21 | 2012-07-26 | Stats Chippac, Ltd. | Semiconductor Device and Method for Forming Semiconductor Package Having Build-Up Interconnect Structure Over Semiconductor Die with Different CTE Insulating Layers |
US20120211885A1 (en) | 2011-02-17 | 2012-08-23 | Choi Yunseok | Semiconductor package having through silicon via (tsv) interposer and method of manufacturing the semiconductor package |
US20120267751A1 (en) * | 2011-04-21 | 2012-10-25 | Tessera Research Llc | Interposer having molded low cte dielectric |
US20120267777A1 (en) * | 2011-04-22 | 2012-10-25 | Tessera Research Llc | Multi-chip module with stacked face-down connected dies |
EP2555240A1 (en) | 2011-08-05 | 2013-02-06 | Unimicron Technology Corp. | Packaging substrate having embedded interposer and fabrication method thereof |
US20130050972A1 (en) * | 2011-08-23 | 2013-02-28 | Tessera, Inc. | Interconnection elements with encased interconnects |
US20130093097A1 (en) * | 2011-10-12 | 2013-04-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package-On-Package (PoP) Structure and Method |
US20130161833A1 (en) * | 2011-12-23 | 2013-06-27 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Extended Semiconductor Device with Fan-Out Interconnect Structure to Reduce Complexity of Substrate |
US20130214431A1 (en) * | 2012-02-16 | 2013-08-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fine-Pitch Package-on-Package Structures and Methods for Forming the Same |
US20140048951A1 (en) * | 2012-08-14 | 2014-02-20 | Bridge Semiconductor Corporation | Semiconductor assembly with dual connecting channels between interposer and coreless substrate |
Non-Patent Citations (1)
Title |
---|
International Search Report and Written Opinion for Application No. PCT/US2014/027699 dated Jul. 17, 2014. |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10748840B2 (en) | 2008-05-09 | 2020-08-18 | Invensas Corporation | Chip-size, double side connection package and method for manufacturing the same |
US10181447B2 (en) * | 2017-04-21 | 2019-01-15 | Invensas Corporation | 3D-interconnect |
US20190148324A1 (en) * | 2017-04-21 | 2019-05-16 | Invensas Corporation | 3D-Interconnect |
US11031362B2 (en) * | 2017-04-21 | 2021-06-08 | Invensas Corporation | 3D-interconnect |
US11929337B2 (en) | 2017-04-21 | 2024-03-12 | Invensas Llc | 3D-interconnect |
US11749586B2 (en) | 2021-03-24 | 2023-09-05 | Samsung Electronics Co., Ltd. | Semiconductor device including through via structure |
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US20140264794A1 (en) | 2014-09-18 |
KR102037114B1 (en) | 2019-10-28 |
TW201448138A (en) | 2014-12-16 |
US10396114B2 (en) | 2019-08-27 |
CN105122445B (en) | 2018-09-21 |
WO2014152756A1 (en) | 2014-09-25 |
US20150044820A1 (en) | 2015-02-12 |
KR20150129773A (en) | 2015-11-20 |
CN105122445A (en) | 2015-12-02 |
TWI559474B (en) | 2016-11-21 |
US20170194373A1 (en) | 2017-07-06 |
US9558964B2 (en) | 2017-01-31 |
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