US9271398B2 - Power supply module - Google Patents

Power supply module Download PDF

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Publication number
US9271398B2
US9271398B2 US13/481,887 US201213481887A US9271398B2 US 9271398 B2 US9271398 B2 US 9271398B2 US 201213481887 A US201213481887 A US 201213481887A US 9271398 B2 US9271398 B2 US 9271398B2
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Prior art keywords
power
disposed
inductor
electronic
package
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US20120262145A1 (en
Inventor
Da-Jung Chen
Chun-Tiao Liu
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Cyntec Co Ltd
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Cyntec Co Ltd
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Priority claimed from TW097105555A external-priority patent/TWI355068B/en
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Assigned to CYNTEC CO., LTD. reassignment CYNTEC CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, DA-JUNG, LIU, CHUN-TIAO
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/645Inductive arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00Details of transformers or inductances, in general
    • H01F27/02Casings
    • H01F27/027Casings specially adapted for combination of signal type inductors or transformers with electronic circuits, e.g. mounting on printed circuit boards
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007Types of components
    • H05K2201/1003Non-printed inductor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431Details of mounted components
    • H05K2201/10507Involving several components
    • H05K2201/10515Stacked components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431Details of mounted components
    • H05K2201/10507Involving several components
    • H05K2201/10537Attached components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10742Details of leads
    • H05K2201/10886Other details
    • H05K2201/10924Leads formed from a punched metal foil
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/4902Electromagnet, transformer or inductor

Definitions

  • the present invention relates to a package structure. More particularly, the present invention relates to an electronic package structure.
  • Electronic package structures are formed by complicated package processes. Different electronic package structures have different electrical performances and capacities of heat dissipation, and therefore a designer may select an electronic package structure with a desired electrical performance and capacity of heat dissipation according to a design requirement.
  • FIG. 1 is a schematic diagram of a conventional electronic package structure.
  • the conventional electronic package structure 100 includes a printed circuit board (PCB) 110 and a plurality of electronic elements 120 .
  • the electronic elements 120 are disposed on a surface 112 of the PCB 110 and electrically connected to the PCB 110 .
  • the PCB 110 has a plurality of pins 116 extending out from another surface 114 of the PCB 110 to be electrically connected to an electronic device, for example, a motherboard (not shown).
  • FIG. 2 is a schematic diagram of another conventional electronic package structure.
  • the conventional electronic package structure 200 includes a circuit substrate 210 and a plurality of electronic elements 220 .
  • the electronic elements 220 are disposed on a surface 212 of the circuit substrate 210 , and electrically connected to the circuit substrate 210 via a wire bonding technology, a flip-chip bonding technology or a surface mount technology.
  • the conventional electronic package structure 200 may be electrically connected to an electronic device, for example, a motherboard (not shown), via a solder paste or a plurality of solder balls (not shown).
  • the electronic elements 120 of the conventional electronic package structure 100 are all disposed on the surface 112 of the PCB 110
  • the electronic elements 220 of the conventional electronic package structure 200 are all disposed on the surface 212 of the circuit substrate 210 . Therefore, in the conventional electronic package structures 100 and 200 , spatial utilization of the PCB 110 and the circuit substrate 210 is relatively low, and sizes of the conventional electronic package structures 100 and 200 are relatively great.
  • an electronic package structure can achieve a relatively high utilization of an internal space thereof, so that a size of the electronic package structure can be reduced.
  • an electronic package structure includes at least a first electronic element, a second electronic element and a first lead frame.
  • the second electronic element includes a body having a cavity.
  • the first electronic element is disposed in the cavity.
  • the lead frame has a plurality of leads. Each of the leads has a first end and a second end, and the first end of at least one of the leads extends to the cavity to electrically connect the first electronic element.
  • an electronic package structure includes at least one first electronic element, a second electronic element and a lead frame.
  • the second electronic element includes a body having a first surface.
  • the lead frame has a plurality of leads. Each of the leads has a first end and a second end. The first ends are disposed on the first surface, and the first electronic element is disposed on the first surface and electrically connected to at least one of the leads.
  • an electronic package structure in one embodiment, includes a circuit substrate, at least one first electronic element and a second electronic element.
  • the circuit substrate has a first surface.
  • the first electronic element is disposed on the first surface of the circuit substrate and electrically connected to the circuit substrate.
  • the second electronic element is disposed above the first surface of the circuit substrate and includes a body and a plurality of leads.
  • Each of the leads has a first end and second end, and the second end of each of the leads extends out from the body to electrically connect the circuit substrate.
  • the first electronic element is located among the body of the second electronic element, the first surface of the circuit substrate and the leads.
  • the first electronic element can be disposed in the cavity of the second electronic element or on the second electronic element, or the second electronic element can be stacked on the first electronic element, compared to the conventional electronic package structures, utilization of an internal space of the electronic package structure is relatively high.
  • FIG. 1 is a schematic diagram of a conventional electronic package structure.
  • FIG. 2 is a schematic diagram of another conventional electronic package structure.
  • FIG. 3A is a schematic diagram of an electronic package structure according to a first embodiment of the present invention.
  • FIG. 3B is a schematic diagram of another electronic package structure according to the first embodiment of the present invention.
  • FIG. 3C is a schematic diagram of another electronic package structure according to the first embodiment of the present invention.
  • FIG. 3D is a schematic diagram of still another electronic package structure according to the first embodiment of the present invention.
  • FIG. 4A is a schematic diagram of an electronic package structure according to a second embodiment of the present invention.
  • FIG. 4B is a schematic diagram of another electronic package structure according to the second embodiment of the present invention.
  • FIG. 5A is a schematic diagram of an electronic package structure according to a third embodiment of the present invention.
  • FIG. 5B is a schematic diagram of another electronic package structure according to the third embodiment of the present invention.
  • FIG. 6 is a side view of an embodiment of an inductor, which can be used in the electronic package structure as shown in FIGS. 3A-5B .
  • FIG. 7 is a schematic diagram of an embodiment of a system that incorporates one of the electronic package structures as shown in FIGS. 3A-5B .
  • FIG. 3A is a schematic diagram of an electronic package structure according to a first embodiment of the present invention.
  • the electronic package structure 300 includes at least one first electronic element 310 (two first electronic elements are illustrated in FIG. 3A ), a second electronic element 320 and a first lead frame 330 .
  • the electronic package structure 300 is generally applied to a power-supply module, a voltage regulator module, a network adapter, a graphics processing unit, a DC/DC converter or a point-of-load (POL) converter.
  • Each of the first electronic elements 310 can be a power-supply component such as a logical control element (a controller), a driving element, a metal-oxide-semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), a diode or a passive element.
  • the passive element can be a capacitor, an inductor with lesser inductance, or a resistor.
  • the second electronic element 320 includes a body 322 having a cavity 322 a .
  • the first electronic elements 310 are disposed in the cavity 322 a .
  • the body 322 of the second electronic element 320 has a first surface 322 b , a second surface 322 c opposite to the first surface 322 b and a side surface 322 d .
  • the cavity 322 a sinks in a direction from the second surface 322 c towards the first surface 322 b .
  • the side surface 322 d connects the first surface 322 b and the second surface 322 c .
  • the second electronic element 320 can be an energy-storage element used for storing electric energy.
  • the second electronic element 320 further includes a coil 324 and a plurality of first external electrodes 326 .
  • the coil 324 is disposed within the body 322 .
  • the first external electrodes 326 are respectively connected to two opposite ends of the coil 324 , and extend outside the body 322 to locate on the first surface 322 b and the side surface 322 d .
  • the body 322 comprising a magnetic body encloses the coil 324 .
  • the second electronic element 320 can be an inductive element, such as an inductor, with a greater inductance and a greater size than the first electronic elements 310 .
  • the first lead frame 330 has a plurality of leads 332 .
  • Each of the leads 332 has a first end 332 a and a second end 332 b , and the first end 332 a of each of the leads 332 can be embedded in the body 322 and extends to the cavity 322 a for electrically connecting to the first electronic elements 310 .
  • the second end 332 b of each of the leads 332 is disposed on the first surface 322 b of the body 322 to form a second external electrode 332 c , and a part of each of the leads 332 connecting the first end 332 a and the second end 332 b is disposed on the side surface 322 d of the body 322 .
  • the electronic package structure 300 further includes a platform, such as a circuit substrate 340 , and an insulating encapsulant 350 .
  • the circuit substrate 340 is disposed in the cavity 322 a of the body 322 .
  • the first electronic elements 310 can be disposed on the circuit substrate 340 and electrically connected to the circuit substrate 340 .
  • the circuit substrate 340 is electrically connected to the first end 332 a of each of the leads 332 extending to the cavity 322 a .
  • the first electronic elements 310 may be electrically connected to the circuit substrate 340 via a wire bonding technology, a flip-chip bonding technology or a surface mount technology.
  • the circuit substrate 340 has a first circuit layer 342 , a second circuit layer 344 , a dielectric layer 346 disposed between the first circuit layer 342 and the second circuit layer 344 , and at least a conductive channel 348 .
  • the first electronic elements 310 are disposed on the first circuit layer 342 , and the conductive channel 348 penetrates the dielectric layer 346 for electrically connecting the first circuit layer 342 and the second circuit layer 344 .
  • the circuit board 340 of the electronic package structure 300 may be omitted according to a design requirement of a designer, though it is not illustrated.
  • the insulating encapsulant 350 is disposed in the cavity 322 a and encapsulates the first electronic elements 310 and the circuit substrate 340 for protecting the first electronic elements 310 and the circuit substrate 340 , and enhancing a whole mechanical strength of the electronic package structure 300 .
  • the first electronic elements 310 and the circuit substrate 340 are disposed in the cavity 322 a of the second electronic element 320 , compared to a conventional electronic package structures of FIG. 1 and FIG. 2 , utilization of an internal space of the electronic package structure 300 is relatively high, and the first electronic elements 310 and the circuit substrate 340 can be protected by the cavity 322 a .
  • the insulating encapsulant 350 is disposed in the cavity 322 a , material of the insulating encapsulant 350 can be directly filled into the cavity 322 a without aiding of extra mold during formation of the insulating encapsulant 350 .
  • FIG. 3B is a schematic diagram of another electronic package structure according to the first embodiment of the present invention.
  • a difference between the electronic package structure 300 ′ and the electronic package structure 300 is that a part of each lead 332 ′ connecting a first end 332 a ′ and a second end 332 b ′ penetrates a body 322 ′.
  • the insulating encapsulant 350 of the electronic package structure 300 is different from a magnetic encapsulant 350 ′ of the electronic package structure 300 ′.
  • the magnetic encapsulant 350 ′ is disposed in a cavity 322 a ′ of the body 322 ′.
  • a second electronic element 320 ′ is an inductive element
  • an inductive characteristic of the second electronic element 320 ′ influenced by the cavity 322 ′ then can be compensated by the magnetic encapsulant 350 ′.
  • a part of each of the leads 332 connecting the first end 332 a and the second end 332 b may also penetrate the body 322 according to a design requirement, though it is not illustrated.
  • FIG. 3C is a schematic diagram of another electronic package structure according to the first embodiment of the present invention.
  • a difference between the electronic package structure 300 ′′ and the electronic package structure 300 is that a cavity 322 a ′′ of a body 322 ′′ sinks in a direction from a first surface 322 b ′′ towards a second surface 322 c ′′.
  • an insulating encapsulant 350 ′′ can be substituted by a magnetic encapsulant according to a design requirement, and a part of each lead 332 ′′ connecting a first end 332 a ′′ and a second end 332 b ′′ may also penetrate the body 322 ′′ according to a design requirement, though it is not illustrated.
  • FIG. 3D is a schematic diagram of still another electronic package structure according to the first embodiment of the present invention.
  • a second lead frame 360 is applied in the electronic package structure 300 ′′′ for substituting the circuit substrate 340 of the electronic package structure 300 according to a design requirement.
  • a plurality of first electronic elements 310 ′′′ are disposed on the second lead frame 360 and electrically connected to the second lead frame 360 .
  • the second lead frame 360 is electrically connected to a first end 332 a ′′′ of each lead 332 ′′′ of a first lead frame 330 ′′′ that extends to a cavity 322 a′′′.
  • FIG. 4A is a schematic diagram of an electronic package structure according to a second embodiment of the present invention.
  • a difference between the electronic package structure 400 of the second embodiment and the electronic package structure 300 of the first embodiment is that a body 422 of a second electronic element 420 does not have the cavity 322 a .
  • a first end 432 a of each lead 432 of a lead frame 430 is disposed on a first surface 422 a of a body 422
  • a plurality of first electronic elements 410 are disposed on the first surface 422 a and electrically connected to the leads 432 .
  • a second end 432 b of each of the leads 432 is disposed on a second surface 422 b of the body 422 opposite to the first surface 422 a , and a part of each of the leads 432 connecting the first end 432 a and the second end 432 b is disposed on a side surface 422 c of the body 422 .
  • a platform such as a circuit substrate 440
  • a platform is disposed on the first surface 422 a and electrically connected to the leads 432
  • the first electronic elements 410 are disposed on the circuit substrate 440 and electrically connected to the circuit substrate 440 .
  • the circuit substrate 440 of the electronic package structure 400 may be omitted according to a design requirement of the designer, or the circuit substrate 440 may be substituted by a lead frame, though it is not illustrated.
  • FIG. 4B is a schematic diagram of another electronic package structure according to the second embodiment of the present invention.
  • a difference between the electronic package structure 400 ′ and the electronic package structure 400 is that a part of each lead 432 ′ connecting a first end 432 a ′ and a second end 432 b ′ penetrates a body 422 ′.
  • FIG. 5A is a schematic diagram of an electronic package structure according to a third embodiment of the present invention.
  • a plurality of first electronic elements 510 are disposed on a first surface 532 of a platform, such as a printed circuit board or a circuit substrate 530 as shown in FIG. 5A , and electrically connected to the circuit substrate 530 .
  • a second electronic element 520 is disposed above the first surface 532 of the circuit substrate 530 .
  • the first electronic elements 510 are located between a body 522 of the second electronic element 520 and the first surface 532 of the circuit substrate 530 , and the first electronic elements 510 are located between leads 524 of the second electronic element 520 .
  • the second electronic element 520 covers the first electronic elements 510 .
  • an insulating encapsulant 540 is disposed between the second electronic element 520 and the circuit substrate 530 and encapsulating the first electronic elements 510 for protecting the first electronic elements 510 and enhancing a whole mechanical strength of the electronic package structure 500 .
  • the insulating encapsulant 540 can also be disposed to encapsulate at least part of the circuit substrate 530 , the first electronic elements 510 and the second electronic element 520 , or completely encapsulate all of them.
  • the circuit substrate 530 may further include at least a conductive channel 539 , and each of the conductive channels 539 penetrates a dielectric layer 538 for electrically connecting a first circuit layer 534 and a second circuit layer 536 .
  • At least one of the conductive channels 539 (for example, the two conductive channels 539 located at a left side of FIG. 5A ) is located below at least one of the first electronic elements 510 (for example, the first electronic element 510 located at the left side of FIG. 5A ), so that heat generated by the first electronic element 510 located at the left side may be quickly transmitted to where is outside the electronic package structure 500 via the two conductive channels 539 located at the left side.
  • a second end 524 b of each of the leads 524 of the second electronic element 520 extends out from the body 522 to electrically connect the circuit substrate 530 .
  • the second electronic element 520 may be an inductive element including a coil 526 .
  • the body 522 which is a magnetic wrap wraps the coil 526 , and a first end 524 a of each of the leads 524 is connected to one of two opposite ends of the coil 526 .
  • FIG. 5A an embodiment of a method for manufacturing the electronic package structure 500 is described.
  • the plurality of first electronic elements 510 and any other components of the electronic package structure 500 are mounted to the circuit substrate 530 , the bottom pads of the components are soldered to corresponding pads of the circuit substrate.
  • the upper pads (if any are present) of the components are wire bonded to corresponding pads of the circuit substrate 530 .
  • the leads 524 of the second electronic element 520 are shaped, and the second electronic element 520 is mounted to the circuit substrate 530 , e.g., by soldering the leads to corresponding pads of the circuit substrate.
  • the insulating encapsulant 540 is formed between the second electronic element 520 and the circuit substrate 530 and encapsulating the first electronic elements 510 by conventional methods.
  • the insulating encapsulant 540 can also be formed to encapsulate at least part of the circuit substrate 530 , the first electronic elements 510 and the second electronic element 520 , or completely encapsulate all of them by conventional methods, such as injection molding of epoxy resin.
  • the leads (not shown in FIG. 5A ) of the electronic package structure 500 are shaped, and the electronic package structure can be tested and shipped to customers.
  • the electronic package structure 500 further includes an electromagnetic-interference-shielding element (EMI-shielding element) 550 covering the first electronic elements 510 .
  • EMI-shielding element electromagnetic-interference-shielding element
  • the EMI-shielding element 550 is disposed on the body 522 of the second electronic element 520 , and is located between the body 522 of the second electronic element 520 and the circuit substrate 530 . Therefore, during operation of the electronic package structure 500 , it may be reduced by means of the EMI-shielding element 550 that electrical signals transmitted in the circuit substrate 530 is interfered by a magnetic force generated by the second electronic element 520 which functions as an inductive element.
  • FIG. 5B is a schematic diagram of another electronic package structure according to the third embodiment of the present invention.
  • a difference between the electronic package structure 500 ′ and the electronic package structure 500 is that an EMI-shielding element 550 ′ of the electronic package structure 500 ′ is disposed in a cavity 522 ′ of a second electronic element 520 ′.
  • FIG. 6 is a side view of an embodiment of a second electronic element such as an inductor 620 , which can be used in the aforementioned electronic package structure.
  • Each of the leads 624 is extensions of the inductor winding and has two bends 6240 and 6242 .
  • the angles of the bends 6240 and 6242 can be between approximately 30 and 90 degrees.
  • the bottoms of the leads 624 can also be bent at an approximately 90 degree angle to increase the mounting stability of the inductor 620 .
  • the inductor 620 can have more than two leads (e.g., four leads), to increase the mounting stability of the inductor, to reduce the lead resistance, etc.
  • FIG. 7 is a schematic diagram of an embodiment of a system 70 , which can incorporate one or more embodiments of the aforementioned electronic package structure; for example, the electronic package structure can be a power-supply module 700 as shown in FIG. 7 , where the module 700 includes a buck converter.
  • the system 70 includes an apparatus, such as a load 702 , which receives a regulated voltage Vout from the module, and a filter capacitor (C) 704 .
  • the load 702 include an integrated circuit such as a processor or memory.
  • a power-supply component such as the controller 710 as shown in FIG. 7
  • controls the other power-supply component such as the transistors 712 as shown in FIG. 7 , to alternately couple an input voltage Vin and reference voltage (e.g., ground) to a phase inductor 720 in a manner that generates the regulated voltage Vout from Vin.
  • the module 700 can include any other type of power supply such as a buck-boost converter.
  • the module 700 can include additional components such as a filter inductor coupled between the phase inductor 720 and the load 702 .
  • the filter capacitor 704 can be part of the module.
  • the first electronic elements can be disposed in the cavity of the second electronic element or can be disposed on the second electronic element, or the second electronic element can be stacked on the first electronic elements, compared to the conventional electronic package structures, utilization of an internal space of the electronic package structure is relatively high, so that a size of the electronic package structure can be reduced.

Abstract

A power-supply module includes at least one power-supply component, an inductor and a package. The inductor is disposed over the at least one power-supply components, and the at least a power-supply component and the inductor are disposed within the package. Besides, the power-supply module further comprises a printed circuit board, and the at least one power-supply component and the inductor are mounted to the printed circuit board. Moreover, the inductor comprises a plurality of leads that support the inductor over the at least one power-supply component.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS
This application is a continuation-in-part of U.S. patent application Ser. No. 12/971,671 filed on Dec. 17, 2010, now U.S. Pub. No. 2011/0090648, which is a divisional of U.S. patent application Ser. No. 12/143,143 filed on Jun. 20, 2008, now U.S. Pub. No. 2009/0207574, now abandoned, which claims priority of Taiwan application Ser. No. 97105555 filed on Feb. 18, 2008. The entirety of the above-mentioned patent applications are hereby incorporated by reference herein and made a part of specification.
BACKGROUND OF THE INVENTION
I. Field of the Invention
The present invention relates to a package structure. More particularly, the present invention relates to an electronic package structure.
II. Description of the Prior Art
Electronic package structures are formed by complicated package processes. Different electronic package structures have different electrical performances and capacities of heat dissipation, and therefore a designer may select an electronic package structure with a desired electrical performance and capacity of heat dissipation according to a design requirement.
FIG. 1 is a schematic diagram of a conventional electronic package structure. Referring to FIG. 1, the conventional electronic package structure 100 includes a printed circuit board (PCB) 110 and a plurality of electronic elements 120. The electronic elements 120 are disposed on a surface 112 of the PCB 110 and electrically connected to the PCB 110. The PCB 110 has a plurality of pins 116 extending out from another surface 114 of the PCB 110 to be electrically connected to an electronic device, for example, a motherboard (not shown).
FIG. 2 is a schematic diagram of another conventional electronic package structure. Referring to FIG. 2, the conventional electronic package structure 200 includes a circuit substrate 210 and a plurality of electronic elements 220. The electronic elements 220 are disposed on a surface 212 of the circuit substrate 210, and electrically connected to the circuit substrate 210 via a wire bonding technology, a flip-chip bonding technology or a surface mount technology. Moreover, the conventional electronic package structure 200 may be electrically connected to an electronic device, for example, a motherboard (not shown), via a solder paste or a plurality of solder balls (not shown).
It should be noted that the electronic elements 120 of the conventional electronic package structure 100 are all disposed on the surface 112 of the PCB 110, and the electronic elements 220 of the conventional electronic package structure 200 are all disposed on the surface 212 of the circuit substrate 210. Therefore, in the conventional electronic package structures 100 and 200, spatial utilization of the PCB 110 and the circuit substrate 210 is relatively low, and sizes of the conventional electronic package structures 100 and 200 are relatively great.
SUMMARY OF THE INVENTION
In accordance with the present invention, an electronic package structure can achieve a relatively high utilization of an internal space thereof, so that a size of the electronic package structure can be reduced.
In one embodiment of the present invention, an electronic package structure includes at least a first electronic element, a second electronic element and a first lead frame. The second electronic element includes a body having a cavity. The first electronic element is disposed in the cavity. The lead frame has a plurality of leads. Each of the leads has a first end and a second end, and the first end of at least one of the leads extends to the cavity to electrically connect the first electronic element.
In one embodiment of the present invention, an electronic package structure includes at least one first electronic element, a second electronic element and a lead frame. The second electronic element includes a body having a first surface. The lead frame has a plurality of leads. Each of the leads has a first end and a second end. The first ends are disposed on the first surface, and the first electronic element is disposed on the first surface and electrically connected to at least one of the leads.
In one embodiment, an electronic package structure includes a circuit substrate, at least one first electronic element and a second electronic element. The circuit substrate has a first surface. The first electronic element is disposed on the first surface of the circuit substrate and electrically connected to the circuit substrate. The second electronic element is disposed above the first surface of the circuit substrate and includes a body and a plurality of leads. Each of the leads has a first end and second end, and the second end of each of the leads extends out from the body to electrically connect the circuit substrate. The first electronic element is located among the body of the second electronic element, the first surface of the circuit substrate and the leads.
In the above embodiments of the present invention, since the first electronic element can be disposed in the cavity of the second electronic element or on the second electronic element, or the second electronic element can be stacked on the first electronic element, compared to the conventional electronic package structures, utilization of an internal space of the electronic package structure is relatively high.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, a preferred embodiment accompanied with figures is described in detail below.
The detailed technology and above preferred embodiments implemented for the present invention are described in the following paragraphs accompanying the appended drawings for people skilled in this field to well appreciate the features of the claimed invention.
BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing aspects and many of the accompanying advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description when taken in conjunction with the accompanying drawings, wherein:
FIG. 1 is a schematic diagram of a conventional electronic package structure.
FIG. 2 is a schematic diagram of another conventional electronic package structure.
FIG. 3A is a schematic diagram of an electronic package structure according to a first embodiment of the present invention.
FIG. 3B is a schematic diagram of another electronic package structure according to the first embodiment of the present invention.
FIG. 3C is a schematic diagram of another electronic package structure according to the first embodiment of the present invention.
FIG. 3D is a schematic diagram of still another electronic package structure according to the first embodiment of the present invention.
FIG. 4A is a schematic diagram of an electronic package structure according to a second embodiment of the present invention.
FIG. 4B is a schematic diagram of another electronic package structure according to the second embodiment of the present invention.
FIG. 5A is a schematic diagram of an electronic package structure according to a third embodiment of the present invention.
FIG. 5B is a schematic diagram of another electronic package structure according to the third embodiment of the present invention.
FIG. 6 is a side view of an embodiment of an inductor, which can be used in the electronic package structure as shown in FIGS. 3A-5B.
FIG. 7 is a schematic diagram of an embodiment of a system that incorporates one of the electronic package structures as shown in FIGS. 3A-5B.
DETAILED DESCRIPTION OF THE INVENTION
The detailed explanation of the present invention is described as following. The described preferred embodiments are presented for purposes of illustrations and descriptions, and they are not intended to limit the scope of the present invention.
First Embodiment
FIG. 3A is a schematic diagram of an electronic package structure according to a first embodiment of the present invention. Referring to FIG. 3A, the electronic package structure 300 includes at least one first electronic element 310 (two first electronic elements are illustrated in FIG. 3A), a second electronic element 320 and a first lead frame 330. The electronic package structure 300 is generally applied to a power-supply module, a voltage regulator module, a network adapter, a graphics processing unit, a DC/DC converter or a point-of-load (POL) converter. Each of the first electronic elements 310 can be a power-supply component such as a logical control element (a controller), a driving element, a metal-oxide-semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), a diode or a passive element. The passive element can be a capacitor, an inductor with lesser inductance, or a resistor.
The second electronic element 320 includes a body 322 having a cavity 322 a. The first electronic elements 310 are disposed in the cavity 322 a. In the embodiment, the body 322 of the second electronic element 320 has a first surface 322 b, a second surface 322 c opposite to the first surface 322 b and a side surface 322 d. The cavity 322 a sinks in a direction from the second surface 322 c towards the first surface 322 b. The side surface 322 d connects the first surface 322 b and the second surface 322 c. Besides, the second electronic element 320 can be an energy-storage element used for storing electric energy. In detail, the second electronic element 320 further includes a coil 324 and a plurality of first external electrodes 326. The coil 324 is disposed within the body 322. The first external electrodes 326 are respectively connected to two opposite ends of the coil 324, and extend outside the body 322 to locate on the first surface 322 b and the side surface 322 d. The body 322 comprising a magnetic body encloses the coil 324. The second electronic element 320 can be an inductive element, such as an inductor, with a greater inductance and a greater size than the first electronic elements 310.
The first lead frame 330 has a plurality of leads 332. Each of the leads 332 has a first end 332 a and a second end 332 b, and the first end 332 a of each of the leads 332 can be embedded in the body 322 and extends to the cavity 322 a for electrically connecting to the first electronic elements 310. The second end 332 b of each of the leads 332 is disposed on the first surface 322 b of the body 322 to form a second external electrode 332 c, and a part of each of the leads 332 connecting the first end 332 a and the second end 332 b is disposed on the side surface 322 d of the body 322.
In the present embodiment, the electronic package structure 300 further includes a platform, such as a circuit substrate 340, and an insulating encapsulant 350. The circuit substrate 340 is disposed in the cavity 322 a of the body 322. The first electronic elements 310 can be disposed on the circuit substrate 340 and electrically connected to the circuit substrate 340. The circuit substrate 340 is electrically connected to the first end 332 a of each of the leads 332 extending to the cavity 322 a. The first electronic elements 310 may be electrically connected to the circuit substrate 340 via a wire bonding technology, a flip-chip bonding technology or a surface mount technology. The circuit substrate 340 has a first circuit layer 342, a second circuit layer 344, a dielectric layer 346 disposed between the first circuit layer 342 and the second circuit layer 344, and at least a conductive channel 348. The first electronic elements 310 are disposed on the first circuit layer 342, and the conductive channel 348 penetrates the dielectric layer 346 for electrically connecting the first circuit layer 342 and the second circuit layer 344. It should be noted that the circuit board 340 of the electronic package structure 300 may be omitted according to a design requirement of a designer, though it is not illustrated.
Moreover, the insulating encapsulant 350 is disposed in the cavity 322 a and encapsulates the first electronic elements 310 and the circuit substrate 340 for protecting the first electronic elements 310 and the circuit substrate 340, and enhancing a whole mechanical strength of the electronic package structure 300.
Since the first electronic elements 310 and the circuit substrate 340 are disposed in the cavity 322 a of the second electronic element 320, compared to a conventional electronic package structures of FIG. 1 and FIG. 2, utilization of an internal space of the electronic package structure 300 is relatively high, and the first electronic elements 310 and the circuit substrate 340 can be protected by the cavity 322 a. Besides, since the insulating encapsulant 350 is disposed in the cavity 322 a, material of the insulating encapsulant 350 can be directly filled into the cavity 322 a without aiding of extra mold during formation of the insulating encapsulant 350.
FIG. 3B is a schematic diagram of another electronic package structure according to the first embodiment of the present invention. Referring to FIG. 3A and FIG. 3B, a difference between the electronic package structure 300′ and the electronic package structure 300 is that a part of each lead 332′ connecting a first end 332 a′ and a second end 332 b′ penetrates a body 322′. Besides, the insulating encapsulant 350 of the electronic package structure 300 is different from a magnetic encapsulant 350′ of the electronic package structure 300′. The magnetic encapsulant 350′ is disposed in a cavity 322 a′ of the body 322′. Therefore, if a second electronic element 320′ is an inductive element, an inductive characteristic of the second electronic element 320′ influenced by the cavity 322′ then can be compensated by the magnetic encapsulant 350′. It should be noted that a part of each of the leads 332 connecting the first end 332 a and the second end 332 b may also penetrate the body 322 according to a design requirement, though it is not illustrated.
FIG. 3C is a schematic diagram of another electronic package structure according to the first embodiment of the present invention. Referring to FIG. 3A and FIG. 3C, a difference between the electronic package structure 300″ and the electronic package structure 300 is that a cavity 322 a″ of a body 322″ sinks in a direction from a first surface 322 b″ towards a second surface 322 c″. It should be noted that an insulating encapsulant 350″ can be substituted by a magnetic encapsulant according to a design requirement, and a part of each lead 332″ connecting a first end 332 a″ and a second end 332 b″ may also penetrate the body 322″ according to a design requirement, though it is not illustrated.
FIG. 3D is a schematic diagram of still another electronic package structure according to the first embodiment of the present invention. Referring to FIG. 3A and FIG. 3D, a second lead frame 360 is applied in the electronic package structure 300′″ for substituting the circuit substrate 340 of the electronic package structure 300 according to a design requirement. A plurality of first electronic elements 310′″ are disposed on the second lead frame 360 and electrically connected to the second lead frame 360. The second lead frame 360 is electrically connected to a first end 332 a′″ of each lead 332′″ of a first lead frame 330′″ that extends to a cavity 322 a′″.
Second Embodiment
FIG. 4A is a schematic diagram of an electronic package structure according to a second embodiment of the present invention. Referring to FIG. 4A and FIG. 3A, a difference between the electronic package structure 400 of the second embodiment and the electronic package structure 300 of the first embodiment is that a body 422 of a second electronic element 420 does not have the cavity 322 a. In detail, a first end 432 a of each lead 432 of a lead frame 430 is disposed on a first surface 422 a of a body 422, and a plurality of first electronic elements 410 are disposed on the first surface 422 a and electrically connected to the leads 432. Moreover, a second end 432 b of each of the leads 432 is disposed on a second surface 422 b of the body 422 opposite to the first surface 422 a, and a part of each of the leads 432 connecting the first end 432 a and the second end 432 b is disposed on a side surface 422 c of the body 422.
Furthermore, a platform, such as a circuit substrate 440, is disposed on the first surface 422 a and electrically connected to the leads 432, and the first electronic elements 410 are disposed on the circuit substrate 440 and electrically connected to the circuit substrate 440. It should be noted that the circuit substrate 440 of the electronic package structure 400 may be omitted according to a design requirement of the designer, or the circuit substrate 440 may be substituted by a lead frame, though it is not illustrated.
FIG. 4B is a schematic diagram of another electronic package structure according to the second embodiment of the present invention. Referring to FIG. 4A and FIG. 4B, a difference between the electronic package structure 400′ and the electronic package structure 400 is that a part of each lead 432′ connecting a first end 432 a′ and a second end 432 b′ penetrates a body 422′.
Third Embodiment
FIG. 5A is a schematic diagram of an electronic package structure according to a third embodiment of the present invention. Referring to FIG. 5A, in the electronic package structure 500 of the present embodiment, a plurality of first electronic elements 510 are disposed on a first surface 532 of a platform, such as a printed circuit board or a circuit substrate 530 as shown in FIG. 5A, and electrically connected to the circuit substrate 530. A second electronic element 520 is disposed above the first surface 532 of the circuit substrate 530. The first electronic elements 510 are located between a body 522 of the second electronic element 520 and the first surface 532 of the circuit substrate 530, and the first electronic elements 510 are located between leads 524 of the second electronic element 520. In other words, in the present embodiment, the second electronic element 520 covers the first electronic elements 510. Besides, an insulating encapsulant 540 is disposed between the second electronic element 520 and the circuit substrate 530 and encapsulating the first electronic elements 510 for protecting the first electronic elements 510 and enhancing a whole mechanical strength of the electronic package structure 500. Alternatively, the insulating encapsulant 540 can also be disposed to encapsulate at least part of the circuit substrate 530, the first electronic elements 510 and the second electronic element 520, or completely encapsulate all of them. Moreover, the circuit substrate 530 may further include at least a conductive channel 539, and each of the conductive channels 539 penetrates a dielectric layer 538 for electrically connecting a first circuit layer 534 and a second circuit layer 536. At least one of the conductive channels 539 (for example, the two conductive channels 539 located at a left side of FIG. 5A) is located below at least one of the first electronic elements 510 (for example, the first electronic element 510 located at the left side of FIG. 5A), so that heat generated by the first electronic element 510 located at the left side may be quickly transmitted to where is outside the electronic package structure 500 via the two conductive channels 539 located at the left side. A second end 524 b of each of the leads 524 of the second electronic element 520 extends out from the body 522 to electrically connect the circuit substrate 530. The second electronic element 520 may be an inductive element including a coil 526. The body 522 which is a magnetic wrap wraps the coil 526, and a first end 524 a of each of the leads 524 is connected to one of two opposite ends of the coil 526.
Still referring to FIG. 5A, an embodiment of a method for manufacturing the electronic package structure 500 is described.
First, the plurality of first electronic elements 510 and any other components of the electronic package structure 500 are mounted to the circuit substrate 530, the bottom pads of the components are soldered to corresponding pads of the circuit substrate.
Next, the upper pads (if any are present) of the components are wire bonded to corresponding pads of the circuit substrate 530.
Then, the leads 524 of the second electronic element 520 are shaped, and the second electronic element 520 is mounted to the circuit substrate 530, e.g., by soldering the leads to corresponding pads of the circuit substrate.
Next, the insulating encapsulant 540 is formed between the second electronic element 520 and the circuit substrate 530 and encapsulating the first electronic elements 510 by conventional methods. Alternatively, the insulating encapsulant 540 can also be formed to encapsulate at least part of the circuit substrate 530, the first electronic elements 510 and the second electronic element 520, or completely encapsulate all of them by conventional methods, such as injection molding of epoxy resin.
Then, the leads (not shown in FIG. 5A) of the electronic package structure 500 are shaped, and the electronic package structure can be tested and shipped to customers.
It should be noted that the electronic package structure 500 further includes an electromagnetic-interference-shielding element (EMI-shielding element) 550 covering the first electronic elements 510. In the present embodiment, the EMI-shielding element 550 is disposed on the body 522 of the second electronic element 520, and is located between the body 522 of the second electronic element 520 and the circuit substrate 530. Therefore, during operation of the electronic package structure 500, it may be reduced by means of the EMI-shielding element 550 that electrical signals transmitted in the circuit substrate 530 is interfered by a magnetic force generated by the second electronic element 520 which functions as an inductive element.
FIG. 5B is a schematic diagram of another electronic package structure according to the third embodiment of the present invention. Referring to FIG. 5A and FIG. 5B, a difference between the electronic package structure 500′ and the electronic package structure 500 is that an EMI-shielding element 550′ of the electronic package structure 500′ is disposed in a cavity 522′ of a second electronic element 520′.
FIG. 6 is a side view of an embodiment of a second electronic element such as an inductor 620, which can be used in the aforementioned electronic package structure. Each of the leads 624 is extensions of the inductor winding and has two bends 6240 and 6242. For example, the angles of the bends 6240 and 6242 can be between approximately 30 and 90 degrees. Furthermore, although not shown, the bottoms of the leads 624 can also be bent at an approximately 90 degree angle to increase the mounting stability of the inductor 620. Moreover, although only two leads 624 are shown, the inductor 620 can have more than two leads (e.g., four leads), to increase the mounting stability of the inductor, to reduce the lead resistance, etc.
FIG. 7 is a schematic diagram of an embodiment of a system 70, which can incorporate one or more embodiments of the aforementioned electronic package structure; for example, the electronic package structure can be a power-supply module 700 as shown in FIG. 7, where the module 700 includes a buck converter.
In addition to the module 700, the system 70 includes an apparatus, such as a load 702, which receives a regulated voltage Vout from the module, and a filter capacitor (C) 704. Examples of the load 702 include an integrated circuit such as a processor or memory. In operation, a power-supply component, such as the controller 710 as shown in FIG. 7, controls the other power-supply component, such as the transistors 712 as shown in FIG. 7, to alternately couple an input voltage Vin and reference voltage (e.g., ground) to a phase inductor 720 in a manner that generates the regulated voltage Vout from Vin.
Still referring to FIG. 7, alternate embodiments of the system 70 are contemplated. For example, embodiments described above in conjunction with FIGS. 3A-5B can be applicable to the system 70. Furthermore, although described as a buck converter, the module 700 can include any other type of power supply such as a buck-boost converter. Moreover, the module 700 can include additional components such as a filter inductor coupled between the phase inductor 720 and the load 702. In addition, although described as being external to the module 700, the filter capacitor 704 can be part of the module.
In summary, in the aforementioned embodiments of the present invention, since the first electronic elements can be disposed in the cavity of the second electronic element or can be disposed on the second electronic element, or the second electronic element can be stacked on the first electronic elements, compared to the conventional electronic package structures, utilization of an internal space of the electronic package structure is relatively high, so that a size of the electronic package structure can be reduced.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure and method of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Claims (14)

What is claimed is:
1. A power-supply module, comprising:
at least one power-supply component;
an inductor disposed over the at least one power-supply component, wherein the inductor has a magnetic body and a coil encapsulated in the magnetic body, wherein the magnetic body encloses the coil therein and contiguously extends into the hollow space formed by the coil, wherein the magnetic body further contiguously extends to a first lateral side of the at least one power-supply component;
a package, wherein the at least one power-supply component and the inductor are disposed within the package, wherein the package comprises epoxy resin to encapsulate the at least one power-supply component and the inductor; and
a first lead frame, wherein a first portion of the first lead frame is disposed between the at least one power-supply component and the inductor inside the package, and a second portion extending from the first portion of the first lead frame is disposed on a top or bottom surface of the package for connecting with an external circuit.
2. The power-supply module as claimed in claim 1, wherein the magnetic body further contiguously extends to a second lateral side of the at least one power-supply component.
3. The power-supply module as claimed in claim 1, wherein the at least one power-supply component comprises a plurality of electrical components that are electrically connected.
4. The power-supply module as claimed in claim 1, wherein the at least one power-supply component comprises a controller.
5. The power-supply module as claimed in claim 1, wherein the at least one power-supply component comprises a transistor.
6. The power-supply module as claimed in claim 1, wherein the at least one power-supply component comprises a resistor.
7. The power-supply module as claimed in claim 1, wherein the at least one power-supply component comprises a capacitor.
8. The power-supply module as claimed in claim 1, further comprising:
a platform, wherein the at least one power-supply component and the inductor are mounted to the platform.
9. The power-supply module as claimed in claim 1, further comprising:
a printed circuit board, wherein the at least one power-supply component and the inductor are mounted to the printed circuit board.
10. The power-supply module as claimed in claim 1, wherein the at least one power-supply component comprises a plurality of electrical components, further comprising: a circuit substrate disposed between the plurality of electrical components and the inductor, wherein the plurality of electrical components and the inductor are electrically connected to the circuit substrate.
11. A power-supply module, comprising:
an electronic module comprising at least one power-supply component;
an inductor disposed over the electronic module, wherein the inductor has a magnetic body and a coil encapsulated in the magnetic body, wherein the magnetic body encloses the coil therein and contiguously extends into the hollow space formed by the coil, wherein the magnetic body further contiguously extends to a first lateral side of the electronic module;
a package, wherein the electronic module and the inductor are disposed within the package, wherein the package comprises epoxy resin to encapsulate the electronic module and the inductor; and
a first lead frame, wherein a first portion of the first lead frame is disposed between the electronic module and the inductor inside the package, and a second portion extending from the first portion of the first lead frame is disposed on a top or bottom surface of the package for connecting with an external circuit.
12. The power-supply module as claimed in claim 11, wherein the second portion of the lead frame extends from the first portion to said top or bottom surface of the package through a third portion of the lead frame disposed on a lateral surface of the package.
13. The power-supply module as claimed in claim 11, wherein the second portion of the lead frame extends from the first portion to said top or bottom surface of the package through a third portion of the lead frame disposed inside the package.
14. The power-supply module as claimed in claim 11, further comprising a second lead frame having a third portion disposed between the at least one power-supply component and the inductor inside the package, and a fourth portion extending from the third portion is disposed on the same surface on which the second portion of the first lead frame is disposed.
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TW097105555A TWI355068B (en) 2008-02-18 2008-02-18 Electronic package structure
US12/143,143 US20090207574A1 (en) 2008-02-18 2008-06-20 Electronic package structure
US12/971,671 US20110090648A1 (en) 2008-02-18 2010-12-17 Electronic package structure
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210358895A1 (en) * 2020-05-18 2021-11-18 Analog Devices, Inc. Package with overhang inductor

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9001527B2 (en) * 2008-02-18 2015-04-07 Cyntec Co., Ltd. Electronic package structure
TWI445103B (en) * 2010-08-19 2014-07-11 Cyntec Co Ltd Electronic package structure and method for making the same
US9743522B2 (en) * 2012-09-26 2017-08-22 Apple Inc. Printed circuit board with compact groups of devices
US9865387B2 (en) 2015-12-02 2018-01-09 Intel IP Corporation Electronic package with coil formed on core
US10069417B2 (en) * 2016-01-04 2018-09-04 Kinetic Technologies Power conversion device with integrated discrete inductor
US10925164B2 (en) 2016-09-23 2021-02-16 Apple Inc. Stackable passive component
WO2019218344A1 (en) * 2018-05-18 2019-11-21 瑞典爱立信有限公司 Power supply device and printed circuit board device comprising same

Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4096581A (en) * 1976-08-16 1978-06-20 Texas Instruments Incorporated External drive coil magnetic bubble package
US5621635A (en) * 1995-03-03 1997-04-15 National Semiconductor Corporation Integrated circuit packaged power supply
US20010023983A1 (en) * 2000-02-28 2001-09-27 Toshiyuki Kobayashi Semiconductor devices
US20030031339A1 (en) * 2000-01-13 2003-02-13 Marshall Bowen F. Packaging and rf shielding for telecoils
US20030143971A1 (en) * 2000-08-22 2003-07-31 Toyohiko Hongo Radio transmitting/receiving device
US20040130020A1 (en) * 2002-12-27 2004-07-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US20040238857A1 (en) * 2001-08-28 2004-12-02 Tessera, Inc. High frequency chip packages with connecting elements
US20070215996A1 (en) * 2006-03-15 2007-09-20 Ralf Otremba Electronic Component and Method for its Assembly
US20070247268A1 (en) * 2006-03-17 2007-10-25 Yoichi Oya Inductor element and method for production thereof, and semiconductor module with inductor element
US20080029907A1 (en) * 2006-07-19 2008-02-07 Texas Instruments Incorporated Power Semiconductor Devices Having Integrated Inductor
US20080150623A1 (en) * 2006-12-26 2008-06-26 Megica Corporation Voltage Regulator Integrated with Semiconductor Chip
US20080179722A1 (en) * 2007-01-31 2008-07-31 Cyntec Co., Ltd. Electronic package structure
US20080180921A1 (en) * 2007-01-31 2008-07-31 Cyntec Co., Ltd. Electronic package structure
US20080303125A1 (en) * 2007-06-08 2008-12-11 Da-Jung Chen Three-dimensional package structure
US20080309442A1 (en) * 2007-06-12 2008-12-18 Francois Hebert Semiconductor power device having a stacked discrete inductor structure
US20090057822A1 (en) * 2007-09-05 2009-03-05 Yenting Wen Semiconductor component and method of manufacture
US7560811B2 (en) * 2005-12-08 2009-07-14 Yamaha Corporation Semiconductor device

Patent Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4096581A (en) * 1976-08-16 1978-06-20 Texas Instruments Incorporated External drive coil magnetic bubble package
US5621635A (en) * 1995-03-03 1997-04-15 National Semiconductor Corporation Integrated circuit packaged power supply
US20030031339A1 (en) * 2000-01-13 2003-02-13 Marshall Bowen F. Packaging and rf shielding for telecoils
US20010023983A1 (en) * 2000-02-28 2001-09-27 Toshiyuki Kobayashi Semiconductor devices
US20030143971A1 (en) * 2000-08-22 2003-07-31 Toyohiko Hongo Radio transmitting/receiving device
US20040238857A1 (en) * 2001-08-28 2004-12-02 Tessera, Inc. High frequency chip packages with connecting elements
US20040130020A1 (en) * 2002-12-27 2004-07-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US7560811B2 (en) * 2005-12-08 2009-07-14 Yamaha Corporation Semiconductor device
US20070215996A1 (en) * 2006-03-15 2007-09-20 Ralf Otremba Electronic Component and Method for its Assembly
US20070247268A1 (en) * 2006-03-17 2007-10-25 Yoichi Oya Inductor element and method for production thereof, and semiconductor module with inductor element
US20080029907A1 (en) * 2006-07-19 2008-02-07 Texas Instruments Incorporated Power Semiconductor Devices Having Integrated Inductor
US20080150623A1 (en) * 2006-12-26 2008-06-26 Megica Corporation Voltage Regulator Integrated with Semiconductor Chip
US20080179722A1 (en) * 2007-01-31 2008-07-31 Cyntec Co., Ltd. Electronic package structure
US20080180921A1 (en) * 2007-01-31 2008-07-31 Cyntec Co., Ltd. Electronic package structure
US20080303125A1 (en) * 2007-06-08 2008-12-11 Da-Jung Chen Three-dimensional package structure
US20080309442A1 (en) * 2007-06-12 2008-12-18 Francois Hebert Semiconductor power device having a stacked discrete inductor structure
US20090057822A1 (en) * 2007-09-05 2009-03-05 Yenting Wen Semiconductor component and method of manufacture

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210358895A1 (en) * 2020-05-18 2021-11-18 Analog Devices, Inc. Package with overhang inductor
US11270986B2 (en) * 2020-05-18 2022-03-08 Analog Devices, Inc. Package with overhang inductor

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