USRE35934E - Semiconductor memory device synchronous with external clock signal for outputting data bits through a small number of data lines - Google Patents
Semiconductor memory device synchronous with external clock signal for outputting data bits through a small number of data lines Download PDFInfo
- Publication number
- USRE35934E USRE35934E US08/879,516 US87951697A USRE35934E US RE35934 E USRE35934 E US RE35934E US 87951697 A US87951697 A US 87951697A US RE35934 E USRE35934 E US RE35934E
- Authority
- US
- United States
- Prior art keywords
- address
- bits
- address bits
- internal
- memory cells
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
Abstract
Description
Claims (4)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/879,516 USRE35934E (en) | 1993-04-02 | 1997-06-20 | Semiconductor memory device synchronous with external clock signal for outputting data bits through a small number of data lines |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5077236A JPH06290582A (en) | 1993-04-02 | 1993-04-02 | Semiconductor memory |
JP5-077236 | 1993-04-02 | ||
US08/221,574 US5426606A (en) | 1993-04-02 | 1994-04-01 | Semiconductor memory device synchronous with external clock signal for outputting data bits through a small number of data lines |
US08/879,516 USRE35934E (en) | 1993-04-02 | 1997-06-20 | Semiconductor memory device synchronous with external clock signal for outputting data bits through a small number of data lines |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/221,574 Reissue US5426606A (en) | 1993-04-02 | 1994-04-01 | Semiconductor memory device synchronous with external clock signal for outputting data bits through a small number of data lines |
Publications (1)
Publication Number | Publication Date |
---|---|
USRE35934E true USRE35934E (en) | 1998-10-27 |
Family
ID=13628237
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/221,574 Ceased US5426606A (en) | 1993-04-02 | 1994-04-01 | Semiconductor memory device synchronous with external clock signal for outputting data bits through a small number of data lines |
US08/879,516 Expired - Lifetime USRE35934E (en) | 1993-04-02 | 1997-06-20 | Semiconductor memory device synchronous with external clock signal for outputting data bits through a small number of data lines |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/221,574 Ceased US5426606A (en) | 1993-04-02 | 1994-04-01 | Semiconductor memory device synchronous with external clock signal for outputting data bits through a small number of data lines |
Country Status (5)
Country | Link |
---|---|
US (2) | US5426606A (en) |
EP (2) | EP0618585B1 (en) |
JP (1) | JPH06290582A (en) |
KR (1) | KR0160360B1 (en) |
DE (2) | DE69430076T2 (en) |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6256255B1 (en) | 1997-03-11 | 2001-07-03 | Micron Technology, Inc. | Multi-bank memory input/output line selection |
US6272608B1 (en) | 1997-07-10 | 2001-08-07 | Micron Technology, Inc. | Method and apparatus for synchronous data transfers in a memory device with lookahead logic for detecting latency intervals |
US6278633B1 (en) | 1999-11-05 | 2001-08-21 | Multi Level Memory Technology | High bandwidth flash memory that selects programming parameters according to measurements of previous programming operations |
US6405280B1 (en) | 1998-06-05 | 2002-06-11 | Micron Technology, Inc. | Packet-oriented synchronous DRAM interface supporting a plurality of orderings for data block transfers within a burst sequence |
US6519719B1 (en) | 1997-06-13 | 2003-02-11 | Micron Technology, Inc. | Method and apparatus for transferring test data from a memory array |
US6539454B2 (en) * | 1998-04-01 | 2003-03-25 | Mosaid Technologies Incorporated | Semiconductor memory asynchronous pipeline |
US6567338B1 (en) | 1996-04-19 | 2003-05-20 | Integrated Device Technology, Inc. | Fully synchronous pipelined RAM |
US6591354B1 (en) | 1998-02-23 | 2003-07-08 | Integrated Device Technology, Inc. | Separate byte control on fully synchronous pipelined SRAM |
US6772312B2 (en) * | 1998-04-01 | 2004-08-03 | Mosaid Technologies Incorporated | Semiconductor memory having asynchronous pipeline stages |
US20040202036A1 (en) * | 2000-07-07 | 2004-10-14 | Paul Demone | High speed DRAM architecture with uniform access latency |
US20070153621A1 (en) * | 2006-01-02 | 2007-07-05 | Ji Ho Cho | Semiconductor memory device and word line addressing method in which neighboring word lines are discontinuously addressed |
US20070291553A1 (en) * | 2006-06-09 | 2007-12-20 | Samsung Electronics Co., Ltd. | Data output circuits for an integrated circuit memory device in which data is output responsive to selective invocation of a plurality of clock signals, and methods of operating the same |
US8862811B2 (en) | 2011-09-29 | 2014-10-14 | Ps4 Luxco S.A.R.L. | Semiconductor device performing burst order control and data bus inversion |
Families Citing this family (46)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB9405914D0 (en) | 1994-03-24 | 1994-05-11 | Discovision Ass | Video decompression |
US6034674A (en) * | 1992-06-30 | 2000-03-07 | Discovision Associates | Buffer manager |
US5835740A (en) | 1992-06-30 | 1998-11-10 | Discovision Associates | Data pipeline system and data encoding method |
US5861894A (en) | 1993-06-24 | 1999-01-19 | Discovision Associates | Buffer manager |
JPH07122099A (en) * | 1993-10-29 | 1995-05-12 | Nec Corp | Semiconductor memory |
JP2734957B2 (en) * | 1993-12-24 | 1998-04-02 | 日本電気株式会社 | Control method of semiconductor memory circuit |
CA2145363C (en) | 1994-03-24 | 1999-07-13 | Anthony Mark Jones | Ram interface |
EP0683457A1 (en) * | 1994-05-20 | 1995-11-22 | Advanced Micro Devices, Inc. | A computer system including a snoop control circuit |
JP3157681B2 (en) * | 1994-06-27 | 2001-04-16 | 日本電気株式会社 | Logical data input latch circuit |
JP2982618B2 (en) * | 1994-06-28 | 1999-11-29 | 日本電気株式会社 | Memory selection circuit |
US6804760B2 (en) * | 1994-12-23 | 2004-10-12 | Micron Technology, Inc. | Method for determining a type of memory present in a system |
US5610864A (en) | 1994-12-23 | 1997-03-11 | Micron Technology, Inc. | Burst EDO memory device with maximized write cycle timing |
US6525971B2 (en) | 1995-06-30 | 2003-02-25 | Micron Technology, Inc. | Distributed write data drivers for burst access memories |
US5526320A (en) * | 1994-12-23 | 1996-06-11 | Micron Technology Inc. | Burst EDO memory device |
JPH0963262A (en) * | 1995-08-17 | 1997-03-07 | Fujitsu Ltd | Synchronous dram |
JP2907074B2 (en) * | 1995-08-25 | 1999-06-21 | 日本電気株式会社 | Semiconductor storage device |
KR100192573B1 (en) * | 1995-09-18 | 1999-06-15 | 윤종용 | Memory device of multi-bank structure |
JP2991094B2 (en) * | 1995-09-19 | 1999-12-20 | 日本電気株式会社 | Semiconductor storage device |
US6035369A (en) | 1995-10-19 | 2000-03-07 | Rambus Inc. | Method and apparatus for providing a memory with write enable information |
JPH09161471A (en) * | 1995-12-06 | 1997-06-20 | Internatl Business Mach Corp <Ibm> | Dram system and operating method for dram system |
US5715476A (en) * | 1995-12-29 | 1998-02-03 | Intel Corporation | Method and apparatus for controlling linear and toggle mode burst access sequences using toggle mode increment logic |
US7681005B1 (en) * | 1996-01-11 | 2010-03-16 | Micron Technology, Inc. | Asynchronously-accessible memory device with mode selection circuitry for burst or pipelined operation |
US6209071B1 (en) | 1996-05-07 | 2001-03-27 | Rambus Inc. | Asynchronous request/synchronous data dynamic random access memory |
JPH09320269A (en) * | 1996-05-31 | 1997-12-12 | Nippon Steel Corp | Address device |
US6009038A (en) * | 1996-05-31 | 1999-12-28 | United Microelectronics Corporation | Addressing unit |
KR980004988A (en) * | 1996-06-26 | 1998-03-30 | 김광호 | Burst counter |
US6401186B1 (en) | 1996-07-03 | 2002-06-04 | Micron Technology, Inc. | Continuous burst memory which anticipates a next requested start address |
US6981126B1 (en) * | 1996-07-03 | 2005-12-27 | Micron Technology, Inc. | Continuous interleave burst access |
JPH1050958A (en) * | 1996-08-05 | 1998-02-20 | Toshiba Corp | Semiconductor storage device and layout method for semiconductor storage device, and operation method for semiconductor storage device, and circuit arrangement pattern of semiconductor storage device |
US5784329A (en) * | 1997-01-13 | 1998-07-21 | Mitsubishi Semiconductor America, Inc. | Latched DRAM write bus for quickly clearing DRAM array with minimum power usage |
EP1895538A1 (en) * | 1997-10-10 | 2008-03-05 | Rambus, Inc. | Apparatus and method for pipelined memory operations |
US7103742B1 (en) | 1997-12-03 | 2006-09-05 | Micron Technology, Inc. | Burst/pipelined edo memory device |
JP3204384B2 (en) | 1997-12-10 | 2001-09-04 | エヌイーシーマイクロシステム株式会社 | Semiconductor memory circuit |
US6279071B1 (en) | 1998-07-07 | 2001-08-21 | Mitsubishi Electric And Electronics Usa, Inc. | System and method for column access in random access memories |
JP4748828B2 (en) * | 1999-06-22 | 2011-08-17 | ルネサスエレクトロニクス株式会社 | Semiconductor memory device |
JP2002245779A (en) * | 2001-02-20 | 2002-08-30 | Nec Microsystems Ltd | Semiconductor memory |
US20040148226A1 (en) * | 2003-01-28 | 2004-07-29 | Shanahan Michael E. | Method and apparatus for electronic product information and business transactions |
KR100535102B1 (en) * | 2003-05-23 | 2005-12-07 | 주식회사 하이닉스반도체 | Structure and method for transferring column address |
KR100546339B1 (en) * | 2003-07-04 | 2006-01-26 | 삼성전자주식회사 | Semiconductor device for implementing differential data strobe mode and single data strobe mode with data inversion scheme selectively |
KR100532471B1 (en) * | 2003-09-26 | 2005-12-01 | 삼성전자주식회사 | IO bandwidth controllable memory device and the control method of IO bandwidth |
KR100560773B1 (en) * | 2003-10-09 | 2006-03-13 | 삼성전자주식회사 | Semiconductor memory device capable of controlling burst length without resetting mode of operation and memory system including the same |
US20090097301A1 (en) * | 2005-06-01 | 2009-04-16 | Matsushita Electric Industrial Co., Ltd. | Semiconductor storage apparatus and semiconductor integrated circuit incorporating the same |
KR100615580B1 (en) * | 2005-07-05 | 2006-08-25 | 삼성전자주식회사 | Semiconductor memory device and data input and output method of the same, and memory system comprising the same |
JP2011034629A (en) * | 2009-07-31 | 2011-02-17 | Elpida Memory Inc | Semiconductor device |
US9330735B2 (en) | 2011-07-27 | 2016-05-03 | Rambus Inc. | Memory with deferred fractional row activation |
KR101983286B1 (en) | 2018-11-05 | 2019-05-28 | 선진테크 주식회사 | Snowfall Measuring Apparatus and Drive Method of the Same |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS621182A (en) * | 1985-06-26 | 1987-01-07 | Hitachi Ltd | Semiconductor memory device |
US4856106A (en) * | 1987-08-19 | 1989-08-08 | Mitsubishi Denki Kabushiki Kaisha | Synchronous static random access memory having precharge system and operating method thereof |
EP0393436A2 (en) * | 1989-04-21 | 1990-10-24 | Siemens Aktiengesellschaft | Static memory with pipe-line registers |
US5047984A (en) * | 1989-05-09 | 1991-09-10 | Nec Corporation | Internal synchronous static RAM |
US5341341A (en) * | 1992-03-26 | 1994-08-23 | Nec Corporation | Dynamic random access memory device having addressing section and/or data transferring path arranged in pipeline architecture |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100214435B1 (en) * | 1990-07-25 | 1999-08-02 | 사와무라 시코 | Synchronous burst-access memory |
US5253212A (en) * | 1990-12-01 | 1993-10-12 | Hitachi, Ltd. | Semiconductor memory IC and semiconductor memory device |
US5319759A (en) * | 1991-04-22 | 1994-06-07 | Acer Incorporated | Burst address sequence generator |
-
1993
- 1993-04-02 JP JP5077236A patent/JPH06290582A/en active Pending
-
1994
- 1994-03-30 DE DE69430076T patent/DE69430076T2/en not_active Expired - Lifetime
- 1994-03-30 DE DE69411428T patent/DE69411428T2/en not_active Expired - Lifetime
- 1994-03-30 EP EP94105060A patent/EP0618585B1/en not_active Expired - Lifetime
- 1994-03-30 EP EP97122998A patent/EP0840324B1/en not_active Expired - Lifetime
- 1994-04-01 US US08/221,574 patent/US5426606A/en not_active Ceased
- 1994-04-02 KR KR1019940007001A patent/KR0160360B1/en not_active IP Right Cessation
-
1997
- 1997-06-20 US US08/879,516 patent/USRE35934E/en not_active Expired - Lifetime
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS621182A (en) * | 1985-06-26 | 1987-01-07 | Hitachi Ltd | Semiconductor memory device |
US4856106A (en) * | 1987-08-19 | 1989-08-08 | Mitsubishi Denki Kabushiki Kaisha | Synchronous static random access memory having precharge system and operating method thereof |
EP0393436A2 (en) * | 1989-04-21 | 1990-10-24 | Siemens Aktiengesellschaft | Static memory with pipe-line registers |
US5047984A (en) * | 1989-05-09 | 1991-09-10 | Nec Corporation | Internal synchronous static RAM |
US5341341A (en) * | 1992-03-26 | 1994-08-23 | Nec Corporation | Dynamic random access memory device having addressing section and/or data transferring path arranged in pipeline architecture |
Cited By (43)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6567338B1 (en) | 1996-04-19 | 2003-05-20 | Integrated Device Technology, Inc. | Fully synchronous pipelined RAM |
US6785188B2 (en) | 1996-04-19 | 2004-08-31 | Integrated Device Technology, Inc. | Fully synchronous pipelined RAM |
US6256255B1 (en) | 1997-03-11 | 2001-07-03 | Micron Technology, Inc. | Multi-bank memory input/output line selection |
US6519719B1 (en) | 1997-06-13 | 2003-02-11 | Micron Technology, Inc. | Method and apparatus for transferring test data from a memory array |
US6560668B2 (en) | 1997-07-10 | 2003-05-06 | Micron Technology, Inc. | Method and apparatus for reading write-modified read data in memory device providing synchronous data transfers |
US6415340B1 (en) | 1997-07-10 | 2002-07-02 | Micron Technology, Inc. | Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths |
US6789175B2 (en) | 1997-07-10 | 2004-09-07 | Micron Technology, Inc. | Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths |
US6556483B2 (en) | 1997-07-10 | 2003-04-29 | Micron Technology, Inc. | Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths |
US6614698B2 (en) | 1997-07-10 | 2003-09-02 | Micron Technology, Inc. | Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths |
US6272608B1 (en) | 1997-07-10 | 2001-08-07 | Micron Technology, Inc. | Method and apparatus for synchronous data transfers in a memory device with lookahead logic for detecting latency intervals |
US6611885B2 (en) | 1997-07-10 | 2003-08-26 | Micron Technology, Inc. | Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths |
US20050033899A1 (en) * | 1998-01-04 | 2005-02-10 | Mosaid Technologies Incorporated | Semiconductor memory asynchronous pipeline |
US6591354B1 (en) | 1998-02-23 | 2003-07-08 | Integrated Device Technology, Inc. | Separate byte control on fully synchronous pipelined SRAM |
US6772312B2 (en) * | 1998-04-01 | 2004-08-03 | Mosaid Technologies Incorporated | Semiconductor memory having asynchronous pipeline stages |
US20070186034A1 (en) * | 1998-04-01 | 2007-08-09 | Mosaid Technologies Incorporated | Semiconductor memory asynchronous pipeline |
US6539454B2 (en) * | 1998-04-01 | 2003-03-25 | Mosaid Technologies Incorporated | Semiconductor memory asynchronous pipeline |
US7509469B2 (en) | 1998-04-01 | 2009-03-24 | Mosaid Technologies Incorporated | Semiconductor memory asynchronous pipeline |
US9548088B2 (en) | 1998-04-01 | 2017-01-17 | Conversant Intellectual Property Management Inc. | Semiconductor memory asynchronous pipeline |
US20100217928A1 (en) * | 1998-04-01 | 2010-08-26 | Ian Mes | Semiconductor Memory Asynchronous Pipeline |
US8601231B2 (en) | 1998-04-01 | 2013-12-03 | Mosaid Technologies Incorporated | Semiconductor memory asynchronous pipeline |
US7865685B2 (en) | 1998-04-01 | 2011-01-04 | Mosaid Technologies Incorporated | Semiconductor memory asynchronous pipeline |
US7178001B2 (en) | 1998-04-01 | 2007-02-13 | Mosaid Technologies Inc. | Semiconductor memory asynchronous pipeline |
US8122218B2 (en) | 1998-04-01 | 2012-02-21 | Mosaid Technologies Incorporated | Semiconductor memory asynchronous pipeline |
US20090175103A1 (en) * | 1998-04-01 | 2009-07-09 | Mosaid Technologies Incorporated | Semiconductor memory asynchronous pipeline |
US8078821B2 (en) | 1998-04-01 | 2011-12-13 | Mosaid Technologies Incorporated | Semiconductor memory asynchronous pipeline |
US20110202713A1 (en) * | 1998-04-01 | 2011-08-18 | Mosaid Technologies Incorporated | Semiconductor Memory Asynchronous Pipeline |
US6405280B1 (en) | 1998-06-05 | 2002-06-11 | Micron Technology, Inc. | Packet-oriented synchronous DRAM interface supporting a plurality of orderings for data block transfers within a burst sequence |
US6278633B1 (en) | 1999-11-05 | 2001-08-21 | Multi Level Memory Technology | High bandwidth flash memory that selects programming parameters according to measurements of previous programming operations |
US6330185B1 (en) | 1999-11-05 | 2001-12-11 | Multi Level Memory Technology | High bandwidth multi-level flash memory using dummy memory accesses to improve precision when writing or reading a data stream |
US20060146641A1 (en) * | 2000-07-07 | 2006-07-06 | Paul Demone | High speed DRAM architecture with uniform access latency |
US8045413B2 (en) | 2000-07-07 | 2011-10-25 | Mosaid Technologies Incorporated | High speed DRAM architecture with uniform access latency |
US7751262B2 (en) | 2000-07-07 | 2010-07-06 | Mosaid Technologies Incorporated | High speed DRAM architecture with uniform access latency |
US20090034347A1 (en) * | 2000-07-07 | 2009-02-05 | Mosaid Technologies Incorporated | High speed dram architecture with uniform access latency |
US20100232237A1 (en) * | 2000-07-07 | 2010-09-16 | Mosaid Technologies Incorporated | High speed dram architecture with uniform access latency |
US20040202036A1 (en) * | 2000-07-07 | 2004-10-14 | Paul Demone | High speed DRAM architecture with uniform access latency |
US7450444B2 (en) | 2000-07-07 | 2008-11-11 | Mosaid Technologies Incorporated | High speed DRAM architecture with uniform access latency |
US6891772B2 (en) | 2000-07-07 | 2005-05-10 | Mosaid Technologies Incorporated | High speed DRAM architecture with uniform access latency |
US8503250B2 (en) | 2000-07-07 | 2013-08-06 | Mosaid Technologies Incorporated | High speed DRAM architecture with uniform access latency |
US20070153621A1 (en) * | 2006-01-02 | 2007-07-05 | Ji Ho Cho | Semiconductor memory device and word line addressing method in which neighboring word lines are discontinuously addressed |
US7646663B2 (en) * | 2006-01-02 | 2010-01-12 | Samsung Electronics Co., Ltd. | Semiconductor memory device and word line addressing method in which neighboring word lines are discontinuously addressed |
US20070291553A1 (en) * | 2006-06-09 | 2007-12-20 | Samsung Electronics Co., Ltd. | Data output circuits for an integrated circuit memory device in which data is output responsive to selective invocation of a plurality of clock signals, and methods of operating the same |
US7474588B2 (en) | 2006-06-09 | 2009-01-06 | Samsung Electronics Co., Ltd. | Data output circuits for an integrated circuit memory device in which data is output responsive to selective invocation of a plurality of clock signals, and methods of operating the same |
US8862811B2 (en) | 2011-09-29 | 2014-10-14 | Ps4 Luxco S.A.R.L. | Semiconductor device performing burst order control and data bus inversion |
Also Published As
Publication number | Publication date |
---|---|
EP0618585B1 (en) | 1998-07-08 |
EP0840324A3 (en) | 1998-12-09 |
EP0618585A2 (en) | 1994-10-05 |
DE69411428T2 (en) | 1999-03-04 |
EP0618585A3 (en) | 1994-12-14 |
DE69430076T2 (en) | 2002-11-14 |
DE69411428D1 (en) | 1998-08-13 |
US5426606A (en) | 1995-06-20 |
KR0160360B1 (en) | 1999-02-01 |
EP0840324B1 (en) | 2002-03-06 |
JPH06290582A (en) | 1994-10-18 |
DE69430076D1 (en) | 2002-04-11 |
EP0840324A2 (en) | 1998-05-06 |
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Legal Events
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AS | Assignment |
Owner name: NEC CORPORATION, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TAKAI, YASUHIRO;REEL/FRAME:008643/0804 Effective date: 19940517 |
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