USRE37413E1 - Semiconductor package for a semiconductor chip having centrally located bottom bond pads - Google Patents
Semiconductor package for a semiconductor chip having centrally located bottom bond pads Download PDFInfo
- Publication number
- USRE37413E1 USRE37413E1 US09/152,702 US15270298A USRE37413E US RE37413 E1 USRE37413 E1 US RE37413E1 US 15270298 A US15270298 A US 15270298A US RE37413 E USRE37413 E US RE37413E
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- US
- United States
- Prior art keywords
- leads
- semiconductor chip
- support
- attached
- contoured
- Prior art date
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- Y10T29/49121—Beam lead frame or beam lead device
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49169—Assembling electrical component directly to terminal or elongated conductor
- Y10T29/49171—Assembling electrical component directly to terminal or elongated conductor with encapsulating
- Y10T29/49172—Assembling electrical component directly to terminal or elongated conductor with encapsulating by molding of insulating material
Definitions
- the present invention relates to a semiconductor package, and more particularly to a semiconductor package suitable for packaging a center pad layout-shaped memory chip wherein paddles of a lead frame are removed and outer leads of a lead frame are not protruded from the package but only exposed to a lower surface of molding resin of a semiconductor package.
- semiconductor packages may be mainly classified into a semiconductor of SOP (small outline package) type and a semiconductor of SOJ (small outline J-lead) type.
- the semiconductor packages are manufactured in accordance to following procedures.
- a semiconductor chip is attached on paddles of a lead frame and then wire bonding is carried out between inner leads of the lead frame and pads on the semiconductor chip.
- the wire bonded semiconductor and lead frame are molded by molding resin. Thereafter, the resulting product is subjected to deflash, trimming and forming procedures so that outer leads of the lead frame are protruded from the molded resin and then bent into predetermined shape respectively.
- FIGS. 2 and 3 there are shown a front section and a bottom of a semiconductor package of LOC (lead on chip) type.
- a semiconductor chip 3 is formed with a plurality of bond pads 3 a at central portion thereof.
- Inner leads 4 a of a lead frame 4 without paddles are attached on a surface of the semiconductor chip 3 at both sides of the bond pads 3 a by means of insulation tapes 6 .
- the inner leads 4 a are electrically connected to the bond pads 3 a of the semiconductor chip 3 by means of metal wires 7 , respectively.
- power supplying pads of the bond pads 3 a are electrically connected to bus bars 5 by metal wires 7 , respectively.
- the resulting semiconductor chip 3 and the inner leads 4 a of the lead frame 4 are molded by molding resin 1 .
- the above-mentioned prior semiconductor packages are manufactured in such a manner that a semiconductor chip aggregate is subjected to a sawing step for dividing the semiconductor chip aggregate into separate semiconductor chips 3 and the semiconductor chip 3 is subjected to a die bonding step for attaching the separated semiconductor chip 3 to a lead frame 4 , a wire bonding step for electrically connecting bond pads 3 a of the semiconductor chip 3 to inner leads 4 a of the lead frame 4 respectively, a molding step for enveloping the wire bonded semiconductor chip 3 and lead frame 4 , a deflashing step, a solder plating step, a trimming step for cutting dampers of the lead frame 4 , a forming step for bending outer leads into a certain shape, and a marking step.
- the semiconductor package prepared as described above have outer leads protruded from the mold resin.
- the outer leads are formed into a certain shape and then mounted on a printed circuit board.
- the prior semiconductor packages have various disadvantages as follows.
- the prior semiconductor packages occupy large space due to the outer leads protruded from mold resins when the semiconductor packages are mounted on printed circuit boards.
- the semiconductor packages require a trimming step and a forming step after a molding procedure, manufacturing process of the packages becomes complicated so that their manufacturing cost and poor products occurring rate are increased.
- the present invention is made in view of the above-described prior art problems and an object of the invention is to provide a semiconductor package which is designed to occupy small space required to be mounted on a printed circuit board and to reduce manufacturing cost by omitting manufacturing procedures next to a molding procedure.
- Another object of the invention is to provide a semiconductor package which has improved lead conductance and thus electrical property by reducing length between its inner leads and outer leads.
- a semiconductor package comprising: a semiconductor chip which is formed with a plurality of bond pads at a central portion of its bottom surface; a lead frame including leads connected to bond pads for input/output of the bond pads respectively and bus bars connected to power supplying pads of the bond pads; insulation adhesives for attaching inner leads of the leads and inner leads of the bus bars to a bottom surface of the semiconductor chip formed with the bond pads; metal wires for electrically connecting the inner leads of the leads and the inner leads of the bus bars to the bond pads respectively; and a molding compound enveloping the semiconductor chip assembly with outer leads of the lead frame exposed to outside.
- the leads are bent into a certain shape respectively at their inner leads and the outer leads and then the outer leads are attached to polyimide based adhesive tapes.
- the inner leads of the leads are attached to a bottom surface of the semiconductor chip via insulating films or insulating paste applied to the bottom surface.
- the attached lead frame and the semiconductor chip are molded such that the outer leads are not protruded from the molded resin but exposed to outside.
- paddles are omitted and the outer leads are not protruded from the package but exposed to outside so that the exposed outer leads can be connected to a connection pattern of a printed circuit board. Since the semiconductor package has not protruded outer leads, space occupied by the package is reduced when the package is mounted on a printed circuit board. Also, it is possible to abbreviate trimming and forming procedures next to a molding procedure in its manufacturing process.
- FIG. 1A is a schematic view of a prior SOP type of semiconductor package
- FIG. 1B is a schematic view of a prior SOJ type of semiconductor package
- FIG. 2 is a vertical sectional view of a prior LOC type of semiconductor package
- FIG. 3 is a bottom plan view of the semiconductor package shown in FIG. 2, showing its inner construction
- FIG. 4 is a vertical sectional view of a semiconductor package according to the present invention.
- FIG. 5 is a bottom plan view of the semiconductor package shown in FIG. 4, showing its inner construction
- FIG. 6A is a front elevational view of a semiconductor package according to the invention.
- FIG. 6B is a bottom plan view of the semiconductor package shown in FIG. 6 A. ;
- FIG. 4 shows a vertical section of a semiconductor package according to the present invention
- FIG. 5 shows an inner construction of the semiconductor package shown in FIG. 4 .
- the semiconductor package of the present invention comprises a semiconductor chid 3 which is formed with a plurality of bond pads 3 a at a central portion of its bottom surface, a lead frame 10 including leads 11 connected to bond pads for input/output of the bond pads 3 a respectively and bus bars 12 connected to power supplying pads of the bond pads 3 a, insulation adhesives 6 for attaching inner leads 11 of the leads 11 and inner leads 12 a of the bus bars 12 to a bottom surface of the semiconductor chip 3 formed with the bond pads 3 a, metal wires 7 for electrically connecting the inner leads 11 a of the leads 11 and the inner leads 12 a of the bus bars 12 to the bond pads 3 a respectively, and a molding compound 8 enveloping the semiconductor chip assembly with outer leads 11 b and 12 b of the lead frame 10 exposed to outside.
- the plurality of inner leads 11 a, 12 a and outer leads 11 b, 12 b of the leads 11 and the bus bars 12 are bent into a predetermined shape respectively and arranged in a row. Then, the outer leads 11 b, 12 b are attached to adhesive tapes (not shown) at their outer surfaces so that the leads 11 and the bus bars 12 are integrally held.
- the adhesive tapes which may serve as a support during a molding procedure, are removed after a the molding procedure.
- the lead frame 10 is attached to the semiconductor package 3 in such a manner that insulating adhesives 6 such as insulating films and insulating paste are applied to the bottom surface of the semiconductor chip 3 formed with the bond pads 3 a and then the inner leads 11 a, 12 a of the leads 11 and the bus bars 12 are attached to the insulating adhesives 6 .
- insulating adhesives 6 such as insulating films and insulating paste are applied to the bottom surface of the semiconductor chip 3 formed with the bond pads 3 a and then the inner leads 11 a, 12 a of the leads 11 and the bus bars 12 are attached to the insulating adhesives 6 .
- the leads 11 and the bus bars 12 of the semiconductor package of the present invention are shorter than those of a prior LOC type of semiconductor package in lengths between its inner leads 11 a, 12 a and its outer leads 11 b, 12 b so that lead conductance is increased when a memory chip of 16-mega-bit DRAM or greater is packaged.
- heat occurring in operation of chip can be easily discharged from the short leads.
- FIG. 6A shows a front side of the semiconductor package of the invention and FIG. 6B shows a bottom surface of semiconductor package of the invention.
- the outer leads 11 b and 12 b of the leads 11 and the bus bars 12 are not protruded from the semiconductor package but are flush with the bottom surface of the semiconductor package.
- the outer leads 11 b and 12 b of the leads 11 and the bus bars 12 are arranged in a row at the bottom surface of the package and faces to outside to be contacted with elements of a printed circuit board, as shown in FIG. 6B.
- the leads may be elongated and contoured and extend away from the bottom surface, and the exposed portion of the leads may occupy less than a majority portion of the bottom surface.
- a semiconductor chip 3 which has been cut separately is applied with insulating adhesive 6 such insulating film and insulating paste at its bottom surface formed with bond pads 3 a.
- Inner leads 11 a and 12 a of leads 11 and bus bars 12 are attached to the bottom surface of the chid via the insulating adhesive 6 applied to the bottom surface.
- the lead frame 10 attached to the semiconductor chip 3 is die-attached in a wire bonder (a wire bonding apparatus) and subjected to a wire bonding procedure for electrically connecting the inner leads 11 a, 12 a of the leads 11 and the bus bars 12 to the bond pads 3 a by metal wires 7 such as gold and aluminum wires.
- a wire bonder a wire bonding apparatus
- the resulting semiconductor chip assembly is subjected to a known transfer molding procedure to be enveloped. Then, as adhesive tapes attached to a bottom surface of the molded resin are removed, the outer leads 11 b and 12 b of the leads 11 and the bus bars 12 are exposed to outside. Thereafter, as the bottom surface of the molded package and the exposed outer leads are simply removed by a deflash procedure, the manufacturing process of the semiconductor package is completed.
- the semiconductor package of the invention as prepared above is mounted on a printed circuit board such that the exposed outer leads 11 b and 12 b are connected to a pattern of printed circuit board by a soldering.
- FIG. 7 illustrates a manufacturing process such as described herein.
- the semiconductor chip is manufactured, as described earlier.
- leads 11 are formed and attached to the support, which may be an adhesive tape as described earlier.
- inner leads 11 a and 12 a are attached to semiconductor chip 3 with insulating adhesive 6 .
- inner leads 11 a and 12 a are wire bonded to bond pads 3 a.
- the resulting semiconductor chip assembly is subjected to a transfer molding procedure.
- the adhesive tapes serving as the support during the molding procedure are removed.
- the semiconductor package of the present invention is mounted on a printed circuit board.
- the present invention can leave out procedures next to a molding step. That is, since a prior semiconductor package has outer leads protruded therefrom, a manufacturing process of a prior semiconductor package requires a forming procedure for bending the protruded outer leads and a trimming procedure for cutting dampers of leads. However, since leads according to the invention are attached to adhesive tapes to form an integral lead frame and outer leads of leads are exposed to outside, a manufacturing process of the invention does not require trimming and forming procedures.
- the present invention has advantages in that since the number of manufacturing steps is significantly reduced, occurrence of poor products and manufacturing cost are reduced.
- the semiconductor package of the invention since the semiconductor package of the invention has not outer leads protruded therefrom, space occupied by the semiconductor package is reduced thereby allowing the packages to be densely mounted when the packages are mounted on a printed circuit board.
- the semiconductor package of the invention has leads shortened as possible as, it is possible to improve its electrical property and to radiate heat easily as compared with prior art.
- the semiconductor package of the invention While prior semiconductor package may have gaps between outer leads and a molded resin due to outer shock applied to the outer leads during trimming and forming procedures, the semiconductor package of the invention has outer leads exposed to out side and does not require trimming and forming procedures so that the outer leads are not shocked. Therefore, the semiconductor package of the invention can prevent gaps from occurring in the contact area and thus improve humidity resistance. Also, since the semiconductor package is tested in state of tip, the test can be precisely carried out without a particular testing socket. That is, “Good rate” can be reduced.
Abstract
Description
Claims (43)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/152,702 USRE37413E1 (en) | 1991-11-14 | 1998-09-14 | Semiconductor package for a semiconductor chip having centrally located bottom bond pads |
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR91-19458 | 1991-11-14 | ||
KR2019910019458U KR940007757Y1 (en) | 1991-11-14 | 1991-11-14 | Semiconductor package |
US07/970,771 US5363279A (en) | 1991-11-14 | 1992-11-03 | Semiconductor package for a semiconductor chip having centrally located bottom bond pads |
US08/748,460 USRE36097E (en) | 1991-11-14 | 1996-11-08 | Semiconductor package for a semiconductor chip having centrally located bottom bond pads |
US09/152,702 USRE37413E1 (en) | 1991-11-14 | 1998-09-14 | Semiconductor package for a semiconductor chip having centrally located bottom bond pads |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US07/970,771 Reissue US5363279A (en) | 1991-11-14 | 1992-11-03 | Semiconductor package for a semiconductor chip having centrally located bottom bond pads |
Publications (1)
Publication Number | Publication Date |
---|---|
USRE37413E1 true USRE37413E1 (en) | 2001-10-16 |
Family
ID=19322207
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US07/970,771 Ceased US5363279A (en) | 1991-11-14 | 1992-11-03 | Semiconductor package for a semiconductor chip having centrally located bottom bond pads |
US08/748,460 Expired - Lifetime USRE36097E (en) | 1991-11-14 | 1996-11-08 | Semiconductor package for a semiconductor chip having centrally located bottom bond pads |
US09/152,702 Expired - Lifetime USRE37413E1 (en) | 1991-11-14 | 1998-09-14 | Semiconductor package for a semiconductor chip having centrally located bottom bond pads |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US07/970,771 Ceased US5363279A (en) | 1991-11-14 | 1992-11-03 | Semiconductor package for a semiconductor chip having centrally located bottom bond pads |
US08/748,460 Expired - Lifetime USRE36097E (en) | 1991-11-14 | 1996-11-08 | Semiconductor package for a semiconductor chip having centrally located bottom bond pads |
Country Status (4)
Country | Link |
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US (3) | US5363279A (en) |
JP (2) | JPH0546045U (en) |
KR (1) | KR940007757Y1 (en) |
DE (1) | DE4238646B4 (en) |
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US20030116839A1 (en) * | 2001-12-24 | 2003-06-26 | Wolfgang Knapp | Semiconductor module and method of producing a semiconductor module |
US6921969B2 (en) * | 2001-12-24 | 2005-07-26 | Abb Research Ltd. | Semiconductor module and method of producing a semiconductor module |
Also Published As
Publication number | Publication date |
---|---|
JPH1093001A (en) | 1998-04-10 |
DE4238646A1 (en) | 1993-06-03 |
JPH0546045U (en) | 1993-06-18 |
USRE36097E (en) | 1999-02-16 |
KR940007757Y1 (en) | 1994-10-24 |
US5363279A (en) | 1994-11-08 |
DE4238646B4 (en) | 2006-11-16 |
KR930012117U (en) | 1993-06-25 |
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