USRE40112E1 - Semiconductor package and method for fabricating the same - Google Patents
Semiconductor package and method for fabricating the same Download PDFInfo
- Publication number
- USRE40112E1 USRE40112E1 US10/825,670 US82567004A USRE40112E US RE40112 E1 USRE40112 E1 US RE40112E1 US 82567004 A US82567004 A US 82567004A US RE40112 E USRE40112 E US RE40112E
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- Prior art keywords
- circuit board
- major surface
- strip
- board strip
- fashion
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Abstract
Description
Claims (35)
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US10/825,670 USRE40112E1 (en) | 1999-05-20 | 2004-04-14 | Semiconductor package and method for fabricating the same |
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KR1019990018244A KR20000074350A (en) | 1999-05-20 | 1999-05-20 | semi-conductor package and manufacturing method thereof |
KR10-1999-0037928A KR100369394B1 (en) | 1999-09-07 | 1999-09-07 | substrate for semiconductor package and manufacturing method of semiconductor package using it |
KR1019990037925A KR100365054B1 (en) | 1999-09-07 | 1999-09-07 | substrate for semiconductor package and manufacturing method of semiconductor package using it |
US09/574,541 US6395578B1 (en) | 1999-05-20 | 2000-05-19 | Semiconductor package and method for fabricating the same |
US10/825,670 USRE40112E1 (en) | 1999-05-20 | 2004-04-14 | Semiconductor package and method for fabricating the same |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US20080085572A1 (en) * | 2006-10-05 | 2008-04-10 | Advanced Chip Engineering Technology Inc. | Semiconductor packaging method by using large panel size |
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