|Número de publicación||USRE41016 E1|
|Tipo de publicación||Concesión|
|Número de solicitud||US 10/952,594|
|Fecha de publicación||1 Dic 2009|
|Fecha de prioridad||27 Sep 1995|
|Número de publicación||10952594, 952594, US RE41016 E1, US RE41016E1, US-E1-RE41016, USRE41016 E1, USRE41016E1|
|Cesionario original||Kabushiki Kaisha Toshiba|
|Exportar cita||BiBTeX, EndNote, RefMan|
|Citas de patentes (14), Clasificaciones (4), Eventos legales (1)|
|Enlaces externos: USPTO, Cesión de USPTO, Espacenet|
More than one reissue application has been filed for the reissue of U.S. Pat. No. 5,818,249. This is a continuation of application Ser. No. 09/686,200 filed Oct. 5, 2000, now U.S. Pat. No. RE40105 issued on Feb. 26, 2008, which is a reissue application of U.S. Pat. No. 5,818,249 issued Oct. 6, 1998. This continuation application also claims benefit of priority under 35 U.S.C. § 119 to Japanese Patent Application No. 7- 249531, filed on Sep. 27, 1995.
1. Field of the Invention
The present invention relates to a probe card for testing semiconductor integrated circuits and also to a method of probe-testing semiconductor integrated circuits by using the probe card.
2. Description of the Related Art
Probing test is performed on semiconductor integrated circuits for their electrical characteristics. The test is carried out after the wafer process and before the dicing process, namely after the integrated circuits have been formed in a semiconductor wafer, arranged in rows and columns. By this test it is determined whether the integrated circuits are defective or not. Any integrated circuit found defective is not subjected to an assembly step. This helps to prevent an unnecessary increase in the manufacturing cost of semiconductor devices.
The integration density of semiconductor integrated circuits (ICs) has much increased in recent years. Because of the increased integration density, the time of testing each integrated circuit, or each IC chip (hereinafter called “chip”), has increased. Until recently the probing test has been performed, chip by chip. At present a plurality of chips are tested simultaneously, in order to shorten the time of testing one chip.
The integration density of semiconductor integrated circuits, particularly semiconductor memories, is still increasing. The time for testing one chip inevitably increases even if the probe card 5 (
When the probe card 5′ was used to accomplish a probing test, however, more chips were likely found to be found defective than in the case where the probe card 5 shown in
Some reasons for the insufficient test accuracy, that are conceivable at present, will be discussed below.
The response signals output from all chips simultaneously tested are supplied at the same time to the tester via the probe card 5′. The tester compares the levels, leading edge time and trailing edge time of the response signals with prescribed values or ranges, determining whether the chips are flawless or not.
The probe needles of the groups 9a to 9h are connected to probe contacts 11 provided on the circumferential edge of the probe card 5′ by wires (not shown) which are provided within the card 5′. It is at the probe contacts 11 that the probe card 5′ can contact a tester. The response signal from each chip tested has its level lowered before reaching the tester, because of the resistance of the wire provided in the card 5′. It is natural that the leading and trailing edge time of the response signal shift in accordance with the capacitance of the wire.
The more groups of probe needles provided to test more chips at a time, the greater the diameter D of the probe card 5′. As the diameter D increases, so does the difference in length between a wire connecting a needle located at the center of the card 5′ to the associated contact 11 and a wire associated a needle at the edge of the card 5′ to the associated contact 11. As this difference increases, the differences in resistance and capacitance among the wires increase in proportion. Further, the longer the wires, the higher the probability of crosstalk among the wires.
Moreover, the larger the diameter D, the more likely the probe card 5′ will warp. If the card 5′ warps, the contact resistances between the chip pads on the one hand and the probe needles on the other will become different, and so will become the contact resistances between the probe needles on the one hand and the tester on the other hand. As the probe card 5′ warps, a stress is exerted on the wires provided in the card 5′. Each wire may have its electrical characteristics altered at that part on which an excessive stress is applied.
Any or some of the problems described above impair the accuracy of the probing test achieved by the probe card 5′. Due to these problems, some of the chips simultaneously tested may be determined to be defective though they are actually flawless, particularly when the tester compares the levels, leading edges and trailing edges of the response signals from the chips with the prescribed values or ranges. In other words, the difference in resistance and capacitance among the wires provided in the card 5′, the difference in pad-needle contact resistance, the difference in needle-tester contact resistance, the changes in the electrical characteristics of the wires, and the crosstalk among the wires prevent the tester from detecting the true characteristics of the chips tested at the same time.
This deterioration of probing-test accuracy is particularly prominent in the test of semiconductor memories having a large storage capacity. This is because these memories operate at so high a speed that only a little allowance is provided for the shifting of the leading and trailing edge time of each signal.
A semiconductor memory having a large storage capacity is one of the most delicate and sensitive devices. Its operation will be jeopardized if even a very small error is made. To see whether such a small error occurs or not, the memory is subjected to proving test which is performed by using a probe card under strict conditions. Therefore, a problem with the wires provided in the probe card lower the test accuracy, even if the problem is a very small one.
As indicated above, it is demanded that the time for performing probing test on semiconductor integrated circuits (ICs) be reduced as much as possible. To meet the demand it suffices to test as many IC chips as possible, at the same time. However, the more IC chips are tested simultaneously, the more chips will be determined to be defective though they are actually flawless. This would increase the manufacturing cost of the semiconductor integrated circuit.
Accordingly, the object of the present invention is to provide a probe card which can help to enhance the productivity of semiconductor integrated circuits and to reduce the manufacturing cost thereof, and also to provide a method of probe-testing semiconductor integrated circuits by using the probe card.
A probe card according to the invention is designed to test semiconductor integrated circuits formed on a semiconductor wafer and arranged in rows and columns. The probe card has groups of probe needles provided to contact semiconductor integrated circuits arranged in two columns and at least two rows. It receives a test signal from the tester and supplies the test signal simultaneously to these semiconductor integrated circuits through the groups of probe needles. It receives response signals simultaneously from the semiconductor integrated circuits through the groups of probe needles and then supplies the response signals to the tester.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention and, together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.
Embodiments of the present invention will now be described, with reference to the accompanying drawings. The components shown in one drawing, which are similar or identical to those shown in any other drawing, are designated at the same reference numerals and will not be described in detail.
The probe card 15 is designed to probe-test the chips 3. It comprises eight groups 19a to 19h of probe needles, a substrate 20 and probe contacts 21. The probe needles of the groups 19a to 19h can contact eight chips 3a to 3h arranged in four rows and two columns. The card substrate 20 has a rectangular through hole 17 having two short sides and two long sides. The first to fourth groups 19a to 19d of needles are provided on the card substrate 20 along one long side of the hole 17, and the fifth to eighth groups 19e to 19h of needles are provided on the card substrate 20 along the other long side of the hole 17. In other words, the groups 19a to 19h of needles are arranged in two rows, each row consisting of four groups. As shown in
In operation, the probe card 15 is positioned with respect to the semiconductor wafer 1, such that the probe needles of the groups 19a to 19h contact the outer pads 31 of the chips 3a to 3h, respectively, as is illustrated in
The probe card 15 shown in
Furthermore, the probe card 15 has a diameter D as small as that of the conventional probe card 5 (
In view of these advantages, the probe card 15 can serve to enhance the productivity production of semiconductor integrated circuits and also to reduce the manufacturing cost of semiconductor integrated circuits.
When the probe card 15 was used, testing chips 3a to 3h arranged in four rows and two columns, six of the chips were found to be flawless, as can be seen from FIG. 5B. Only one of the chips was found to be defective, though it was actually flawless, as can be understood from FIG. 5B. It should be noted that the eight chips tested by using the probe card 15 were respectively identical in characteristics to those eight chips tested by using the conventional probe card 5′.
Namely, some of the flawless chips which were regarded as defective when tested by using the conventional probe card 5′ were correctly found to flawless when tested by using the probe card 15 according to the invention. In other words, the probe card 15 serves to test chips with high accuracy, thus saving flawless chips which would have been discarded as defective if the conventional probe card 5′ had been used. As a result, the probe card 15 serves to decrease the manufacturing cost of semiconductor integrated circuits.
A probe card 15 according to the second embodiment will be described, with reference to
As shown in
Thus the four groups 19a to 19d of probe needles to contact the chips 3a to 3d, groups 21a to 21d of probe contacts, and groups 37a to 37d of wires are arranged in the right half 33R of the substrate. The remaining four groups 19e to 19h of probe needles to contact the chips 3e to 3h, groups 21e to 21h of probe contacts, and groups 37e to 37h of wires are arranged in the right left half 33L of the substrate.
Arranged as shown in
Another probe card 15 according to the third embodiment of this invention will be described, with reference to
As illustrated in
Since the wires 37 of each type are provided on one layer, not together with the wires of any other type, the crosstalk among the wires 37 is far less than in the case all wires are arranged densely on one and the same layer. The probe card 15 according to the third embodiment can, therefore, help to achieve high-accuracy probing test. It has eight groups of probe needles and can serve to test eight chips at the same time.
The third embodiment can be used in combination with the probe card according to the second embodiment.
Methods of probe-testing semiconductor integrated circuits by using the probe card according to the invention will be described as the fourth, fifth and sixth embodiments.
As shown in
With this method, the more test stations are installed, the more chips can be tested at the same time with high accuracy. Namely, L×M chips can be tested at a time, where L is the number of chips that can be simultaneously tested by using one probe card, and M is the number of test stations installed.
In the instance shown in
As illustrated in
Still further, the number of chips tested simultaneously at one test station increases since two or more probe cards 15 are attached to one test station. Therefore, the facility cost for testing one chip is low. Having only one test station, the prober probing system shown in
As may be understood from
In the sixth embodiment, two test stations 43-1 and 43-2 are provided for one tester 41, and two probe cards are attached to each test station. To be more specific, probe cards 15-1 and 15-2 are attached to the first test station 43-1, and probe cards 15-3 and 15-4 to the second test station 43-2. Two semiconductor wafers 1—1 and 1-2 are simultaneously tested at the test stations 43-1 and 43-2, respectively, by using the four probe cards 15-1 to 15-4.
The probe-testing method according to the sixth embodiment can test L×M×N chips at the same time, where L is the number of chips one probe card can test at a time, M is the number of test station provided, and N is the number of probe cards attached to one test station. The sixth embodiment can serve to test many chips simultaneously with high accuracy as does the fourth embodiment, and can achieve good cost performance as does the fifth embodiment.
A semiconductor IC chips chip which can be easily tested by using a probe card which is according to the seventh embodiment of the invention will now be described.
Like the first to third embodiments, this probe card is designed to test IC chips arranged in two columns and at least two rows, at the same time, to determine whether the chips are flawless or defective. The probe card comprises a substrate having a rectangular through hole. It is desirable that some of the probe needles be arranged along one long side of the hole to contact the pads of the chips provided on a semiconductor wafer and forming one column and that the other probe needles be arranged along the other long side of the hole to contact the pads of chips provided on the wafer and forming a next column. If the probe needles are thus arranged, the wires provided on or in the substrate can be made shortest as has been explained in conjunction with the second embodiment.
A semiconductor IC chip should have pads arranged in a column to be tested by using the a probe card according to the invention, which has groups of probe needles arranged in the specific manner described above.
It is easy to bring the probe needles of one group 19 provided on the probe card into contact with the pads 31 because the pads 31 are arranged in a column. Even if identical chips on the semiconductor wafer are arranged in two columns as shown in
Alternatively, the pads 31 may be arranged in staggered fashion as is illustrated in FIG. 12.
A probe card 15 according to the eighth embodiment of this invention will be described, with reference to
As shown in
Designed to test chips arranged in eight rows, the probe card 15 inevitably have has a larger diameter D than the first embodiment (FIG. 3). Hence, it may have the same problems as does the conventional probe card 5′ (FIG. 2). Nevertheless, the eighth embodiment will be practically useful since the probe card technology is well expected to advance to simultaneously test 16 chips arranged in eight rows and two columns, with accuracy as high as in the case eight chips arranged in four rows and two columns are tested at the same time. Needless to say, the eighth embodiment has a smaller diameter than a conventional probe card which is designed to test 16 chips arranged in a single column. The eighth embodiment (
As can be understood from the eighth embodiment, the present invention is not limited to probe cards which are designed to test eight chips arranged in four rows and two columns. Rather, the invention can provide probe cards which serve to test more chips at a time, arranged in more rows and two columns.
A probe card according to the ninth embodiment of the present invention will be described, with reference to
As shown in
A probe card according to the tenth embodiment of the invention will be described, with reference to
In the probe cards 15 according to the invention, which are shown in
As has been described, the present invention can provide a probe card which can help to enhance the productivity of semiconductor integrated circuits and to reduce the manufacturing cost thereof, and can also provide a method of probe-testing semiconductor integrated circuits by using the probe card.
Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details, representative devices, and illustrated examples shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.
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|JPH0992694A||Título no disponible|
|JPH04230045A||Título no disponible|
|JPH05113451A||Título no disponible|
|Clasificación de EE.UU.||324/754.07, 324/750.3, 324/762.02|