USRE41792E1 - Controllable integrator - Google Patents

Controllable integrator Download PDF

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USRE41792E1
USRE41792E1 US10/614,084 US61408403A USRE41792E US RE41792 E1 USRE41792 E1 US RE41792E1 US 61408403 A US61408403 A US 61408403A US RE41792 E USRE41792 E US RE41792E
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amplifier
cells
pair
output
amplifier cells
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Sehat Sutardja
Pantas Sutardja
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Cavium International
Marvell Asia Pte Ltd
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Marvell International Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
    • G06G7/18—Arrangements for performing computing operations, e.g. operational amplifiers for integration or differentiation; for forming integrals
    • G06G7/184—Arrangements for performing computing operations, e.g. operational amplifiers for integration or differentiation; for forming integrals using capacitive elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G1/00—Details of arrangements for controlling amplification
    • H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
    • H03G1/0017—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier
    • H03G1/0029—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier using FETs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G5/00—Tone control or bandwidth control in amplifiers
    • H03G5/02—Manually-operated control
    • H03G5/04—Manually-operated control in untuned amplifiers
    • H03G5/10—Manually-operated control in untuned amplifiers having semiconductor devices

Definitions

  • This invention relates to integrators and more particularly to circuitry in an integrated circuit that controls frequency response characteristics over a wide range of frequencies with adjustable capacitance and controllable transconductance.
  • Circuit components formed in integrated circuits commonly exhibit wide variations in operating characteristics attributable to variations in the semiconductor processes that form the integrated circuit of such components.
  • additional or redundant components may be formed in an integrated circuit during the processing phase, and such additional components may thereafter be connected in or out of a circuit using a laser beam to selectively sever connecting links as required to adjust the operating characteristics of the circuit.
  • signal controllable switches may be incorporated into the design of the integrated circuit to selectively connect additional components in response to externally applied control signals.
  • switches are not ideal in that they incorporate appreciable resistance into a circuit in the conductive state which can be detrimental to high frequency operating characteristics of the integrated circuit.
  • additional capacitive components may be selectively switched into circuit configuration in response to external control signals without introducing significant resistance with the capacitive components.
  • controllable gain elements may be selectively controlled to amplify the effectiveness of capacitive components in the circuit for a wide range of operating frequency characteristics of the circuit as selectively configured.
  • FIG. 1 is a circuit diagram of a conventional transconductance integrator
  • FIG. 2 is a circuit diagram of one embodiment of the present invention.
  • FIG. 3 is a graph illustrating the operating characteristics of a transconductance amplifier
  • FIG. 4 is a circuit diagram of another embodiment of the present invention for providing wide dynamic control of operating frequency characteristics of the composite circuitry.
  • a conventional integrator including a differential pair of gain stages 9 , 11 such as field-effect transistors having control electrodes, or gates, coupled to receive control signals applied to inputs 13 , 15 .
  • the source electrodes, or sources, of the gain stages are coupled together and to a controllable current source 17
  • each of the drain electrodes, or drains is coupled to a controllable current sources 19 , 21 and to one or more capacitive elements 23 , 25 .
  • the sum of the current sources 19 , 21 is usually set equal to the current from source 17 .
  • Selected ones of the capacitive elements may be coupled to ground, for example, via links that may be removed via laser-beam machining to alter the operating frequency characteristics of the circuit.
  • semiconductor switches may be substituted (not shown) for the links to facilitate control of capacitance in the circuit in response to externally applied signals.
  • semiconductor switches commonly introduce significant resistance along with capacitance thus switched into the circuit, and this adversely affects high frequency operating characteristics of the circuit thus configured.
  • each capacitive element is formed as a pair of gain elements 27 , 29 such as insulated-gate field-effect transistors with source and drain connected in common as one capacitive electrode and with the gate forming another capacitive electrode.
  • the source-drain connections are connected in common to a control switch 31 that may also include a gain element responsive to an applied control signal for switching in or out the differential pair of capacitive components 27 , 29 .
  • control input 33 representsative of the ON condition for NMOS type transistors 27 , 29
  • the source-drain connections form conductive channels in the region of the respective gates in known manner to form capacitive components differentially connected across the outputs of the gain stages 35 , 37 .
  • the differential connection of such components yields C/ 2 capacitance, without the equivalent resistance 39 of a control switch (in the biasing circuit) affecting the capacitance in the circuit thus configured.
  • control input 33 At high-level applied control signal appearing on control input 33 (representative of the OFF condition for NMOS type transistors 27 , 29 ), wide depletion regions form adjacent the sources-drains, or essentially no channels form in the vicinities of the gates to contribute only a small fraction of the original capacitance introduced into the circuit.
  • One or more banks of differentially connected capacitive components, each controlled by such bias-adjusting switching circuitry, may be provided to facilitate adjustment or control of the frequency response characteristics of the circuit thus configured.
  • FIG. 3 there is shown a graph of the transfer function of the differential amplifier of FIG. 2 that includes gain elements 35 , 37 and current sources 41 , 43 , 45 connected as shown.
  • the sum of the drain currents 41 , 43 substantially equals the combined current 45 , and reducing these current levels typically alters the transfer function of the semiconductor amplifier, as shown by curve 53 .
  • the range of control voltages 55 over which the transfer function remains substantially linear diminishes with reduced current levels, as illustrated with reference to curve 53 .
  • the substantially linear range of the transfer function on applied control voltages is narrow, and widens 55 with increased current levels.
  • significant increases in applied signal voltages appearing at inputs 47 , 49 introduces significant non-linearity in the transfer function for operation at applied signal levels beyond the substantially linear range 55 .
  • a plurality of amplifiers similar to the amplifier of FIG. 2 are assembled in parallel, as illustrated in FIG. 4 , between the differential inputs 47 , 49 and the differential outputs 57 , 59 .
  • Each of the amplifiers may be selectively controlled, for example, via a controllable current source 45 that conducts the currents from the commonly connected sources in each amplifier.
  • each of the amplifiers 61 , 63 , 65 may be selectively disabled or enabled to selectively expand the linear range 55 , 55 ′ of the combined transfer function.
  • the range of frequencies over which the integrated circuit may be operated can be greatly increased, for example, to over 6:1 for operations at about 40 MHz to about 270 MHz.
  • control of one or more of the current sources in the amplifiers 61 , 63 , 65 may thus be externally controlled to maintain the transconductance (g m ) to capacitance (C) ratio (g m /C) substantially constant over a population of integrated circuits thus configured, and for operation of a particular integrated circuit with selected frequency response characteristics.
  • various known semiconductor technologies such as bi-polar or NMOS or CMOS processes may be used to form integrated circuits including amplifiers and capacitive components, as described above.
  • one design of integrated circuit according to the present invention facilitates formation of g m /C integrators operable over a wide range of frequencies, with dynamic responses conveniently controllable by signals that may be internal or external to the integrated circuit.

Abstract

Integrated circuitry for selectively introducing capacitance and for controlling the transconductance transfer function of one or more amplifiers includes concatenated differential amplifiers with one or more pairs of switchable capacitive components differentially connected across outputs of the differential amplifiers to facilitate operation over a wide range of operating frequencies under control of external signals.

Description

Notice: More than one reissue application has been filed for the reissue of U.S. Pat. No. 5,805,006. The reissue applications are application Ser. No. 09/609,007 (now U.S. Reissue Pat. No. RE37,739 ), application Ser. No. 09/950,086 (now U.S. Reissue Pat. No. RE38,455 ) and application Ser. No. 10/614,084 (the present application), which is a continuation U.S. Pat. No. RE37,739, which is a continuation of U.S. Pat. No. RE38,455, which is a reissue of U.S. Pat. No. 5,805,006.
FIELD OF THE INVENTION
This invention relates to integrators and more particularly to circuitry in an integrated circuit that controls frequency response characteristics over a wide range of frequencies with adjustable capacitance and controllable transconductance.
BACKGROUND OF THE INVENTION
Circuit components formed in integrated circuits commonly exhibit wide variations in operating characteristics attributable to variations in the semiconductor processes that form the integrated circuit of such components. By traditional design practices, additional or redundant components may be formed in an integrated circuit during the processing phase, and such additional components may thereafter be connected in or out of a circuit using a laser beam to selectively sever connecting links as required to adjust the operating characteristics of the circuit. Alternatively, signal controllable switches may be incorporated into the design of the integrated circuit to selectively connect additional components in response to externally applied control signals. However, such switches are not ideal in that they incorporate appreciable resistance into a circuit in the conductive state which can be detrimental to high frequency operating characteristics of the integrated circuit.
SUMMARY OF THE INVENTION
In accordance with one embodiment of the present invention, additional capacitive components may be selectively switched into circuit configuration in response to external control signals without introducing significant resistance with the capacitive components. In addition, controllable gain elements may be selectively controlled to amplify the effectiveness of capacitive components in the circuit for a wide range of operating frequency characteristics of the circuit as selectively configured.
DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit diagram of a conventional transconductance integrator;
FIG. 2 is a circuit diagram of one embodiment of the present invention;
FIG. 3 is a graph illustrating the operating characteristics of a transconductance amplifier; and
FIG. 4 is a circuit diagram of another embodiment of the present invention for providing wide dynamic control of operating frequency characteristics of the composite circuitry.
 DETAILED DESCRIPTION OF THE INVENTION
Referring now to FIG. 1, there is shown a conventional integrator including a differential pair of gain stages 9, 11 such as field-effect transistors having control electrodes, or gates, coupled to receive control signals applied to inputs 13, 15. The source electrodes, or sources, of the gain stages are coupled together and to a controllable current source 17, and each of the drain electrodes, or drains, is coupled to a controllable current sources 19, 21 and to one or more capacitive elements 23, 25. The sum of the current sources 19, 21 is usually set equal to the current from source 17. Selected ones of the capacitive elements may be coupled to ground, for example, via links that may be removed via laser-beam machining to alter the operating frequency characteristics of the circuit. Alternatively, semiconductor switches may be substituted (not shown) for the links to facilitate control of capacitance in the circuit in response to externally applied signals. However, such semiconductor switches commonly introduce significant resistance along with capacitance thus switched into the circuit, and this adversely affects high frequency operating characteristics of the circuit thus configured.
In accordance with one embodiment of the present invention, one or more differential pairs of capacitive elements are formed for selective connection into the circuit in response to an applied control signal. Specifically, as shown in FIG. 2, each capacitive element is formed as a pair of gain elements 27, 29 such as insulated-gate field-effect transistors with source and drain connected in common as one capacitive electrode and with the gate forming another capacitive electrode. The source-drain connections are connected in common to a control switch 31 that may also include a gain element responsive to an applied control signal for switching in or out the differential pair of capacitive components 27, 29. Specifically, at low-level applied control signal appearing on control input 33 (representative of the ON condition for NMOS type transistors 27, 29) the source-drain connections form conductive channels in the region of the respective gates in known manner to form capacitive components differentially connected across the outputs of the gain stages 35, 37. Thus, for each capacitive component of capacitance C, the differential connection of such components yields C/2 capacitance, without the equivalent resistance 39 of a control switch (in the biasing circuit) affecting the capacitance in the circuit thus configured. At high-level applied control signal appearing on control input 33 (representative of the OFF condition for NMOS type transistors 27, 29), wide depletion regions form adjacent the sources-drains, or essentially no channels form in the vicinities of the gates to contribute only a small fraction of the original capacitance introduced into the circuit. One or more banks of differentially connected capacitive components, each controlled by such bias-adjusting switching circuitry, may be provided to facilitate adjustment or control of the frequency response characteristics of the circuit thus configured.
Referring now to FIG. 3, there is shown a graph of the transfer function of the differential amplifier of FIG. 2 that includes gain elements 35, 37 and current sources 41, 43, 45 connected as shown. Specifically, as the differential of the control voltages 47, 49 applied to the control electrodes increases, the differential of drain currents I1, I2 (ΔI=I1−I2) increases, as shown by the curve 51. In the semiconductor amplifier circuit of FIG. 2, the sum of the drain currents 41, 43 substantially equals the combined current 45, and reducing these current levels typically alters the transfer function of the semiconductor amplifier, as shown by curve 53. The range of control voltages 55 over which the transfer function remains substantially linear diminishes with reduced current levels, as illustrated with reference to curve 53. Thus, at low levels of the combined source currents through current source 45, the substantially linear range of the transfer function on applied control voltages is narrow, and widens 55 with increased current levels. However, for a given level of the combined currents through source 45, significant increases in applied signal voltages appearing at inputs 47, 49 introduces significant non-linearity in the transfer function for operation at applied signal levels beyond the substantially linear range 55.
In accordance with another embodiment of the present invention, a plurality of amplifiers similar to the amplifier of FIG. 2 are assembled in parallel, as illustrated in FIG. 4, between the differential inputs 47, 49 and the differential outputs 57, 59. Each of the amplifiers may be selectively controlled, for example, via a controllable current source 45 that conducts the currents from the commonly connected sources in each amplifier. In this way, each of the amplifiers 61, 63, 65 may be selectively disabled or enabled to selectively expand the linear range 55, 55′ of the combined transfer function. In addition, with one or more pairs of differentially connected capacitive components 27, 29 connected across the outputs 57, 59, the range of frequencies over which the integrated circuit may be operated can be greatly increased, for example, to over 6:1 for operations at about 40 MHz to about 270 MHz. Additionally, for selected values of capacitance C switched into the circuit in the manner previously described, control of one or more of the current sources in the amplifiers 61, 63, 65 may thus be externally controlled to maintain the transconductance (gm) to capacitance (C) ratio (gm/C) substantially constant over a population of integrated circuits thus configured, and for operation of a particular integrated circuit with selected frequency response characteristics. Of course, various known semiconductor technologies such as bi-polar or NMOS or CMOS processes may be used to form integrated circuits including amplifiers and capacitive components, as described above.
Therefore, one design of integrated circuit according to the present invention facilitates formation of gm/C integrators operable over a wide range of frequencies, with dynamic responses conveniently controllable by signals that may be internal or external to the integrated circuit.

Claims (74)

1. Integrator apparatus comprising:
an amplifier including a pair of outputs and being responsive to differential input signals for producing differential output signals on the pair of outputs; and
a pair of capacitive components connected to the pair of outputs and to a common source of first control signal, the capacitive components including insulated-gate, field-effect transistors having gates connected to respective ones of the pair of outputs and having sources and drains connected in common to receive said first control signal for altering the capacitance of each pair of capacitive component in response to the first control signal applied to the sources and drains thereof.
2. Integrator apparatus according to claim 1 comprising a plurality of pairs of capacitive components, each including insulated-gate, field-effect transistors having gates connected to respective ones on the pair of outputs and having sources and drains connected in common to receive the first control signal therefor for altering the capacitance of the capacitive components in response to the first control signal applied to the sources and drains of each of the plurality of pairs of capacitive components.
3. Integrator apparatus according to claim 2 wherein the amplifier includes a plurality of differential amplifiers, each having a pair of outputs coupled in common to the plurality of pairs of capacitive components, and each having a pair of inputs connected in common to receive applied differential signals, at least one of the plurality of differential amplifiers also having a transfer function from inputs thereof to outputs thereof that is controllable in response to a second control signal applied thereto for altering the combined transfer function of the plurality of differential amplifiers from the inputs thereof connected in common to the differential outputs thereof coupled in common in response to applied second control signal.
4. Integrator apparatus according to claim 1 wherein said amplifier includes a pair of field-effect transistors, each having a drain electrode connected to respective ones of said pair of outputs, and having source electrodes connected in common, with the source and drain electrodes of each transistor forming a conduction channel thereof, and transistors having gate electrodes connected to receive the differential input signals applied thereto to alter the conduction channel thereof; and
a current source connected to the drain electrode of each transistor, and another current source connected to the common connection of the source electrodes for conducting the sum of currents in the conduction channels of the pair of transistors.
5. Integrator apparatus according to claim 4 wherein said another current source is adjustable to alter the transfer function of the amplifier from the gate electrodes to the pair of outputs thereof.
6. Integrator apparatus according to claim 3 wherein the second control signal is adjusted to maintain substantially constant the ratio of the transconductance of the amplifier to the capacitance provided by the capacitive components in response to first control signal applied thereto.
7. An amplifier apparatus, comprising:
a plurality of amplifier cells,
wherein each of the plurality of amplifier cells includes (i) at least one first input in communication with a common control voltage, (ii) a second input in communication with a controllable current signal, and (iii) an output,
wherein the plurality of amplifier cells are arranged in parallel,
wherein the first input of each of the plurality of amplifier cells is in communication with the first inputs of other ones of the plurality of amplifier cells,
wherein the output of each of the plurality of amplifier cells is in communication with the outputs of other ones of the plurality of amplifier cells,
wherein each of the plurality of amplifier cells has a transconductance from the first input thereof to the output thereof,
wherein each of the plurality of amplifier cells is selectively controllable in response to the controllable current signal applied thereto to one of enable and disable each of the plurality of amplifier cells for adjusting a combined transconductance of the plurality of amplifier cells from the first inputs thereof to the outputs thereof, and
wherein an adjustable capacitance is connected to the output of each of the plurality of amplifier cells, the adjustable capacitance includes a pair of gain elements, and the adjustable capacitance is adjustable based on a control signal applied at a common node of the pair of gain elements.
8. The amplifier apparatus of claim 7, wherein each of the plurality of amplifier cells comprises at least one transistor.
9. The amplifier apparatus of claim 8, wherein each of the plurality of amplifier cells comprises a pair of transistors.
10. The amplifier apparatus of claim 9, wherein each pair of transistors comprises (i) a pair of input terminals, (ii) a pair of output terminals, and (iii) a pair of common terminals coupled to the controllable current signal, and
wherein each of the amplifier cells includes first and second current sources respectively coupled to the pair of output terminals.
11. The amplifier apparatus of claim 9, wherein each of the pairs of transistors includes gates coupled to a common control voltage, and wherein said pairs of input and output terminals include sources and drains coupled together.
12. The amplifier apparatus of claim 7, wherein the transconductance of each of the plurality of amplifier cells is substantially identical.
13. The amplifier apparatus of claim 7, wherein the transconductance of at least one of the plurality of amplifier cells is different than the transconductance of other ones of the plurality of amplifier cells.
14. The amplifier apparatus of claim 6, wherein each of the plurality of amplifier cells comprises a controllable current source that generates the controllable current signal to adjust the transconductance of the amplifier cell.
15. The amplifier apparatus of claim 14, wherein the controllable current source of the amplifier cell is in communication with the second input.
16. An amplifier device, comprising:
a plurality of amplifier cells, each of the plurality of amplifier cells comprising at least one transistor,
wherein the plurality of amplifier cells are arranged in parallel,
wherein each of the plurality of amplifier cells includes an input terminal,
wherein the input terminal of each of the plurality of amplifier cells is in communication with input terminals of other ones of the plurality of amplifier cells,
wherein each of the plurality of amplifier cells includes an output terminal,
wherein the output terminal of each of the plurality of amplifier cells is in communication with output terminals of other ones of the plurality of amplifier cells, and
wherein each of the plurality of amplifier cells has a transconductance from an input thereof to an output thereof; and
means for selectively controlling each of the plurality amplifier cells to enable at least one of the plurality of amplifier cells for adjusting a combined transconductance of the amplifier device in response to a controllable current signal,
wherein an adjustable capacitance is connected to the output of each of the plurality of amplifier cells, the adjustable capacitance includes a pair of gain elements, and the adjustable capacitance is adjustable based on a control signal applied at a common node of the pair of gain elements.
17. The amplifier device of claim 16, wherein each of the plurality of amplifier cells comprises a pair of transistors.
18. The amplifier device of claim 17, wherein each pair of transistors comprises (i) a pair of input terminals, (ii) a pair of output terminals, and (iii) a pair of common terminals connected together, and
wherein each of the amplifier cells includes first and second current sources respectively coupled to the pair of output terminals.
19. The amplifier device of claim 17, wherein each of the pairs of transistors includes gates coupled to respective control signals, and wherein each of the pairs of transistors includes sources and drains coupled together to receive the controllable current signal.
20. The amplifier device of claim 16, wherein the transconductance of each of the plurality of amplifier cells is substantially identical.
21. The amplifier device of claim 16, wherein the transconductance of at least one of the plurality of amplifier cells is different than the transconductance of other ones of the plurality of amplifier cells.
22. An amplifier device, comprising:
a plurality of amplifier cells, wherein each of the plurality of amplifier cells comprises:
a pair of gain elements, wherein each of the pair of gain elements comprises:
i.) a pair of input terminals,
ii.) a pair of output terminals, and
iii.) a pair of common terminals connected together in communication with a controllable current signal,
wherein the plurality of amplifier cells are arranged in parallel,
wherein each of the pair of input terminals of the plurality of amplifier cells are in communication with a control voltage and with the pairs of input terminals of other ones of the plurality of amplifier cells,
wherein each of the pair of output terminals of the plurality of amplifier cells are in communication with the pairs of output terminals of other ones of the plurality of amplifier cells,
wherein each of the plurality of amplifier cells has a transconductance from the input thereof to the output thereof,
wherein each of the plurality of amplifier cells is selectively controllable in response to the controllable current signal applied thereto to one of enable and disable each of the plurality of amplifier cells for adjusting a combined transconductance of the plurality of amplifier cells, and
wherein an adjustable capacitance is connected to the output of each of the plurality of amplifier cells, the adjustable capacitance includes a pair of gain elements, and the adjustable capacitance is adjustable based on a control signal applied at a common node of the pair of gain elements.
23. The amplifier device of claim 22, wherein each of the pair of gain elements comprises a pair of transistors.
24. The amplifier device of claim 23, wherein each of the pairs of transistors includes gates coupled to the control voltage, and wherein each of the pairs of transistors includes sources and drains coupled together to receive the controllable current signal.
25. The amplifier device of claim 22, wherein each of the amplifier cells includes first and second current sources respectively coupled to the pair of output terminals.
26. The amplifier device of claim 22, wherein the transconductance of each of the plurality of amplifier cells is substantially identical.
27. The amplifier device of claim 22, wherein the transconductance of at least one of the plurality of amplifier cells is different than the transconductance of other ones of the plurality of amplifier cells.
28. The amplifier device of claim 22, wherein each of the plurality of amplifier cells comprises a controllable current source that generates the controllable current signal to adjust the transconductance of the amplifier cell.
29. The amplifier apparatus of claim 28, wherein the controllable current source in each of the plurality of amplifier cells is in communication with the corresponding pair of common terminals in each of the plurality of amplifier cells.
30. A method of controlling an amplifier apparatus, comprising the steps of:
providing a plurality of amplifier cells,
wherein each of the plurality of amplifier cells includes (i) at least one first input in communication with a common control voltage, (ii) a second input in communication with a controllable current signal, and (iii) an output,
wherein the plurality of amplifier cells are arranged in parallel,
wherein the first input of each of the plurality of amplifier cells is in communication with the first inputs of other ones of the plurality of amplifier cells,
wherein the output of each of the plurality of amplifier cells is in communication with the outputs of other ones of the plurality of amplifier cells, and
wherein each of the plurality of amplifier cells has a transconductance from the first input thereof to the output thereof;
receiving the controllable current signal at the second inputs of each of the plurality of amplifier cells;
selectively controlling each of the plurality of amplifier cells in response to the received controllable current signal to one of enable and disable each of the plurality of amplifier cells to adjust a combined transconductance of the plurality of amplifier cells from the first inputs thereof to the outputs thereof; and
providing an adjustable capacitance connected to the output of each of the plurality of amplifier cells, wherein the adjustable capacitance includes a pair of gain elements, and the adjustable capacitance is adjustable based on a control signal applied at a common node of the pair of gain elements.
31. The method of claim 30, wherein each of the plurality of amplifier cells includes at least one transistor.
32. The method of claim 30, wherein the transconductance of each of the plurality of amplifier cells is substantially identical.
33. The method of claim 30, wherein the transconductance of at least one of the plurality of amplifier cells is different than the transconductance of other ones of the plurality of amplifier cells.
34. A method of controlling an amplifier device, comprising the steps of:
providing a plurality of amplifier cells, each of the plurality of amplifier cells including at least one transistor,
wherein each of the plurality of amplifier cells includes an input terminal, wherein each of the plurality of amplifier cells includes an output terminal, and
wherein each of the plurality of amplifier cells has a transconductance from an input thereof to an output thereof;
arranging the plurality of amplifier cells in parallel,
wherein the input terminal of each of the plurality of amplifier cells is in communication with the input terminals of other ones of the plurality of amplifier cells, and
wherein the output terminal of each of the plurality of amplifier cells is in communication with the output terminals of other ones of the plurality of amplifier cells;
selectively controlling each of the plurality amplifier cells to enable at least one of the plurality of amplifier cells to adjust a combined transconductance of the amplifier device in response to a controllable current signal; and
providing an adjustable capacitance connected to the output of each of the plurality of amplifier cells, wherein the adjustable capacitance includes a pair of gain elements, and the adjustable capacitance is adjustable based on a control signal applied at a common node of the pair of gain elements.
35. The method of claim 34, wherein the transconductance of each of the plurality of amplifier cells is substantially identical.
36. The method of claim 34, wherein the transconductance of at least one of the plurality of amplifier cells is different than the transconductance of other ones of the plurality of amplifier cells.
37. A method for controlling an amplifier device, comprising the steps of:
providing a plurality of amplifier cells, wherein each of the plurality of amplifier cells comprises:
a pair of gain elements, wherein each of the pair of gain elements comprises:
i.) a pair of input terminals,
ii.) a pair of output terminals, and
iii.) a pair of common terminals connected together in communication with a controllable current signal,
wherein each of the plurality of amplifier cells has a transconductance from the input thereof to the output thereof;
arranging the plurality of amplifier cells in parallel;
arranging each pair of input terminals of the plurality of amplifier cells in common with the pairs of input terminals of other ones of the plurality of amplifier cells;
arranging each pair of output terminals of the plurality of amplifier cells in common with the pairs of output terminals of other ones of the plurality of amplifier cells;
selectively controlling each of the plurality of amplifier cells in response to the controllable current signal applied thereto to one of enable and disable each of the plurality of amplifier cells to adjust a combined transconductance of the plurality of amplifier cells; and
providing an adjustable capacitance connected to the output of each of the plurality of amplifier cells, wherein the adjustable capacitance includes a pair of gain elements, and the adjustable capacitance is adjustable based on a control signal applied at a common node of the pair of gain elements.
38. The method of claim 37, wherein the transconductance of each of the plurality of amplifier cells is substantially identical.
39. The method of claim 37, wherein the transconductance of at least one of the plurality of amplifier cells is different than the transconductance of other ones of the plurality of amplifier cells.
40. An amplifier apparatus, comprising:
means for providing a plurality of amplifier cells,
wherein each of the plurality of amplifier cells includes (i) at least one first input in communication with a common control voltage, (ii) a second input in communication with a controllable current signal, and (iii) an output,
wherein the plurality of amplifier cells are arranged in parallel,
wherein the first input of each of the plurality of amplifier cells is in communication with the first inputs of other ones of the plurality of amplifier cells,
wherein the output of each of the plurality of amplifier cells is in communication with the outputs of other ones of the plurality of amplifier cells, and
wherein each of the plurality of amplifier cells has a transconductance from the first input thereof to the output thereof;
means for receiving the control signal at each of the plurality of amplifier cells; and
means for selectively controlling each of the plurality of amplifier cells in response to the received controllable current signal to one of enable and disable each of the plurality of amplifier cells to adjust a combined transconductance of the plurality of amplifier cells from the first inputs thereof to the outputs thereof,
wherein an adjustable capacitance is connected to the output of each of the plurality of amplifier cells, the adjustable capacitance includes a pair of gain elements, and the adjustable capacitance is adjustable based on a control signal applied at a common node of the pair of gain elements.
41. The amplifier apparatus of claim 40, wherein each of the plurality of amplifier cells comprises at least one transistor.
42. The amplifier apparatus of claim 40, wherein the transconductance of each of the plurality of amplifier cells is substantially identical.
43. The amplifier apparatus of claim 40, wherein the transconductance of at least one of the plurality of amplifier cells is different than the transconductance of other ones of the plurality of amplifier cells.
44. An amplifier device, comprising:
means for providing a plurality of amplifier cells, each of the plurality of amplifier cells including at least one transistor,
wherein each of the plurality of amplifier cells includes an input terminal, wherein each of the plurality of amplifier cells includes an output terminal, and
wherein each of the plurality of amplifier cells has a transconductance from an input thereof to an output thereof;
means for arranging the plurality of amplifier cells in parallel,
wherein the input terminal of each of the plurality of amplifier cells is in communication with the input terminals of other ones of the plurality of amplifier cells, and
wherein the output terminal of each of the plurality of amplifier cells is in communication with the output terminals of other ones of the plurality of amplifier cells; and
means for selectively controlling each of the plurality amplifier cells to enable at least one of the plurality of amplifier cells to adjust a combined transconductance of the amplifier device in response to a controllable current signal,
wherein an adjustable capacitance is connected to the output of each of the plurality of amplifier cells, the adjustable capacitance includes a pair of gain elements, and the adjustable capacitance is adjustable based on a control signal applied at a common node of the pair of gain elements.
45. The method of claim 44, wherein the transconductance of each of the plurality of amplifier cells is substantially identical.
46. The method of claim 44, wherein the transconductance of at least one of the plurality of amplifier cells is different than the transconductance of other ones of the plurality of amplifier cells.
47. An amplifier device, comprising:
means for providing a plurality of amplifier cells, wherein each of the plurality of amplifier cells comprises:
a pair of gain elements, wherein each of the pair of gain elements comprises:
i.) a pair of input terminals,
ii.) a pair of output terminals, and
iii.) a pair of common terminals connected together in communication with a controllable current signal,
wherein each of the plurality of amplifier cells has a transconductance from the input thereof to the output thereof;
means for arranging the plurality of amplifier cells in parallel;
means for arranging each pair of input terminals of the plurality of amplifier cells in common with the pairs of input terminals of other ones of the plurality of amplifier cells;
means for arranging each pair of output terminals of the plurality of amplifier cells in common with the pairs of output terminals of other ones of the plurality of amplifier cells; and
means for selectively controlling each of the plurality of amplifier cells in response to the controllable current signal applied thereto to one of enable and disable each of the plurality of amplifier cells to adjust a combined transconductance of the plurality of amplifier cells,
wherein an adjustable capacitance is connected to the output of each of the plurality of amplifier cells, the adjustable capacitance includes a pair of gain elements, and the adjustable capacitance is adjustable based on a control signal applied at a common node of the pair of gain elements.
48. The method of claim 47, wherein the transconductance of each of the plurality of amplifier cells is substantially identical.
49. The method of claim 47, wherein the transconductance of at least one of the plurality of amplifier cells is different than the transconductance of other ones of the plurality of amplifier cells.
50. An amplifier apparatus, comprising:
a plurality of amplifier cell means,
wherein each of the plurality of amplifier cell means includes (i) at least one first input in communication with a common control voltage, (ii) a second input in communication with a controllable current signal, and (iii) an output,
wherein the plurality of amplifier cell means are arranged in parallel,
wherein the output of each of the plurality of amplifier cell means is in communication with the outputs of other ones of the plurality of amplifier cell means,
wherein the first input of each of the plurality of amplifier cell means is in communication with the first inputs of other ones of the plurality of amplifier cell means,
wherein each of the plurality of amplifier cell means has a transconductance from the first input thereof to the output thereof,
wherein each of the plurality of amplifier cell means is selectively controllable in response to the controllable current signal applied thereto to one of enable and disable each of the plurality of amplifier cell means for adjusting a combined transconductance of the plurality of amplifier cell means from the first inputs thereof to the outputs thereof, and
wherein an adjustable capacitance is connected to the output of each of the plurality of amplifier cell means, the adjustable capacitance includes a pair of gain elements, and the adjustable capacitance is adjustable based on a control signal applied at a common node of the pair of gain elements.
51. An amplifier device, comprising:
a plurality of amplifier cell means, each of the plurality of amplifier cell means comprising at least one transistor,
wherein the plurality of amplifier cell means are arranged in parallel,
wherein each of the plurality of amplifier cell means includes an input terminal,
wherein the input terminal of each of the plurality of amplifier cell means is in communication with input terminals of other ones of the plurality of amplifier cell means,
wherein each of the plurality of amplifier cell means includes an output terminal,
wherein the output terminal of each of the plurality of amplifier cell means is in communication with output terminals of other ones of the plurality of amplifier cell means, and
wherein each of the plurality of amplifier cell means has a transconductance from an input thereof to an output thereof; and
means for selectively controlling each of the plurality amplifier cell means to enable at least one of the plurality of amplifier cell means for adjusting a combined transconductance of the amplifier device in response to a controllable current signal,
wherein an adjustable capacitance is connected to the output of each of the plurality of amplifier cell means, the adjustable capacitance includes a pair of gain elements, and the adjustable capacitance is adjustable based on a control signal applied at a common node of the pair of gain elements.
52. An amplifier apparatus with a controllable Gm, comprising:
a plurality of Gm cells,
wherein each of the plurality of Gm cells includes (i) at least one first input in communication with a common control voltage, (ii) a second input in communication with a controllable current signal, and (iii) an output,
wherein the plurality of Gm cells are arranged in parallel,
wherein the first input of each of the plurality of Gm cells is in communication with the first inputs of other ones of the plurality of Gm cells,
wherein the output of each of the plurality of Gm cells is in communication with the outputs of other ones of the plurality of Gm cells, and
wherein each of the plurality of Gm cells is selectively controllable in response to the controllable current signal applied thereto to one of enable and disable each of the plurality of Gm cells for adjusting a combined Gm of the plurality of Gm cells, and
wherein an adjustable capacitance is connected to the output of each of the plurality of Gm cells, the adjustable capacitance includes a pair of gain elements, and the adjustable capacitance is adjustable based on a control signal applied at a common node of the pair of gain elements.
53. The amplifier apparatus of claim 52, wherein each of the plurality of Gm cells comprises at least one transistor.
54. The amplifier apparatus of claim 53, wherein each of the plurality of Gm cells comprises a pair of transistors.
55. The amplifier apparatus of claim 54, wherein each pair of transistors comprises (i) a pair of input terminals, (ii) a pair of output terminals, and (iii) a pair of common terminals connected together in communication with the controllable current signal, and
wherein each of the Gm cells includes first and second current sources respectively coupled to the pair of output terminals.
56. The amplifier apparatus of claim 54, wherein each of the pairs of transistors includes gates coupled to the common control voltage, and wherein each of the pairs of transistors includes sources and drains coupled together to receive the control controllable current signal.
57. The amplifier apparatus of claim 52, wherein the Gm of each of the plurality of Gm cells is substantially identical.
58. The amplifier apparatus of claim 52, wherein the Gm of at least one of the plurality of Gm cells is different than the Gm of other ones of the plurality of Gm cells.
59. The amplifier apparatus of claim 52, wherein each of the plurality of Gm cells comprises a controllable current source to generate the controllable current signal to adjust the Gm of the Gm cell.
60. The amplifier apparatus of claim 59, wherein the controllable current source of the Gm cell is in communication with the second input.
61. An amplifier device with a controllable Gm, comprising:
a plurality of Gm cells, each of the plurality of Gm cells comprising at least one transistor,
wherein the plurality of Gm cells are arranged in parallel,
wherein each of the plurality of Gm cells includes an input terminal,
wherein the input terminal of each of the plurality of Gm cells is in communication with input terminals of other ones of the plurality of Gm cells,
wherein each of the plurality of Gm cells includes an output terminal,
wherein the output terminal of each of the plurality of Gm cells is in communication with output terminals of other ones of the plurality of Gm cells, and
means for selectively controlling each of the plurality Gm cells to enable at least one of the plurality of Gm cells for adjusting a combined Gm of the amplifier device in response to a controllable current signal,
wherein an adjustable capacitance is connected to the output terminal of each of the plurality of Gm cells, the adjustable capacitance includes a pair of gain elements, and the adjustable capacitance is adjustable based on a control signal applied at a common node of the pair of gain elements.
62. The amplifier device of claim 61, wherein each of the plurality of Gm cells comprises a pair of transistors.
63. The amplifier device of claim 62, wherein each pair of transistors comprises (i) a pair of input terminals, (ii) a pair of output terminals, and (iii) a pair of common terminals connected together in communication with the controllable current signal, and
wherein each of the Gm cells includes first and second current sources respectively coupled to the pair of output terminals.
64. The amplifier device of claim 62, wherein each of the pairs of transistors includes gates coupled to a common control voltage, and wherein each of the pairs of transistors includes sources and drains coupled together to receive the controllable current signal.
65. The amplifier device of claim 61, wherein the Gm of each of the plurality of Gm cells is substantially identical.
66. The amplifier device of claim 61, wherein the Gm of at least one of the plurality of Gm cells is different than the Gm of other ones of the plurality of Gm cells.
67. A method of controlling Gm, comprising the steps of:
providing a plurality of Gm cells,
wherein each of the plurality of Gm cells includes (i) at least one first input in communication with a common control voltage, (ii) a second input in communication with a controllable current signal, and (iii) an output,
wherein the plurality of Gm cells are arranged in parallel,
wherein the first input of each of the plurality of Gm cells is in communication with the first inputs of other ones of the plurality of Gm cells,
wherein the output of each of the plurality of Gm cells is in communication with the outputs of other ones of the plurality of Gm cells; and
providing an adjustable capacitance connected to the output of each of the plurality of Gm cells, wherein the adjustable capacitance includes a pair of gain elements, and the adjustable capacitance is adjustable based on a control signal applied at a common node of the pair of gain elements.
68. The method of claim 67, wherein the Gm of each of the plurality of Gm cells is substantially identical.
69. The method of claim 67, wherein the Gm of at least one of the plurality of Gm cells is different than the Gm of other ones of the plurality of Gm cells.
70. A method of controlling Gm, comprising the steps of:
providing a plurality of Gm cells, each of the plurality of Gm cells comprising at least one transistor,
arranging the plurality of Gm cells in parallel,
wherein each of the plurality of Gm cells includes an input terminal,
wherein the input terminal of each of the plurality of Gm cells is in communication with input terminals of other ones of the plurality of Gm cells,
wherein each of the plurality of Gm cells includes an output terminal,
wherein the output terminal of each of the plurality of Gm cells is in communication with output terminals of other ones of the plurality of Gm cells, and
selectively controlling each of the plurality Gm cells to enable at least one of the plurality of Gm cells for adjusting a combined Gm of the plurality of Gm cells in response to a controllable current signal; and
providing an adjustable capacitance connected to the output of each of the plurality of amplifier cells, wherein the adjustable capacitance includes a pair of gain elements, and the adjustable capacitance is adjustable based on a control signal applied at a common node of the pair of gain elements.
71. The method of claim 70, wherein the Gm of each of the plurality of Gm cells is substantially identical.
72. The method of claim 70, wherein the Gm of at least one of the plurality of Gm cells is different than the Gm of other ones of the plurality of Gm cells.
73. An amplifier apparatus, comprising:
a plurality of amplifier cells,
wherein each of the plurality of amplifier cells includes (i) at least one first input in communication with a common control voltage, (ii) a second input in communication with a controllable current signal, and (iii) an output,
wherein each of the plurality of amplifier cells has a transconductance from the input thereof to the output thereof,
wherein each of the plurality of amplifier cells is selectively controllable in response to the controllable current signal applied thereto to one of enable and disable each of the plurality of amplifier cells for adjusting a combined transconductance of the plurality of amplifier cells from the inputs thereof to the outputs thereof, and
wherein an adjustable capacitance is connected to the output of each of the plurality of amplifier cells, the adjustable capacitance includes a pair of gain elements, and the adjustable capacitance is adjustable based on a control signal applied at a common node of the pair of gain elements.
74. An amplifier device, comprising:
a plurality of amplifier cells, each of the plurality of amplifier cells comprising at least one transistor,
wherein the plurality of amplifier cells are arranged in parallel, and
wherein each of the plurality of amplifier cells has a transconductance from an input thereof to an output thereof; and
means for selectively controlling each of the plurality amplifier cells to enable at least one of the plurality of amplifier cells for adjusting a combined transconductance of the amplifier device in response to a controllable current signal,
wherein an adjustable capacitance is connected to the output of each of the plurality of amplifier cells, the adjustable capacitance includes a pair of gain elements, and the adjustable capacitance is adjustable based on a control signal applied at a common node of the pair of gain elements.
US10/614,084 1997-04-28 2003-07-08 Controllable integrator Expired - Lifetime USRE41792E1 (en)

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