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Número de publicaciónUSRE42814 E1
Tipo de publicaciónConcesión
Número de solicitudUS 12/322,858
Fecha de publicación4 Oct 2011
Fecha de presentación5 Feb 2009
Fecha de prioridad30 Oct 1998
También publicado comoUS6321335, USRE41076, USRE41294, USRE41961, USRE43119, USRE44933
Número de publicación12322858, 322858, US RE42814 E1, US RE42814E1, US-E1-RE42814, USRE42814 E1, USRE42814E1
InventoresWilliam W. Y. Chu
Cesionario originalAcqis Technology, Inc.
Exportar citaBiBTeX, EndNote, RefMan
Enlaces externos: USPTO, Cesión de USPTO, Espacenet
Password protected modular computer method and device
US RE42814 E1
Resumen
A method and device for securing a removable Attached Computer Module (“ACM”) 10. ACM 10 inserts into a Computer Module Bay (“CMB”) 40 within a peripheral console to form a functional computer such as a desktop computer or portable computer. The present ACM 10 includes a locking system, which includes hardware and software 600, 700, to prevent accidental removal or theft of the ACM from the peripheral console. While ACM is in transit, further security is necessary against illegal or unauthorized use. If ACM contains confidential data, a high security method is needed to safeguard against theft.
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Reclamaciones(53)
1. A computer module, said module comprising:
an enclosure, said enclosure being insertable into a console;
a central processing unit in said enclosure, said central processing unit comprising a microprocessor based integrated circuit chip;
a hard disk drive in said enclosure, said hard disk drive being coupled to said central processing unit; and
a programmable memory device in said enclosure, said programmable memory device being configurable to store a password for preventing a possibility of unauthorized use of said hard disk drive.
2. The computer module of claim 1 further comprising a host interface controller for providing a status of a locking device in said enclosure.
3. The computer module of claim 1 further comprising a mechanical locking device that is coupled to said programmable memory device.
4. The computer module of claim 1 further comprising a host interface controller coupled to a mechanical locking device, said host interface controller being coupled to said programmable memory device.
5. The computer module of claim 1 wherein said programmable memory device comprises a flash memory device.
6. The computer module of claim 1 wherein said programmable memory device comprises a flash memory device having at least 8 Mbits of cells and greater.
7. The computer module of claim 1 further comprising a security program in a main memory.
8. The computer module of claim 7 wherein said security program comprises a code for storing a password on said programmable memory device.
9. The computer module of claim 8 wherein said security program comprises a code for checking a time from said real-time clock circuit.
10. The computer module of claim 1 further comprising a host interface controller coupled to a solenoid that drives a mechanical lock in a first position to a second position.
11. The computer module of claim 10 wherein said solenoid also drives said mechanical lock from said second position to said first position.
12. The computer module of claim 1 further comprising a real-time clock circuit coupled to said central processing unit.
13. The computer module of claim 12 further comprising a battery coupled to a host interface controller that includes said real-time clock.
14. A method for operating a computer system, said method comprising:
inserting an attached computer module (“ACM”) into a bay of a modular computer system, said ACM comprising a microprocessor unit coupled to a mass memory storage device;
applying power to said computer system and said ACM to execute a security program, said security program being stored in said mass memory storage device; and
prompting for a user password from a user on a display.
15. The method of claim 14 wherein said ACM comprises an enclosure that houses said microprocessor unit and said mass memory storage device.
16. The method of claim 14 further comprising providing a user password to said security program.
17. The method of claim 14 further comprising a flash memory device for storing a desired password for said ACM.
18. The method of claim 17 wherein said flash memory device maintains said desired password when power is removed from said ACM.
19. The method of claim 18 wherein said flash memory device is coupled to a host interface controller that is coupled to said microprocessor based unit.
20. The method of claim 14 wherein said mass memory storage device comprises a code directed to comparing said user password with a desired password.
21. The method of claim 14 further comprising identifying a permanent password or user code on said attached computer module.
22. The method of claim 21 wherein said permanent password or user code is stored in said microprocessor unit.
23. The method of claim 21 wherein said permanent password or user code is stored in a flash memory device coupled to said microprocessor unit.
24. A method for operating a computer system, said method comprising:
inserting an attached computer module (“ACM”) into a bay of a console in a modular computer system, the console comprising a first low voltage differential signal (LVDS) channel comprising two unidirectional serial channels that transmit encoded data of Peripheral Component Interconnect (PCI) bus transaction in opposite directions; said ACM comprising
a microprocessor unit coupled to a mass memory storage device;
a north bridge to communicate address and data bits of PCI bus transaction in serial form, said north bridge directly coupled to said microprocessor unit;
a main memory coupled to said microprocessor unit through said north bridge; and
a second LVDS channel comprising two unidirectional serial channels that transmit data in opposite directions, said second LVDS channel extending from said north bridge to convey said address and data bits of PCI bus transaction in serial form;
applying power to said computer system and said ACM to execute a security program, said security program being stored in said mass memory storage device; and
prompting for a user password from a user on a LCD display coupled to the console.
25. The method of claim 24 wherein said mass memory storage device comprises a flash memory.
26. The method of claim 24 further comprises entering the user password from a keyboard coupled to the console.
27. A method for operating a computer system, said method comprising:
inserting an attached computer module (“ACM”) into a bay of a modular computer system housed in a console, said console comprising a first low voltage differential signal (LVDS) channel comprising two sets of unidirectional serial channels that transmit encoded data of Peripheral Component Interconnect (PCI) bus transaction, and an interface controller coupled to the first LVDS channel; said ACM comprising
a microprocessor unit coupled to a mass memory storage device;
an integrated interface controller and bridge unit to output address and data bits of PCI bus transaction in serial form, said integrated interface controller and bridge unit directly coupled to said microprocessor unit;
a main memory coupled to said microprocessor unit through said integrated interface controller and bridge unit; and
a second LVDS channel comprising two sets of unidirectional serial channels that transmit data in opposite directions, said second LVDS channel extending from said integrated interface controller and bridge unit to convey said address and data bits of PCI bus transaction in serial form;
applying power to said computer system, the ACM executing a security program, said security program being stored in said mass storage device;
storing a user password in said ACM; and
prompting for said user password from a user on a display coupled to the console.
28. The method of claim 27 wherein said mass memory storage device comprises a flash memory.
29. The method of claim 27 wherein said security program manages a user's privilege to access data based on said password.
30. The method of claim 27 further comprises transmitting the encoded data as a serial bit stream in 10 bit packets.
31. A method for operating a computer system, said method comprising:
inserting an attached computer module (“ACM”) into a bay of a console in a modular computer system, said console comprising a LAN communication device and a first low voltage differential signal (LVDS) channel comprising two sets of unidirectional serial channels that transmit data in opposite directions, said ACM comprising
a microprocessor unit coupled to a mass memory storage device;
a second LVDS channel comprising two sets of unidirectional serial channels that transmit data in opposite directions; and
a peripheral bridge coupled to said microprocessor unit without any intervening Peripheral Component Interconnect (PCI) bus, said peripheral bridge coupled to said second LVDS channel to communicate address and data bits of PCI bus transaction in serial form over said second LVDS channel;
applying power to said computer system and said ACM to execute a security program, said security program being stored in said mass memory storage device; and
prompting for a user password from a user on a display.
32. The method of claim 31 wherein said mass memory storage device comprises a flash memory.
33. The method of claim 31 further comprises entering the user password from a keyboard coupled to the console.
34. A method for operating a computer system, said method comprising:
inserting an attached computer module (“ACM”) into a bay of a console in a modular computer system, said console comprising an integrated LCD display, and a first low voltage differential signal (LVDS) channel comprising two sets of unidirectional serial channels that transmit data in opposite directions, said ACM comprising
a microprocessor unit coupled to a mass memory storage device;
a peripheral bridge to output address and data bits of Peripheral Component Interconnect (PCI) bus transaction in serial form, said peripheral bridge coupled to said microprocessor unit without any intervening PCI bus;
a main memory coupled to said microprocessor unit through said peripheral bridge; and
a second LVDS channel comprising two sets of unidirectional serial channels that transmit data in opposite directions, said second LVDS channel extending from said peripheral bridge to convey said address and data bits of PCI bus transaction in serial form;
applying power to said computer system and said ACM to execute a security program, said security program being stored in said mass memory storage device; and
prompting for a user password from a user on the LCD display.
35. The method of claim 34 wherein said mass memory storage device comprises a flash memory.
36. The method of claim 34 further comprises entering the user password from a keyboard coupled to the console.
37. A computer module, said module comprising:
an enclosure, said enclosure being insertable into a console, said console comprising a LAN communication device, and a first channel comprising two low voltage differential signal (LVDS), unidirectional serial channels that transmit in opposite directions;
a central processing unit in said enclosure, said central processing unit comprising a microprocessor based integrated circuit chip;
a peripheral bridge in said enclosure, said peripheral bridge directly coupled to said central processing unit without any intervening Peripheral Component Interconnect (PCI) bus, said peripheral bridge comprising an interface controller to transmit and receive address and data bits of PCI bus transaction in serial form;
a second channel in said enclosure, said second channel comprising two LVDS, unidirectional serial channels that transmit in opposite directions, said second channel extending from said peripheral bridge to convey said address and data bits of PCI bus transaction in serial form;
a hard disk drive in said enclosure, said hard disk drive being coupled to said central processing unit; and
a programmable memory device in said enclosure, said programmable memory device being configurable to store a password for preventing unauthorized use of said hard disk drive.
38. The computer module of claim 37 wherein said first channel communicates an encoded serial bit stream of PCI bus address and data transaction.
39. The computer module of claim 37 wherein the computer module further comprises an interface device that couples to said second channel.
40. A computer module comprising:
an enclosure insertable into a console to form a functional computer, said console comprising two sets of low voltage differential signal (LVDS), unidirectional serial bit channels to transmit data in opposite directions;
a central processing unit in said enclosure, said central processing unit comprising a microprocessor based integrated circuit chip;
a hard disk drive in said enclosure, said hard disk drive being coupled to said central processing unit;
a peripheral bridge in said enclosure, said peripheral bridge directly coupled to said central processing unit without any intervening Peripheral Component Interconnect (PCI) bus, said peripheral bridge comprising an interface controller coupled to the LVDS channels; and
a programmable memory device in said enclosure, said programmable memory device being configurable to store a password for preventing unauthorized use of said hard disk drive.
41. The computer module of claim 40 wherein the low voltage differential signal channels communicate an encoded serial bit stream of Peripheral Component Interconnect (PCI) bus address and data transaction.
42. The computer module of claim 40 further comprising a security program configured to manage a user's access privilege of data based on said password.
43. A computer module comprising:
an enclosure being insertable into a console; said console comprising an LCD display, and a first channel comprising two sets of low voltage differential signal (LVDS), unidirectional serial channels that transmit encoded data of Peripheral Component Interconnect (PCI) bus transaction in opposite directions;
a central processing unit in said enclosure, said central processing unit comprising a microprocessor based integrated circuit chip;
an integrated interface controller and bridge unit in said enclosure, said integrated interface controller and bridge unit configured to output address and data bits of PCI bus transaction in serial form, said integrated interface controller and bridge unit coupled to said central processing unit without any intervening PCI bus;
a main memory in said enclosure, said main memory coupled to said central processing unit through said integrated interface controller and bridge unit; and
a second channel in said enclosure, said second channel comprising two sets of LVDS, unidirectional serial channels that transmit data in opposite directions, said second channel extending from said integrated interface controller and bridge unit to convey said address and data bits of PCI bus transaction in serial form;
a hard disk drive in said enclosure, said hard disk drive being coupled to said central processing unit; and
a programmable memory device in said enclosure, said programmable memory device being configurable to store a password for preventing unauthorized use of said hard disk drive.
44. The computer module of claim 43 wherein the computer module further comprises an interface device that couples to the LVDS channels in the console.
45. The computer module of claim 43 wherein the programmable memory device comprise a flash memory.
46. A computer module comprising:
an enclosure configured to be inserted into a console to form a functional computer; said console comprises a first channel comprising two sets of low voltage differential signal (LVDS), serial channels transmitting data in opposite directions;
a central processing unit in said enclosure, said central processing unit comprising a microprocessor based integrated circuit chip;
a peripheral bridge in said enclosure, said peripheral bridge configured to communicate address and data bits of Peripheral Component Interconnect (PCI) bus transaction in serial form, said peripheral bridge directly coupled to said central processing unit without any intervening PCI bus;
a second channel in said enclosure, said second channel comprising two sets of LVDS, serial channels transmitting data in opposite directions, said second channel extending from said peripheral bridge to convey said address and data bits of PCI bus transaction in serial form;
a hard disk drive in said enclosure, said hard disk drive coupled to said central processing unit;
a programmable memory device in said enclosure, said programmable memory device being configurable to store a password for preventing unauthorized use of said hard disk drive; and
an interface device coupled to at least one of said first channel and said second channel.
47. The computer module of claim 46 wherein the console further comprises a LAN communication device wherein the computer module communicates to an external LAN network through the console.
48. A computer module comprising:
an enclosure insertable into a console comprising a Universal Serial Bus (USB) and an interface controller coupled to a first channel comprising two sets of low voltage differential signal (LVDS), unidirectional channels configured to communicate data in opposite directions;
a central processing unit in said enclosure, said central processing unit comprising a microprocessor based integrated circuit chip;
an integrated interface controller and bridge unit in said enclosure, said integrated interface controller and bridge unit configured to output address and data bits of Peripheral Component Interconnect (PCI) bus transaction in serial form, said integrated interface controller and bridge unit directly coupled to said central processing unit without any intervening PCI bus;
a second channel in said enclosure, said second channel comprising two sets of LVDS, unidirectional channels configured to communicate data in opposite directions, said second channel extending from said integrated interface controller and bridge unit to convey said address and data bits of PCI bus transaction in serial form;
a hard disk drive in said enclosure, said hard disk drive being coupled to said central processing unit; and
a programmable memory device in said enclosure, said programmable memory device being configurable to store a password for preventing unauthorized use of said hard disk drive.
49. The computer module of claim 48 wherein the console further comprises a power supply that supplies power to the computer module upon insertion.
50. A method for operating a computer system, said method comprising:
inserting an attached computer module (“ACM”) into a bay of a console of a modular computer system, said console comprising two sets of differential signal, unidirectional serial channels configured to communicate data in opposite directions, and said ACM comprising
a microprocessor unit coupled to a mass memory storage device;
a peripheral bridge directly coupled to said microprocessor unit without any intervening Peripheral Component Interconnect (PCI) bus; and
a low voltage differential signal (LVDS) channel comprising two sets of unidirectional, multiple serial bit channels configured to communicate data in opposite directions, said LVDS channel extending from said peripheral bridge to convey address and data bits of PCI bus transaction in serial form;
applying power to said computer system and said ACM executing a security program, said security program being stored in said mass memory storage device;
communicating from the computer module to the console through serial bit lines transmitting data packets in Universal Serial Bus (USB) protocol;
prompting for a user password from a user on a LCD display; and
wherein the mass storage device comprises a flash memory.
51. A method for operating a computer system, said method comprising:
inserting an attached computer module (“ACM”) into a bay of a console of a modular computer system, said console comprising a LAN communication device, and differential signal, unidirectional serial channels configured to communicate data in opposite directions, and said ACM comprising
a microprocessor unit coupled to a mass memory storage device comprising a flash memory;
a peripheral bridge directly coupled to said microprocessor unit without any intervening Peripheral Component Interconnect (PCI) bus; and
a low voltage differential signal (LVDS) channel comprising at least two unidirectional, differential signal pairs configured to communicate data in opposite directions, said LVDS channel extending from said peripheral bridge to convey address and data bits of PCI bus transaction in serial form;
applying power to said computer system and said ACM executing a security program, said security program being stored in said mass memory storage device;
communicating from the computer module to the console through serial bit lines transmitting data packets in Universal Serial Bus (USB) protocol;
prompting for a user password from a user on a display coupled to the console.
52. The method of claim 51 further comprises entering the user password from a keyboard coupled to the console.
53. The method of claim 51, further comprising communicating said address and data bits of PCI bus transaction data in 10 bit packets through said LVDS channel.
Descripción
CROSS REFERENCE TO RELATED APPLICATIONS

Notice: More than one reissue application has been filed for the reissue of U.S. Pat. No. 6,321,335. The reissue applications are U.S. application Ser. Nos. 10/963,825 (a parent reissue application), 11/474,256 (which is a continuation reissue of the parent reissue application), 11/517,601 (which is a continuation reissue of the parent reissue application), 12/577,074 (which is a continuation reissue of the parent reissue application), and 12/322,858 (the present application, which is a continuation reissue of U.S. application Ser. No. 11/517,601).

This application is a continuation reissue of U.S. application Ser. No. 11/517,601, which is a continuation reissue of U.S. application Ser. No. 10/963,825, which is a reissue of U.S. Pat. No. 6,321,335, which are incorporated herein by reference.

The following two commonly-owned copending applications, including this one, are being filed concurrently and the other one is hereby incorporated by reference in their entirety for all purposes:

1. U.S. patent application Ser. No. 09/183,816, William W. Y. Chu, entitled, “Modular Computer Security Method and Device”. and

2. U.S. patent application Ser. No. 09/183,493, William W. Y. Chu, entitled, “Password Protected Modular Computer Method and Device”.

BACKGROUND OF THE INVENTION

The present invention relates to computing devices. More particularly, the present invention provides a method and device for securing a personal computer or set-top box using password protection techniques. Merely by way of example, the present invention is applied to a modular computing environment for desk top computers, but it will be recognized that the invention has a much wider range of applicability. It can be applied to a server as well as other portable or modular computing applications.

Many desktop or personal computers, which are commonly termed PCs, have been around and used for over ten years. The PCs often come with state-of-art microprocessors such as the Intel Pentium™ microprocessor chips. They also include a hard or fixed disk drive such as memory in the giga-bit range. Additionally, the PCs often include a random access memory integrated circuit device such as a dynamic random access memory device, which is commonly termed DRAM. The DRAM devices now provide up to millions of memory cells (i.e., mega-bit) on a single slice of silicon. PCs also include a high resolution display such as cathode ray tubes or CRTs. In most cases, the CRTs are at least 15 inches or 17 inches or 20 inches in diameter. High resolution flat panel displays are also used with PCs.

Many external or peripheral devices can be used with the PCs. Among others, these peripheral devices include mass storage devices such as a Zip™ Drive product sold by Iomega Corporation of Utah. Other storage devices include external hard drives, tape drives, and others. Additional devices include communication devices such as a modem, which can be used to link the PC to a wide area network of computers such as the Internet. Furthermore, the PC can include output devices such as a printer and other output means. Moreover, the PC can include special audio output devices such as speakers the like.

PCs also have easy to use keyboards, mouse input devices, and the like. The keyboard is generally configured similar to a typewriter format. The keyboard also has the length and width for easily inputting information by way of keys to the computer. The mouse also has a sufficient size and shape to easily move a curser on the display from one location to another location.

Other types of computing devices include portable computing devices such as “laptop” computers and the like. Although somewhat successful, laptop computers have many limitations. These computing devices have poor display technology. In fact, these devices often have a smaller flat panel display that has poor viewing characteristics. Additionally, these devices also have poor input devices such as smaller keyboards and the like. Furthermore, these devices have limited common platforms to transfer information to and from these devices and other devices such as PCs.

Up to now, there has been little common ground between these platforms including the PCs and laptops in terms of upgrading, ease-of-use, cost, performance, and the like. Many differences between these platforms, probably somewhat intentional, has benefited computer manufacturers at the cost of consumers. A drawback to having two separate computers is that the user must often purchase both the desktop and laptop to have “total” computing power, where the desktop serves as a “regular” computer and the laptop serves as a “portable” computer. Purchasing both computers is often costly and runs “thousands” of dollars. The user also wastes a significant amount of time transferring software and data between the two types of computers. For example, the user must often couple the portable computer to a local area network (i.e., LAN), to a serial port with a modem and then manually transfer over files and data between the desktop and the portable computer. Alternatively, the user often must use floppy disks to “zip” up files and programs that exceed the storage capacity of conventional floppy disks, and transfer the floppy disk data manually.

Another drawback with the current model of separate portable and desktop computer is that the user has to spend money to buy components and peripherals the are duplicated in at least one of these computers. For example, both the desktop and portable computers typically include hard disk drives, floppy drives, CD-ROMs, computer memory, host processors, graphics accelerators, and the like. Because program software and supporting programs generally must be installed upon both hard drives in order for the user to operate programs on the road and in the office, hard disk space is often wasted.

One approach to reduce some of these drawbacks has been the use of a docking station with a portable computer. Here, the user has the portable computer for “on the road” use and a docking station that houses the portable computer for office use. The docking station typically includes a separate monitor, keyboard, mouse, and the like and is generally incompatible with other desktop PCs. The docking station is also generally not compatible with portable computers of other vendors. Another drawback to this approach is that the portable computer typically has lower performance and functionality than a conventional desktop PC. For example, the processor of the portable is typically much slower than processors in dedicated desktop computers, because of power consumption and heat dissipation concerns. As an example, it is noted that at the time of drafting of the present application, some top-of-the-line desktops include 400 MHz processors, whereas top-of-the-line notebook computers include 266 MHz processors.

Another drawback to the docking station approach is that the typical cost of portable computers with docking stations can approach the cost of having a separate portable computer and a separate desktop computer. Further, as noted above, because different vendors of portable computers have proprietary docking stations, computer users are held captive by their investments and must rely upon the particular computer vendor for future upgrades, support, and the like.

Thus what is needed are computer systems that provide reduced user investment in redundant computer components and provide a variable level of performance based upon computer configuration.

SUMMARY OF THE INVENTION

According to the present invention, a technique including a method and device for securing a computer module using a password in a computer system is provided. In an exemplary embodiment, the present invention provides a security system for an attached computer module (“ACM”). In an embodiment, the ACM inserts into a Computer Module Bay (CMB) within a peripheral console to form a functional computer.

In a specific embodiment, the present invention provides a computer module. The computer module has an enclosure that is insertable into a console. The module also has a central processing unit (i.e., integrated circuit chip) in the enclosure. The module has a hard disk drive in the enclosure, where the hard disk drive is coupled to the central processing unit. The module further has a programmable memory device in the enclosure, where the programmable memory device can be configurable to store a password for preventing a possibility of unauthorized use of the hard disk drive and/or other module elements. The stored password can be any suitable key strokes that a user can change from time to time. In a further embodiment, the present invention provides a permanent password or user identification code stored in flash memory, which also can be in the processing unit, or other integrated circuit element. The permanent password or user identification code is designed to provide a permanent “finger print” on the attached computer module.

In a specific embodiment, the present invention provides a variety of methods. In one embodiment, the present invention provides a method for operating a computer system such as a modular computer system and others. The method includes inserting an attached computer module (“ACM”) into a bay of a modular computer system. The ACM has a microprocessor unit (e.g., microcontroller, microprocessor) coupled to a mass memory storage device (e.g., hard disk). The method also includes applying power to the computer system and the ACM to execute a security program, which is stored in the mass memory storage device. The method also includes prompting for a user password from a user on a display (e.g., flat panel, CRT). In a further embodiment, the present method includes a step of reading a permanent password or user identification code stored in flash memory, or other integrated circuit element. The permanent password or user identification code provides a permanent finger print on the attached computer module. The present invention includes a variety of these methods that can be implemented in computer codes, for example, as well as hardware.

Numerous benefits are achieved using the present invention over previously existing techniques. The present invention provides mechanical and electrical security systems to prevent theft or unauthorized use of the computer system in a specific embodiment. Additionally, the present invention substantially prevents accidental removal of the ACM from the console. In some embodiments, the present invention prevents illegal or unauthorized use during transit. The present invention is also implemented using conventional technologies that can be provided in the present computer system in an easy and efficient manner. Depending upon the embodiment, one or more of these benefits can be available. These and other advantages or benefits are described throughout the present specification and are described more particularly below.

These and other embodiments of the present invention, as well as its advantages and features, are described in more detail in conjunction with the text below and attached FIGS.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified diagram of a computer system according to an embodiment of the present invention;

FIG. 2 is a simplified diagram of a computer module according to an embodiment of the present invention;

FIG. 3 is a simplified side-view diagram of a computer module according to an embodiment of the present invention;

FIG. 4 is a simplified layout diagram of a security system for a computer system according to an embodiment of the present invention;

FIG. 5 is a simplified block diagram of a security system for a computer module according to an embodiment of the present invention; and

FIGS. 6 and 7 show simplified flow diagrams of security methods according to embodiments of the present invention.

FIG. 8 is a block diagram of one embodiment of a computer system employing the present invention.

FIG. 9 is a block diagram of an attached computing module (ACM).

FIG. 10 is a block diagram of a peripheral console (PCON).

FIG. 11 is a block diagram of one embodiment of a computer system using the interface of the present invention.

FIG. 12 is a detailed block diagram of one embodiment of the host interface controller (HIC) of the present invention.

FIG. 13 is a detailed block diagram of one embodiment of the PIC of the present invention.

FIG. 14 is a schematic diagram of the signal lines PCK, PD0 to PD3, and PCN.

FIG. 15 is a block diagram of another embodiment of the HIC and PIC of the present invention and the interface therebetween.

FIG. 16 is a detailed block diagram of another embodiment of the HIC of the present invention.

FIG. 17 is a schematic diagram of the signal lines PCK and PD0 to PD3.

FIG. 18 is a partial block diagram of a computer system in which the north and south bridges are integrated with the host and peripheral interface controllers, respectively.

DESCRIPTION OF SPECIFIC EMBODIMENTS

I. System Hardware

FIG. 1 is a simplified diagram of a computer system 1 according to an embodiment of the present invention. This diagram is merely an illustration and should not limit the scope of the claims herein. One of ordinary skill in the art would recognize other variations, modifications, and alternatives. The computer system 1 includes an attached computer module (i.e., ACM) 10, a desktop console 20, among other elements. The computer system is modular and has a variety of components that are removable. Some of these components (or modules) can be used in different computers, workstations, computerized television sets, and portable or laptop units.

In the present embodiment, ACM 10 includes computer components, as will be described below, including a central processing unit (“CPU”), IDE controller, hard disk drive, computer memory, and the like. The computer module bay (i.e., CMB) 40 is an opening or slot in the desktop console. The CMB houses the ACM and provides communication to and from the ACM. The CMB also provides mechanical protection and support to ACM 10. The CMB has a mechanical alignment mechanism for mating a portion of the ACM to the console. The CMB further has thermal heat dissipation sinks, electrical connection mechanisms, and the like. Some details of the ACM can be found in co-pending patent application Nos. 09/149,882 and 09/149,548 filed Sep. 8, 1998, commonly assigned, and hereby incorporated by reference for all purposes.

In a preferred embodiment, the present system has a security system, which includes a mechanical locking system, an electrical locking system, and others. The mechanical locking system includes at least a key 11. The key 11 mates with key hole 13 in a lock, which provides a mechanical latch 15 in a closed position. The mechanical latch, in the closed position, mates and interlocks the ACM to the computer module bay. The mechanical latch, which also has an open position, allows the ACM to be removed from the computer module bay. Further details of the mechanical locking system are shown in the Fig. below.

FIG. 2 is a simplified diagram of a computer module 10 according to an embodiment of the present invention. This diagram is merely an illustration and should not limit the scope of the claims herein. One of ordinary skill in the art would recognize other variations, modifications, and alternatives. Some of the reference numerals are similar to the previous Fig. for easy reading. The computer module 10 includes key 11, which is insertable into keyhole 13 of the lock. The lock has at least two position, including a latched or closed position and an unlatched or open position. The latched position secures the ACM to the computer module bay. The unlatched or open position allows the ACM to be inserted into or removed from the computer bay module. As shown, the ACM also has a slot or opening 14, which allows the latch to move into and out of the ACM. The ACM also has openings 17 in the backside for an electrical and/or mechanical connection to the computer module bay, which is connected to the console.

FIG. 3 is a simplified side-view diagram of a computer module according to an embodiment of the present invention. This diagram is merely an illustration and should not limit the scope of the claims herein. One of ordinary skill in the art would recognize other variations, modifications, and alternatives. Some of the reference numerals are similar to the previous FIG. for easy reading. As shown, the ACM module inserts into the computer module bay frame 19, which is in the console. A side 27 and a bottom 19 of ACM slide and fit firmly into the computer module bay frame, which has at least a bottom portion 19 and back portion 26. A backside 23 of the ACM faces backside 26 of the frame. ACM also has a front-side or face 25 that houses the lock and exposes the keyhole 13 to a user. The key 11 is insertable from the face into the keyhole.

As the ACM inserts into the frame, connector 17 couples and inserts into connector 21. Connector 17 electrically and mechanically interface elements of the ACM to the console through connector 21. Latch 14 should be moved away from the bottom side 19 of the module bay frame before inserting the ACM into the frame. Once the ACM is inserted fully into the frame, latch 15 is placed in a closed or lock position, where it keeps the ACM firmly in place. That is, latch 15 biases against a backside portion 29 of the ACM enclosure to hold the ACM in place, where the connector 17 firmly engages, electrically and mechanically, with connector 21. To remove the ACM, latch 15 is moved away or opened from the back side portion of the ACM enclosure. ACM is manually pulled out of the computer module bay frame, where connector 17 disengages with connector 21. As shown, the key 11 is used to selectively move the latch in the open or locked position to secure the ACM into the frame module.

In most embodiments, the ACM includes an enclosure such as the one described with the following components, which should not be limiting:

    • 1) A CPU with cache memory;
    • 2) Core logic device or means;
    • 3) Main memory;
    • 4) A single primary Hard Disk Drive (“HDD”) that has a security program;
    • 5) Flash memory with system BIOS and programmable user password;
    • 6) Operating System, application software, data files on primary HDD;
    • 7) An interface device and connectors to peripheral console;
    • 8) A software controllable mechanical lock, lock control means, and other accessories.

The ACM connects to a peripheral console with power supply, a display device, an input device, and other elements. Some details of these elements with the present security system are described in more detail below.

FIG. 4 is a simplified layout diagram of a security system for a computer system according to an embodiment of the present invention. This diagram is merely an illustration and should not limit the scope of the claims herein. One of ordinary skill in the art would recognize other variations, modifications, and alternatives. The layout diagram illustrates the top-view of the module 10, where the backside components (e.g., Host Interface Controller) are depicted in dashed lines. The layout diagram has a first portion, which includes a central processing unit (“CPU”) module 400, and a second portion, which includes a hard drive module 420. A common printed circuit board 437 houses these modules and the like. Among other features, the ACM includes the central processing unit module 400 with a cache memory 405, which is coupled to a north bridge unit 421, and a host interface controller 401. The host interface controller includes a lock control 403. As shown, the CPU module is disposed on a first portion of the attached computer module, and couples to connectors 17. Here, the CPU module is spatially located near connector 17.

The CPU module can use a suitable microprocessing unit, microcontroller, digital signal processor, and the like. In a specific embodiment, the CPU module uses, for example, a 400 MHz Pentium II microprocessor module from Intel Corporation and like microprocessors from AMD Corporation, Cyrix Corporation (now National Semiconductor Corporation), and others. In other aspects, the microprocessor can be one such as the Compaq Computer Corporation Alpha Chip, Apple Computer Corporation PowerPC G3 processor, and the like. Further, higher speed processors are contemplated in other embodiments as technology increases in the future.

In the CPU module, host interface controller 401 is coupled to BIOS/flash memory 405. Additionally, the host interface controller is coupled to a clock control logic, a configuration signal, and a peripheral bus. The present invention has a host interface controller that has lock control 403 to provide security features to the present ACM. Furthermore, the present invention uses a flash memory that includes codes to provide password protection or other electronic security methods.

The second portion of the attached computer module has the hard drive module 420. Among other elements, the hard drive module includes north bridge 421, graphics accelerator 423, graphics memory 425, a power controller 427, an IDE controller 429, and other components. Adjacent to and in parallel alignment with the hard drive module is a personal computer interface (“PCI”) bus 431, 432. A power regulator 435 is disposed near the PCI bus.

In a specific embodiment, north bridge unit 421 often couples to a computer memory, to the graphics accelerator 423, to the IDE controller, and to the host interface controller via the PCI bus. Graphics accelerator 423 typically couples to a graphics memory 423, and other elements. IDE controller 429 generally supports and provides timing signals necessary for the IDE bus. In the present embodiment, the IDE controller is embodied as a 643U2 PCI-to IDE chip from CMD Technology, for example. Other types of buses than IDE are contemplated, for example EIDE, SCSI, 1394, and the like in alternative embodiments of the present invention.

The hard drive module or mass storage unit 420 typically includes a computer operating system, application software program files, data files, and the like. In a specific embodiment, the computer operating system may be the Windows98 operating system from Microsoft Corporation of Redmond Wash. Other operating systems, such as WindowsNT, MacOS8, Unix, and the like are also contemplated in alternative embodiments of the present invention. Further, some typical application software programs can include Office98 by Microsoft Corporation, Corel Perfect Suite by Corel, and others. Hard disk module 420 includes a hard disk drive. The hard disk drive, however, can also be replaced by removable hard disk drives, read/write CD ROMs, flash memory, floppy disk drives, and the like. A small form factor, for example 2.5″, is currently contemplated, however, other form factors, such as PC card, and the like are also contemplated. Mass storage unit 240 may also support other interfaces than IDE. Among other features, the computer system includes an ACM with security protection. The ACM connects to the console, which has at least the following elements, which should not be limiting.

    • 1) Connection to input devices, e.g. keyboard or mouse;
    • 2) Connection to display devices, e.g. Monitor;
    • 3) Add-on means, e.g. PCI add-on slots;
    • 4) Removable storage media subsystem, e.g. Floppy drive, CDROM drive;
    • 5) Communication device, e.g. LAN or modem;
    • 6) An interface device and connectors to ACM;
    • 7) A computer module bay with a notch in the frame for ACM's lock; and
    • 8) Power supply and other accessories.

As noted, the computer module bay is an opening in a peripheral console that receives the ACM. The computer module bay provides mechanical support and protection to ACM. The module bay also includes, among other elements, a variety of thermal components for heat dissipation, a frame that provides connector alignment, and a lock engagement, which secures the ACM to the console. The bay also has a printed circuit board to mount and mate the connector from the ACM to the console. The connector provides an interface between the ACM and other accessories.

FIG. 5 is a simplified block diagram 500 of a security system for a computer module according to an embodiment of the present invention. This diagram is merely an illustration and should not limit the scope of the claims herein. One of ordinary skill in the art would recognize other variations, modifications, and alternatives. The block diagram 500 has a variety of features such as those noted above, as well as others. In the present diagram, different reference numerals are used to show the operation of the present system.

The block diagram is an attached computer module 500. The module 500 has a central processing unit, which communicates to a north bridge 541, by way of a CPU bus 527. The north bridge couples to main memory 523 via memory bus 529. The main memory can be any suitable high speed memory device or devices such as dynamic random access memory (“DRAM”) integrated circuits and others. The DRAM includes at least 32 Meg. or 64 Meg. and greater of memory, but can also be less depending upon the application. Alternatively, the main memory can be coupled directly with the CPU in some embodiments. The north bridge also couples to a graphics subsystem 515 via bus 542. The graphics subsystem can include a graphics accelerator, graphics memory, and other devices. Graphics subsystem transmits a video signal to an interface connector, which couples to a display, for example.

The attached computer module also includes a primary hard disk drive that serves as a main memory unit for programs and the like. The hard disk can be any suitable drive that has at least 2 GB and greater. As merely an example, the hard disk is a Marathon 2250 (2.25 GB, 2 ½ inch drive) product made by Seagate Corporation of Scotts Valley, but can be others. The hard disk communicates to the north bridge by way of a hard disk drive controller and bus lines 502 and 531. The hard disk drive controller couples to the north bridge by way of the host PCI bus, which connects bus 537 to the north bridge. The hard disk includes computer codes that implement a security program according to the present invention. Details of the security program are provided below.

The attached computer module also has a flash memory device 505 with a BIOS. The flash memory device 505 also has codes for a user password that can be stored in the device. The flash memory device generally permits the storage of such password without a substantial use of power, even when disconnected. As merely an example, the flash memory device has at least 4 Meg. or greater of memory, or 16 Meg. or greater of memory. A host interface controller 507 communications to the north bridge via bus 535 and host PCI bus. The host interface controller also has a lock control 509, which couples to a lock. The lock is attached to the module and has a manual override to the lock on the host interface controller in some embodiments. Host interface controller 507 communicates to the console using bus 511, which couples to connection 513.

In one aspect of the present invention the security system uses a combination of electrical and mechanical locking mechanisms. Referring to FIG. 5A, for example, the present system provides a lock status mechanism in the host interface controller 509. The lock status of the lock is determined by checking a lock status bit 549, which is in the host interface controller. The lock status bit is determined by a signal 553, which is dependent upon the position of the lock. Here, the position of the lock is closed in the ground 559 position, where the latch couples to a ground plane in the module and/or system. Alternatively, the signal of the lock is at Vcc, for example, which is open. Alternatively, the signal can be ground in the open position and Vcc in the closed position, depending upon the application. Other signal schemes can also be used depending upon the application.

Once the status is determined, the host interface controller turns the lock via solenoid 557 in a lock on or lock off position, which is provided through the control bit 551, for example. The control bit is in a register of the host interface controller in the present example. By way of the signal schemes noted and the control bit, it is possible to place the lock in the lock or unlock position in an electronic manner. Once the status of the lock is determined, the host interface controller can either lock or unlock the latch on the module using a variety of prompts, for example.

In a preferred embodiment, the present invention uses a password protection scheme to electronically prevent unauthorized access to the computer module. The present password protection scheme uses a combination of software, which is a portion of the security program, and a user password, which can be stored in the flash memory device 505. By way of the flash memory device, the password does not become erased by way of power failure or the lock. The password is substantially fixed in code, which cannot be easily erased. Should the user desire to change the password, it can readily be changed by erasing the code, which is stored in flash memory and a new code (i.e., password) is written into the flash memory. An example of a flash memory device can include a Intel Flash 28F800F3 series flash, which is available in 8 Mbit and 16 Mbit designs. Other types of flash devices can also be used, however. Details of a password protection method are further explained below by way of the FIGS.

In a specific embodiment, the present invention also includes a real-time clock 510 in the ACM, but is not limited. The real-time clock can be implemented using a reference oscillator 14.31818 MHz 508 that couples to a real-lime clock circuit. The real-time clock circuit can be in the host interface controller. An energy source 506 such as a battery can be used to keep the real-time clock circuit running even when the ACM has been removed from the console. The real-time clock can be used by a security program to perform a variety of functions. As merely an example, these functions include: (1) fixed time period in which the ACM can be used, e.g., ACM cannot be used at night; (2) programmed ACM to be used after certain date, e.g., high security procedure during owner's vacation or non use period; (3) other uses similar to a programmable time lock. Further details of the present real-time clock are described in the application listed under Ser. No. 09/183,816 noted above.

In still a further embodiment, the present invention also includes a permanent password or user identification code to identify the computer module. In one embodiment, the permanent password or user code is stored in a flash memory device. Alternatively, the permanent password or user code is stored in the central processing unit. The password or user code can be placed in the device upon manufacture of such device. Alternatively, the password or user code can be placed in the device by a one time programming techniques using, for example, fuses or the like. The present password or user code provides a permanent “finger print” on the device, which is generally hardware. The permanent finger print can be used for identification purposes for allowing the user of the hardware to access the hardware itself, as well as other systems. These other systems include local and wide area networks. Alternatively, the systems can also include one or more servers. The present password and user identification can be quite important for electronic commerce applications and the like. In one or more embodiments, the permanent password or user code can be combined with the password on flash memory for the security program, which is described below in more detail.

II. SECURITY DETECTION PROGRAMS

FIGS. 6 and 7 show simplified flow diagrams 600, 700 of security methods according to embodiments of the present invention. These diagrams are merely illustrations and should not limit the scope of the claims herein. One of ordinary skill in the art would recognize other variations, modifications, and alternatives. Referring to FIG. 6, which considers an example for when the ACM is inserted into the computer module bay in the console, ACM has already been inserted into the console and is firmly engaged in an electrical and mechanical manner. A computer system is powered up 601, which provides selected signals to the microprocessor. The microprocessor oversees the operation of the computer system. The microprocessor searches the memory in, for example, the hard disk drive and execute a security program, step 603.

The security program runs through a sequence of steps before allowing a user to operate the present system with the ACM. Among other processes, the security program determines if an “Auto-lock” is ON. If so, the security program goes via branch 606 to step 607. Alternatively, the security program goes to step 609, which determines that the lock stays OFF and loops to step 627, which indicates that the ACM can be removed physically from the console. In step 607, the security program turns a switch or switching means that turns ON a lock, which can be electrical, mechanical, or a combination of electrical and mechanical.

In a specific embodiment, the security program turns OFF the power of the ACM and console. Here, the security program directs the OS to turn the power OFF, step 613. In an embodiment where power failure occurs (step 611), a key is used to release a latch in the ACM on the lock 615, where the ACM can be removed, step 627. From step 613, the security program determines if the ACM is to be removed, step 617. If not, the lock stays ON, step 619. Alternatively, the security detection program determines if the password (or other security code) matches with the designated password, step 621. If not, the lock stays ON, step 623. Alternatively, the security program releases the lock 625, which frees the ACM. Next, the ACM can be removed, step 627.

In an alternative embodiment, the present invention provides a security system for the ACM, which is outside the console or computer module bay. See, FIG. 7, for example. As shown, the security system is implemented to prevent illegal or unauthorized use (step 701) of the ACM, which has not been used in the console. Here, a key turns ON a lock (step 703). The lock moves a latch in the ACM to a specific spatial location that physically blocks the passage of the ACM into the computer module bay. Accordingly, the ACM cannot insert (step 705) into the computer module bay.

In an alternative aspect, the key can be used to turn the lock OFF, step 707. Here, the key moves the latch in a selected spatial location that allows the ACM to be inserted into the computer bay module. In the OFF position, the ACM inserts into the computer module bay, step 709. Once the ACM is in the bay, a user can begin operating the ACM through the console. In one embodiment, the computer console including the ACM goes through the sequence of steps in the above FIG., but is not limited.

In a specific embodiment, the present invention implements the sequences above using computer software. In other aspects, computer hardware can also be used and is preferably in some applications. The computer hardware can include a mechanical lock, which is built into the ACM. An example of such mechanical lock is shown above, but can also be others. In other aspects, the lock can be controlled or accessed electronically by way of computer software. Here, the key can be used to as a manual override if the ACM or computer fails.

The lock is used to prevent theft and accidental removal inside CMB. The current invention locates the lock inside the ACM to allow a user to keep a single key as ACM is moved from console to console at different locations. When ACM is in transit, the lock can be engaged using the key so that the latch extends outside ACM's enclosure. The extended latch prevents ACM from being inserted into any CMB. This prevents any illegal use of ACM by someone other than the user.

In one aspect of the invention, the user password is programmable. The password can be programmable by way of the security program. The password can be stored in a flash memory device within the ACM. Accordingly, the user of the ACM and the console would need to have the user password in order to access the ACM. In the present aspect, the combination of a security program and user password can provide the user a wide variety of security functions as follows:

    • 1) Auto-lock capability when ACM is inserted into CMB;
    • 2) Access privilege of program and data;
    • 3) Password matching for ACM removal; and
    • 4) Automatic HDD lock out if tempering is detected.

In still a further embodiment, the present invention also includes a method for reading a permanent password or user identification code to identify the computer module. In one embodiment, the permanent password or user code is stored in a flash memory device. Alternatively, the permanent password or user code is stored in the central processing unit. The password or user code can be placed in the device upon manufacture of such device. Alternatively, the password or user code can be placed in the device by a one time programming techniques using, for example, fuses or the like. The present password or user code provides a permanent “finger print” on the device, which is generally hardware. The permanent finger print can be used for identification purposes for allowing the user of the hardware to access the hardware itself, as well as other systems. These other systems include local and wide area networks. Alternatively, the systems can also include one or more servers. The present method allows a third party confirm the user by way of the permanent password or user code. The present password and user identification can be quite important for electronic commerce applications and the like, which verify the user code or password. In one or more embodiments, the permanent password or user code can be combined with the password on flash memory for the security program.

FIG. 8 is a block diagram of the components in one computer system employing the present invention. The computer system comprises an attached computer module (ACM), a peripheral console (PCON), and the interconnection apparatus between them. The ACM includes the central processing unit (CPU) 810, system memory 820, high performance devices 850, primary mass storage 830, and related interface and support circuitry 840. The PCON includes primary display 910, primary input 920, secondary mass storage 950, other devices 960, expansion slots 970, the primary power supply 930, and related interface and support circuitry 940. The interconnection apparatus 1000 includes circuitry to convey power and operational signals between the ACM and PCON.

Within the ACM 800, the CPU 810 executes instructions and manipulates data stored in the system memory. The CPU 810 and system memory 820 represent the user's core computing power. The core computing power may also include high performance devices 850 such as advanced graphics processor chips that greatly increase overall system performance and which, because of their speed, need to be located close to the CPU. The primary mass storage 830 contains persistent copies of the operating system software, application software, configuration data, and user data. The software and data stored in the primary mass storage device represent the user's computing environment. Interface and support circuitry 840 primarily includes interface chips and signal busses that interconnect the CPU, system memory, high performance devices, and primary mass storage. The interface and support circuitry also connects ACM-resident components with the ACM-to-PCON interconnection apparatus as needed.

Within the PCON 900, the primary display component 910 may include an integrated display device or connection circuitry for an external display device. This primary display device may be, for example, an LCD, plasma, or CRT display screen used to display text and graphics to the user for interaction with the operating system and application software. The primary display component is the primary output of the computer system, i.e., the paramount vehicle by which programs executing on the CPU can communicate toward the user.

The primary input component 920 of the PCON may include an integrated input device or connection circuitry for attachment to an external input device. The primary input may be, for example, a keyboard, touch screen, keypad, mouse, trackball, digitizing pad, or some combination thereof to enable the user to interact with the operating system and application software. The primary input component is the paramount vehicle by which programs executing on the CPU receive signals from the user.

The PCON may contain secondary mass storage 950 to provide additional high capacity storage for data and software. Secondary mass storage may have fixed or removable media and may include, for example, devices such as diskette drives, hard disks, CD-ROM drives, DVD drives, and tape drives.

The PCON may be enhanced with additional capability through the use of integrated “Other Devices” 960 or add-on cards inserted into the PCON's expansion slots 970. Examples of additional capability include sound generators, LAN connections, and modems. Interface and support circuitry 940 primarily includes interface chips, driver chips, and signal busses that interconnect the other components within the PCON. The interface and support circuitry also connects PCON-resident components with the ACM-to-PCON interconnection apparatus as needed.

Importantly, the PCON houses the primary power supply 930. The primary power supply has sufficient capacity to power both the PCON and the ACM 800 for normal operation. Note that the ACM may include a secondary “power supply” in the form, for example, of a small battery. Such a power supply would be included in the ACM to maintain, for example, a time-of-day clock, configuration settings when the ACM is not attached to a PCON, or machine state when moving an active ACM immediately from one PCON to another. The total energy stored in such a battery would, however, be insufficient to sustain operation of the CPU at its rated speed, along with the memory and primary mass storage, for more than a fraction of an hour, if the battery were able to deliver the required level of electrical current at all.

FIG. 9 is a block diagram of an attached computing module (ACM) 800. The physical ACM package 800 contains the ACM functional components 801 and the ACM side of the ACM-to-PCON Interconnection 1000. The ACM 801 comprises a CPU component 810, a system memory component 820, a primary mass storage component 830, a high performance devices components 850, and an interface and support component 840.

The ACM side of the ACM-to-PCON Interconnection 1000 comprises a Host Interface Controller (HIC) component 1020 and an ACM connector component 1030. The HIC 1020 and connector 1030 components couple the ACM functional components 800 with the signals of an ACM-to-PCON interface bus 1010 used to operatively connect an ACM with a PCON. The ACM-to-PCON interface bus 1010 comprises conveyance for electrical power 1014 and signals for a peripheral bus 1012, video 1016, video port 1017, and console type 1018. The preferred ACM-to-PCON Interconnection 1000 is described in detail in a companion U.S. patent application Ser. No. 09/149,882, entitled “A Communication Channel and Interface Devices for Bridging Computer Interface Buses,” by the same inventor, filed on the same day herewith, and hereby incorporated by reference. The preferred ACM-to-PCON interconnection 1000 includes circuitry to transmit and receive parallel bus information from multiple signal paths as a serial bit stream on a single signal path. This reduces the number of physical signal paths required to traverse the interconnection 1000. Further, employing low-voltage differential signaling (LVDS) on the bit stream data paths provides very reliable, high-speed transmission across cables. This represents a further advantage of the present invention.

The CPU component 810 of the ACM functional circuitry 801 of the presently described embodiment comprises a microprocessor 812, which is the chief component of the personal computer system, power supply connection point 813, and cache memory 814 tightly coupled to the microprocessor 812 by the CPU-to-cache bus 874 comprising signal paths for address, data, and control information. The microprocessor 812 of this embodiment is one of the models from the Pentium II family of processors from Intel Corporation. Microprocessor 812 receives electrical power from power bus 168 via connection point 813. Microprocessor 812 couples to the Host Interface Controller (HIC) 320 via CPU-to-HIC bus 863 comprising signal paths to exchange control information such as an interrupt request. Microprocessor 812 also couples to CPU Bridge 846 via CPU main bus 864 comprising signal paths for address, data, and control information.

The CPU Bridge component 846 of the interface and support circuitry 840 operates to couple the high speed CPU main bus 864 to specialty buses of varying speeds and capability that connect other computer components. The CPU Bridge of the presently described embodiment incorporates memory controller circuitry, advanced graphics processor support circuitry, and a general, industry-standard PCI bus controller in a single package. A CPU Bridge 146 such as the 82443LX PCI/AGP Controller from Intel Corporation may be used.

The system memory component 820 of the ACM functional circuitry 801 in the present embodiment comprises main system memory (RAM) 822, BIOS memory 824, and flash memory 826. The system memory 820 is used to contain data and instructions that are directly addressable by the CPU. The RAM 822 comprises volatile memory devices such as DRAM or SDRAM memory chips that do not retain their stored contents when power is removed. This form of memory represents the largest proportion of total system memory 820 capacity. The BIOS memory 824 comprises non-volatile memory devices such as ROM or EPROM memory chips that retain their stored contents regardless of the application of power and are read-only memory under normal operating conditions. The BIOS memory 824 stores, for example, start-up instructions for the microprocessor 812 and sets of instructions for rudimentary input/output tasks. The flash memory 826 comprises non-volatile memory devices that retain their stored contents regardless of the application of power. Unlike the BIOS non-volatile memory, however, the stored contents of the flash memory 826 are easily changed under normal operating conditions. The flash memory 826 may be used to store status and configuration data, such as security identifiers or ACM specifications like the speed of the microprocessor 812. Some embodiments may combine the BIOS functions into the flash memory device, thus permitting BIOS contents to be rewritten, improving field upgradability.

The main system memory (RAM) 822 is coupled to memory controller circuitry resident within the CPU Bridge 846 via direct memory bus 865. The BIOS 824 and flash memory 826 are coupled to HIC 1020 via switched memory bus 866. This permits the BIOS 824 and flash 826 memories to be accessed by circuitry in the HIC 1020 or other circuitry connected thereto. The direct memory bus 865 and the switch memory bus 866 each comprises conductors to convey signals for data, address, and control information.

The primary mass storage component 830 of the ACM functional circuitry 801 in the present embodiment comprises a compact hard disk drive with an industry-standard, IDE interface. The hard disk drive (HDD) 832 has a formatted storage capacity sufficient to contain an operating system for the computer, application software desired by the user, and related user configuration and operating parameter data. The HDD 832 in the present embodiment serves as the “boot” device for the personal computer from which the operating system is loaded into RAM 122 by the start-up program stored in the BIOS 824.

The present HDD 832 has a capacity of approximately 2,000 megabytes to provide adequate storage for common software configurations and reasonable space for user data. One example of a common software configuration includes the Windows 95 operating system from Microsoft Corporation, a word processing program, a spreadsheet program, a presentation graphics program, a database program, an email program, and a web browser such as Navigator from Netscape Corporation. The hard disk 832 stores program and data files for each software component, including files distributed by the vendor as well as files created or updated by operation of the software after it is installed. For example, a word processor program may maintain information about a user's identity and latest preferences in an operating system registry file. Or, for example, the web browser may maintain a file of the user's favorite web sites or most recently viewed web pages. An HDD with 2000 megabyte capacity is readily available in the small size of hard disk (e.g., 2.5-inch or 3.5-inch) to minimize the space required within the ACM for the primary mass storage device 130.

The HDD 832 is coupled to IDE controller circuitry 848 via IDE bus 872. The IDE controller circuitry 848 is coupled to the CPU Bridge 846 via the Host PCI bus 867. IDE controllers and busses, and the PCI bus are well known and understood in the industry. The above components operate together to couple the hard disk drive 832 to the microprocessor 812.

The high performance devices component 850 of the ACM functional circuitry 801 in the present embodiment comprises an Advanced Graphics Processor (AGP) 852. The Model 740 Graphics Device from Intel Corporation may be used in the present embodiment as the AGP.

Increases in computer screen size, graphics resolution, color depth, and visual motion frame rates, used by operating system and application software alike, have increased the computing power required to generate and maintain computer screen displays. An AGP removes a substantial portion of the graphics computing burden from the CPU to the specialized high-performance processor, but a high level of interaction between the CPU and the specialized processor is nonetheless required. To maximize the effective contribution of having a specialized processor in the presently described embodiment, the AGP 852 is located in the ACM 800, where it is in close proximity to the microprocessor 812. The AGP 852 is coupled to the microprocessor 812 via the advanced graphics port bus 873 of the CPU Bridge 846. The visual display signal generated by the AGP are conveyed toward actual display devices at the peripheral console (PCON) via video signal bus 870. Video information from a source external to the ACM and appearing as video port signals 1017 may be conveyed to the AGP 852 via video port signal path 871.

Other types of high performance components may be included in different ACM configurations. For example, an interface to an extremely high speed data communication facility may be desirable in some future computer where CPU-to-network interaction is of comparable intensity to today's CPU-to-graphics interaction. Because such high performance components tend to be high in cost, their inclusion in the ACM is desirable. Inclusion of high cost, high performance components in the ACM concentrates a user's core computing power and environment in a portable package. This represents a further advantage of the invention.

The interface and support component 840 of the ACM functional circuitry 801 in the present embodiment comprises circuitry for power regulation 842, clocking 844, CPU Bridge 846, IDE controller 848, and signal conveyance paths 861-874. The CPU Bridge 846 couples the CPU component 810 of the ACM 800 with the other components of the ACM 820-850 and the CPU-to-PCON Interconnection 1000. The CPU Bridge 846 and IDE controller 848 have already been discussed. Power regulation circuitry 842 receives electrical power via the electrical power conduction path 1014 of the CPU-to-PCON Interconnection 1000, conditions and distributes it to the other circuitry in the ACM using power distribution bus 868. Such regulation and distribution is well known and understood in the art.

Clocking circuitry 844 generates clock signals for distribution to other components within the ACM 800 that require a timing and synchronization clock source. The CPU 810 is one such component. Often, the total power dissipated by a CPU is directly proportional to the frequency of its main clock signal. The presently described embodiment of the ACM 800 includes circuitry that can vary the frequency of the main CPU clock signal conveyed to the CPU via signal path 862, in response to a signal received from the host interface controller (HIC) 1020 via signal path 861. The generation and variable frequency control of clocking signals is well understood in the art. By varying the frequency, the power consumption of the CPU (and thus the entire ACM) can be varied.

The variable clock rate generation may be exploited to match the CPU power consumption to the available electrical power. Circuitry in the host interface controller (HIC) 1020 of the presently described embodiment adjusts the frequency control signal sent via signal path 861 to the clocking circuitry 844, based on the “console type” information signal 1018 conveyed from the peripheral console (PCON) by the CPU-to-PCON interconnection 1000. In this arrangement, the console type signal originating from a desktop PCON would result in the generation of a maximum speed CPU clock. The desktop PCON, presumably has unlimited power from an electrical wall outlet and does not need to sacrifice speed for power conservation. The console type signal originating from a notebook PCON would, however, result in the generation of a CPU clock speed reduced from the maximum in order to conserve battery power and extend the duration of computer operation obtained from the energy stored in the battery. The console type signal originating from a notepad PCON would result in the generation of a CPU clock speed reduced further yet, the notepad PCON presumably having smaller batteries than the notebook PCON. Inclusion of control signals and circuitry to effect a CPU clock signal varying in frequency according to characteristics of the PCON to which the ACM is connected facilitates the movement of the user's core computing power and environment to different work settings, which is a further advantage of the present invention.

FIG. 10 is a block diagram of a peripheral console (PCON). A peripheral console couples with an ACM to form an operating personal computer system. The peripheral console (PCON) supplies an ACM with primary input, display, and power supply; the ACM supplies the core computing power and environment of the user. In the presently described embodiment the physical PCON package 900 contains the PCON functional components 901 and the PCON side of the ACM-to-PCON Interconnection 1000. The PCON functional components 901 comprise primary display 910, a primary input 920, a primary power supply 930, interface and support 940, secondary mass storage 950, other devices 960, and expansion slots 970.

The PCON side of the ACM-to-PCON Interconnection 1000 comprises a Peripheral Interface Controller (PIC) component 1040, a PCON connector component 1050, console-type component 1042, and flash memory device 1048. The PIC 1040 and connector 1050 components couple the PCON functional components 901 with the signals of an ACM-to-PCON interface bus 1010 used to operatively connect an ACM with a PCON. The ACM-to-PCON interface bus 1010 comprises conveyance for electrical power 1014 and signals for a peripheral bus 1012, video 1016, video port 1017, and console-type 1018. The preferred ACM-to-PCON Interconnection 1000 is described in detail in the U.S. patent application entitled “A Communication Channel and Interface Devices for Bridging Computer Interface Buses,” already incorporated herein by reference.

Connector component 1050 may be selected to mate directly with the connector component 1030 of an ACM (shown in FIG. 9). Alternatively, connector component 1050 may be selected to mate with, for example, the connector on one end of a cable intervening between the PCON and an ACM in a particular embodiment. The ACM-to-PCON interconnection described in the aforementioned companion patent application has the advantage of providing reliable signal conveyance across low cost cables.

Flash memory device 1048 provides non-volatile storage. This storage may be accessible to devices in both the ACM and the PCON, including the host interface controller and the peripheral interface controller to which it is connected. As such, flash memory 1048 may be used to store configuration and security data to facilitate an intelligent mating between an ACM and a PCON that needs no participation of the CPU.

The primary display component 910 of the PCON functional circuitry 901 of the presently described embodiment comprises integrated display panel 912 and video connector 913. Integrated display panel 912 is a color LCD display panel having a resolution of 640 horizontal by 480 vertical pixels. 640-by-480 resolution is popularly considered to be the minimum screen size to make practical use of the application software in widespread use today. One skilled in the art recognizes that the type and resolution of the display can vary greatly from embodiment to embodiment, depending on factors such as cost and intended application. Any display device may be used, without departing from the scope and spirit of the invention, that provides principal visual output to the computer user for operating system and application software executing in its customary and intended fashion using the CPU component (810 of FIG. 8) of an ACM presently coupled to PCON 900.

Integrated display panel 912 is coupled to video signal bus 949 and displays a screen image in response to video signals presented on bus 949. Certain pins of connector 1050 receive video output signals 1016 of the ACM-to-PCON interface bus 1010 from a mated connector that is coupled to an ACM. These certain pins of connector 1050 couple to video signal bus 949 which conveys the video output signals 1016 throughout the PCON 900 as needed. Video connector 913 is exposed at the exterior of PCON 900 and couples to video signal bus 949. Connector 913 permits easy attachment of an external display device that is compatible with the signals carried by bus 949, such as a CRT monitor (not shown). The external display device may be used in addition, or as an alternative, to integrated display panel 912.

The isolation of the relatively heavy and sizable primary display 910 from the core computing power and user environment contained within an ACM represents a further advantage of the present invention.

The primary input component 920 of the PCON functional circuitry 901 of the presently described embodiment comprises keyboard interface circuitry 922, keyboard connector 923, pointer interface circuitry 924, and pointer connector 925. Keyboard interface circuitry 922 and pointer interface circuitry 924 connect to ISA bus 945 and are thereby coupled to the CPU component (810 of FIG. 8) of any ACM attached to PCON 900. Keyboard interface circuitry 922 interfaces a standard computer keyboard (not shown), attached at connector 923, to ISA bus 945. Pointer interface circuitry 922 interfaces a standard computer pointing device (not shown), such as a computer mouse attached at connector 925, to ISA bus 945. Computer keyboards, pointing devices, connectors 923, 925, keyboard interface circuitry 922, and pointer interface circuitry 924 are well known in the art. The isolation of the relatively heavy and sizable primary input devices 920 from the core computing power and user environment contained within an ACM represents a further advantage of the present invention.

The primary power supply component 930 of the PCON functional circuitry 901 of the presently described embodiment provides electrical energy for the sustained, normal operation of the PCON 900 and any ACM coupled to connector 1050. The power supply may be of the switching variety well known in the art that receives electrical energy from an AC source 989, such as a wall outlet. Power supply 930 reduces the alternating current input voltage, to a number of distinct outputs of differing voltages and current capacities. The outputs of power supply 930 are applied to power bus 931. Power bus 931 distributes the power supply outputs to the other circuitry within the PCON 900. Bus 931 also connects to certain pins of connector 1050 to provide the electrical power 1014 for an ACM conveyed by ACM-to-PCON interconnection 1000. The isolation of the usually heavy power supply 930 from the core computing power and user environment contained within the ACM represents a further advantage of the present invention.

The interface and support component 940 of the PCON functional circuitry 901 of the presently described embodiment comprises peripheral bridge 246, diskette controller 242, IDE controller 948, and signal conveyance paths 941, 943, 944, 945, 947 and 949. Peripheral bridge 946 couples PCI peripheral bus 941 with peripheral busses of other formats such as ISA peripheral bus 945 and others 947. PCI and ISA peripheral busses are industry standards, well known and understood in the art. Other peripheral busses 947 may include, for example, a bus compliant with the universal serial bus (USB) industry standard. While other embodiments of a peripheral console 900 may include a single peripheral bus that is coupled to an attached ACM via ACM-to-PCON interconnection 1000, such as PCI bus 941, this embodiment includes peripheral bridge 946 to establish additional busses 945, 947. The additional busses 945, 947 permit the use of the many low-cost and readily available components compatible with these bus specifications.

Diskette controller 942 interfaces a floppy disk drive 954 with the CPU component 810 of an attached ACM (shown in FIG. 9) so that the CPU may control and use the diskette drive 954 hardware to store and retrieve data. Diskette controller 942 couples to the CPU via a connection to ISA bus 945. Diskette controller 942 connects to the diskette drive 954 via one of device cables 943.

Similarly, IDE controller 948 interfaces a hard disk drive 952 and a CDROM drive 956 with the CPU component 810 of an attached ACM (shown in FIG. 9) so that the CPU may control and use the hard disk drive 952 and CDROM 956 hardware to store and retrieve data. IDE controller 948 couples to the CPU via connection to PCI peripheral bus 941. IDE controller 948 connects to each of hard disk drive 952 and CD-ROM drive 956 via one of device cables 943. Some embodiments of PCON 900 may take advantage of VLSI integrated circuits such as an 82371SB (PIIX4) integrated circuit from Intel Corporation. An 82371SB integrated circuit includes circuitry for both the peripheral bridge 946 and the IDE controller 948 in a single package.

The secondary mass storage component 950 of the PCON functional circuitry 901 of the presently described embodiment comprises diskette drive 954, hard disk drive 952, and CD-ROM drive 956. Secondary mass storage 950 generally provides low-cost, non-volatile storage for data files which may include software program files. Data files stored on secondary mass storage 950 are not part of a computer user's core computing power and environment. Secondary mass storage 950 may be used to store, for example, seldom used software programs, software programs that are used only with companion hardware devices installed in the same peripheral console 900, or archival copies of data files that are maintained in primary mass storage 850 of an ACM (shown in FIG. 9). Storage capacities for secondary mass storage 950 devices may vary from the 1.44 megabytes of the 3.5-inch high density diskette drive 954, to more than 10 gigabytes for a large format (5-inch) hard disk drive 952. Hard disk drive 952 employs fixed recording media, while diskette drive 954 and CD-ROM drive 956 employ removable media. Diskette drive 954 and hard disk drive 952 support both read and write operations (i.e., data stored on their recording media may be both recalled and modified) while CD-ROM drive 956 supports only read operations.

The other devices component 960 of the PCON functional circuitry 901 of the presently described embodiment comprises a video capture card. A video capture card accepts analog television signals, such as those complying with the NTSC standard used for television broadcast in the United States, and digitizes picture frames represented by the analog signal for processing by the computer. Video capture cards at present are considered a specialty, i.e., not ubiquitous, component of personal computer systems. Digitized picture information from video capture card 960 is carried via signal conveyance path 944 to the peripheral interface controller 1040 which transforms it to the video port signals 1017 of the ACM-to-PCON interconnection 1000 for coupling to the advanced graphics processor 852 in an attached ACM (shown in FIG. 9).

Video capture card 960 is merely representative of the many types of “other” devices that may be installed in a PCON to expand the capabilities of the personal computer. Sound cards and laboratory data acquisition cards are other examples. Video capture card 960 is shown installed in one of expansion slots 970 for coupling to the interface and control circuitry 940 of the PCON. Any of other devices 960 could be coupled to the interface and control circuitry 940 of the PCON by different means, such as direct installation on the circuit board that includes the interface and control circuitry 940; e.g., a motherboard.

The expansion slots component 970 of the PCON functional circuitry 901 of the presently described embodiment comprises PCI connectors 971 and ISA connectors 972. A circuit card may be inserted into one of the connectors 971, 972 in order to be operatively coupled with the CPU 1010 of an attached ACM (shown in FIG. 9). Each of connectors 971 electrically connects to PCI bus 941, and may receive and hold a printed circuit card which it electrically couples to PCI bus 941. Each of connectors 972 electrically connects to ISA bus 945, and may receive and hold a printed circuit card which it electrically couples to ISA bus 945. The PCI 941 and ISA 945 busses couple to the CPU 1010 of an attached ACM (shown in FIG. 9) by circuitry already described.

Embodiments in accordance with the present invention may interface two PCI or PCI-like buses using a non-PCI or non-PCI-like channel. In accordance with embodiments of the present invention, PCI control signals are encoded into control bits and the control bits, rather than the control signals that they represent, are transmitted on the interface channel. At the receiving end, the control bits representing control signals are decoded back into PCI control signals prior to being transmitted to the intended PCI bus.

The fact that control bits rather than control signals are transmitted on the interface channel allows using a smaller number of signal channels and a correspondingly small number of conductive lines in the interface channel than would otherwise be possible. This is because the control bits can be more easily multiplexed at one end of the interface channel and recovered at the other end than control signals. This relatively small number of signal channels used in the interface channel allows using LVDS channels for the interface. As mentioned above, an LVDS channel is more cable friendly, faster, consumes less power, and generates less noise than a PCI bus channel, which is used in the prior art to interface two PCI buses. Therefore, the present invention advantageously uses an LVDS channel for the hereto unused purpose of interfacing PCI or PCI-like buses. The relatively smaller number of signal channels in the interface also allows using connectors having smaller pins counts. As mentioned above an interface having a smaller number of signal channels and, therefore, a smaller number of conductive lines is less bulky and less expensive than one having a larger number of signal channels. Similarly, connectors having a smaller number of pins are also less expensive and less bulky than connectors having a larger number of pins.

In a preferred embodiment, the interface channel has a plurality of serial bit channels numbering fewer than the number of parallel bus lines in each of the PCI buses and operates at a clock speed higher than the clock speed at which any of the bus lines operates. More specifically, the interface channel includes two sets of unidirectional serial bit channels which transmit data in opposite directions such that one set of bit channels transmits serial bits from the HIC to the PIC while the other set transmits serial bits from the PIC to the HIC. For each cycle of the PCI clock, each bit channel of the interface channel transmits a packet of serial bits.

FIG. 11 is a block diagram of one embodiment of a computer system 1100 using the interface of the present invention. Computer system 1100 includes an attached computer module (ACM) 1105 and a peripheral console 1110. The ACM 1105 and the peripheral console 1110 are interfaced through an exchange interface system (XIS) bus 1115. The XIS bus 1115 includes power bus 1116, video bus 1117 and peripheral bus (XPBus) 1118, which is also herein referred to as an interface channel. The power bus 1116 transmits power between ACM 1105 and peripheral console 1110. In a preferred embodiment power bus 1116 transmits power at voltage levels of 3.3 volts, 5 volts and 12 volts. Video bus 1117 transmits video signals between the ACM 1105 and the peripheral console 1110. In a preferred embodiment, the video bus 1117 transmits analog Red Green Blue (RGB) video signals for color monitors, digital video signals (such as Video Electronics Standards Association (VESA) Plug and Display's Transition Minimized Differential Signaling (TMDS) signals for flat panel displays), and television (TV) and/or super video (S-video) signals. The XPBus 1118 is coupled to host interface controller (HIC) 1119 and to peripheral interface controller (PIC) 1120, which is also sometimes referred to as a bay interface controller.

FIG. 12 is a detailed block diagram of one embodiment of the host interface controller (HIC) of the present invention. As shown in FIG. 12, HIC 1200 comprises bus controller 1210, translator 1220, transmitter 1230, receiver 1240, a PLL 1250, an address/data multiplexer (A/D MUX) 1260, a read/write controller (RD/WR Cntl) 1270, a video serial to parallel converter 1280 and a CPU control & general purpose input/output latch/driver (CPU CNTL & GPIO latch/driver) 1290.

HIC 1200 is coupled to an optional flash memory BIOS configuration unit 1201. Flash memory unit 1201 stores basic input output system (BIOS) and PCI configuration information and supplies the BIOS and PCI configuration information to A/D MUX 1260 and RD/WR Control 1270, which control the programming, read, and write of flash memory unit 1201.

Bus controller 1210 is coupled to the host PCI bus, which is also referred to herein as the primary PCI bus, and manages PCI bus transactions on the host PCI bus. Bus controller 1210 includes a slave (target) unit 1211 and a master unit 1216. Both slave unit 1211 and master unit 1216 each include two first in first out (FIFO) buffers, which are preferably asynchronous with respect to each other since the input and output of the two FIFOs in the master unit 1216 as well as the two FIFOs in the slave unit 1211 are clocked by different clocks, namely the PCI clock and the PCK. Additionally, slave unit 1211 includes encoder 1222 and decoder 1223, while master unit 1216 includes encoder 1227 and decoder 1228. The FIFOs 1212, 1213, 1217 and 1218 manage data transfers between the host PCI bus and the XPBus, which in the embodiment shown in FIG. 12 operate at 33 MHz and 66 MHz, respectively. PCI address/data (AD) from the host PCI bus is entered into FIFOs 1212 and 1217 before they are encoded by encoders 1222 and 1223. Encoders 1222 and 1223 format the PCI address/data bits to a form more suitable for parallel to serial conversion prior to transmittal on the XPBus. Similarly, address and data information from the receivers is decoded by decoders 1223 and 1228 to a form more suitable for transmission on the host PCI bus. Thereafter the decoded data and address information is passed through FIFOs 1213 and 1218 prior to being transferred to the host PCI bus. FIFOs 1212, 1213, 1217 and 1218, allow bus controller 1210 to handle posted and delayed PCI transactions and to provide deep buffering to store PCI transactions.

Bus controller 1210 also comprises slave read/write control (RD/WR Cntl) 1214 and master read/write control (RD/WR Cntl) 1215. RD/WR controls 1214 and 1215 are involved in the transfer of PCI control signals between bus controller 1210 and the host PCI bus.

Bus controller 1210 is coupled to translator 1220. Translator 1220 comprises encoders 1222 and 1227, decoders 1223 and 1228, control decoder & separate data path unit 1224 and control encoder & merge data path unit 1225. As discussed above encoders 1222 and 1227 are part of slave data unit 1211 and master data unit 1216, respectively, receive PCI address and data information from FIFOs 1212 and 1217, respectively, and encode the PCI address and data information into a form more suitable for parallel to serial conversion prior to transmittal on the XPBus. Similarly, decoders 1223 and 1228 are part of slave data unit 1211 and master data unit 1216, respectively, and format address and data information from receiver 1240 into a form more suitable for transmission on the host PCI bus. Control encoder & merge data path unit 1225 receives PCI control signals from the slave RD/WR control 1214 and master RD/WR control 1215. Additionally, control encoder & merge data path unit 1225 receives control signals from CPU CNTL & GPIO latch/driver 1290, which is coupled to the CPU and north bridge (not shown in FIG. 12). Control encoder & merge data path unit 1225 encodes PCI control signals as well as CPU control signals and north bridge signals into control bits, merges these encoded control bits and transmits the merged control bits to transmitter 1230, which then transmits the control bits on the data lines PD0 to PD3 and control line PCN of the XPBus. Examples of control signals include PCI control signals and CPU control signals. A specific example of a control signal is FRAME# used in PCI buses. A control bit, on the other hand is a data bit that represents a control signal. Control decoder & separate data path unit 1224 receives control bits from receiver 1240 which receives control bits on data lines PDR0 to PDR3 and control line PCNR of the XPBus. Control decoder & separate data path unit 1224 separates the control bits it receives from receiver 1240 into PCI control signals, CPU control signals and north bridge signals, and decodes the control bits into PCI control signals, CPU control signals, and north bridge signals all of which meet the relevant timing constraints.

Transmitter 1230 receives multiplexed parallel address/data (A/D) bits and control bits from translator 1220 on the AD[31::0] out and the CNTL out lines, respectively. Transmitter 1230 also receives a clock signal from PLL 1250. PLL 1250 takes a reference input clock and generates PCK that drives the XPBus. PCK is asynchronous with the PCI clock signal and operates at 66 MHz, twice the speed of the PCI clock of 33 MHz. The higher speed is intended to accommodate at least some possible increases in the operating speed of future PCI buses. As a result of the higher speed, the XPBus may be used to interface two PCI or PCI-like buses operating at 66 MHz rather than 33 MHz or having 64 rather than 32 multiplexed address/data lines.

The multiplexed parallel A/D bits and some control bits input to transmitter 1230 are serialized by parallel to serial converters 1232 of transmitter 1230 into 10 bit packets. These bit packets are then output on data lines PD0 to PD3 of the XPBus. Other control bits are serialized by parallel to serial converter 1233 into 10 bit packets and send out on control line PCN of the XPBus.

The XPBus lines, PD0 to PD3, PCN, PDR0 to PDR3 and PCNR, and the video data and clock lines, VPD and VPCK, are not limited to being LVDS lines, as they may be other forms of bit based lines. For example, in another embodiment, the XPBus lines may be IEEE 1394 lines.

It is to be noted that although each of the lines PCK, PD0 to PD3, PCN, PCKR, PDR0 to PDR3, PCNR, VPCK, and VPD is referred to as a line, in the singular rather than plural, each such line may contain more than one physical line. For example, in the embodiment shown in FIG. 14, each of lines PCK, PD0 to PD3 and PCN includes two physical lines between each driver and its corresponding receiver. The term line, when not directly preceded by the terms physical or conductive, is herein used interchangeably with a signal or bit channel which may consist of one or more physical lines for transmitting a signal. In the case of non-differential signal lines, generally only one physical line is used to transmit one signal. However, in the case of differential signal lines, a pair of physical lines is used to transmit one signal. For example, a bit line or bit channel in an LVDS or IEEE 1394 interface consists of a pair of physical lines which together transmit a signal.

A bit based line (i.e., a bit line) is a line for transmitting serial bits. Bit based lines typically transmit bit packets and use a serial data packet protocol. Examples of bit lines include an LVDS line, an IEEE 1394 line, and a Universal Serial Bus (USB) line.

It is to be noted that although each of the lines PCK, PD0 to PD3, PCN, PCKR, PDR0 to PDR3, PCNR, VPCK, and VPD is referred to as a line, in the singular rather than plural, each such line may contain more than one physical line. For example, in the embodiment of FIG. 14, each of lines PCK, PD0 to PD3 and PCN includes two physical lines between each driver and its corresponding receiver. The term line, when not directly preceded by the terms physical or conductive, is herein used interchangeably with a signal or bit channel which may consist of one or more physical lines for transmitting a signal. In the case of non-differential signal lines, generally only one physical line is used to transmit one signal. However, in the case of differential signal lines, a pair of physical lines is used to transmit one signal. For example, a bit line or bit channel in an LVDS or IEEE 1394 interface consists of a pair of physical lines which together transmit a signal.

FIG. 13 is a detailed block diagram of one embodiment of the PIC of the present invention. PIC 1300 is nearly identical to HIC 1200 in its function, except that HIC 1200 interfaces the host PCI bus to the XPBus while PIC 1300 interfaces the secondary PCI bus to the XPBus. Similarly, the components in PIC 1300 serve the same function as their corresponding components in HIC 1200. Reference numbers for components in PIC 1300 have been selected such that a component in PIC 1300 and its corresponding component in HIC 1200 have reference numbers that differ by 100 and have the same two least significant digits. Thus for example, the bus controller in PIC 1300 is referenced as bus controller 1310 while the bus controller in HIC 1200 is referenced as bus controller 1210. As many of the elements in PIC 1300 serve the same functions as those served by their corresponding elements in HIC 1200 and as the functions of the corresponding elements in HIC 1200 have been described in detail above, the function of elements of PIC 1300 having corresponding elements in HIC 1200 will not be further described herein. Reference may be made to the above description of FIG. 12 for an understanding of the functions of the elements of PIC 1300 having corresponding elements in HIC 1200.

As suggested above, there are also differences between HIC 1200 and PIC 1300. Some of the differences between HIC 1200 and PIC 1300 include the following. First, receiver 1340 in PIC 1300, unlike receiver 1240 in HIC 1200, does not contain a synchronization unit. As mentioned above, the synchronization unit in HIC 1200 synchronizes the PCKR clock to the PCK clock locally generated by PLL 1250. PIC 1300 does not locally generate a PCK clock and therefore, it does not have a locally generated PCK clock with which to synchronize the PCK clock signal that it receives from HIC 1200. Another difference between PIC 1300 and HIC 1200 is the fact that PIC 1300 contains a video parallel to serial converter 1389 whereas HIC 1200 contains a video serial to parallel converter 1280. Video parallel to serial converter 1389 receives 16 bit parallel video capture data and video control signals on the Video Port Data [0::15] and Video Port Control lines, respectively, from the video capture circuit (not shown in FIG. 11) and converts them to a serial video data stream that is transmitted on the VPD line to the HIC. The video capture circuit may be any type of video capture circuit that outputs a 16 bit parallel video capture data and video control signals. Another difference lies in the fact that PIC 1300, unlike HIC 1200, contains a clock doubler 1382 to double the video clock rate of the video clock signal that it receives. The doubled video clock rate is fed into video parallel to serial converter 1382 through buffer 1383 and is sent to serial to parallel converter 1280 through buffer 1384. Additionally, reset control unit 1335 in PIC 1300 receives a reset signal from the CPU CNTL & GPIO latch/driver unit 13190 and transmits the reset signal on the RESET# line to the HIC 1200 whereas reset control unit 1245 of HIC 600 receives the reset signal and forwards it to its CPU CNTL & GPIO latch/driver unit 1290 because, in the above embodiment, the reset signal RESET# is unidirectionally sent from the PIC 1300 to the HIC 1200.

Like HIC 1200, PIC 1300 handles the PCI bus control signals and control bits from the XPBus representing PCI control signals in the following ways:

1. PIC 1300 buffers clocked control signals from the secondary PCI bus, encodes them and sends the encoded control bits to the XPBus;

2. PIC 1300 manages the signal locally; and

3. PIC 1300 receives control bits from XPBus, translates them into PCI control signals and sends the PCI control signals to the secondary PCI bus.

PIC 1300 also supports a reference arbiter on the secondary PCI Bus to manage the PCI signals REQ# and GNT#.

The XPBus which includes lines PCK, PD0 to PD3, PCN, PCKR, PDR0 to PDR3, and PCNR, has two sets of unidirectional lines transmitting clock signals and bits in opposite directions. The first set of unidirectional lines includes PCK, PD0 to PD3, and PCN. The second set of unidirectional lines includes PCKR, PDR0 to PDR3, and PCNR. Each of these unidirectional set of lines is a point-to-point bus with a fixed transmitter and receiver, or in other words a fixed master and slave bus. For the first set of unidirectional lines, the HIC is a fixed transmitter/master whereas the PIC is a fixed receiver/slave. For the second set of unidirectional lines, the PIC is a fixed transmitter/master whereas the HIC is a fixed receiver/slave. The LVDS lines of XPBus, a cable friendly and remote system I/O bus, transmit fixed length data packets within a clock cycle.

FIG. 14 is a schematic diagram of lines PCK, PD0 to PD3, and PCN. These lines are unidirectional LVDS lines for transmitting clock signals and bits from the HIC to the PIC. The bits on the PD0 to PD3 and the PCN lines are sent synchronously within every clock cycle of the PCK. Another set of lines, namely PCKR, PDR0 to PDR3, and PCNR, are used to transmit clock signals and bits from the PIC to HIC. The lines used for transmitting information from the PIC to the HIC have the same structure as those shown in FIG. 14, except that they transmit data in a direction opposite to that in which the lines shown in FIG. 14 transmit data. In other words they transmit information from the PIC to the HIC. The bits on the PDR0 to PDR3 and the PCNR lines are sent synchronously within every clock cycle of the PCKR. Some of the examples of control information that may be sent in the reverse direction, i.e., on PCNR line, include a request to switch data bus direction because of a pending operation (such as read data available), a control signal change in the target requiring communication in the reverse direction, target busy, and transmission error detected.

The XPBus which includes lines PCK, PD0 to PD3, PCN, PCKR, PDR0 to PDR3, and PCNR, has two sets of unidirectional lines transmitting clock signals and bits in opposite directions. The first set of unidirectional lines includes PCK, PD0 to PD3, and PCN. The second set of unidirectional lines includes PCKR, PDR0 to PDR3, and PCNR. Each of these unidirectional set of lines is a point-to-point bus with a fixed transmitter and receiver, or in other words a fixed master and slave bus. For the first set of unidirectional lines, the HIC is a fixed transmitter/master whereas the PIC is a fixed receiver/slave. For the second set of unidirectional lines, the PIC is a fixed transmitter/master whereas the HIC is a fixed receiver/slave. The LVDS lines of XPBus, a cable friendly and remote system I/O bus, transmit fixed length data packets within a clock cycle.

FIG. 15 is a block diagram of another embodiment of the HIC and PIC of the present invention and the interface therebetween. One important difference between the XPBuses shown in FIGS. 12 and 15 is the fact that unlike the XPBus of FIG. 12, the XPBus of FIG. 15 does not have control lines PCN and PCNR. Another difference lies in the fact that the XPBus of FIG. 15 has two dedicated reset lines RSTEH# and RSTEP# instead of only one as is the case for the XPBus of FIG. 12. RSTEH# and RSTEP# are unidirectional reset and error condition signal lines that transmit a reset and error condition signal from the host PCI to the peripheral PCI and from the peripheral PCI to host PCI, respectively.

In one embodiment, each of reset lines RSTEH#, RSTEP#, and RESET# (shown in FIG. 12), is preferably a non-differential signal line consisting of one physical line. In other embodiments, one or more of the above lines may be a differential signal line having more than one physical line.

FIG. 16 shows a detailed block diagrams of the HIC shown in FIG. 15. HIC 1600 shown in FIG. 16 is, other than for a few difference, identical to HIC 1200 shown in FIG. 12. Accordingly, reference numbers for components in HIC 1600 have been selected such that a component in HIC 1600 and its corresponding component in HIC 1200 have reference numbers that differ by 400 and have the same two least significant digits. One of the differences between HIC 1600 and HIC 1200 is the fact that, unlike HIC 1200, HIC 1600 does not have a parallel to serial converter or a serial to parallel converter dedicated exclusively to CNTL out and CNTL in signals, respectively. This is due to the fact that XPBus for HIC 1600 does not contain a PCN or PCNR line. Another important difference between HIC 1600 and HIC 1200 is the fact that HIC 1600, unlike HIC 1200, has two reset lines, RSTEP# and RSTEH#, instead of only one reset line. Reset line RSTEP# is coupled to Reset & XPBus Parity Error Control Unit 1636 which receives, on the reset line RSTEP#, a reset signal and a parity error signal generated by the PIC, sends a reset signal to the CPU CNTL & GPIO latch/driver 1690, and controls retransmission of bits from the parallel to serial converters 1632. Reset & XPBus Parity Error Detection and Control Unit 1446 takes bits from serial to parallel converters 1642, performs a parity check to detect any transmission error, and sends reset and parity error signals to the PIC on the reset line RSTEH#. The reset and parity error signals may be distinguished by different signal patterns and/or different signal durations. In the two reset line system, the reset and error parity signals are transmitted on the same line and it is possible to send a parity error confirmation signal on one line while receiving a reset signal on the other line. Because HIC 1600 provides for parity error detection, the parallel to serial converters 1632 include buffers. The buffers in parallel to serial converters 1632 store previously transmitted bits (e.g., those transmitted within the previous two clock cycles) for retransmission if transmission error is detected and a parity error signal is received on line RSTEP#. It is to be noted that parallel to serial converters 1232 do not contain buffers such as those contained in parallel to serial converters 1632 for purposes of retransmission since HIC 1200 does not provide for parity error signal detection. Yet another difference between HIC 1200 and HIC 1600 is the fact that in HIC 1600 clock multipliers 1631 and 1641 multiply the PCK and PCKR clocks, respectively, by a factor of 6 rather than 10 because the XPBus coupled to HIC 1600 transmits six bit packets instead of ten bit packets during each XPBus clock cycle. Sending a smaller number of bits per XPBus clock cycle provides the benefit of improving synchronization between the data latching clock output by clock multipliers 1631 and 1641 and the XPBus clocks, PCK and PCKR. In another embodiment, one may send 5 or some other number of bits per XPBus clock cycle. As mentioned above, the remaining elements in HIC 1600 are identical to those in HIC 1200 and reference to the description of the elements in HIC 1200 may be made to understand the function of the corresponding elements in HIC 1600.

FIG. 17 is a schematic diagram of the lines PCK and PD0 to PD3. These lines are unidirectional LVDS lines for transmitting signals from HIC 1600 to the PIC of FIG. 15. Another set of lines, namely PCKR and PDR0 to PDR3, are used to transmit clock signals and bits from the PIC to HIC 1600.

In the embodiment shown in FIG. 11, HIC 1119 is coupled to an integrated unit 1121 that includes a CPU, a cache and a north bridge. In yet another embodiment, such as that shown in FIG. 18, the HIC and PIC are integrated with the north and south bridges, respectively, such that integrated HIC and north bridge unit 1805 includes an HIC and a north bridge, while integrated PIC and south bridge unit 1810 includes a PIC and a south bridge.

The above embodiments are described generally in terms of hardware and software. It will be recognized, however, that the functionality of the hardware can be further combined or even separated. The functionality of the software can also be further combined or even separated. Hardware can be replaced, at times, with software. Software can be replaced, at times, with hardware. Accordingly, the present embodiments should not be construed as limiting the scope of the claims here. One of ordinary skill in the art would recognize other variations, modifications, and alternatives.

While the above is a full description of the specific embodiments, various modifications, alternative constructions and equivalents may be used. Therefore, the above description and illustrations should not be taken as limiting the scope of the present invention which is defined by the appended claims.

Citas de patentes
Patente citada Fecha de presentación Fecha de publicación Solicitante Título
US399658522 Ene 19767 Dic 1976International Business Machines CorporationVideo generator circuit for a dynamic digital television display
US414106824 Mar 197720 Feb 1979Xerox CorporationAuxiliary ROM memory system
US42284967 Sep 197614 Oct 1980Tandem Computers IncorporatedMultiprocessor system
US44532151 Oct 19815 Jun 1984Stratus Computer, Inc.Central processing apparatus for fault-tolerant computing
US462396422 Dic 198218 Nov 1986International Business Machines CorporationHomogeneous hierarchial computer business system
US467083725 Jun 19842 Jun 1987American Telephone And Telegraph CompanyElectrical system having variable-frequency clock
US468067416 Jul 198414 Jul 1987Moore Fergus EModular computer system with integral electronic bus
US470036221 Ago 198413 Oct 1987Dolby Laboratories Licensing CorporationA-D encoder and D-A decoder system
US47602769 Nov 198726 Jul 1988Unisys CorporationPower supply system, for segmented loads, having phantom redundancy
US476976411 Ago 19866 Sep 1988Isaac LevanonModular computer system with portable travel unit
US479152418 Nov 198713 Dic 1988International Business Machines CorporationElectrostatic discharge protection for electronic packages
US47992587 Feb 198517 Ene 1989National Research Development CorporationApparatus and methods for granting access to computers
US487209115 Jul 19873 Oct 1989Ricoh Company, Ltd.Memory cartridge
US48902828 Mar 198826 Dic 1989Network Equipment Technologies, Inc.Mixed mode compression for data transmission
US491857227 Dic 198817 Abr 1990Motorola Computer X, Inc.Modular electronic package
US493973521 Jul 19883 Jul 1990International Business Machines CorporationInformation handling system having serial channel to control unit link
US505614118 Jun 19868 Oct 1991Dyke David WMethod and apparatus for the identification of personnel
US508649923 May 19894 Feb 1992Aeg Westinghouse Transportation Systems, Inc.Computer network for real time control with automatic fault identification and by-pass
US51034469 Nov 19907 Abr 1992Moses Computers, Inc.Local area network adaptive throughput control for instantaneously matching data transfer rates between personal computer nodes
US51876457 Jun 199116 Feb 1993Ergo Computing, Inc.Portable computer with docking connector for peripheral devices
US51915817 Dic 19902 Mar 1993Digital Equipment CorporationMethod and apparatus for providing high performance interconnection between interface circuits coupled to information buses
US525109711 Jun 19905 Oct 1993Supercomputer Systems Limited PartnershipPackaging architecture for a highly parallel multiprocessor system
US52785093 Feb 199211 Ene 1994At&T Bell LaboratoriesMethod for monitoring battery discharge by determining the second derivative of battery voltage over time
US527873026 Jul 199311 Ene 1994Cordata, Inc.Modular notebook computer having a planar array of module bays
US528224712 Nov 199225 Ene 1994Maxtor CorporationApparatus and method for providing data security in a computer system having removable memory
US529348727 Dic 19918 Mar 1994Digital Equipment CorporationNetwork adapter with high throughput data transfer circuit to optimize network data transfers, with host receive ring resource monitoring and reporting
US529349715 Abr 19938 Mar 1994Traveling Software, Inc.Cable for transmitting eight-bit parallel data
US53113976 Ago 199210 May 1994Logistics Management Inc.Computer with modules readily replaceable by unskilled personnel
US531744121 Oct 199131 May 1994Advanced Micro Devices, Inc.Transceiver for full duplex signalling on a fiber optic cable
US531747730 Jun 199231 May 1994International Business Machines CorporationHigh density interconnection assembly
US531977126 Abr 19937 Jun 1994Seiko Epson CorporationCPU clock generator having a low frequency output during I/O operations and a high frequency output during memory operations
US532551717 May 198928 Jun 1994International Business Machines CorporationFault tolerant data processing system
US533150918 Nov 199319 Jul 1994Cordata, Inc.Modular notebook computer having a planar array of module bays and a pivotally attached flat-panel display
US533940830 Dic 199216 Ago 1994Digital Equipment CorporationMethod and apparatus for reducing checking costs in fault tolerant processors
US53553916 Mar 199211 Oct 1994Rambus, Inc.High speed bus system
US542880622 Ene 199327 Jun 1995Pocrass; Alan L.Computer networking system including central chassis with processor and input/output modules, remote transceivers, and communication links between the transceivers and input/output modules
US543060731 Dic 19924 Jul 1995North Atlantic Industries, Inc.Rugged modular portable computer including modules hinged along an edge
US543293927 May 199211 Jul 1995International Business Machines Corp.Trusted personal computer system with management control over initial program loading
US543685722 Nov 199325 Jul 1995Ncr CorporationPersonal computer module system and method of using
US54369025 Abr 199425 Jul 1995First Pacific NetworksEthernet extender
US54637425 Mar 199331 Oct 1995Hitachi Computer Products (America), Inc.Personal processor module and docking station for use therewith
US551984315 Mar 199321 May 1996M-SystemsFlash memory system providing both BIOS and user storage capability
US553312518 Jul 19952 Jul 1996International Business Machines CorporationRemovable computer security device
US553754416 Ago 199316 Jul 1996Kabushiki Kaisha ToshibaPortable computer system having password control means for holding one or more passwords such that the passwords are unreadable by direct access from a main processor
US5539616 *29 Nov 199323 Jul 1996Elonex Technologies, Inc.Modular portable computer
US554646312 Jul 199413 Ago 1996Information Resource Engineering, Inc.Pocket encrypting and authenticating communications device
US55507109 Sep 199427 Ago 1996Hitachi Computer Products (America), Inc.Computer system module
US555086128 Oct 199427 Ago 1996Novalink Technologies, Inc.Modular PCMCIA modem and pager
US555277624 Jun 19943 Sep 1996Z-MicrosystemsEnhanced security system for computing devices
US55724414 Abr 19945 Nov 1996Lucent Technologies Inc.Data connector for portable devices
US557720521 Abr 199519 Nov 1996Ht Research, Inc.Chassis for a multiple computer system
US55789404 Abr 199526 Nov 1996Rambus, Inc.Modular bus with single or double parallel termination
US55888508 Ago 199531 Dic 1996Tongrand LimitedGrounding means for memory card connector
US5590377 *7 Jun 199531 Dic 1996Ast Research, Inc.Automatic control of distributed DMAs in a PCI bus system supporting dual ISA buses
US560080019 Jul 19944 Feb 1997Elonex I.P. Holdings, Ltd.Personal computer system having a docking bay and a hand-held portable computer adapted to dock in the docking bay by a full-service parallel bus
US56030448 Feb 199511 Feb 1997International Business Machines CorporationInterconnection network for a multi-nodal data processing system which exhibits incremental scalability
US56067175 Mar 199225 Feb 1997Rambus, Inc.Memory circuitry having bus interface for receiving information in packets and access time registers
US5608608 *17 Abr 19964 Mar 1997International Business Machines CorporationCartridge-based design for portable and fixed computers
US562363717 May 199622 Abr 1997Telequip CorporationEncrypted data storage card including smartcard integrated circuit for storing an access password and encryption keys
US56300571 Jul 199613 May 1997Progressive Technology Inc.Secure architecture and apparatus using an independent computer cartridge
US56385215 Feb 199610 Jun 1997Leunig GmbhApparatus using a parallel interface for data transfer between a plurality of computers, as well as for transfer of data from computers to shared peripheral devices
US564030211 Mar 199617 Jun 1997Elonex Ip HoldingsModular portable computer
US5648762 *1 Feb 199515 Jul 1997Canon Kabushiki KaishaBuilt-in electronic apparatus and device-detaching method therefor
US565977314 Nov 199019 Ago 1997International Business Machines CorporationPersonal computer with input/output subsystem
US566366112 Jul 19962 Sep 1997Rambus, Inc.Modular bus with single or double parallel termination
US56731725 Ene 199630 Sep 1997Compaq Computer CorporationApparatus for electromagnetic interference and electrostatic discharge shielding of hot plug-connected hard disk drives
US567317423 Mar 199530 Sep 1997Nexar Technologies, Inc.Computer having means for external replacement of circuit boards
US568012623 Ago 199421 Oct 1997Elonex I.P. Holdings, Ltd.Modular portable computer
US568053629 Nov 199521 Oct 1997Tyuluman; Samuel A.Dual motherboard computer system
US56896547 Nov 199418 Nov 1997Elonex F.P. Holdings, Ltd.Digital assistant system including a host computer with a docking bay for the digital assistant wherein a heat sink is moved into contact with a docked digital assistant for cooling the digital assistant
US57088404 Mar 199613 Ene 1998Elonex I.P. Holdings, Ltd.Scanning and image capturing system
US572183715 Oct 199624 Feb 1998Elonex I.P. Holdings, Ltd.Micro-personal digital assistant including a temperature managed CPU
US572184225 Ago 199524 Feb 1998Apex Pc Solutions, Inc.Interconnection system for viewing and controlling remotely connected computers with on-screen video overlay for controlling of the interconnection switch
US572459126 Ene 19963 Mar 1998Hitachi, Ltd.Multiprocessor system with reduced power mode and improved variation of power demand
US573719429 Jul 19967 Abr 1998Cray Research, Inc.Input/output module assembly
US573752422 May 19957 Abr 1998International Business Machines CorporationAdd-in board with programmable configuration registers for use in PCI bus computers
US57457339 Ago 199528 Abr 1998Ncr CorporationComputer system including a portable portion and a stationary portion providing both uni-processing and multiprocessing capabilities
US5751711 *26 Mar 199612 May 1998Kabushiki Kaisha ToshibaDigital information processing device
US575208022 Dic 199412 May 1998Intel CorporationCable terminal unit using bit set for selectively enabling a plurality of hardware functions with some functions having a plurality of selectively enabled hardware functions
US576492424 Ago 19959 Jun 1998Ncr CorporationMethod and apparatus for extending a local PCI bus to a remote I/O backplane
US57747035 Ene 199630 Jun 1998Motorola, Inc.Data processing system having a register controllable speed
US577470429 Jul 199630 Jun 1998Silicon Graphics, Inc.In a computer system
US57952283 Jul 199618 Ago 1998Ridefilm CorporationInteractive computer-based entertainment system
US58023914 Oct 19951 Sep 1998Ht Research, Inc.Direct-access team/workgroup server shared by team/workgrouped computers without using a network operating system
US580590321 May 19968 Sep 1998Compaq Computer CorporationProtection of computer system against incorrect card insertion during start-up
US580926230 Ago 199615 Sep 1998Dell U.S.A., L.P.Commonly housed multiple processor type computing system and method of manufacturing the same
US58095387 Feb 199615 Sep 1998General Instrument CorporationDRAM arbiter for video decoder
US581568121 May 199629 Sep 1998Elonex Plc Ltd.Integrated network switching hub and bus structure
US581905029 Feb 19966 Oct 1998The Foxboro CompanyAutomatically configurable multi-purpose distributed control processor card for an industrial control system
US582604831 Ene 199720 Oct 1998Vlsi Technology, Inc.PCI bus with reduced number of signals
US583893230 Jun 199717 Nov 1998Compaq Computer CorporationTransparent PCI to PCI bridge with dynamic memory and I/O map programming
US584824911 Jul 19978 Dic 1998Intel CorporationMethod and apparatus for enabling intelligent I/O subsystems using PCI I/O devices
US5857085 *13 Nov 19965 Ene 1999Cypress Semiconductor CorporationInterface device for XT/AT system devices on high speed local bus
US585966926 Nov 199612 Ene 1999Texas Instruments IncorporatedSystem for encoding an image control signal onto a pixel clock signal
US58623503 Ene 199719 Ene 1999Intel CorporationMethod and mechanism for maintaining integrity within SCSI bus with hot insertion
US586238126 Nov 199619 Ene 1999International Business Machines CorporationVisualization tool for graphically displaying trace data
US587821120 Dic 19962 Mar 1999N C R CorporationMulti-functional retail terminal and associated method
US5884049 *31 Dic 199616 Mar 1999Compaq Computer CorporationIncreased processor performance comparable to a desktop computer from a docked portable computer
US588405311 Jun 199716 Mar 1999International Business Machines CorporationConnector for higher performance PCI with differential signaling
US590756629 May 199725 May 19993Com CorporationContinuous byte-stream encoder/decoder using frequency increase and cyclic redundancy check
US5909559 *4 Abr 19971 Jun 1999Texas Instruments IncorporatedBus bridge device including data bus of first width for a first processor, memory controller, arbiter circuit and second processor having a different second data width
US59301105 Jun 199727 Jul 1999Kabushiki Kaisha ToshibaComputer system having detachable expansion unit
US5933609 *8 Abr 19963 Ago 1999Vlsi Technology, Inc.Method and system for hot docking a portable computer to a docking station via the primary PCI bus
US5935226 *20 Mar 199710 Ago 1999Micron Electronics, Inc.Method and apparatus for issuing transaction requests to a target device in accordance with the state of connection between the portable computer and the target device
US594196512 Jul 199624 Ago 1999Electronics Accessory Specialists International, Inc.Computer system
US594804729 Ago 19967 Sep 1999Xybernaut CorporationDetachable computer structure
US596021311 Dic 199628 Sep 19993D Labs Inc. LtdDynamically reconfigurable multi-function PCI adapter device
US596595710 Jul 199712 Oct 1999Aerospatiale Societe Nationale IndustrielleSwitching apparatus, in particular for systems under test
US596814427 Jun 199619 Oct 1999Vlsi Technology, Inc.System for supporting DMA I/O device using PCI bus and PCI-PCI bridge comprising programmable DMA controller for request arbitration and storing data transfer information
US5974486 *12 Ago 199726 Oct 1999Atmel CorporationUniversal serial bus device controller comprising a FIFO associated with a plurality of endpoints and a memory for storing an identifier of a current endpoint
US5991833 *13 Mar 199823 Nov 1999Compaq Computer CorporationComputer system with bridge logic that reduces interference to CPU cycles during secondary bus transactions
US5999476 *21 Nov 19977 Dic 1999Advanced Micro Devices, Inc.Bios memory and multimedia data storage combination
US6006243 *30 May 199721 Dic 1999International Business Machines CorporationFoldable personal computer with detachable cover section
US6012145 *14 Nov 19944 Ene 2000Calluna Technology LimitedSecurity system for hard disk drive
US6199134 *13 Mar 19986 Mar 2001Compaq Computer CorporationComputer system with bridge logic that asserts a system management interrupt signal when an address is made to a trapped address and which also completes the cycle to the target address
US6226700 *13 Mar 19981 May 2001Compaq Computer CorporationComputer system with bridge logic that includes an internal modular expansion bus and a common master interface for internal master devices
US6301637 *8 Jun 19989 Oct 2001Storage Technology CorporationHigh performance data paths
US6460106 *20 Oct 19981 Oct 2002Compaq Information Technologies Group, L.P.Bus bridge for hot docking in a portable computer system
Otras citas
Referencia
1"Features Chart", (Feb. 1, 1997) >, downloaded from web on Jun. 23, 2004, 3 pgs.
2"SQL Server and NT Cluster Manager Availability Demo," Microsoft Server Programmer Developers Conference, Nov. 1996, 15 pages total.
3"Think Modular", PC Magazine, Jun. 10, 1997, wysiwyg://60/http://homezdnet.com/pcmag/issues/1611/pcmg0072.htm.
4"Acqis LLC's Disclosure of Proposed Terms and Claim Elements for Construction Pursuant to Patent Rule 4-1," Case No. 6:09-cv-00148-LED, filed Mar. 5, 2010, 3 pages.
5"Acqis, LLC's P.R.-4-2 Disclosure of Preliminary Claim Constructions and Extrinsic Evidence," Case No. 6:09-cv-00148-LED, filed Apr. 14, 2010, 10 pages.
6"Affidavit of Timothy P. Cremen in Support of NEC Corporation of America's Opposition to Plaintiff's Motion to Dismiss and Strike," Case No. 6:09-cv-00148-LED, filed Oct. 9, 2009, 4 pages.
7"Amended Joint Claim Construction Statement," Case No. 6:09-cv-00148-LED, filed May 5, 2010, 44 pages.
8"Answer to Plaintiff's Second Amended Complaint and Counterclaims of Defendant Fujitsu Computer Systems Corp., n/k/a/ Fujitsu America, Inc. to Acqis LLC's Second Amended Complaint for Patent Infringement," Case No. 6:09-cv-00148-LED, filed Aug. 10, 2009, 34 pages.
9"Answer, Affirmative Defenses, and Counterclaims of Defendant Hewlett-Packard Company to Acqis LLC's Second Amended Complaint for Patent Infringement," Case No. 6:09-cv-148- LED, filed Aug. 10, 2009, 40 pages.
10"Appendix 6A—Disclosure of Asserted Claims and Infringement Contentions", submitted by the Plaintiff in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED, 14 pages.
11"Astro Sciences Corp. Announces Results for Second Quarter," Astro Sciences Corporation, Press Release, Nov. 17, 1995, 2 pages.
12"Astro Sciences Corp. Signs Agreement With Storage Computer Corp.," Astro Sciences Corporation, Press Release, Nov. 7, 1995, 2 pages.
13"Astro Sciences Corporation Announces Results for the First Quarter of the Fiscal Year," Astro Sciences Corporation, Press Release, Aug. 3, 1995, 1 page.
14"Astro Sciences Corporation Announces Results for the Fourth Quarter and the Fiscal Yeart," Astro Sciences Corporation, News Release, Jun. 26, 1995, 1 page.
15"Astro Sciences Corporation Announces Results for the Third Quarter," Astro Sciences Corporation, Press Release, Feb. 8, 1996, 23 pages.
16"Astro Sciences Corporation Announces Signing of $4 Million Credit Facility With Deutsche Financial Services," Astro Sciences Corporation, News Release, May 19, 1995, 1 page.
17"Astro Sciences Corporation Appoints Interim President/CEO Board Expanded by Two Seats," Astro Sciences Corporation, Press Release, Aug. 17, 1995, 1 page.
18"Astro Sciences Corporation Introduces New Generation of Products at PC Expo Show," Astro Sciences Corporation, Press Release, Jun. 23, 1995, 1 page.
19"Astro Sciences Corporation Receives Patent for Network Security and Management," Astro Sciences Corporation, News Release, Jun. 6, 1995, 2 pages.
20"Astro Sciences Corporation Retains Technology Strategies and Alliance Partners," Astro Sciences Corporation, News Release, Jun. 29, 19951 page.
21"Astro Sciences Corporation Shareholders Elect Two New Directors, and Vote to Change Corporate Name to ChatCom, Inc.," Astro Sciences Corporation, Press Release, Feb. 12, 1996, 2 pages.
22"Astro Sciences Corporation to Strengthen Management Team Board," Astro Sciences Corporation, News Release, Apr. 21, 1995, 1 page.
23"Astro Sciences Receives Microsoft Certification and Announces New Director," Astro Sciences Corporation, Press Release, Nov. 21, 1995, 2 pages.
24"Astro Sciences Shareholders Elect Two New Directors, and Vote to Change Corporate Name to Chatcom, Inc.," Astro Sciences Corporation, Press Release, Feb. 12, 1996, 2 pages.
25"Best of Show 97," LAN Times, undated, 1 page.
26"ChatCom Adds New Senior Management Team Members," ChatCom, Inc., Press Release, Jul. 2, 1996, 1 page.
27"ChatCom Announces Complete Line of Scaleable Application and Communication Servers," ChatCom, Inc., Press Release, Aug. 30, 1996, 4 pages.
28"ChatCom Announces Comprehensive VAR Program, Commitment to VARs is Key to Corporate Strategy," ChatCom, Inc., Press Release, Jan. 13, 1997, 1 page.
29"ChatCom Announces Major Push into International Markets, Significant International Sales Opportunities for ChatCom's Consolidated Server Technology," ChatCom, Inc., Press Release, Mar. 18, 1997, 2 pages.
30"ChatCom Announces Mass Storage Subsystem, ChatRAID to Address Application Server Market," ChatCom, Inc., Press Release, Aug. 12, 1996, 1 page.
31"ChatCom Announces Mass Storage Subsystem, ChatRAID to Address Application Server Market," ChatCom, Inc., Press Release, Aug. 14, 1996, 2 pages.
32"ChatCom Books Additional Orders with Major Facilities-Based Carrier Companies, ChatCom Products Provide Internet Platforms for Carrier's Customers Worldwide," ChatCom, Inc., Press Release, Mar. 12, 1997, 2 pages.
33"ChatCom Defines Specification for Future Consolidated Server Products, RAINS™ Concept to Accelerate the Adoption of Consolidated Servers," ChatCom, Inc., Press Release, Mar. 31, 1997, 2 pages.
34"ChatCom Names James B. Mariner President/CEO," ChatCom, Inc., Press Relase, Mar. 7, 1996, 2 pages.
35"ChatCom Receives Product Award From LAN Times Magazine, Consolidated Server Product Comparison Puts ChatCom on Top," ChatCom, Inc., Press Release, Feb. 17, 1997, 2 pages.
36"ChatCom Receives Product Award From LAN Times Magazine, Consolidated Server Product Comparison Puts ChatCom on Top," ChatCom, Inc., Press Release, Feb. 20, 1997, 2 pages.
37"ChatCom Selected as Partner in Anixter Race '96 Program and Completes First Part of Financing," ChatCom, Inc., Press Release, Mar. 26, 1996, 2 pages.
38"ChatCom Strengthens Sales Management Team, Three New Sales Directors to Address Growing Demand for ChatCom's ChatterBox™," ChatCom, Inc., Press Release, Mar. 18, 1997, 2 pages.
39"ChatCom, Inc. Announces Commitment to ISO 9001 Quality Certification, ISO 9001 Quality Control Programs are High Priority Company Imperative," ChatCom, Inc., Press Release, Aug. 1, 1996, 1 page.
40"ChatCom, Inc. Announces Highly Adaptable Intranet and Web Servers, Servers reduce costs associated with radical change," Press Release, Sep. 3, 1996, 1 page.
41"ChatCom, Inc. Announces PentiumPro/200 MHz Server Module, Server Module Offers Scalability and High Availability for File Server Environments," ChatCom, Inc., Press Release, Mar. 24, 1997, 3 pages.
42"ChatCom, Inc. Announces Results for the Dec. 31, 1996 Quarter," ChatCom, Inc., Press Release, Feb. 12, 1997, 2 pages.
43"ChatCom, Inc. Announces Results for the Jun. 30 Quarter," ChatCom, Inc., News Release, Aug. 16, 1996, 2 pages.
44"ChatCom, Inc. Reports Completion of $2.5 Million Private Placement," ChatCom, Inc., Press Release, Jan. 9, 1997, 2 pages.
45"ChatCom, Inc., (Formerly Astro Sciences Corporation) Trades Under New Symbol—NASDAQ/NMS: CHAT," ChatCom, Inc., News Release, Feb. 22, 1996, 1 page.
46"ChatCom, Inc., Announces Commitment to ISO 9001 Quality Certification, ISO 9001 Quality Control Programs are High Priority Company Imperative," ChatCom, Inc., Press Release, Aug. 1, 1996, 1 page.
47"ChatterBox Communications and Server Solutions Products," ChatCom, Inc., Apr. 24, 1996, 7 pages.
48"ChatterBox Communications and Server Solutions," ChatCom, Inc., Mar. 7, 1996, 12 pages.
49"ChatterBox/SAS™—Scaleable Access Server™," J&L Information Systems, Networks Expo—Boston '96, Dec. 22, 1995, 1 page.
50"Claim Chart for International Business Machines Corp.," Case No. 6:09-cv-00148-LED, filed Jun. 15, 2010, 12 pages.
51"ClusterDirector™ Product Description, Fault Tolerance for Industry Standard Processors, Operating Systems, and Applications," Network Engines, Inc., 1998, 4 pages.
52"Clustered Servers for Network Based Applications," Network Engines, Inc., undated, 27 pages.
53"Comparison [by NEC] of Rejected Elements in Office Action and Elements of Exemplary Claims of Acqis's Patents," Case No. 6:09-cv-00148-LED, filed Oct. 9, 2009, 7 pages.
54"Complaint for Patent Infringement," Acqis v. Appro Int'l, Inc. et al., Case No. 6:09-cv-00148, filed Apr. 2, 2009, 13 pages.
55"Corrected p. 13 of Plaintiff's Opening Brief Concerning Claim Construction (D.I. 261)," Case No. 6:09-cv-00148-LED, filed Jun. 2, 2010, 2 pages.
56"Declaration of Carolyn V. Juarez in Support of Plaintiff Acqis LLC's Opening Brief Regarding Claim Construction," Case No. 6:09-cv-00148-LED, filed Jun. 1, 2010, 3 pages.
57"Declaration of Jennifer Chen in Support of Defendants' Motion for Leave to Amend Defendants' Invalidity Contentions," Case No. 6:09-cv-00148-LED, Aug. 5, 2010, 3 pages.
58"Declaration of Monty McGraw in Support of Defendants' Motion for Leave to Amend Defendants' Invalidity Contentions," Case No. 6:09-cv-00148-LED, Aug. 5, 2010, 3 pages.
59"Defendant Appro's Answer, Affirmative Defenses, and Counterclaims to Acqis LLC's Second Amended Complaint for Patent Infringement," Case No. 6:09-cv-148, filed Aug. 5, 2009, 43 pages.
60"Defendant Clearcube Technology, Inc.'s Answer, Counterclaims to Acqis LLC's First Amended Complaint for Patent Infringement, and Jury Demand," Case No. 6:08-cv-00148, filed Jul. 2, 2009, 28 pages.
61"Defendant Clearcube Technology, Inc.'s Answer, Counterclaims to Acqis LLC's Second Amended Complaint for Patent Infringement, and Jury Demand," Case No. 6:08-cv-00148, filed Aug. 10, 2009, 39 pages.
62"Defendant Clearcube Technology, Inc.'s First Amended Answer, Counterclaims to Acqis LLC's Second Amended Complaint for Patent Infringement and Jury Demand," Case No. 6:09-cv-00148, filed Aug. 11, 2009, 39 pages.
63"Defendant Clearcube Technology, Inc.'s Fourth Amended Answer to Acqis LLC's Second Amended Complaint for Patent Infringement and Jury Demand," Case No. 6:09-cv-00148, filed Jan. 8, 2010, 26 pages.
64"Defendant Clearcube Technology, Inc.'s Second Amended Answer Counterclaims to Acqis LLC's Second Amended Complaint for Patent Infringement and Jury Demand," Case No. 6:09-Cv-00148, filed Aug. 31, 2009, 45 pages.
65"Defendant Clearcube Technology, Inc.'s Third Amended Answer to Acqis LLC's Second Amended Complaint for Patent Infringement and Jury Demand," Case No. 6:09-cv-00148, filed Nov. 11, 2009, 26 pages.
66"Defendant Hitachi Ameirca, Ltd.'s, Answer to Acqis LLC's First Amended Complaint for Patent Infringement, and Affirmative Defenses and Counterclaims," Case No. 6:09-cv-00148-LED, filed Jul. 8, 2009, 22 pages.
67"Defendant International Business Machines Corp.'s Answer to Acqis LLC's First Amended Complaint, Affirmative Defenses, and Counterclaims," Case No. 6:09-cv-148-LED, filed Jul. 8, 2009, 22 pages.
68"Defendant International Business Machines Corp.'s Answer to Acqis LLC's Second Amended Complaint, Affirmative Defenses, and Counterclaims," Case No. 6:09-cv-148-LED, filed Aug. 10, 2009, 28 pages.
69"Defendant NEC Corporation of America's Opposition to Plaintiffs Motion to Dismiss and Motion to Strike," Case No. 6:09-cv-00148-LED, filed Oct. 9, 2010, 36 pages.
70"Defendant Nex Computers Technology, Inc.'s Answer to Acqis LLC's First Amended Complaint for Patent Infringement, and Jury Demand," Case No. 6:09-cv-00148-LED, filed Jul. 8, 2009, 16 pages.
71"Defendant Nex Computers Technology, Inc.'s Answer to Acqis LLC's Second Amended Complaint for Patent Infringement, and Jury Demand," Case No. 6:09-cv-00148-LED, filed Aug. 10, 2009, 28 pages.
72"Defendant Sun Microsystems, Inc.'s Answer and Counterclaims to Acqis LLC's Second Amended Complaint for Patent Infringement," Case No. 6:09-cv-148, filed Aug. 10, 2009, 95 pages.
73"Defendant Sun Microsystems, Inc.'s Responses and Objections to Plaintiff Acqis LLC's Second Set of Common Interrogatories," Case No. 6:09-cv-00148-LED, filed May 12, 2010, 9 pages.
74"Defendant Super Micro Computer, Inc.'s Answer and Counterclaims to Acqis LLC's Second Amended Complaint for Patent Infringement," Case No. 6:09-cv-148, filed Aug. 10, 2009, 96 pages.
75"Defendants' Amended Invalidity Contentions," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 18 pages.
76"Defendant's Amended List of Proposed Terms and Claim Elements for Construction," Case No. 6:09-cv-00148-LED, filed Mar. 31, 2010, 11 pages.
77"Defendant's Brief in Response to Plaintiff's Opening Brief Regarding Claim Construction," Case No. 6:09-cv-00148-LED, filed Jun. 15, 2010, 40 pages.
78"Defendant's Corrected List of Proposed Terms and Claim Elements for Construction," Case No. 6:09-cv-00148-LED, filed Apr. 2, 2010, 9 pages.
79"Defendant's List of Proposed Terms and Claim Elements for Construction," Case No. 6:09-cv-00148-LED, filed Mar. 5, 2010, 15 pages.
80"Defendants' Notice of Errata Relating to Defendants' P.R. 3-3 Invalidity Contentions," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 14 pages.
81"Defendant's P.R.-4-2 Disclosure of Preliminary Claim Constructions and Extrinsic Evidence," Case No. 6:09-cv-00148-LED, filed Apr. 14, 2010, 16 pages.
82"Dell's Answer and Counterclaims to Acqis LLC's Second Amended Complaint," Case No. 6:09-cv-00148-LED, filed Aug. 10, 2009, 36 pages.
83"Dell's First Amended Answer and Counterclaims to Plaintiff's Second Amended Complaint," Case No. 6:09-cv-00148-LED, filed Apr. 22, 2010, 38 pages.
84"Disclosure of Asserted Claims and Infringement Contentions", submitted by the Plaintiff in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED, served on Sep. 14, 2009, 5 pages.
85"Disclosure of Plaintiff's Reduced List of Asserted Claims ," submitted by the Plaintiff in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-00148-LED, served on Jul. 30, 2010, 6 pages.
86"Engineering Design Proposal for RocketLogix, Inc.," Anigma, Inc., Apr. 19, 2000, 35 pages.
87"Enterprise Application Servers," Powerstation Technologies, Inc., undated, 4 pages.
88"Eversys Corporation System 8000 Consolidated Server Peripheral Sharing Switch," Eversys Corporation, undated, 1 page.
89"Exhibit 5—Disclosure of Asserted Claims and Infringement Contentions", submitted by the Plaintiff in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED, 14 pages.
90"Exhibit A (Asserted Claims)," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 2 pages.
91"Exhibit B—Table 1," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 75 pages.
92"Exhibit C," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 2 pages.
93"Exhibit D," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 106 pages.
94"Exhibit E," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 2 pages.
95"Expanding the Reach of the Internet with a New Breed of Web Server Appliances," RocketLogix, Inc., May 2000, 10 pages.
96"Family of VME Technology Specifications," [online], date unknown, [retrieved on Dec. 29, 2010], Retrieved from the Internet: <URL: http://www.vita.com/specifications.html>, 1 page.
97"Features Chart", (Feb. 1, 1997) <<http://www.lantimes.com/testing/97feb/702b072a.html>>, downloaded from web on Jun. 23, 2004, 3 pgs.
98"Final Judgement," Issued by the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2011, 1 page.
99"Firmware Interface Specification,Orbiter 1680, Orbiter 3360," Anigma, Inc., Aug. 17, 2000, 16 pages.
100"First Amended Complaint for Patent Infringement," Acqis v. Appro Int'l, Inc. et al., Case No. 6:09-cv-00148, filed May 18, 2009, 14 pages.
101"GMAC/EDS Case Study," Network Engines, Inc., undated, 1 page.
102"HMU—586 Card Guide (Mustang) Pentium PCI," Issue 0.0.14 Preliminary, HM Systems, Inc., Nov. 18, 1996, 57 pages.
103"IEEE STD 1355-1995 Standard for Heterogeneous InterConnect (HIC)," Open Microprocessor systems Initiative (OMI), [online], Oct. 30, 1998, [retrieved on Aug. 6, 2010], Retrieved from the Internet: <URL: http://grouper.ieee.org/groups/1355/index.html>, 6 pages.
104"Introducing the new ChatterBox™ Corporate and Office Series . . . The Power Behind Your Network," ChatCom, Inc., May 31, 1996, 15 pages.
105"Invalidity Chart for Base Reference ChatCom," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 52 pages.
106"Invalidity Chart for Base Reference Compaq ProLiant Cluster," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 81 pages.
107"Invalidity Chart for Base Reference Cubix Bc/Density," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 64 pages.
108"Invalidity Chart for Base Reference Ergo Moby Brick", submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 5 pages.
109"Invalidity Chart for Base Reference Eversys 8000 System," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 60 pages.
110"Invalidity Chart for Base Reference Eversys CAPserver," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 59 pages.
111"Invalidity Chart for Base Reference Gallagher 068 and Gallagher 503," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 108 pages.
112"Invalidity Chart for Base Reference Hong 737," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 77 pages.
113"Invalidity Chart for Base Reference IBM 8260," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 53 pages.
114"Invalidity Chart for Base Reference IBM 8265," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 56 pages.
115"Invalidity Chart for Base Reference Japanese Patent Application Publication H6-289953 (Hitachi)", submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 5 pages.
116"Invalidity Chart for Base Reference Japanese Patent Application Publication H7-84675 (Hitachi)", submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 5 pages.
117"Invalidity Chart for Base Reference JP6-289956," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 62 pages.
118"Invalidity Chart For Base Reference Network Engines P6000 Server," Jun. 4, 2010, 64 pages.
119"Invalidity Chart for Base Reference Network Engines P6000 Server," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 59 pages.
120"Invalidity Chart for Base Reference Origin2000," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 56 pages.
121"Invalidity Chart for Base Reference QuantumNet," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 49 pages.
122"Invalidity Chart for Base Reference Tyuluman 536," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 76 pages.
123"Invalidity Chart for Base Reference U.S. 5,339,408," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 61 pages.
124"Invalidity Chart for Base Reference U.S. 5,436,857 (Nelson)," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 6 pages.
125"Invalidity Chart for Base Reference U.S. 5,608,608 (Flint)", submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 6 pages.
126"Invalidity Chart for Base Reference U.S. 5,809,262," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 62 pages.
127"Invalidity Chart for Base Reference U.S. 5,978,821 (Freeny)", submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 6 pages.
128"Invalidity Chart for Base Reference U.S. 5,999,952 (Jenkins)", submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 6 pages.
129"Invalidity Chart for Base Reference U.S. Patent No. 4,453,215 (Reid)," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 56 pages.
130"Invalidity Chart for Base Reference U.S. Patent No. 5,187,645 (Spalding)", submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 6 pages.
131"Invalidity Chart for Base Reference U.S. Patent No. 5,325,517 to Baker et al. (Appendix 1, Exhibit 15)," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 59 pages.
132"Invalidity Chart for Base Reference U.S. Patent No. 5,463,742 (Kobayashi)", submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 5 pages.
133"Invalidity Chart for Base Reference U.S. Patent No. 5,577,205," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 60 pages.
134"Invalidity Chart for Base Reference U.S. Patent No. 5,802,391," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 61 pages.
135"Invalidity Chart for Base Reference U.S. Patent No. 6,564,274 (Heath)," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 57 pages.
136"Invalidity Chart for Base Reference U.S. Patent No. 6,715,100," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 64 pages.
137"Invalidity Chart for Base Reference U.S. Patent No. 7,339,786 (Bottom et al.)," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 57 pages.
138"Invalidity Chart for Base Reference WhiteCross 9800 System," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 62 pages.
139"Invalidity Chart for Base Reference WO 92/18924 (Wallsten)", submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 6 pages.
140"Invalidity Chart for Base Reference Ziatech Corp. Ketris 9000 System," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 68 pages.
141"Invalidity Chart for Base Reference Ziatech STD 32 Star System," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 62 pages.
142"Invalidity Chart for Base References RLX Patents, U.S. Patent Nos. 6,747,878, 6,411,506, 6,325,636, 6,757,748, and 6,985,967 (Hipp et al.)," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 58 pages.
143"Invalidity Chart for Japanese Patent Application H7-64672 (Toshiba '672)," submitted by the Defendants in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Mar. 1, 2010, 55 pages.
144"J&L Announces ChatAccess/PC™, a PCMCIA Based Remote LAN Node Server," J&L Information Systems, Press Release, Jun. 19, 1995, 2 pages.
145"J&L Announces ChatExpress-P120 Rackmounted Applications Server at PC Expo, New York," J&L Information Systems, Press Release, Jun. 19, 1994, 2 pages.
146"J&L Announces the NRS-T10RS™ a Fault Tolerant Applications Server Platform at FOSE," J&L Information Systems, Press Release, Mar. 20, 1994, 2 pages.
147"J&L Announces their ChatAccess™ Family of Remote LAN Node Servers at Networld+Intertop Las Vegas," J&L Information Systems, Press Release, Mar. 27, 1994, 2 pages.
148"J&L Announces their ChatExpress-P100 Rackmounted Applications Server at Networks Expo. Boston," J&L Information Systems, Press Release, Feb. 13, 1994, 3 pages.
149"J&L Announces their ChatExpress-P75Applications Server at Networks Expo," J&L Information Systems, Press Release, Feb. 13, 1994, 3 pages.
150"J&L Announces Two Patents," J&L Information Systems, Press Release, Feb. 9, 1995, 1 page.
151"J&L Doubles the Rack-Mounted Communications Server Density with ChatVantage/486™," J&L Information Systems, Press Release, Sep. 11, 1995, 2 pages.
152"J&L Information Systems Announces ChatPower-Plus™ a Revolutionary Redundant Power Supply System," J&L Information Systems, Press Release, Jun. 19, 1995, 2 pages.
153"J&L Information Systems Announces two DX4 for their ChatterBox Family of Remote Access Servers," J&L Information Systems, Press Release, Feb. 13, 1994, 2 pages.
154"Joint Claim Construction Statement," Case No. 6:09-cv-00148-LED, filed Apr. 30, 2010, 46 pages.
155"Jury Verdict Form," Returned by the Jury in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Februrary 23, 2011, 2 pages.
156"Kognitio—Infrastructure Partners," Retrieved from the Internet on Sep. 8, 2010, Retrieved at URL: www.kognito.com/partners/infrastructure.php, 2 pages.
157"List of Representative Customers," Network Engines, Inc., undated, 1 page.
158"Logical Management Process," RocketLogix, Rev. 5, Apr. 5, 2000, 1 page.
159"Memorandum Opinion and Order Construing Claim Terms and Denying Defendants' Motion for Partial Summary Judgment," Issued by the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Aug. 2, 2010, 18 pages.
160"Memorandum Opinion and Order Construing Claim Terms," Issued by the U.S. District Court for the Eastern District of Texas, Tyler Division, Case No. 6:09-cv-148-LED, Document 602, Feb. 3, 2011, 12 pgs.
161"Memorandum Opinion Construing Claim Terms ‘Hub’ and ‘PCI bus transaction’," Issued by the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED on Februrary 3, 2011, 12 pages.
162"Microsoft Press Computer Dictionary, Third Edition," Microsoft Press, 1997, pp. 199 and 332, Kim Fryer ed.
163"Motion to Dismiss Counterclaim Pursuant to Rule 12(b)(6) and Motion to Strike Affirmative Defense Pursuant to Rule 12(f)," Case 6:09-00148-LED, filed Sep. 16, 2009, 18 pages.
164"Narus and Whitecross Join Forces to Deliver Comprehensive Usage Pattern Analysis Applications for IP Service Providers," Press Release, Palo Alto, CA, Mar. 27, 2000, 4 pages.
165"NEC Corporation of America's Answer, Affirmative Defenses, and Counterclaims to Acqis LLC's Second Amended Complaint for Patent Infringement," Case No. 6:09-cv-00148-LED, filed Aug. 10, 2009, 38 pages.
166"Network Engines Announces New Clustered Application Servers for Web, Thin-Client and Windows NT Enterprise Environments," Network Engines, Inc., Press Release, Oct. 8, 1997, 3 pages.
167"Network Engines Announces Partnership With Telegration Associates, Inc.," Network Engines, Inc., Press Release, Dec. 10, 1997, 2 pages.
168"Network Engines Awarded Best of Show at Networld + Interop 97, New company debuts product and wins," Network Engines, Inc., Press Release, Oct. 14, 1997, 2 pages.
169"Network Engines Debuts ClusterDirector in Internet/Intranet Load Balanced Environment," Network Engines, Inc., Press Release, Jan. 27, 1998, 3 pages.
170"P6000 Fault-Tolerant Multiprocessor Application Server," Powerstation Technologies, Inc., 1996, 3 pages.
171"P6000 IP Application Server," Network Engines, undated, 1 page.
172"Plaintiff Acqis LLC's Answer to Defendant Appro International, Inc.'s Counterclaims," Case No. 6:09-00148-LED, filed Aug. 28, 2009, 16 pages.
173"Plaintiff Acqis LLC's Answer to Defendant Dell Inc.'s Counterclaims," Case No. 6:09-00148-LED, filed Sep. 2, 2009, 16 pages.
174"Plaintiff Acqis LLC's Answer to Defendant Dell Inc.'s First Amended Counterclaims," Case No. 6:09-00148-LED, filed May 10, 2010, 16 pages.
175"Plaintiff Acqis LLC's Answer to Defendant Fujitsu Computer Systems Corp., N/K/A Fujitsu America, Inc.'s Counterclaims," Case No. 6:09-00148-LED, filed Sep. 16, 2009, 7 pages.
176"Plaintiff Acqis LLC's Answer to Defendant Hewlett-Packard Company's Counterclaims," Case No. 6:09-00148-LED, filed Sep. 16, 2009, 14 pages.
177"Plaintiff Acqis LLC's Answer to Defendant International Business Machines Corp.'s Counterclaims," Case No. 6:09-00148-LED, filed Sep. 2, 2009, 11 pages.
178"Plaintiff Acqis LLC's Answer to Defendant NEC Corporation of America's Counterclaims," Case No. 6:09-00148-LED, filed Sep. 16, 2009, 8 pages.
179"Plaintiff Acqis LLC's Answer to Defendant Sun Microsystems, Inc.'s Counterclaims," Case No. 6:09-cv-00148-LED, filed Sep. 2, 2009, 14 pages.
180"Plaintiff Acqis LLC's Answer to Defendant Super Micro Computer, Inc.'s Counterclaims," Case No. 6:09-00148-LED, filed Sep. 2, 2009, 15 pages.
181"Plaintiff Acqis LLP's First Supplemental Objections and Responses to Defendants' Third Set of Interrogatories," Case No. 6:09-cv-00148-LED, filed Aug. 5, 2010, 14 pages.
182"Plaintiff Acqis LLP's Objections and Responses to Defendants' First Set of Interrogatories," Case No. 6:09-cv-00148-LED, filed Aug. 5, 2010, 21 pages.
183"Plaintiff Acqis LLP's Objections and Responses to Defendants' Third Set of Interrogatories," Case No. 6:09-cv-00148-LED, filed Aug. 5, 2010, 13 pages.
184"Plaintiffs Opening Brief Regarding Claim Construction," Case No. 6:09-cv-00148-LED, filed Jun. 1, 2010, 35 pages.
185"Plaintiff's Reply Brief Regarding Claim Construction," Case No. 6:09-cv-00148-LED, filed Jun. 28, 2010, 14 pages.
186"Plexnet™ Product Overview," Plexcom, Inc., 1992, 8 pages.
187"Proposed Claim Construction Statement," Case No. Case No. 6:09-cv-00148-LED, filed Jun. 15, 2010, 39 pages.
188"PTI Fault Tolerant System Working Document Specification," Rev 0, Feb. 26, 1996, 2 pages.
189"QuantumNet 6000 Sharing Modules," QuantumNet, Inc., 1996, Retrieved from the Internet on Oct. 22, 2008, Retrieved at URL: www.web.archive.org/web/19971011194326/www.quantumnet.com/ds60xx.htm, 3 pages.
190"Redefining Server Economics—Take Control," RLX Technologies, 2001, 2 pages.
191"RLX Control Tower™ Take Control," RLX Technologies, undated, 4 pages.
192"RLX System 324 Technical Guide: RLX Red Hat Installation," RLX Technologies, Inc., 2001, 22 pages.
193"RocketLogix Passive I/O Board Topology," RocketLogix, Inc., Revision 6, May 24, 2000, 1 page.
194"RocketLogix Switched I/O Board Topology," RocketLogix, Inc., Revision 6, May 24, 2000, 1 page.
195"Second Amended Complaint for Patent Infringement," Acqis v. Appro Int'l, Inc. et al., Case No. 6:09-cv-00148, filed Jul. 22, 2009, 49 pages.
196"Telecom Australia to Receive Astro Sciences/J&L 486 Services," Astro Sciences Corporatoin, Press Release, Jan. 4, 1996, 1 page.
197"Thin Client Servers High-Speed Data Switching Technical Summary," QuantumNet, Inc., Aug. 29, 2010, 28 pages.
198"TLD Queries Complete Call Detail Record Database with WhiteCross Data Exploration Server," Data Mining Product Reviews, Feb. 2000, 1 page.
199"Transcript of Videotaped Deposition of William Mangione-Smith," taken by the Defendants in connection with Case No. 6:09-cv-148-LED in the U.S. District Court for the Eastern District of Texas, Sep. 9, 2010, 192 pages.
200"Venture financing is fuel for Powerstation's Growth Plans," Mass High Tech Communications, Inc., Jun. 2, 1997, 1 page.
201"WhiteCross Data Exploration Announces ExplorationSTUDIO™," Press Release, New York, Ny, Sep. 2, 1999, 2 pages.
202"WhiteCross Introduces ‘World's Most Powerful Exploration Warehouse System,’" Press Release, New York, NY, Sep. 2, 1999, 2 pages.
2038260 ATM Product Architecture, IBM International Technical Support Organization, Raleigh Center, Sep. 1997, First Edition, International Business Machines Corporation, 220 pgs.
2048265 Nways ATM Switch, Product Description, Sep. 1998, Fifth Edition, International Business Machines Corporation, 141 pages.
205Accton Technology Corporation, "Gigabit Ethernet PCI Adapter," Cheetah Gigabit Adapter (EN1407-SX) Brochure, 1999, 2 pgs.
206Advanced Micro Devices, Inc., "AMD-K6-III Processor Data Sheet," 21918B/0, Oct. 1999, 326 pages.
207Agerwala, T., "SP2 System Architecture.," IBM Systems Journal, vol. 34, No. 2, pp. 152-184 (1995).
208Amendment filed with Continued Prosecution Application for U.S. Patent No. 6,345,330, filed Jan. 17, 2001, 5 pages.
209Amendment for U.S. Patent No. 6,345,330, filed Sep. 12, 2000, 5 pages.
210Amendment for U.S. Patent No. 7,818,487, filed May 11, 2010, 15 pages.
211Amendment Submitted After Notice of Allowance for U.S. Patent No. 7,818,487, filed Aug. 17, 2010, 14 pages.
212Amendment Submitted with RCE for RE 41,076, filed Aug. 4, 2009, 2 pages.
213Amendment Submitted with RCE for RE 41,076, filed Dec. 8, 2008, 44 pages.
214Amendment Submitted with RCE for RE 41,076, filed Nov. 5, 2007, 19 pages.
215Amendment Submitted with RCE for RE 41,294, filed May 27, 2008, 14 pages.
216Amendment Submitted with RCE for U.S. Appl. No. 10/963,825, filed Feb. 20, 2009, 24 pages.
217Amendment Submitted with RCE for U.S. Appl. No. 10/963,825, filed Jul. 27, 2006, 29 pages.
218Amendment Submitted With RCE for U.S. Patent No. 7,099,981, filed Mar. 1, 2006, 23 pages.
219Anderson, C.R. et al., "IEEE 1355 HS-Links: Present Status and Future Prospects," [online], 1998, [retrieved on Aug. 11, 2010], Retrieved from the Internet: <URL: http://www94.web.cern.ch/HIS/dshs/publications/wotug21/hslink/pdf/hslinkpaper.pdf>, 14 pages.
220Appellants' Brief for U.S. Appl. No. 10/963,825, filed Jan. 8, 2007, 31 pages.
221Applicant Summary of Interview, filed Mar. 24, 2009, 1 page.
222Athavale, A., "How to Lower the Cost of PCI Express Adoption by Using FPGAs," EETimes Design [online] Apr. 26, 2006, [retrieved on May 3, 2011]. Retrieved from the Internet at <URL: http://www.eetimes.com/General/DisplayPrintViewContent?contentItemID=4014824>, 6 pages.
223Bernal, Carlos, product brochure entitled: "PowerSMP Series 4000" (Mar. 1998) <<http://www.winnetmag.com/Windows/Article/ArticleID/3095//3095.html, downloaded from web on Jun. 22, 2004, 2 pgs.
224Berst, "Hope for the Modular PCs We all Really Want" (Dec. 5, 1997).
225Black Box Corporation, "Black Box Serve Switch Duo," Black Box Network Services Manual, Jul. 1998, 52 pages.
226Black Box Corporation, Black Box Network Services, Black Box ServSwitch Duo, Jul. 1998, 52 pages.
227Board Specifications for DataModule Board, DataStation Backplane, DataStation Front Bezel, and BaseStation Backplane, Rev. E, Anigma, Inc., Mar. 2, 2000, 5 pages.
228Boyd-Merritt, "Upgradable-PC Effort Takes Divergent Paths" (EE Times 1997) http://techweb.cmp/com/eet/news/97/949news/effort.html.
229Burrow, M., "A Technical Overview of the WXDES/9800," Whitecross Data Exploration, Apr. 21, 1999, Software, 102 pages.
230Burrow, M., "A Technical Overview of the WXDES/9800," Whitecross Data Exploration, White Cross Systems Limited, Apr. 21, 1999, 90 pages.
231Burrow, M., WhiteCross Data Exploration, "A Technical Overview of the WXDES/9800," Apr. 21, 1999, White Cross Systems Limited, 222 pages.
232Burrow, M., WhiteCross Data Exploration, "A Technical Overview of the WXDES/9800," Mar. 2, 1999, Revision 2.00, White Cross Systems Limited, pp. 1-90.
233Cetia Brochure "Cetia Powerengine CVME 603e" pp. 1-6 downloaded from the intetnet at. http://www.cetia.com/ProductAddOns/wp-47-01.pdf on Feb. 15, 2006.
234Chapter 7: Designing a Data Protection Plan, (undated), pp. 170-171.
235Chapter 7: Maintaining the NetWare Server, "Supervising the Network," (undated), pp. 514-517.
236Charlesworth, I., "Technology Audit, Data Exploration Server," Butler Group, Sep. 1999, 8 pages.
237Cisco Systems, Inc., "Cisco AS5800 Universal Access Server Dial Shelf Controller Card Installation and Replacement," Doc. No. 78-4653-02, 1997, 28 pages.
238Compaq Computer Corporation, Compaq ActiveAnswers Installation Guide, Installation and Configuration Guide for Linux and Apache Web Server on Compaq Prosignia and ProLiant Servers, May 1999, pp. 1-40.
239Compaq Computer Corporation, Compaq Performance Brief, ProLiant 1600 ServerBench Performance Summary, Aug. 1998, pp. 1-7.
240Compaq Computer Corporation, Compaq White Paper, "Accelerating Financial Spreadsheet Simulations with Workstation Clusters," Oct. 1998, pp. 1-14.
241Compaq Computer Corporation, Compaq White Paper, "Microsoft Internet Information Server 4.0 on the Compaq ProLiant 6500," Aug. 1998, pp. 1-14.
242Compaq Computer Corporation, Compaq White Paper, "ServerNet-A High Bandwith, Low Latency Cluster Interconnection," Sep. 1998, pp. 1-9.
243Compaq Computer Corporation, Compaq White Paper, "ServerNet—A High Bandwith, Low Latency Cluster Interconnection," Sep. 1998, pp. 1-9.
244Compaq Computer Corporation, et al., "Universal Serial Bus Specification," Apr. 27, 2000, Revision 2.0, 650 pages.
245Compaq Computer Corporation, et al., "Universal Serial Bus Specification," Sep. 23, 1998, Revision 1.1, 327 pages.
246Compaq Computer Corporation, ProLiant 6500-PDC/01000 C/S with 4 ProLiant 1850R, TPC-C Rev. 3.4, Report Date: Dec. 22, 1998, pp. 1-3.
247Compaq Computer Corporation, QuickSpecs, Compaq ProLiant Cluster Series F Model 100, (undated), pp. 8-36 to 8-37.
248Compaq Computer Corporation, White Paper, "Order and Configuration Guide for Compaq ProLiant Cluster Series F Model 100," Sep. 1998, pp. 1-8.
249Concepts, Disk Driver and Disk Duplexing, (undated), pp. 82-83.
250Cragle, Jonathan, "Density System 1100", May 1999) >, downloaded from web on Jun. 21, 2004, 3 pgs.
251Cragle, Jonathan, "Density System 1100", May 1999) <<http://www.winnetmag.com/Windows/Article/ArticleID/5199/5199.html>>, downloaded from web on Jun. 21, 2004, 3 pgs.
252Crystal Advertisement for "QuickConnect® Cable Management", (@2000-2004) > downloaded from web on Jun. 17, 2004, 4 pgs.
253Crystal Advertisement for "Rackmount Computers", (@2000-2004) >, downloaded from web on Jun. 17, 2004, 8 pgs.
254Crystal Advertisement for "QuickConnect® Cable Management", (@2000-2004) <<http://www.crystalpc.com/products/quickconnect.asp>> downloaded from web on Jun. 17, 2004, 4 pgs.
255Crystal Advertisement for "Rackmount Computers", (@2000-2004) <<http:/www.crystalpc.com/products/roservers.asp>>, downloaded from web on Jun. 17, 2004, 8 pgs.
256Cubix Corporation, BC Series, Processor Boards Installation Guide, DOC 800A, Aug. 1994, 149 pages.
257Cubix Corporation, Cubix ERS/FT II Systems [online], 1997 [retrieved on Jul. 31, 2009], Retrieved from the Internet: , 5 pages.
258Cubix Corporation, Cubix ERS/FT II Systems [online], 1997 [retrieved on Jul. 31, 2009], Retrieved from the Internet: <URL: http://web.archive.org/web/19980124213320/www.cubix.com/support/steps/ersft2/intro.htm>, 5 pages.
259Cubix Corporation, Cubix Pentium II Plug-In Computers for Density Series Systems, Sep. 15, 1998, 1 page.
260Cubix Corporation, Cubix Product Catalog, Summer 1995, 56 pages.
261Cubix Corporation, Datasheet: ERS/FT II Server Chassis [online], 1997 [retrieved on Jul. 31, 2009], Retrieved from the Internet: , 3 pages.
262Cubix Corporation, Datasheet: ERS/FT II Server Chassis [online], 1997 [retrieved on Jul. 31, 2009], Retrieved from the Internet: <URL: http://web.archive.org/web/19970716204623/www.cubix.com/corporate/data/ersft2.htm>, 3 pages.
263Cubix Corporation, Datasheet: Single-Board Computers with Pentium Processors [online], 1997 [retrieved on Jul. 31, 2009], Retrieved from the Internet: , 5 pages.
264Cubix Corporation, Datasheet: Single-Board Computers with Pentium Processors [online], 1997 [retrieved on Jul. 31, 2009], Retrieved from the Internet: <URL: http://web.archive.org/web/19970716204717/www.cubix.com/corporate/data/bcp5t.htm>, 5 pages.
265Cubix Corporation, Density Series Multi-Server Systems, Sep. 10, 1999, 4 pages.
266Cubix Corporation, Density Series Plug-In Servers, Plug-In Computers for Managed Server Farms, Sep. 15, 1998, 2 pages.
267Cubix Corporation, ERS/FT II-Enhanced Resource Subsystem/Fault Tolerant II, Nov. 1994, 4 pages.
268Cubix Corporation, ERS/FT II—Enhanced Resource Subsystem/Fault Tolerant II, Nov. 1994, 4 pages.
269Cubix Corporation, White Paper: Benefits of High-Density Servers [online], 1997 [retrieved on Jul. 31, 2009], Retrieved from the Internet: , 6 pages.
270Cubix Corporation, White Paper: Benefits of High-Density Servers [online], 1997 [retrieved on Jul. 31, 2009], Retrieved from the Internet: <URL: http://web.archive.org/web/19970716204215/www.cubix.com/corporate/whitep/densit.htm>, 6 pages.
271Cubix Product Brochure entitled, "Density System", (@2000) > downloaded from web on Jun. 22, 2004, 3 pgs.
272Cubix Product Brochure entitled, "Density System, Technical Specifications", (@2000) > downloaded from web on Jun. 22, 2004, 2 pgs.
273Cubix Product Brochure entitled, "Density System, Technical Specifications", (@2000) <http://64.173.211.7/support/techinfo/system/density/info/spec.htm>> downloaded from web on Jun. 22, 2004, 2 pgs.
274Cubix Product Brochure entitled, "Density System", (@2000) <<http://64.173.211.7/support/techinfo/system/density/density10.htm>> downloaded from web on Jun. 22, 2004, 3 pgs.
275Cubix Product Manual entitled, "Density System", Chapter 3-Operation, (@2000), > downloaded from web on Jun. 22, 2004, 4 pgs.
276Cubix Product Manual entitled, "Density System", Chapter2-Installation, (@2000) > downloaded from web on Jun. 22, 2004, 9 pgs.
277Cubix Product Manual entitled, "Density System," Chapter 4-Maintenance and Repair, (@2000) > downloaded from web on Jun. 22, 2004, 5 pgs.
278Cubix Product Manual entitled, "Density System," Chapter 4—Maintenance and Repair, (@2000) <<http://64.173.211.7/support/techinfo/manuals/density/Chap4-htm>> downloaded from web on Jun. 22, 2004, 5 pgs.
279Cubix Product Manual entitled, "Density System", Chapter 3—Operation, (@2000), <<http://64.173.211.7/support/techinfo/manuals/density/Chap-3.htm>> downloaded from web on Jun. 22, 2004, 4 pgs.
280Cubix Product Manual entitled, "Density System", Chapter2—Installation, (@2000) <<http://64.173.211.7/support/techiknfo/manuals/density/Chap-2.htm>> downloaded from web on Jun. 22, 2004, 9 pgs.
281Cubix Product Manual entitled; "Density System", Chapter 1-Introduction, (@2000) > downloaded from web on Jun. 22, 2004, 5 pgs.
282Cubix Product Manual entitled; "Density System", Chapter 1—Introduction, (@2000) <<http://64.173.211.7/support/techinfo/manuals/density/Chap-1.htm>> downloaded from web on Jun. 22, 2004, 5 pgs.
283Cubix, "Click on the front panel that matches your system", (@2000) >, downloaded from web on Jun. 22, 2004, 1 pg.
284Cubix, "DP 6200 'D' Series Plug-in Computers" >, downloaded from web on Jun. 22, 2004, 2 pgs.
285Cubix, "Installing DP or SP Series Boards" (@2000) >, downloaded from web on Jun. 22, 2004, 2 pgs.
286Cubix, "Multiplexing Video, Keyboard & Mouse with Multiple Density Systems", (@2000) >, downloaded from web on Jun. 22, 2004, 2 pgs.
287Cubix, "Powering On/Off or Resetting Plug-in Computers in an Density System", (@2000) , downloaded from web on Jun. 22, 2004, 2 pgs.
288Cubix, "SP 5200 Series" Chapter 1-Introduction, (@2000) >, downloaded from web on Jun. 22, 2004, 3 pgs.
289Cubix, "SP 5200 Series" Chapter 2-Switches & Jumpers, (@2000) >, downloaded from web on Jun. 22, 2004, 3 pgs.
290Cubix, "SP 5200 Series" Chapter3-Installation, (@2000) >, downloaded from web on Jun. 22, 2004, 4 pgs.
291Cubix, "SP 5200 Series" Chapter4-Technical Reference, (@2000) >, downloaded from web on Jun. 22, 2004, 3 pgs.
292Cubix, "SP 5200XS Series Plug-in Computers", (@2000) >, downloaded from web on Jun. 22, 2004, 2 pgs.
293Cubix, "SP 5200XS Series Technical Specifications", (@2000) >, downloaded from web on Jun. 22, 2004, 2 pgs.
294Cubix, "What are Groups?", (@2000) >, downloaded from web on Jun. 22, 2004, 3 pgs.
295Cubix, "Click on the front panel that matches your system", (@2000) <<http://64.173.211.7/support/techinfo/system/density/density.htm>>, downloaded from web on Jun. 22, 2004, 1 pg.
296Cubix, "DP 6200 ‘D’ Series Plug-in Computers" <<http://64.173.211.7/support/techinfo/bc/dp/6200d/Intro.htm>>, downloaded from web on Jun. 22, 2004, 2 pgs.
297Cubix, "Installing DP or SP Series Boards" (@2000) <<http://64.173.211.7/support/techinfo/system/density/info/pic-inst.htm>>, downloaded from web on Jun. 22, 2004, 2 pgs.
298Cubix, "Multiplexing Video, Keyboard & Mouse with Multiple Density Systems", (@2000) <<http://64.173.211.7/support/techinfo/system/density/info/vkm-mux.htm>>, downloaded from web on Jun. 22, 2004, 2 pgs.
299Cubix, "Powering On/Off or Resetting Plug-in Computers in an Density System", (@2000) <<http://64.173.211.7/support/techinfo/system/density/info/power.htm>, downloaded from web on Jun. 22, 2004, 2 pgs.
300Cubix, "SP 5200 Series" Chapter 1—Introduction, (@2000) <<http://64.173.211.7/support/techinfo/manuals/sp5200/chap-1.htm>>, downloaded from web on Jun. 22, 2004, 3 pgs.
301Cubix, "SP 5200 Series" Chapter 2—Switches & Jumpers, (@2000) <<http://64.173.211.7/support/techinfo/manuals/sp5200/chap-2.htm>>, downloaded from web on Jun. 22, 2004, 3 pgs.
302Cubix, "SP 5200 Series" Chapter3—Installation, (@2000) <<http://64.173.211.7/support/techinfo/manuals/sp5200/chap-3.htm> >, downloaded from web on Jun. 22, 2004, 4 pgs.
303Cubix, "SP 5200 Series" Chapter4—Technical Reference, (@2000) <<http://64.173.211.7/support/techinfo/manuals/sp5200/chap-4.htm>>, downloaded from web on Jun. 22, 2004, 3 pgs.
304Cubix, "SP 5200XS Series Plug-in Computers", (@2000) <<http://64.173.211.7/support/techinfo/bc/sp5200xs/intro.htm>>, downloaded from web on Jun. 22, 2004, 2 pgs.
305Cubix, "SP 5200XS Series Technical Specifications", (@2000) <<http://64.173.211.7/support/techinfo/bc/sp5200xs/spec.htm>>, downloaded from web on Jun. 22, 2004, 2 pgs.
306Cubix, "What are Groups?", (@2000) <<http://64.173.211.7/support/techinfo/system/density/info/groups.htm>>, downloaded from web on Jun. 22, 2004, 3 pgs.
307Decision on Appeal for U.S. Appl. No. 10/963,825, mailed Feb. 4, 2009, 13 pages.
308Defendant's Invalidty Chart for Base Reference RLX System 324, proposed on Jul. 15, 2010, 58 pages.
309Dell, Inc., White Paper, "PCI Express Technology," Feb. 2004, pp. 1-11.
310Digital Equipment Corporation, "Digital AlphaServer 4000 and 4100 systems," [Brochure], 1998, 4 pages.
311Digital Semiconductor Product Brief, "21152 PCI-to-PCI Bridge," Feb. 1996, 6 pages.
312Dirk S. Faegre et al., "CTOS Revealed", http://www.byte.com/art/9412/sec13/art2.htm.
313eBay Advertisement for "Total IT Group Network Engines", <<http//egi.ebay.com/we/eBayISAPI.dll?ViewItem&Item=5706388046&sspagename+STRK%3 AMDBI%3AMEBI3AIT&rd=1>>, downloaded from web on Jun. 25. 2004, 1 pg.
314Ellis, S., "IRIS FailSafe™ Administrators Guide," Document No. 007-3109-003, Apr. 6, 1997, 212 pages.
315Email Emanuel to Juarez regarding Invalidity Chart for Base Reference IBM BladeCenter, dated Aug. 20, 2010, 54 pages.
316Engineering Department Electronic Industries Association (EIA), "Electrical Cahracteristics of Balanced Voltage Digital Interface Circuits", EIA Standard, EIA-422-A, Dec. 1978, 20 pgs.
317Evergreen Systems, Inc., "CAPserver, The Communication/Application server for local area networks," Product Guide, (undated), 18 pages.
318Eversys CAPcard 9500/sa Product Brief [online], (undated), [retrieved on Nov. 16, 2009], Retrieved from the Internet: <URL: http://web.archive.org/web/19961104093144/www.eversys.com/cc95sa—Brief.htm>, 3 pages.
319Eversys CAPserver Product Brief [online], (undated), [retrieved on Nov. 16, 2009], Retrieved from the Internet: <URL: http://web.archive.org/web/19961104093115/www.eversys.com/CAPbrief.htm>, 10 pages.
320Eversys Corporation Business Plan, Eversys Corporation, Mar. 21, 1997, 53 pages.
321Eversys Corporation, Eversys System 8000 Peripheral Sharing Switch (PSS) User's Guide, 1st Edition—Jun. 1997, 2nd Edition—Jan. 1998, 17 pages.
322Eversys Corporation, S8000 Single Module Body Assemby, Oct. 9, 1998, 9 pages.
323Eversys Corporation, System 8000 Consolidated Network Server Product Brief, (undated), 2 pages.
324Eversys Corporation, System 8000 Consolidated Network Server, Pentium II Processor Module User's Guide for Module version P2D-BXT, Jan. 1998, 49 pages.
325Eversys Corporation, System 8000 Consolidated Server Presentation, (undated), 23 pages.
326Eversys Corporation, System 8000 Consolidated Server, (undated), [retrieved on Nov. 9, 2009], Retrieved from C: drive <path: file://C:\Documents and Settings\Daniel\MDocuments\Eversys\Eversys Web Site Master...>, 6 pages.
327Eversys Corporation, WebView 8000 version 1.1 User's Guide, Web-Based Management Software fo the Eversys System 8000 Consolidated Server, Revision A—Nov. 1998, Revision B—Dec. 1998, 56 pages.
328Eversys, "CAPserver Product Brief" [online], [retrieved on Nov. 16, 2009], Retrieved from the Internet: <URL: http://web.archieve.org/web/19961104093115/www.eversys.com/CAPbrief.htm>, 10 pages.
329Eversys, "Products" [online], [retrieved on Nov. 16, 2009], Retrieved from the Internet: <URL: http://web.archieve.org/web/19961104093103/www.eversys.com/prodinfo.htm>, 2 pages.
330Eversys, "Welcome to EverSys" [online], [retrieved on Nov. 16, 2009], Retrieved from the Internet: <URL: http://web.archieve.org/web/19961104092834/www.eversys.com/index2.htm>, 1 page.
331Examiner Interview Summary Record, mailed Feb. 24, 2009, 4 pages.
332Examiner Interview Summary Record, mailed Jan. 15, 2009, 1 page.
333Examiner Interview Summary Record, mailed Sep. 22, 2009, 5 pages.
334Examiner's Amendment for RE 41,092, mailed Nov. 4, 2009, 4 pages.
335Examiner's Answer for U.S. Appl. No. 10/963,825, mailed Aug. 8, 2007, 30 pages.
336Excerpt from "Microsoft Computer Dictionary, 4th Edition", Microsoft Press, 1999, pp. 184-185, 241, 432 (7 pages.).
337Excerpt from "Microsoft Computer Dictionary, 4th Edition", Microsoft Press, 1999, pp. 40, 241, 432 (6 pages).
338Excerpt from "Microsoft Computer Dictionary, 5th Edition", Microsoft Press, 2002, pp. 96 and 547.
339Excerpt from "Microsoft Computer Dictionary, 5th Edition", Microsoft Press, 2002, pp. 96, 329, 624 and 625.
340Excerpt from IEEE 100: The Authoritative Dictionary of IEEE Standards Terms (7th Ed., 2000), pp. 181,304 and 771.
341Excerpt from IEEE 100: The Authoritative Dictionary of IEEE Standards Terms (7th Ed., 2000), pp. 78, 79 and 128.
342Excerpts of Transcript of "Videotaped Deposition of William W.Y. Chu," taken by the Defendants in connection with Case No. 6:09-cv-148-LED in the U.S. District Court for the Eastern District of Texas, Jun. 7, 2010, 20 pages.
343Exhibit 1, Disclosure of Asserted Claims and Infringement Contentions for Defendant Appro International, Inc., submitted by the Plaintiff in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED, served on Sep. 14, 2009, 105 pages.
344Exhibit 2, Disclosure of Asserted Claims and Infringement Contentions for Defendant ClearCube Technology, Inc., submitted by the Plaintiff in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED, served on Sep. 14, 2009, 163 pages.
345Exhibit 3, Disclosure of Asserted Claims and Infringement Contentions for Defendant Dell Inc., submitted by the Plaintiff in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED, served on Sep. 14, 2009, 184 pages.
346Exhibit 4, Disclosure of Asserted Claims and Infringement Contentions for Defendant Fujitsu America, Inc., submitted by the Plaintiff in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED, served on Sep. 14, 2009, 210 pages.
347Exhibit 5, Disclosure of Asserted Claims and Infringement Contentions for Defendant Hewlett-Packard Co., submitted by the Plaintiff in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED, served on Sep. 14, 2009, 279 pages.
348Exhibit 6, Disclosure of Asserted Claims and Infringement Contentions for Defendant IBM Corp., submitted by the Plaintiff in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED, served on Sep. 14, 2009, 242 pages.
349Exhibit 7, Disclosure of Asserted Claims and Infringement Contentions for Defendant NEC Corp. Of America, submitted by the Plaintiff in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED, served on Sep. 14, 2009, 166 pages.
350Exhibit 8, Disclosure of Asserted Claims and Infringement Contentions for Defendant Sun Microsystems, Inc., submitted by the Plaintiff in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED, served on Sep. 14, 2009, 243 pages.
351Exhibit 9, Disclosure of Asserted Claims and Infringement Contentions for Defendant Super Micro Computer, Inc., submitted by the Plaintiff in the U.S. District Court for the Eastern District of Texas, Case No. 6:09-cv-148-LED, served on Sep. 14, 2009, 220 pages.
352Facsimile from Procrass to Paunovich attaching "QuantumNet Network Computing Systems," Aug. 30, 2010, 8 pages.
353Faegre, et al., "Unisys' Best-Kept Secret Is An Operating System Built For Distributed Business Applications." BYTE (Dec. 1994).
354Feakes, L., "Disk Connector Card Functional Requirement Specification," Jan. 14, 1998, White Cross Systems Limited, pp. 1-4.
355Feakes, L., "Disk Connector Card Layout Specification," Jan. 14, 1998, White Cross Systems Limited, pp. 1-6.
356Feakes. L., "Fast Ethernet Switch Card Design Specification," Revision 4.00, White Cross Systems Limited, Jul. 27, 2010, 23 pages.
357Feibel, W., Encyclopedia of Networking, Third Edition, p. 265, The Network Press, 2000, 4 pages.
358Feldman, Jonathan, "Rack Steady: The Four Rack-Mounted Servers That Rocked Our Network", >, Jun. 23, 2004, 3 pgs.
359Feldman, Jonathan, "Rack Steady: The Four Rack-Mounted Servers That Rocked Our Network", <<http://www.networkcomputing.com/shared/printArticle.jhtml?article=910/910r3side1.htm...> >, Jun. 23, 2004, 3 pgs.
360Fetters, Dave, "Cubix High-Density Server Leads the Way With Standout Management Software", (Feb. 8, 1999) >, downloaded from web on Jun. 23, 2004, 5 pgs.
361Fetters, Dave, "Cubix High-Density Server Leads the Way With Standout Management Software", (Feb. 8, 1999) <<http://www.nwc.com/shared/printArticle.jhtml?article=/1003/1003r3full.html&pub= nwc>>, downloaded from web on Jun. 23, 2004, 5 pgs.
362Galles, M., "Spider: A Hide-Speed Network Interconnect," IEEE Micro, 1997, pp. 34-39. (6 pages.).
363Gardner, Michael and Null, Christopher, "A Server Condominium", >, Jun. 23, 2004, 3 pgs.
364Gardner, Michael and Null, Christopher, "A Server Condominium", <<http://www.lantimes.com/testing/98jun/806a042a.html>>, Jun. 23, 2004, 3 pgs.
365Goldman, A, "ISP Profiles: RLX Technologies," ISP-Planet, May 17, 2001, retrieved from the Internet on Jul. 26, 2001, Retrieved at URL: www.isp-planet.com/profiles/2001/rlx.html, 3 pages.
366Grigonis, R., "Fault Resilient PC's," Flatiron Publishing, 1996, 314 pages.
367Grigonis, R., "Life-Saving Computers: Network Engines," Computer Telephony, Sep., 1997, 1 page.
368Groom, P., "WhiteCross 9800 pre-release configuration details and USA Pricing Information," WhiteCross Systems Limited, Nov. 3, 1998, 4 pages.
369Grow, R. et al., "Gigabit Media Independent Interface Proposal," Nov. 11, 1996, IEEE 802.3Z, Vancouver, 22 pages.
370Gruener, J., "Vendors pack in more servers," [retrieved on Oct. 22, 2009], Retrieved from the Internet: <URL: http://www.galenet.galegroup.com.ezproxy.sfpl.org.servlet/BCR...>, 2 pages.
371Gruener, J., "Vendors Pack in More Servers," PC Week, vol. 14, No. 1, Mar. 17, 1997, 2 pages.
372Haas, S., "The IEEE 1355 Standard: Developments, Performance and Application in High Energy Physics," Thesis for degree of Doctor of Philosophy, University of Liverpool, Dec. 1998, 138 pages.
373Harrison, Dave, "VME in the Military: the M1 A2 Main Battle Tank Upgrade Relies on COTS VME" >>, (Feb. 9, 1998), pp. 1-34.
374Harrison, Dave, "VME in the Military: the M1 A2 Main Battle Tank Upgrade Relies on COTS VME" <<http://www.dy4.com>>>, (Feb. 9, 1998), pp. 1-34.
375High Bandwidth Synchronization Bus Arbiter FPA Implementation, Network Engines, Inc., undated, 49 pages.
376Hill, Goff (editor), "The Cable and Telecommunications Professional's Reference: vol. 1," Third Edition, Focal Press, 2007, pp. 227-229, 5 pages.
377HotDock and Orbiter 3360—Technical Specifications, Product Overview, and Configurations, RocketLogix, Inc., 2000, 4 pages.
378HP: HDMP-1636, "Gigabit Ethernet Transceiver Chip", May 1997, 16 pgs.
379Huq et al., "An Overview of LVDS Technology," Application Note 971, Jul. 1998, 6 pgs.
380IBM Corporation, "Grounding Spring for Peripheral Device and Bezel Bracket," IBM Technical Disclosure Bulletin, Nov. 1, 1993, vol. 36, No. 11, 2 pages.
381IBM Dictionary of Computing, Tenth Ed., pp. 139, 439, 480 and 629, George McDaniel ed., McGraw-Hill, Inc., Aug. 1993, 16 pages.
382IBM Thinkpad Product Information Guide, IBM PC Company, Apr. 28, 1998, 26 pages.
383IEEE 100: The Authoritative Dictionary of IEEE Standards Terms, Seventh Ed., pp. 703, 704, 856 and 1064, The Institute of Electrical and Electronics Engineers, Inc., 2000, 13 pages.
384IEEE Standard for a High Performance Serial Bus, IEEE Std 1394-1995, The Institute of Electrical and Electronics Engineers, Inc., 1996, 392 pages.
385Intel Corp., 21143 "PCI/CardBus 10/100Mb/s Ethernet LAN Controller" Oct. 1998, 8 pgs.
386Intel Corp., 82559 "Fast Ethernet Multifunction PCI/Cardbus Controller" Jan. 1999, 56 pgs.
387Intel Corporation Advance Information, "Intel 440LX AGPSET: 82443LX PCI A.G.P. Controller (PAC)," Aug. 1997, 4 pages.
388Intel Corporation Architectural Overview, "Intel 430TX PCISET: 82439TX System Controller (MTXC)," Feb. 1997, 4 pages.
389Intel Corporation Architectural Overview, "Intel 82371AB PCI-to-ISA/IDE Xcelerator (PIIX4)," Apr. 1997, 3 pages.
390Intel Corporation, Intel 82559 Fast Ethernet Controller, [retrieved on Mar. 14, 2011], Retrieved from the Internet: <URL: http://www.intel.com/design/network/products/lan/controllers/82559.htm>, 1 page.
391Intel Corporation, Intel 82559 Fast Ethernet Multifunction PCI/Cardbus Controller, Networking Silicon, Preview Datasheet, Jan. 1999, 56 pgs.
392Intel, "Pentium® II Processor at 350 MHz, 400 MHz, and 450 MHz, Datasheet," Order No. 243657-003, Aug. 1998, 83 pages.
393International Preliminary Examination Report for International Patent Application No. PCT/US99/09369, report completed Jul. 5, 2000, 4 pages.
394International Search Report for International Patent Application No. PCT/US99/09369, report mailed Nov. 16, 1999, 7 pages.
395Internet Telephone Roundup, "Industrial Computers", >, downloaded from the web on Jun. 23, 2004, 5 pgs.
396Internet Telephone Roundup, "Industrial Computers", <<http://www.tmcnet.com/articles/itmag/0499/0499roundup.htm>>, downloaded from the web on Jun. 23, 2004, 5 pgs.
397J&L Introduces Twin Pentium for ChatterBox Systems, J&L Information Systems, Press Release, Jan. 29, 1996, 1 page.
398Jesse Berst's Anchor Desk, http://www.zdnet.com/anchordesk/story/story—1504.html.
399Jesse Berst's Anchor Desk, http://www.zdnet.com/anchordesk/talkback/talkback—56555.html.
400JL ChatCom, Inc.- Web Site, JL ChatCom, Inc., ChatterBox Communications and Server Solutions [online], 1996 [retrieved on Dec. 2, 2009], Retrieved from the Internet: , 1 page.
401JL ChatCom, Inc.— Web Site, JL ChatCom, Inc., ChatterBox Communications and Server Solutions [online], 1996 [retrieved on Dec. 2, 2009], Retrieved from the Internet: <URL: http://web.archive.org/web/19970104221841/http://www.jlchatcom.com/>, 1 page.
402JL ChatCom, Inc., "ChatExpress PB5 Series P166 Pentium PCI/ISA CPU Card," 1996 [retrieved on Dec. 2, 2009], JL ChatCom, Inc., ChatterBox Communications and Server Solutions [online], Retrieved from the Internet: , 2 pages.
403JL ChatCom, Inc., "ChatExpress-2 Slot," [retrieved on Dec. 2, 2009], JL ChatCom, Inc., ChatterBox Communications and Server Solutions [online], Retrieved from the Internet: , 1 page.
404JL ChatCom, Inc., "ChatPower Plus," 1996 [retrieved on Dec. 2, 2009], JL ChatCom, Inc., ChatterBox Communications and Server Solutions [online], Retrieved from the Internet: , 3 pages.
405JL ChatCom, Inc., "ChatterBox ChatPower Plus," (undated) [retrieved on Dec. 2, 2009], JL ChatCom, Inc., ChatterBox Communications and Server Solutions [online], Retrieved from the Internet: , 1 page.
406JL ChatCom, Inc., "ChatExpress PB5 Series P166 Pentium PCI/ISA CPU Card," 1996 [retrieved on Dec. 2, 2009], JL ChatCom, Inc., ChatterBox Communications and Server Solutions [online], Retrieved from the Internet: <URL: http://web.archive.org/web/19970104222157/www.jlchatcom.com/chatp599.htm>, 2 pages.
407JL ChatCom, Inc., "ChatExpress—2 Slot," [retrieved on Dec. 2, 2009], JL ChatCom, Inc., ChatterBox Communications and Server Solutions [online], Retrieved from the Internet: <URL: http://web.archive.org/web/19970104222644/www.jlchatcom.com/exp2ill.gif>, 1 page.
408JL ChatCom, Inc., "ChatPower Plus," 1996 [retrieved on Dec. 2, 2009], JL ChatCom, Inc., ChatterBox Communications and Server Solutions [online], Retrieved from the Internet: <URL: http://web.archive.org/web/19970104222122/www.jlchatcom.com/chatplus.htm>, 3 pages.
409JL ChatCom, Inc., "ChatterBox ChatPower Plus," (undated) [retrieved on Dec. 2, 2009], JL ChatCom, Inc., ChatterBox Communications and Server Solutions [online], Retrieved from the Internet: <URL: http://web.archive.org/web/19970104222556/www.jlchatcom.com/cpp1.gif>, 1 page.
410JL ChatCom, Inc., "ChatTwin," [retrieved on Dec. 2, 2009], JL ChatCom, Inc., ChatterBox Communications and Server Solutions [online], Retrieved from the Internet: <URL: http://web.archive.org/web/19970104222644/www.jlchatcom.com/chattwin.htm>, 2 pages.
411JL ChatCom, Inc.-Highly Adaptable Intranet and Web Servers, "ChatCom, Inc. Announces Highly Adaptable Intranet and Web Servers," Sep. 3, 1996 [retrieved on Dec. 2, 2009], JL ChatCom, Inc., ChatterBox Communications and Server Solutions [online], Retrieved from the Internet: , 2 pages.
412JL ChatCom, Inc.—Highly Adaptable Intranet and Web Servers, "ChatCom, Inc. Announces Highly Adaptable Intranet and Web Servers," Sep. 3, 1996 [retrieved on Dec. 2, 2009], JL ChatCom, Inc., ChatterBox Communications and Server Solutions [online], Retrieved from the Internet: <URL: http://web.archive.org/web/19970104221941/www.jlchatcom.com/chat4int.htm>, 2 pages.
413JL ChatCom, Inc.-Scaleable Application and Communication Servers, "ChatCom, Inc. Announces Complete Line of Scaleable Application and Communication Servers," Aug. 30, 1996 [retrieved on Dec. 2, 2009], JL ChatCom, Inc., ChatterBox Communications and Server Solutions [online], Retrieved from the Internet: , 4 pages.
414JL ChatCom, Inc.—Scaleable Application and Communication Servers, "ChatCom, Inc. Announces Complete Line of Scaleable Application and Communication Servers," Aug. 30, 1996 [retrieved on Dec. 2, 2009], JL ChatCom, Inc., ChatterBox Communications and Server Solutions [online], Retrieved from the Internet: <URL: http://web.archive.org/web/19970104221932/www.jlchatcom.com/cpofrel.htm>, 4 pages.
415Kelly Spang, "Component House: Design Technology for PCs in a snap'-NeoSystmes Offers Building Blocks", Computer Reseller News, Apr. 21, 1997, Issue 732, Section: Channel Assembly, http://www.techweb.com/se/directlink.cgi?CRN19970421S0054.
416Kelly Spang, "Component House: Design Technology for PCs in a snap'—NeoSystmes Offers Building Blocks", Computer Reseller News, Apr. 21, 1997, Issue 732, Section: Channel Assembly, http://www.techweb.com/se/directlink.cgi?CRN19970421S0054.
417Khan, M. F., "Ethernet Switch Card Design Specification," Mar. 8, 2001, White Cross Systems Limited, pp. 1-32.
418Khan, M. F., "Ethernet Switch Card Layout Specifications," Mar. 8, 2001, pp. 1-31.
419KTI Networks, "Installation Guide 10/100 Dual-speed Fast Ethernet PCI Acdapters", Doc.990420-KF230TX/2-K, P/N: 750-0124-001, 1999, 24 pgs.
420Lazik, G., "Remote Access—a Historical Perspective," Network News, vol. 3, No. 7, NPA The Network Professional Association, Jul. 1994, 6 pages.
421Lazik, G., "Remote Access—Part II, Cost Analysis," Network News, vol. 3, No. 8, NPA The Network Professional Association, Sep. 1994, 5 pages.
422Letter Martiniak to Byers regarding Proposed Amendment to the Invalidity Contentions based on products from RLX Systems and a description of RLX products, dated Jul. 15, 2010, 2 pages.
423Letter to Barac from Pacotti, Jr. with attachments on WhiteCross Data Exploration, undated, 12 pages.
424Liquorman, "Convergent Technologies Had This Idea" (Dec. 5, 1997).
425Maintenance and Service Guide, Compaq Armada 4100 and 4200 Families of Personal Computers, 190 pages.
426Mamakos, L. et al., "Request for Comments 2516—A method for Transmitting PPP Over Ethernet (PPPoE)," [online], 1999, [retrieved on Aug. 18, 2010], Retrieved from the Internet: <URL: http://ttols.ietf.org/html/rfc2516>, 35 pages.
427 *Marcel Boosten, "Transmission overhead and optimal packet size", Mar. 11, 1998, printed on: Jan. 28, 2011, 2 pages.
428McKenzie, L., "Fujitsu Reaches Deal in Acqis Blade Server IP Spat," Law360 [online], [retrieved on Jun. 16, 2010], Retrieved from the Internet at <URL: http://ip.law360.com/print—article/175004>, 2 pages.
429Miastkowski, S. (Editor), "A Whale of a System," BYTE, Aug. 1991, 4 pages, vol. 16, No. 8.
430Micronet, "SP2500R Series EtherFast 10/100 Mbps Adapter User's Guide", Document Version 2.0, 10 pgs.
431Microsoft Cluster Service Center, "MSCS Basics," downloaded from >, Feb. 7, 2005, 4 pages total.
432Microsoft Cluster Service Center, "MSCS Basics," downloaded from <http://www.nwnetworks.com/mscsbasics.htm>>, Feb. 7, 2005, 4 pages total.
433Microsoft Press Computer Dictionary, Second Edition, pp. 82, 92, 93 and 260, Alice Smith ed., Microsoft Press, 1994, 13 pages.
434Microsoft Press Computer Dictionary, Third Ed., pp. 96, 313, and 355, Kim Fryer ed., Microsoft Press, 1997, 5 pages.
435Microsoft Press Computer User's Dictionary, pp. 232, 262, and 275, Kim Fryer ed., Microsoft Press, 1998, 12 pages.
436Microsoft Press Computer User's Dictionary, pp. 82 and 232, Kim Fryer ed., Microsoft Press, 1998, 5 pages.
437MP700 User Guide, Issue 0.0.89, Network Engines, Inc., Oct. 16, 1997, 29 pages.
438MPL Brochure "1st Rugged All in One Industrial 486FDX-133 MHz PC" pp. 1-2, downloaded from the internet at. http://www.mpl.ch/DOCs/ds-48600.pdf on Feb. 15, 2006.
439MPL Brochure "IPM 486 Brochure/IPM5 User manual" pp. 1-9 downloaded from the internet at http://www.mpl.ch/DOCs/u48600xd.pdf on Feb. 15, 2006.
440MPL, "The First Rugged All-in-One Industrial 486FDX-133 MHz PC"IPM 486 Brochure/IPM5 User manual, 1998, pp. 1-52.
441National Semiconductor Product Folder, "DS90CR215 Plus-3.3V Rising Edge Data Strobe LVDS 21-Bit Channel and Link—66 MHz," National Semiconductor Corporation [online], [retrieved on Oct. 30, 1997]. Retrieved from the Internet at <URL: http://www.national.com/search/search.cgi/design?keywords=DS90CR215>, 2 pages.
442National Semiconductor, DS90CR215/DS90CR216 +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link-66 MHz, Jul. 1997, 2 pages.
443NEC, "Server HX4500 Users Guide," PN: 456-00005-000, Dec. 1998, 160 pages.
444Network Engines ClusterDirector Users' Manual, Network Engines, Inc., Jan. 1998, 52 pages.
445Network Engines ClusterDirector Users' Manual, Revision B, Network Engines, Inc., Jun. 1998, 88 pages.
446Network Engines Network, Network Engines, Inc., Jun. 22, 1999, 20 pages.
447Network Engines P6000 System Guide, Revision C, Network Engines, Inc., Jul., 1998, 89 pages.
448Network Engines P6000EXP System Guide, Revision A, Network Engines, Inc., Jan., 1998, 106 pages.
449Network Engines Website, Network Engines, Inc., retrieved on Feb. 27, 1998, URL: http://www.networkengines.com/, 12 pages.
450Network Engines, "P6000EXP Fault-tolerant Load-balanced Clustered Server," 1997, 3 pages.
451Network Engines, Inc., Company Overview, Aug. 26, 2010, 21 pages.
452Network Engines, Inc., Network Engines ClusterDirector User's Manual, Jun. 1998, 32 pages.
453Network Engines™ SBC1000 User's Manual, Rev. E Draft, Network Engines, Inc., Jun. 1998, 78 pages.
454Network Engines™ SBC2000 User's Manual, Rev. 1.0, Network Engines, Inc., Jul. 1998, 140 pages.
455Network Engines™ SBC2000S Reference Guide, Rev. 1.0, Network Engines, Inc., Sep. 1998, 156 pages.
456Network Engines™ SBC2000ST Reference Guide, Rev. A, Network Engines, Inc., Oct. 1998, 178 pages.
457Nicholls, T., "9800 First level design," White Cross Systems Limited, Mar. 26, 1997, 26 pages.
458Nicholls, T., "9800 System Architecture," White Cross Systems Limited, Mar. 27, 1997, 28 pages.
459Novell, Inc., "Novell's NetWare 4.1 Momentum Continues—NetWare 4 Now World's Best-Selling Network Operating System," [online], Mar. 21, 1996, [retrieved on Nov. 16, 2009]. Retrieved from the Internet: <URL: http://www.novell.com/news/press/archive/1996/03/pr96056.html>, 2 pages.
460Office Action for RE 41,076, mailed Dec. 30, 2008, 8 pages.
461Office Action for RE 41,076, mailed Feb. 11, 2008, 62 pages.
462Office Action for RE 41,076, mailed Jul. 13, 2007, 38 pages.
463Office Action for RE 41,076, mailed Jun. 9, 2008, 25 pages.
464Office Action for RE 41,076, mailed Oct. 17, 2007, 55 pages.
465Office Action for RE 41,092, mailed Sep. 17, 2008, 8 pages.
466Office Action for RE 41,294, mailed Apr. 15, 2008, 10 pages.
467Office Action for RE 41,294, mailed Nov. 16, 2007, 10 pages.
468Office Action for RE 41,294, mailed Sep. 16, 2008, 11 pages.
469Office Action for U.S. Appl. No. 09/312,199, mailed Mar. 26, 2003, 5 pages.
470Office Action for U.S. Appl. No. 09/642,628, mailed Apr. 5, 2001, 9 pages.
471Office Action for U.S. Appl. No. 10/963,825, mailed May 14, 2009, 5 pages.
472Office Action for U.S. Appl. No. 10/963,825, mailed May 31, 2006, 29 pages.
473Office Action for U.S. Appl. No. 10/963,825, mailed Oct. 20, 2006, 28 pages.
474Office Action for U.S. Appl. No. 10/963,825, mailed Oct. 27, 2005, 25 pages.
475Office Action for U.S. Appl. No. 10/963,825, mailed Sep. 15, 2009, 14 pages.
476Office Action for U.S. Appl. No. 11/545,056, mailed Mar. 12, 2010, 26 pages.
477Office Action for U.S. Appl. No. 12/322,858, mailed Jun. 25, 2010, 22 pages.
478Office Action for U.S. Appl. No. 12/322,858, mailed Mar. 4, 2010, 24 pages.
479Office Action for U.S. Appl. No. 12/561,138, mailed Sep. 29, 2010, 4 pages.
480Office Action for U.S. Appl. No. 12/577,074, mailed Apr. 13, 2010, 7 pages.
481Office Action for U.S. Appl. No. 12/577,074, mailed Nov. 10, 2010, 6 pages.
482Office Action for U.S. Patent No. 6,216,185, mailed Apr. 12, 2000, 9 pages.
483Office Action for U.S. Patent No. 6,216,185, mailed Aug. 25, 2000, 9 pages.
484Office Action for U.S. Patent No. 6,345,330, mailed Jun. 15, 2000, 7 pages.
485Office Action for U.S. Patent No. 6,345,330, mailed Mar. 23, 2001, 6 pages.
486Office Action for U.S. Patent No. 6,718,415, mailed Jan. 29, 2003, 7 pages.
487Office Action for U.S. Patent No. 6,718,415, mailed Jun. 4, 2003, 8 pages.
488Office Action for U.S. Patent No. 6,718,415, mailed Oct. 10, 2002, 7 pages.
489Office Action for U.S. Patent No. 7,328,297, mailed Feb. 8, 2007, 5 pages.
490Office Action for U.S. Patent No. 7,328,297, mailed Jul. 12, 2007, 13 pages.
491Office Action for U.S. Patent No. 7,363,415, mailed on Apr. 12, 2007, 23 pages.
492Office Action for U.S. Patent No. 7,363,416, mailed Apr. 12, 2007, 23 pages.
493Office Action for U.S. Patent No. 7,376,779, mailed Sep. 28, 2007, 24 pages.
494Office Action for U.S. Patent No. 7,676,624, mailed Dec. 1, 2008, 8 pages.
495Office Action for U.S. Patent No. 7,818,487, mailed Sep. 29, 2009, 10 pages.
496Office Action for U.S. Publication No. 2010/0174844, mailed Oct. 28, 2010, 11 pages.
497Office Action in Ex Parte Reexamination of US Patent No. 6,216,185, Control No. 90/010,816, mailed Jul. 27, 2010, 103 pages.
498Office Action in Inter Partes Reexamination of US Patent No. 6,718,415, Control No. 95/001,276, mailed May 26, 2010, 39 pages.
499Office Action in Inter Partes Reexamination of US Patent No. 7,099,981, Control No. 95/001,310, mailed Jul. 6, 2010, 83 pages.
500Office Action in Inter Partes Reexamination of US Patent No. 7,146,446, Control No. 95/001,328, mailed Jun. 24, 2010, 86 pages.
501Office Action in Inter Partes Reexamination of US Patent No. 7,328,297, Control No. 95/001,336, mailed Aug. 4, 2010, 95 pages.
502Office Action in Inter Partes Reexamination of US Patent No. 7,363,415, Control No. 95/001,424, mailed Nov. 1, 2010, 75 pages.
503Office Action in Inter Partes Reexamination of US Patent No. 7,363,416, Control No. 95/001,476, mailed Dec. 6, 2010, 63 pages.
504Office Action in Inter Partes Reexamination of US Patent No. 7,376,779, Control No. 95/001,475, mailed Dec. 20, 2010, 105 pages.
505Origin and Onyx Theory of Operations Manual, Document No. 007-3439-002, 1997, Silicon Graphics, Inc., 124 pages.
506Origin2000 Rackmount Owner's Guide, Document No. 007-3456-003, 1997, Silicon Graphics, Inc., 146 pages.
507P6000 System Price Guide, Network Engines, Inc., Feb. 24, 1998, 9 pages.
508Patent Owner's Response to Office Action in Ex Parte Reexamination of US Patent No. 6,216,185, Control No. 90/010,816, filed Sep. 27, 2010, 55 pages.
509Patent Owner's Response to Office Action in Inter Partes Reexamination of US Patent No. 6,718,415, Control No. 95/001,276, Exhibit A, Declaration of William Henry Mangione-Smith under 37 C.F.R. 1.132, filed Jul. 27, 2010, 29 pages.
510Patent Owner's Response to Office Action in Inter Partes Reexamination of US Patent No. 6,718,415, Control No. 95/001,276, filed Jul. 27, 2010, 41 pages.
511Patent Owner's Response to Office Action in Inter Partes Reexamination of US Patent No. 7,099,981, Control No. 95/001,310, Exhibit A, Declaration of William Henry Mangione-Smith under 37 C.F.R. 1.132, filed Sep. 3, 2010, 63 pages.
512Patent Owner's Response to Office Action in Inter Partes Reexamination of US Patent No. 7,099,981, Control No. 95/001,310, filed Sep. 3, 2010, 52 pages.
513Patent Owner's Response to Office Action in Inter Partes Reexamination of US Patent No. 7,146,446, Control No. 95/001,328, Exhibit A, Declaration of William Henry Mangione-Smith under 37 C.F.R. 1.132, filed Sep. 3, 2010, 61 pages.
514Patent Owner's Response to Office Action in Inter Partes Reexamination of US Patent No. 7,146,446, Control No. 95/001,328, filed Aug. 24, 2010, 45 pages.
515Patent Owner's Response to Office Action in Inter Partes Reexamination of US Patent No. 7,328,297, Control No. 95/001,336, Exhibit A, Declaration of William Henry Mangione-Smith under 37 C.F.R. 1.132, filed Oct. 4, 2010, 61 pages.
516Patent Owner's Response to Office Action in Inter Partes Reexamination of US Patent No. 7,328,297, Control No. 95/001,336, filed Oct. 4, 2010, 49 pages.
517PC Magazine, "Think Modular" (Jun. 10, 1997).
518PCI Local Bus Specification, Rev. 2.1, the PCI Special Interest Group, Jun. 1, 1995, 298 pages.
519PCI Local Bus, "PCI Local Bus Specification", Revision 2.2, Dec. 18, 1998, 322 pgs.
520Pentium Processor™ Network Engines™ P586 Guide, Issue 0.0.20 Preliminary, Network Engines, Inc., Nov. 10, 1997, 58 pages.
521Pentium Processor™ Network Engine™ Manual, Network Engines, Inc., undated, 56 pages.
522Phillips, J., "9800 Auxiliary PSU Design Specification," Revision 1.00, White Cross Systems Limited, Oct. 27, 1997, 13 pages.
523Phillips, J., "9800 Disk Card Design Specification," May 26, 1998, White Cross Systems Limited, pp. 1-44.
524Phillips, J., "9800 Disk Card Layout Specification," Apr. 6, 1998, White Cross Systems Limited, pp. 1-22.
525Phillips, J., "9800 Power System Backplane Design Specification," Revision 1.00, White Cross Systems Limited, Oct. 22, 1997, 11 pages.
526Phillips, J., "9800 Processor Card Design Specification," Feb. 25, 1998, White Cross Systems Limited, pp. 1-41.
527Phillips, J., "9800 Processor Card Layout Specification," Sep. 29, 1997, White Cross Systems Limited, pp. 1-13.
528Powerstation Technologies P6000 System Guide, Powerstation Technologies, Inc., 1996, 65 pages.
529Press Release: Hiawatha, Iowa, (Mar. 1. 1997) entitled "Crystal Group Products Offer Industrial PCs with Built-in Flexibility", >, downloaded from web on May 14, 2004, 2 pgs.
530Press Release: Hiawatha, Iowa, (Mar. 1. 1997) entitled "Crystal Group Products Offer Industrial PCs with Built-in Flexibility", <<http/www.crystalpc.com/news/pressreleases/prodpr.asp>>, downloaded from web on May 14, 2004, 2 pgs.
531Press Release: Kanata, Ontario, Canada, (Apr. 1998) entitled "Enhanced COTS SBC from DY 4 Systems features 166MHz Pentium(TM) Processor" >, 2 pgs.
532Press Release: Kanata, Ontario, Canada, (Apr. 1998) entitled "Enhanced COTS SBC from DY 4 Systems features 166MHz Pentium™ Processor" <<http://www.realtimeinfo.be/VPR/layout/display/pr.asp?PRID=363>>, 2 pgs.
533Product Brochure entitled "ERS/FT II System", (@2000) >, downloaded from web on Jun. 22, 2004, 4 pgs.
534Product Brochure entitled "SVME/DM-192 Pentium® II Single Board Computer" (Jun. 1999) pp. 1-9.
535Product Brochure entitled "System 8000", >, downloaded from web on Jun. 22, 2004, 4 pgs.
536Product Brochure entitled "ERS/FT II System", (@2000) <<http://64.173.211.7/support/techinfo/system/ersft2/ersft2.htm>>, downloaded from web on Jun. 22, 2004, 4 pgs.
537Product Brochure entitled "System 8000", <<http://www.bomara.com/Eversys/briefDefault.htm>>, downloaded from web on Jun. 22, 2004, 4 pgs.
538Product Manual entitled "ERS II and ERS/FT II", Chap. 3, System Components, >, downloaded from web on Jun. 22, 2004, 21 pgs.
539Product Manual entitled "ERS II and ERS/FT II", Chap. 3, System Components, <<http://64.173.211.7/support/techinfo/manuals/ers2/ers2-c3.htm>>, downloaded from web on Jun. 22, 2004, 21 pgs.
540QuantumNet, Inc., QuantumNet 6000 Sharing Modules [online], 1996 [retrieved on Nov. 16, 2009], Retrieved from the Internet: <URL: http://web.archive.org/web/19971011194326/www.quantumnet.com/dsq60xx.htm>, 3 pages.
541QuantumNet, Inc., QuantumNet 6500 Processor Modules [online], 1996 [retrieved on Nov. 16, 2009], Retrieved from the Internet: , 4 pages.
542QuantumNet, Inc., QuantumNet 6500 Processor Modules [online], 1996 [retrieved on Nov. 16, 2009], Retrieved from the Internet: <URL:http://web.archive.org/web/19971011194317/www.quantumnet.com/ds6500.htm>, 4 pages.
543QuantumNet, Inc., QuantumNet Product Overview [online], 1996 [retrieved on Nov. 16, 2009], Retrieved from the Internet: , 1 page.
544QuantumNet, Inc., QuantumNet Product Overview [online], 1996 [retrieved on Nov. 16, 2009], Retrieved from the Internet: <URL: http://web.archive.org/web/19971011194003/www.quantumnet.com/products.htm>, 1 page.
545QuantumNet, Inc., QuantumNet: The Next Generation Computing and Networking Environment [online], 1996 [retrieved on Nov. 16, 2009], Retrieved from the Internet: , 7 pages.
546QuantumNet, Inc., QuantumNet: The Next Generation Computing and Networking Environment [online], 1996 [retrieved on Nov. 16, 2009], Retrieved from the Internet: <URL: http://web.archive.org/web/19971011194123/www.quantumnet.com/qnetovw.htm>, 7 pages.
547QuantumNet, Inc., QuantumServer Chassis [online], 1996 [retrieved on Nov. 16, 2009], Retrieved from the Internet: , 3 pages.
548QuantumNet, Inc., QuantumServer Chassis [online], 1996 [retrieved on Nov. 16, 2009], Retrieved from the Internet: <URL: http://web.archive.org/web/19971011194309/www.quantumnet.com/dsq6000.htm>, 3 pages.
549Radigan, J., "A Solution to the Power Shortage?" CFO.com, Jan. 17, 2001, [online] Retrieved from the Internet on Dec. 14, 2007, Retrieved at URL: www.cfo.com/article.cfm/2991376?f=singlepage, 3 pages.
550Reply Brief for U.S. Appl. No. 10/963,825, filed Sep. 4, 2007, 4 pages.
551Request for Ex Parte Reexamination of US Patent No. 6,216,185, Control No. 90/010,816, Banankhah, Majid A., Nonfinal Office Action, Jun. 14, 2011, 44 pgs.
552Request for Ex Parte Reexamination of US Patent No. 6,216,185, Control No. 90/010,816, filed Jan. 8, 2010, 39 pages.
553Request for Ex Parte Reexamination of US Patent No. 6,216,185, Control No. 90/010,816, filed Jan. 8, 2010, Exhibit AA to Request Claim Charts with respect to the Hitachi '953 for Anticipation and Obviousness, 136 pages.
554Request for Ex Parte Reexamination of US Patent No. 6,216,185, Control No. 90/010,816, filed Jan. 8, 2010, Exhibit BB Claim Charts with respect to Kobayashi for Anticipation and Obviousness, 128 pages.
555Request for Ex Parte Reexamination of US Patent No. 6,216,185, Control No. 90/010,816, filed Jan. 8, 2010, Exhibit CC Claim Charts with respect to Byte for Anticipation and Obviousness, 122 pages.
556Request for Ex Parte Reexamination of US Patent No. 6,216,185, Control No. 90/010,816, filed Jan. 8, 2010, Exhibit DD Claim Charts with respect to the Hitachi '675 for Anticipation and Obviousness, 119 pages.
557Request for Inter Partes Reexamination of US Patent No. 6,718,415, Control No. 95/001,276, filed Dec. 2, 2009, 44 pages.
558Request for Inter Partes Reexamination of US Patent No. 6,718,415, Control No. 95/001,276, filed Dec. 2, 2009, Exhibit O, Declaration Under 37 CFR 1.132 of Vincent P. Conroy, Nov. 24, 2009, 3 pages.
559Request for Inter Partes Reexamination of US Patent No. 6,718,415, Control No. 95/001,276, Replacement Exhibit AA, Claim Charts with respect to QuantumNet for Anticipation and Obviousness, filed Jan. 5, 2010, 109 pages.
560Request for Inter Partes Reexamination of US Patent No. 6,718,415, Control No. 95/001,276, Replacement Exhibit BB, Claim Charts with respect to Chatcom for Anticipation and Obviousness, filed Jan. 5, 2010, 91 pages.
561Request for Inter Partes Reexamination of US Patent No. 6,718,415, Control No. 95/001,276, Replacement Exhibit CC, Claim Charts with respect to QuantumNet for Anticipation and Obviousness, filed Jan. 5, 2010, 85 pages.
562Request for Inter Partes Reexamination of US Patent No. 6,718,415, Control No. 95/001,276, Replacement Exhibit DD, Claim Charts with respect to the Origin2000 Manual for Obviousness, filed Jan. 5, 2010, 72 pages.
563Request for Inter Partes Reexamination of US Patent No. 6,718,415, Control No. 95/001,276, Replacement Exhibit EE, Claim Charts with respect to Gallagher for Anticipation and Obviousness, filed Jan. 5, 2010, 107 pages.
564Request for Inter Partes Reexamination of US Patent No. 7,099,981, Control No. 95/001,310, Exhibit AA, Claim Charts with respect to Gallagher for Anticipation and Obviousness, filed Feb. 9, 2010, 164 pages.
565Request for Inter Partes Reexamination of US Patent No. 7,099,981, Control No. 95/001,310, Exhibit BB, Claim Charts with respect to QuantumNet for Anticipation and Obviousness, filed Feb. 9, 2010, 158 pages.
566Request for Inter Partes Reexamination of US Patent No. 7,099,981, Control No. 95/001,310, Exhibit CC, Claim Charts with respect to Chatcom for Anticipation and Obviousness, filed Feb. 9, 2010, 167 pages.
567Request for Inter Partes Reexamination of US Patent No. 7,099,981, Control No. 95/001,310, Exhibit DD, Claim Charts with respect to the Eversys for Obviousness, filed Feb. 9, 2010, 111 pages.
568Request for Inter Partes Reexamination of US Patent No. 7,099,981, Control No. 95/001,310, filed Dec. 2, 2009, Exhibit O, Declaration Under 37 CFR 1.132 of Vincent P. Conroy, Nov. 24, 2009, 3 pages.
569Request for Inter Partes Reexamination of US Patent No. 7,099,981, Control No. 95/001,310, filed Feb. 9, 2010, 33 pages.
570Request for Inter Partes Reexamination of US Patent No. 7,146,446, Control No. 95/001,328, Exhibit AA (Part 1), Claim Charts with respect to Gallagher for Anticipation and Obviousness, filed Mar. 19, 2010, 186 pages.
571Request for Inter Partes Reexamination of US Patent No. 7,146,446, Control No. 95/001,328, Exhibit AA (Part 2), Claim Charts with respect to Gallagher for Anticipation and Obviousness, filed Mar. 19, 2010, 161 pages.
572Request for Inter Partes Reexamination of US Patent No. 7,146,446, Control No. 95/001,328, Exhibit BB (Part 1), Claim Charts with respect to QuantumNet for Anticipation and Obviousness, filed Mar. 19, 2010, 139 pages.
573Request for Inter Partes Reexamination of US Patent No. 7,146,446, Control No. 95/001,328, Exhibit BB (Part 2), Claim Charts with respect to QuantumNet for Anticipation and Obviousness, filed Mar. 19, 2010, 128 pages.
574Request for Inter Partes Reexamination of US Patent No. 7,146,446, Control No. 95/001,328, Exhibit CC, Claim Charts with respect to Chatcom for Anticipation and Obviousness, filed Mar. 19, 2010, 68 pages.
575Request for Inter Partes Reexamination of US Patent No. 7,146,446, Control No. 95/001,328, filed Mar. 19, 2010, 35 pages.
576Request for Inter Partes Reexamination of US Patent No. 7,328,297, Control No. 95/001,336, "Supplemental Comments by Third Party Requester" filed May 12, 2011, 32 pgs.
577Request for Inter Partes Reexamination of US Patent No. 7,328,297, Control No. 95/001,336, Exhibit AA, Claim Charts with respect to Gallagher for Obviousness, filed Apr. 19, 2010, 131 pages.
578Request for Inter Partes Reexamination of US Patent No. 7,328,297, Control No. 95/001,336, Exhibit BB, Claim Charts with respect to QuantumNet for Obviousness, filed Apr. 19, 2010, 139 pages.
579Request for Inter Partes Reexamination of US Patent No. 7,328,297, Control No. 95/001,336, Exhibit CC, Claim Charts with respect to Chatcom for Obviousness, filed Apr. 19, 2010, 114 pages.
580Request for Inter Partes Reexamination of US Patent No. 7,328,297, Control No. 95/001,336, filed Apr. 19, 2010, 33 pages.
581Request for Inter Partes Reexamination of US Patent No. 7,363,415, Control No. 95/001,424, Exhibit AA, Claim Charts with respect to Gallagher and Other References for Obviousness, filed Aug. 25, 2010, 114 pages.
582Request for Inter Partes Reexamination of US Patent No. 7,363,415, Control No. 95/001,424, Exhibit AB, Claim Charts with respect to Gallagher and Other References for Obviousness, filed Aug. 25, 2010, 92 pages.
583Request for Inter Partes Reexamination of US Patent No. 7,363,415, Control No. 95/001,424, Exhibit BA, Claim Charts with respect to QuantumNet and Other References for Obviousness, filed Aug. 25, 2010, 121 pages.
584Request for Inter Partes Reexamination of US Patent No. 7,363,415, Control No. 95/001,424, Exhibit BB, Claim Charts with respect to QuantumNet and Other References for Obviousness, filed Aug. 25, 2010, 99 pages.
585Request for Inter Partes Reexamination of US Patent No. 7,363,415, Control No. 95/001,424, Exhibit CA, Claim Charts with respect to Chatcom and Other References for Obviousness, filed Aug. 25, 2010, 91 pages.
586Request for Inter Partes Reexamination of US Patent No. 7,363,415, Control No. 95/001,424, Exhibit CB, Claim Charts with respect to Chatcom and Other References for Obviousness, filed Aug. 25, 2010, 94 pages.
587Request for Inter Partes Reexamination of US Patent No. 7,363,415, Control No. 95/001,424, filed Aug. 25, 2010, 34 pages.
588Request for Inter Partes Reexamination of US Patent No. 7,363,416, Control No. 95/001,476, Exhibit AA, Claim Charts with respect to Gallagher and Other References for Obviousness, filed Oct. 27, 2010, 70 pages.
589Request for Inter Partes Reexamination of US Patent No. 7,363,416, Control No. 95/001,476, Exhibit AB, Claim Charts with respect to Gallagher and Other References for Obviousness, filed Oct. 27, 2010, 64 pages.
590Request for Inter Partes Reexamination of US Patent No. 7,363,416, Control No. 95/001,476, Exhibit BA, Claim Charts with respect to QuantumNet and Other References for Obviousness, filed Oct. 27, 2010, 64 pages.
591Request for Inter Partes Reexamination of US Patent No. 7,363,416, Control No. 95/001,476, Exhibit BB, Claim Charts with respect to QuantumNet and Other References for Obviousness, filed Oct. 27, 2010, 71 pages.
592Request for Inter Partes Reexamination of US Patent No. 7,363,416, Control No. 95/001,476, Exhibit CA, Claim Charts with respect to Chatcom and Other References for Obviousness, filed Oct. 27, 2010, 64 pages.
593Request for Inter Partes Reexamination of US Patent No. 7,363,416, Control No. 95/001,476, Exhibit CB, Claim Charts with respect to Chatcom and Other References for Obviousness, filed Oct. 27, 2010, 67 pages.
594Request for Inter Partes Reexamination of US Patent No. 7,363,416, Control No. 95/001,476, filed Oct. 27, 2010, 37 pages.
595Request for Inter Partes Reexamination of US Patent No. 7,376,779, Control No. 95/001,475, "Comments by Third Party Requestor", filed Jun. 24, 2011, 24 pgs.
596Request for Inter Partes Reexamination of US Patent No. 7,376,779, Control No. 95/001,475, Banankhah, Majid A., Action Closing Prosecution, Apr. 27, 2011, 209 pgs.
597Request for Inter Partes Reexamination of US Patent No. 7,376,779, Control No. 95/001,475, Exhibit AA, Claim Charts with respect to Gallagher and Other References for Obviousness, filed Oct. 27, 2010, 128 pages.
598Request for Inter Partes Reexamination of US Patent No. 7,376,779, Control No. 95/001,475, Exhibit AB, Claim Charts with respect to Gallagher and Other References for Obviousness, filed Oct. 27, 2010, 153 pages.
599Request for Inter Partes Reexamination of US Patent No. 7,376,779, Control No. 95/001,475, Exhibit BA, Claim Charts with respect to QuantumNet and Other References for Obviousness, filed Oct. 27, 2010, 108 pages.
600Request for Inter Partes Reexamination of US Patent No. 7,376,779, Control No. 95/001,475, Exhibit BB, Claim Charts with respect to QuantumNet and Other References for Obviousness, filed Oct. 27, 2010, 112 pages.
601Request for Inter Partes Reexamination of US Patent No. 7,376,779, Control No. 95/001,475, Exhibit CA, Claim Charts with respect to Chatcom and Other References for Obviousness, filed Oct. 27, 2010, 112 pages.
602Request for Inter Partes Reexamination of US Patent No. 7,376,779, Control No. 95/001,475, Exhibit CB, Claim Charts with respect to Chatcom and Other References for Obviousness, filed Oct. 27, 2010, 118 pages.
603Request for Inter Partes Reexamination of US Patent No. 7,376,779, Control No. 95/001,475, filed Oct. 27, 2010, 35 pages.
604Response for RE 41,076, filed Apr. 7, 2008, 18 pages.
605Response for RE 41,076, filed Jan. 16, 2009, 14 pages.
606Response for RE 41,076, filed Sep. 26, 2007, 18 pages.
607Response for RE 41,092, filed Oct. 27, 2008, 27 pages.
608Response for RE 41,294, filed Dec. 20, 2007, 21 pages.
609Response for RE 41,294, filed Oct. 30, 2008, 14 pages.
610Response for U.S. Appl. No. 09/312,199, filed Jun. 11, 2003, 5 pages.
611Response for U.S. Appl. No. 10/963,825, filed Jan. 9, 2006, 22 pages.
612Response for U.S. Appl. No. 10/963,825, filed May 22, 2009, 2 pages.
613Response for U.S. Appl. No. 10/963,825, filed Oct. 1, 2009, 7 pages.
614Response for U.S. Appl. No. 11/545,056, filed Jun. 14, 2010, 18 pages.
615Response for U.S. Appl. No. 12/322,858, filed Jun. 4, 2010, 15 pages.
616Response for U.S. Appl. No. 12/322,858, filed Oct. 25, 2010, 12 pages.
617Response for U.S. Appl. No. 12/577,074, filed Jul. 13, 2010, 3 pages.
618Response for U.S. Patent No. 6,216,185, filed Aug. 3, 2000, 15 pages.
619Response for U.S. Patent No. 6,216,185, filed Oct. 24, 2000, 10 pages.
620Response for U.S. Patent No. 6,718,415, filed Mar. 6, 2003, 8 pages.
621Response for U.S. Patent No. 6,718,415, filed Nov. 7, 2002, 9 pages.
622Response for U.S. Patent No. 6,718,415, filed Sep. 4, 2003, 10 pages.
623Response for U.S. Patent No. 7,328,297, filed Apr. 19, 2007, 32 pages.
624Response for U.S. Patent No. 7,328,297, filed Jul. 23, 2007, 20 pages.
625Response for U.S. Patent No. 7,363,415, filed on Apr. 24, 2007, 25 pages.
626Response for U.S. Patent No. 7,363,416, filed Apr. 24, 2007, 23 pages.
627Response for U.S. Patent No. 7,376,779, filed Oct. 16, 2007, 23 pages.
628Response for U.S. Patent No. 7,676,624, filed Jan. 13, 2009, 14 pages.
629Response for U.S. Patent No. 7,818,487, filed Nov. 6, 2009, 3 pages.
630Response to Office Action for U.S. Patent No. 6,345,330, filed Jul. 19, 2001, 5 pages.
631Restriction Requirement for U.S. Patent No. 6,345,330, mailed Dec. 19, 2000, 5 pages.
632Revised Appellants' Brief for U.S. Appl. No. 10/963,825, filed Apr. 20, 2007, 34 pages.
633Rick Boyd-Merritt, "Upgradable-PC effort takes divergent paths", http://techweb.cmp.com/eet/news/97/949news/effort.html.
634RLX Blade, RLX Technologies, 2001, 2 pages.
635RLX System 324 Hardware Installation Guide, RLX Technologies, Inc., 2001, 80 pages.
636RLX System 324 Platform Guide: RLX Linux Web Server, RLX Technologies, Inc., 2001, 73 pages.
637RLX System 324 Platform Guide—Windows Powered Web Server—Online, undated, 39 pages.
638RLX System 324 Technical Guide: RLX Control Tower Backup/Restore, Draft, RLX Techologies, May 18, 2001, 8 pages.
639RLX System 324 Technical Guide: RLX Control Tower SNMP Implementation, RLX Techologies, 2001, 32 pages.
640RLX System 324 Technical Guide: RLX Control Tower SNMP Implementation, Supplementary Document, Draft, RLX Techologies, May 26, 2001, 48 pages.
641RLX Technologies Presentation, RLX Technologies, Inc., Apr. 27, 2001, 44 pages.
642RLX Technologies Presentation, RLX Technologies, Inc., Apr. 27, 2001, 53 pages.
643RocketLogix Presentation, RocketLogix, Inc., Apr., 6, 2000, 84 pages.
644Rodgers, A., "NT Clustering Hardware Readied, Vendor Racks up Windows NT Clustering Options at NetWorld+Interop," Internetweek, Oct. 20, 1997, 1 page.
645Rosencrance, L., "IBM agrees to resell RLX high-density servers," Computerworld, May 8, 2001, retrieved from the Internet on Jul. 25, 2001, Retrieved at URL: www.itworld.com/Comp/1362/CWD010508STO60353/pfindex.html, 3 pages.
646Silicon Graphics International, "Additional Information for: IRIS FailSafe Administrator's Guide (IRIX 6.4)," [online], Document No. 007-3109-003, Published Apr. 6, 1997, [retrieved on Nov. 5, 2009], Retrieved from the Internet: <URL: http://techpubs.sgi.com/library/tpl/cgi-bin/summary.cgi?coll=0640&db=bks&docnumber=...>, 2 pages.
647Smith, B., "Processor Backplane Design Specification," Feb. 3, 1998, White Cross Systems Limited, pp. 1-16.
648Smith, B., "Processor Backplane Layout Specification," Nov. 12, 1997, White Cross Systems Limited, pp. 1-7.
649Smith, B., Processor Backplane Functional Requirement Specification, Jul. 31, 1997, White Cross Systems Limited, pp. 1- 11.
650Spang, "Component House: Design Technology for 'PCs in a snap'-NeoSystems Offers Building Blocks" Techweb (Apr. 21, 1997:732).
651Spang, "Component House: Design Technology for ‘PCs in a snap’—NeoSystems Offers Building Blocks" Techweb (Apr. 21, 1997:732).
652Stallings, W., "Computer Organization and Architecture—Designing for Performance," Sixth Edition, Pearson Education, Inc., 2003, pp. 69-89.
653Sun Microsystems Computer Company, "Sun™ Enterprise™ 250 Server Owner's Guide," Jun. 1998, Part No. 805-5160-10, Revision A, 324 pages.
654Sun Microsystems, Inc., "UltraSPARC™ —II CPU Module, Datasheet 400 MHz CPU, 2.0 MP E-Cache," Jul. 1999, 28 pages.
655Sun Microsystems, Inc., White Paper, "Netra™ ft 1800," Apr. 1999, Revision 09, 50 pages.
656Supplemental Amendment Submitted with RCE for RE 41,294, filed Jul. 8, 2008, 12 pages.
657Supplemental Response for RE 41,294, filed Aug. 17, 2009, 3 pages.
658Supplemental Response for RE 41,294, filed Feb. 20, 2009, 13 pages.
659Supplemental Response for U.S. Patent No. 7,676,624, filed on Feb. 6, 2009, 13 pages.
660System 8000 Web Product Brief, Eversys Corporation, [retrieved on Oct. 22, 2009], Retrieved from the Internet: <URL: http://www.web.archive.org/web/1997052509465/www.eversys.com/Products/S8000/Brief/Index/htm, 6 pages.
661System 8000, Consolidated Network Server, Product Brief, Eversys Corporation, undated, 2 pages.
662System 8000, Consolidated Server, Presentation, Eversys Corporation, undated, 23 pages.
663Telecommunications Industries Association, "Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits," TIA/EIA Standard, TIA/EIA-644, Mar. 1996, 42 pgs.
664The American Heritage Dictionary, pp. 536, 607 and 770, Dell Publishing, 1994, 5 pages.
665The New IEEE Standard Dictionary of Electrical and Electronics Terms, Fifth Ed., p. 1236, The Institute of Electrical and Electronics Engineers, Inc., 1993, 3 pages.
666Thoms, I., "IBM Hit with $9M Judgment in Server Patent Suit," Law360 [online], [retrieved on May 3, 2011], Retrieved from the Internet at <URL: http://www.law360.com/articles/229575/print?section=ip>, 2 pages.
667Video Electronics Standards Association (VESA), Plug and Display (P&D) Standard, P&D and Digital Transition Minimized Differential Signaling (TMDS) Video Transmission Overview, 1997, Version 1, Revision 0, pp. 13 & 31-34.
668Whitecross Systems Limited, "Configuration & Maintenance Manual", Version 5.2, (Nov. 2002), 305 pgs.
669Whitecross Systems Limited, Data Exploration, "Configuration and Maintenance Manual", (Draft), (Jul. 2000), 354 pgs.
670Whitecross Systems Limited, Data Exploration, "WXDES—Technical Information," White Paper: R&D 99Q3-01, Sep. 3, 1999, pp. 1-38.
671Whitecross, "WX-DES Hardware Maintenance Course" (2000), 72 pgs.
672Whitecross, "WX-DES Technical Overview", System Architecture of the 9800 Model of the WhiteCross Data Exploration Server, (WX/DES), (2000), 211 pgs.
673Williams, Dennis "EVERSYS Corp. System 8000", Feb. 17, 1997) > downloaded from web on Jun. 22, 2004, 4 pgs.
674Williams, Dennis "EVERSYS Corp. System 8000", Feb. 17, 1997) <<http://www.lantimes.com/testing/97feb/702b070b.html>> downloaded from web on Jun. 22, 2004, 4 pgs.
675Williams, Dennis, "ChatCom Inc. Chatterbox", (Feb. 17, 1997) > downloaded from web on. Jun. 23, 2004, 3 pgs.
676Williams, Dennis, "Consolidated Servers", (Feb. 17, 1997) > downloaded from web on Jun. 23, 2004, 2 pgs.
677Williams, Dennis, "Cubix Corp. ERS/FT II", (Feb. 17, 1997) > downloaded from web on Jun. 23, 2004, 4 pgs.
678Williams, Dennis, "Executive Summary: Consolidate Now", (Feb. 17, 1997) > downloaded from web on Jun. 23, 2004, 2 pgs.
679Williams, Dennis, "Top Scores for Useability and Openness", (Feb. 17, 1997) > downloaded from web on Jun. 23, 2004, 2 pgs.
680Williams, Dennis, "ChatCom Inc. Chatterbox", (Feb. 17, 1997) <<http://www.lantimes.com/testing/97feb/702b066a.html>> downloaded from web on. Jun. 23, 2004, 3 pgs.
681Williams, Dennis, "Consolidated Servers", (Feb. 17, 1997) <<http://www.lantimes.com/testing/97compare/pcconsol.html>> downloaded from web on Jun. 23, 2004, 2 pgs.
682Williams, Dennis, "Cubix Corp. ERS/FT II", (Feb. 17, 1997) <<http://www.lantimes.com/testing/97feb/702b068b.html>> downloaded from web on Jun. 23, 2004, 4 pgs.
683Williams, Dennis, "Executive Summary: Consolidate Now", (Feb. 17, 1997) <<htttp://ww.lantimes.com/testing/97feb/702b064a.html>> downloaded from web on Jun. 23, 2004, 2 pgs.
684Williams, Dennis, "Top Scores for Useability and Openness", (Feb. 17, 1997) <<http://www.lantimes.com/testing/97feb/702b064a.html>> downloaded from web on Jun. 23, 2004, 2 pgs.
685Windows Magazine, "Cubix PowerSMP Series 4000", Nov. 1997, > downloaded from the web on Jun. 22, 2004, p. NT07.
686Windows Magazine, "Cubix PowerSMP Series 4000", Nov. 1997, <http://<www.techweb.com/winmag/library/1997/1101/ntent008.htm>> downloaded from the web on Jun. 22, 2004, p. NT07.
687Wolfpack or Microsoft Cluster Services on Star System, (undated), 3 pgs.
688World Wide System Price Guide, Network Engines, Inc., Sep. 26, 1997, 10 pages.
689Ziatech Corporation, "Ketris 9000 System Hardware Manual", (2000), 46 pgs.
690Ziatech Corporation, "Ketris Manager Software Manual", (2000), 28 pgs.
691Ziatech Corporation, "Ketris Media Blade Hardware Manual", (2000), 17 pgs.
692Ziatech Corporation, "Ketris Server Blade Hardware Manual", (2000), 60 pgs.
693Ziatech Corporation, "Ketris System Management Overview", (Jun. 22, 2000), 4 pgs.
694Ziatech Corporation, "Ketris9000 Product Manual", (Aug. 1, 2000), 4 pgs.
695Ziatech Corporation, "STD 32 Star System Multiprocessing Computer System", Product Description (Sep. 17, 1998), 6 pgs.
696Ziatech Corporation, "New STD 32 Fault Tolerant Computer Provides Modular Platform for ‘Non-Stop’ Applications," Feb. 5, 1996, 2 pgs.
697Ziatech Corporation, "System Designer's Guide: Hot Swap Capability on STD 32 Computers", (Jan. 1996), 6 pgs.
698Ziatech Corporation, STD 32 zVID2 Local Bus Super VGA/FPD Adapter, Apr. 1996, 2 pgs.
699Ziatech, "ZT 8907 Single Board Computer with IntelDX4(TM) Microprocessor", Product Description, (1998), 4 pgs.
700Ziatech, "Industrial BIOS for CompactPCI and STD 32 Systems", Software Manual for Industrial Bios Version 4.7, (Jul. 27, 1998), 134 pgs.
701Ziatech, "System Designer's Guide: Expanding STD Bus Performance Through Multiprocessing", (Apr. 1996), 6 pgs.
702Ziatech, "ZT 8907 Single Board Computer with IntelDX4™ Microprocessor", Product Description, (1998), 4 pgs.
703Ziatech, "ZT 8908 Single Board Computer with Pentium Processor or AMD-K6", Product Description, (Aug. 24, 1998), 6 pgs.
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Clasificaciones
Clasificación de EE.UU.726/34, 726/28, 455/347, 713/183, 455/349
Clasificación internacionalG06F21/00, G06F13/14, G06F1/16
Clasificación cooperativaG06F1/18, G06F1/181, G06F21/88, G06F21/34, G06F1/16, G06F1/1613
Clasificación europeaG06F1/16P, G06F1/16, G06F1/18E, G06F1/18, G06F21/88, G06F21/34
Eventos legales
FechaCódigoEventoDescripción
10 Sep 2013B1Reexamination certificate first reexamination
Free format text: THE PATENTABILITY OF CLAIMS 24-39, 41 AND 43-53 IS CONFIRMED. CLAIMS 1-23 WERE PREVIOUSLY CANCELLED. CLOAIMS 40 AND 42 ARE CANCELLED.
Free format text: THENPATENTABLILITY OF CLAIMS 24-39, 41 AND 43-53 IS CONFIRMED. CLAIMS 1-23 WERE PREVIOUSLY CANCELLED. CLAIMS 40 AND 42 ARE CANCELLED
29 Nov 2011RRRequest for reexamination filed
Effective date: 20111004
1 Nov 2011ASAssignment
Owner name: ACQIS LLC, TEXAS
Effective date: 20111101
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ACQIS TECHNOLOGY, INC.;REEL/FRAME:027154/0398
27 Mar 2009ASAssignment
Effective date: 19981028
Owner name: ACQIS TECHNOLOGY, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CHU, WILLIAM W.Y.;REEL/FRAME:022464/0974