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Número de publicaciónUSRE44383 E1
Tipo de publicaciónConcesión
Número de solicitudUS 12/109,280
Fecha de publicación16 Jul 2013
Fecha de presentación24 Abr 2008
Fecha de prioridad8 Feb 1997
También publicado comoUS6542998, US7036036, US20040083399, USRE44365, USRE45109, USRE45223
Número de publicación109280, 12109280, US RE44383 E1, US RE44383E1, US-E1-RE44383, USRE44383 E1, USRE44383E1
InventoresMartin Vorbach, Robert M. Münch
Cesionario originalMartin Vorbach, Robert M. Münch
Exportar citaBiBTeX, EndNote, RefMan
Enlaces externos: USPTO, Cesión de USPTO, Espacenet
Method of self-synchronization of configurable elements of a programmable module
US RE44383 E1
A method of synchronizing and reconfiguring configurable elements in a programmable unit is provided. A unit has a two- or multi-dimensional, programmable cell architecture (e.g., DFP, DPGA, etc.), and any configurable element can have access to a configuration register and a status register of the other configurable elements via an interconnection architecture and can thus have an active influence on their function and operation. By making synchronization the responsibility of each element, more synchronization tasks can be performed at the same time because independent elements no longer interfere with each other in accessing a central synchronization instance.
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What is claimed is:
1. A method for controlling data processing by an integrated circuit that includes a plurality of data processing elements that are arranged for at least one of arithmetically and logically processing data using a sequence of commands, the sequence including jumps, the method comprising:
for each of a plurality of the processing elements that each include includes at least one corresponding register:
predefining at least one corresponding configuration command; and
storing each of the at least one corresponding configuration command in one of the at least one register corresponding to the processing element;
processing data in at least one first processing element;
obtaining at least one of a comparison, a sign, a carry-over, and an error state during the processing of the data in the at least one first processing element;
in response to the at least one of the comparison, the sign, the carry-over, and the error state, generating for the at least one second processing element at least one first synchronization signal within a data stream during runtime;
processing data in the at least one second processing element in a stream-like manner; and
in response to the at least one first synchronization signal, selecting at least one particular command from the stored configuration commands in order to control a jump in the sequence.

This application is a reissue application of U.S. patent application Ser. No. 10/379,403, filed on Mar. 4, 2003, now U.S. Pat. No. 7,036,036, which is a continuation of U.S. patent application Ser. No. 09/369,653, filed Aug. 6, 1999, now U.S. Pat. No. 6,542,998 which is a continuation-in-part of PCT/DE98/00334, filed on Feb. 7, 1998 and is a continuation-in-part of U.S. patent application Ser. No. 08/946,812 filed on Oct. 8, 1997, now U.S. Pat. No. 6,081,903, and claims the benefit of the priority date dates of these cases under 35 U.S.C. §120, each of which is expressly incorporated herein by reference in its entirety. This application also claims the benefit, under 35 U.S.C. §119, of the priority date of German Application No. DE 19704728.9, filed on Feb. 8, 1997, under 35 U.S.C. §119, which is expressly incorporated herein by reference in its entirety. Further, more than one reissue application of U.S. Pat. No. 7,036,036 has been filed. Specifically, the reissue applications are application Ser. No. 12/109,280, application Ser. No. 12/909,061, application Ser. No. 12/909,150, and application Ser. No. 12/909,203, the latter three of which were all filed on Oct. 21, 2010 as divisional reissue applications of application Ser. No. 12/109,280.


Synchronization of configurable elements of today's modules, e.g., field programmable gate arrays (“FPGAs”), dynamically programmable gate arrays (“DPGAs”), etc., is usually accomplished using the clock of the module. This type of time-controlled synchronization poses many problems because it is often not known in advance how much time is needed for a task until a final result is available. Another problem with time-controlled synchronization is that the event on which the synchronization is based is not triggered by the element to be synchronized itself but rather by an independent element. In this case, two different elements are involved in the synchronization. This leads to a considerably higher administrative complexity.

European Patent No. 0 726 532 describes a method of controlling data flow in SIMD machines composed of several processors arranged as an array. An instruction is sent to all processors which dynamically selects the target processor of a data transfer. The instruction is sent by a higher-level instance to all processors (broadcast instruction) and includes a destination field and a target field. The destination field controls a unit in the processor element to dynamically determine the neighboring processor element to which the result is to be sent. The operand register of another processor element in which another result is to be stored is dynamically selected with the target field.


The present invention relates to a method which permits self-synchronization of elements to be synchronized. Synchronization is neither implemented nor managed by a central entity. By shifting synchronization into each element, more synchronization tasks can also be performed simultaneously, because independent elements no longer interfere with one another when accessing the central synchronization entity.

In accordance with an example embodiment of the present invention, in a module, e.g., a data flow processor (“DFP”) or a DPGA, with a two- or multi-dimensionally arranged programmable cell structure, each configurable element can access the configuration and status register of other configurable elements over an interconnecting structure and thus can have an active influence on their function and operation. A matrix of such cells is referred to below as a processing array (PA). The configuration can thus be accomplished by a load logic from the PA in addition to the usual method.


FIG. 1 shows how a loop construct can be implemented by using triggers, in accordance with an example embodiment of the present invention.

FIG. 2 shows how a comparison construct can be implemented by using multiple triggers, according to an example embodiment of the present invention.

FIG. 3 shows how a comparison construct with multiple outputs can be implemented by using multiple triggers and interleaving them, according to an example embodiment of the present invention.

FIG. 4 shows the required expansions, according to an example embodiment of the present invention, in comparison with conventional FPGAs and DFPs.

FIGS. 5a-5d show an example of the selection of different functions of the configurable elements by triggers, according to the present invention.

FIGS. 6 and 6a show an implementation of multiple configuration registers controlled by triggers for executing different functions, according to an example embodiment of the present invention.

FIGS. 7a and 7b shows an implementation of the method from FIG. 6 in microprocessors, according to an example embodiment of the present invention.


The present invention provides a module which is freely programmable during the running time and can also be reconfigured during the running time. Configurable elements on the chip have one or more configuration registers for different functions. Both read and write access to these configuration registers is permitted. In the method described here, it is assumed that a configuration can be set in an element to be configured for the following information.

    • Interconnection register. In this register, the type of connection to other cells is set.
    • Command register. The function of the configurable element to be executed is entered in this register.
    • Status register. The cell stores its instantaneous status in this register. This status provides other elements of the module with information regarding which processing cycle the cell is in.

A cell is configured by a command which determines the function of the cell to be executed. In addition, configuration data is entered to set the interconnection with other cells and the contents of the status register. After this operation, the cell is ready for operation.

To permit flexible and dynamic cooperation of many cells, each cell can have read or write access to all the configuration registers of another cell. Which of the many configuration registers is accessed by reading or writing is specified by the type of command with which the cell has been configured. Each command that can be executed by the cell exists in as many different types of addressing as there are different independent configuration registers in an element to be configured.

Example: A cell has the configuration register described above (interconnection, command and status) and is to execute the command ADD which performs an addition. It is then possible to select through the various types of ADD command where the result of this function is to be transferred.

  • ADD-A. The result is transferred to operand register A of the target cell.
  • ADD-B. The result is transferred to operand register B of the target cell.
  • ADD-V. The result is transferred to the interconnecting register of the target cell.
  • ADD-S. The result is transferred to the status register of the target cell.
  • ADD-C. The result is transferred to the command register of the target cell.

Control and Synchronization Trigger: In addition to the result, each cell can generate a quantity of trigger signals. The trigger signals need not necessarily be transferred to the same target cell as the result of processing the configured command. One trigger signal or a combination of multiple trigger signals triggers a certain action in the target cell or puts the cell in a certain state. A description of the states is also to be found in the text below. The following are examples of trigger signals:

    • GO trigger. The GO trigger puts the target cell in the READY state.
    • RECONFIG trigger. The RECONFIG trigger puts the target cell in the RECONFIG state, so the cell can be reprogrammed. This trigger is very useful, especially in conjunction with switching tables. If it is assumed that the data to be processed is loaded into the operand register at the rising edge of the clock pulse, processed in the period of the H level and written to the output register at the trailing edge, then the cell can be reconfigured at the trailing edge. The new configuration data is written to the command register at the trailing edge. The period of the L level is sufficient to conclude the reconfiguration successfully.
    • STEP trigger. The STEP trigger initiates unique execution of the configured command in the target cell in the WAIT state.
    • STOP trigger. The STOP trigger stops the target cell by putting the cell in the STOP state.

Due to the possibility of indicating in the processing cell into which register of the target cell the result is to be entered and which type of trigger signal is to be generated, a quantity of management data can be generated from a data stream. This management data is not a result of the actual task to be processed by the chip, but instead it serves only the functions of management, synchronization, optimization, etc. of the internal state.

Each cell can assume the following states which are represented by suitable coding in the status register, for example:

    • READY. The cell is configured with a valid command and can process data. Processing takes place with each clock cycle. The data is entered into the register of the target cell on the basis of the type of addressing of the cell sending the data.
    • WAIT. The cell has been configured with a valid command and can process data. Processing takes place on the basis of a trigger signal which can be generated by other elements of the module. The data is entered into the register of the target cell on the basis of the type of addressing of the cell sending the data.
    • CONFIG. This cell is not configured with a valid command. The data package sent to the cell with the next clock cycle is entered into the command register. The data package is entered into the command register in any case, regardless of which type of addressing was used by the cell sending the data.
    • CONFIG-WAIT. This cell is not configured with a valid command. A data package is entered with the next trigger signal which can be generated by other elements of the module and is written to the command register. The data package is entered into the command register in any case, regardless of which type of addressing was used by the cell sending the data.
    • RECONFIG. The cell is configured with a valid command, but it does not process any additional data, nor does it accept data. The cell can be reconfigured by another element of the module.
    • STOP. The cell is configured with a valid command, but it is not processing any data at the moment. The data is accepted by the cell (transferred to the input register) but is not processed further.

Due to these various states and the possibility of read and write access to the various registers of a cell, each cell can assume an active administrative role. In contrast with that, all existing modules of this type have a central management entity which must always know and handle the entire state of the module.

To achieve greater flexibility, there is another class of commands which change types after the first execution. Based on the example of the ADD command, a command is then as follows:

    • ADD-C-A. The result of the ADD function is written to the command register of the target cell with the first execution of the command. With each additional execution, the result is written to operand register A.

This possibility can be expanded as desired, so that even commands of the type ADD-C-V-A-C- . . . -B are conceivable. Each command can assume all permutated combinations of the various types of addressing and triggers.

Reconfiguration Control by RECONFIG Trigger: In the previous method, each element to be configured received a RECONFIG trigger from an external entity to enter the “reconfigurable” state. This had the disadvantage that distribution of the RECONFIG trigger necessitated a considerable interconnection and configuration expense: Due to the structure of the interconnection, this disadvantage can be eliminated. All configurable elements which are related by the interconnecting information represent a directional graph. Such a graph may have multiple roots (sources) and multiple leaves (targets). The configurable elements are expanded so that they propagate an incoming RECONFIG trigger in the direction of either their outgoing registers, their ingoing registers or a combination thereof. Due to this propagation, all the configurable elements that are directly connected to the configurable element also receive the RECONFIG trigger.

A configuration (graph) can be brought completely into the “reconfigurable” state by sending a RECONFIG trigger to all the roots and propagating the RECONFIG trigger in the direction of the output registers. The quantity of roots in a graph to which a RECONFIG trigger must be sent is considerably smaller than the total quantity of nodes in the graph. This greatly minimizes the complexity. Of course, a RECONFIG trigger may also be sent to all leaves. In this case, the RECONFIG trigger is propagated in the direction of the input registers.

Due to the use of both options or a combination of both methods, a minimum quantity of configurable elements to which a RECONFIG trigger must be sent can be calculated.

The configurable elements can receive an addition record to their status register, indicating whether or not an incoming RECONFIG trigger is to be propagated. This information is needed when two or more different graphs are connected at one or more points (i.e., they have a transition) and it is not desirable for one of the other graphs to enter the “reconfigurable” state. One or more configurable elements thus behave like a lock.

In addition, the status register can be expanded so that an additional entry indicates the direction in which an incoming RECONFIG trigger is to be relayed.

The method described here can be applied to all types of triggers and/or data. In this way, it is possible to establish an automatic distribution hierarchy needing very few access opportunities from the outside to set it in operation.

Implementation of Multiple Functions Simultaneously in the Same Configurable Elements

Basic Function and Required Triggers: An especially complex variant of calling up various macros by a condition is presented below: In execution of a condition (IF COMP THEN A ELSE B; where COMP is a comparison, and A and B are operations to be executed), no GO and STOP triggers are generated. Instead, a trigger vector (TRIGV) is generated, indicating to which result the comparison COMP has led. The trigger vector can therefore assume the states “equal,” “greater” or “less.”

The vector is sent to a following cell which selects exactly a certain configuration register (corresponding to A or B) from a plurality of configuration registers on the basis of the state of the vector. What this achieves is that, depending on the result of the preceding comparison, another function is performed over the data. States such as “greater-equal,” “less-equal” and “equal-not equal” are triggered by writing the same configuration data to two configuration registers. For example, with “greater-equal” the configuration register “greater” and the configuration register “equal” are written with the same configuration word, while the configuration register “less” contains another configuration word.

In implementating trigger vectors TRIGV, no restriction to the states “greater,” “less” and “equal” is necessary. To analyze large “CASE . . . OF” constructs, any number n representing the state of the CASE may be relayed as trigger vectors TRIGV-m to the downstream cell(s). In other words, n indicates the comparison within the CASE which was correct in analysis of the applied data. For implementation of the function assigned to the comparison within the CASE, n is relayed to the executing cells to select the corresponding function. Although the cells need at least three configuration registers in the “greater/less/equal” case, the number of configuration registers must correspond exactly to at least the maximum value of n (max (n)) when using TRIGV-m.

Propagation of the Required Function by Triggers: TRIGV/TRIGV-m are sent to the first cell processing the data. In this cell, TRIGV/TRIGV-M are analyzed and the data is processed accordingly. TRIGV/TRIGV-m are relayed (propagated) together with the data to the downstream cells. They are propagated to all cells executing a certain function on the basis of the analysis (IF or CASE). Propagation is linked directly to propagation of data packages, i.e., propagation is synchronous with the data. TRIGV/TRIGV-m generated at time t are linked to data present at time t at first processing cells CELLS1 (see FIG. 5: 0502, 0505, 0507). TRIG/TRIG-V are propagated so that the vectors are applied to the second processing cells with the data at time t+1, and at time t+2 they are applied to the third processing cells, etc., until TRIG/TRIG-V and the data are present at time t+m to the (m−1)th cells and at the same time to the last cells which depend on the comparison IF/CASE triggered by TRIG/TRIG-V.

A link is by no means such that the TRIG/TRIG-V generated at time t are linked to data applied to CELLS1 at time told<t.

Reacting to the Presence or Absence of Triggers: In special cases, it is necessary to react to the absence of a trigger, i.e., a trigger state occurs, but no change in trigger vector is initiated. Appropriate and important information can also be transferred to the downstream cells in this case. For example, in a comparison of “greater,” “less,” “equal,” the trigger signal “equal” is not present and does not change when switching from the state “less” to the state “greater.” Nevertheless, the absence of “equal” does contain information, namely “not equal.”

To be able to react to both states “present” and “not present,” an entry in the configuration register of the cell is added, indicating which of the states is to be reacted to.

Furthermore, a signal TRIGRDY indicating the presence of a trigger is added to trigger vector TRIGV representing states “equal,” “greater” and “less.” This is necessary because the state “not present” on one of the vectors does not provide any more information regarding the presence of a trigger per se.

TRIGRDY can be used as a handshake protocol between the transmitting cell and the receiving cell by having the receiving cell generate a TRIGACK as soon as it has analyzed the trigger vectors. Only after arrival of TRIGACK does the transmitting cell cancel the trigger state.

On the basis of an entry into the configuration register, a determination is made as to whether to wait for receipt of a TRIGACK or whether the trigger channel is to proceed unsynchronized when a trigger vector is sent out.

Use in Microprocessors

In microprocessors of the most recent architecture, conditional jumps are no longer executed by the known method of branch prediction, i.e., prediction of a jump. Speculative prediction of jumps introduced to increase processor performance calculated jumps in advance on the basis of speculative algorithms and had to reload the entire processor pipeline if the calculations were faulty, which led to a considerable loss of power.

To eliminate these losses, the new predicate/NOP method was introduced. A status flag one bit wide is assigned to each command, indicating whether the command is to be executed—or not. There may be any desired quantity of status flags. Commands are assigned to status flags by a compiler during the translation of the code. The status flags are managed by comparison operations assigned to them at the time of execution and indicate the result of the respective comparison.

Depending on the state of a status flag assigned to a command, the command is then executed by the processor (if the status flag indicates “execute”) or the command is not executed and is replaced by an NOP (if the status flag indicates “not execute”). NOP stands for “No OPERATION,” which means that the processor does not execute any operation in this cycle. Therefore, the cycle is lost for meaningful operations.

Two options are proposed for optimizing the cycle loss:

Multiple Command Registers per Computer Unit: A modem microprocessor has several relatively independent processors.

According to the trigger principle presented here, the individual processors are each equipped with several command registers, with a command register of a processor of a microprocessor being synonymous with a configuration register according to conventional FPGA, DFP, etc. modules. The respective active command register is selected

a) on the basis of trigger vectors generated by other processors on the basis of comparisons,

b) on the basis of multibit status flags (hereinafter referred to as status vectors) allocated to compare commands according to today's related art method.

Revised VLIW Command Set: One special embodiment is possible through VLIW command sets. Thus, several possible commands depending on one comparison can be combined to give one command within one command word. A VLIW word of any width is subdivided into any desired quantity of commands (codes). Each individual one of these codes is referenced by a trigger vector or a status vector. This means that one of the existing codes is selected from the VLIW word and processed during the running time.

The table illustrates a possible VLIW word with four codes referenced by a 2-bit trigger vector or a 2-bit status flag:

VLIW Command Word:

Code 0 Code 1 Code 2 Code 3


Trigger Vector/Status Flag:

00 01 10 11

Expansion of Hardware in Comparison with Conventional FPGAs and DFPs.

Additional Registers: A status register and a configuration register are added to the configuration registers conventionally used in DFPs. Both registers are controlled by the PLU bus and have a connection to the state machine of the sequence control system of the respective cell.

Change in PLU Bus: The configurable registers M-/F-PLUREG in FPGAs and DFPs are managed exclusively over the PLU bus, which represents the connection to the load logic. To guarantee the function according to the present invention, an additional access option must be possible through the normal system bus between the cells. The same thing is true for the new status register and configuration register.

The only part of the system bus relevant for the registers is the part that is interconnected to the PAE over the BM UNIT, i.e., the interface between the system buses and the PAE. Therefore, the bus is relayed from the BM UNIT to the registers where upstream multiplexers or upstream gates are responsible for switching between the PLU bus and the system bus relevant for the PAE. The multiplexers or gates are switched so that they always switch the system bus relevant for the PAE through, except after resetting the module (RESET) or when the RECONFIG trigger is active.

Expansions of Configurable Elements (PAEs) with Respect to Conventional FPGAs and DFPs: Trigger Sources: A configurable element can receive triggers from several sources at the same time. Due to this possibility, flexible semantics of the triggers can be achieved with the help of masking registers.

Multiple Configuration Registers: Instead of one configuration register, a PAE has multiple (max(n)) configuration registers.

Configuration State Machine and Multiplexer: Downstream from the configuration registers is a multiplexer which selects one of the possible configurations.

The multiplexer is controlled by a separate state machine or a state machine integrated into the PAE state machine, controlling the multiplexer on the basis of incoming trigger vectors.

Trigger Analysis and Configuration: A configurable element may contain a masking register in which it is possible to set the trigger inputs to which a trigger signal must be applied, so that the conditions for an action of the configurable element are met. A configurable element reacts not only to a trigger, but also to a set combination of triggers. In addition, a configurable element can perform prioritization of simultaneously incoming triggers.

Incoming triggers are recognized on the basis of the TRIGRDY signal. The trigger vectors are analyzed here according to configuration data also present in the configuration registers.

Trigger Handshake: As soon as the trigger vectors have been analyzed, a TRIGACK is generated for confirmation of the trigger vector.

BM UNIT: The BM UNIT is expanded so that it relays triggers coming from the bus to the sync unit and SM unit according to the configuration in M-PLUREG. Triggers generated by the EALU (e.g., comparator values “greater,” “less,” “equal,” 0 detectors, plus and minus signs, carry-overs, error states (division by 0, etc.), etc.) are relayed from the BM UNIT to the bus according to the wiring information in M-PLUREG.

Expansions of System Bus: The system bus, i.e., the bus system between the cells (PAEs), is expanded so that information is transferred together with the data over the target register. This means that an address which selects the desired register on receipt of the data is also sent. Likewise, the system bus is expanded by the independent transfer of trigger vectors and trigger handshakes.


FIG. 1 shows how a loop construct can be implemented by using triggers. In this example, a macro 0103 is to be executed 70 times. One execution of the macro takes 26 clock cycles. This means that counter 0101 may be decremented by one increment only once in every 26 clock cycles. One problem with freely programmable modules is that it is not always possible to guarantee that processing of macro 0103 will actually be concluded after 26 clock cycles. For example, a delay may occur due to the fact that a macro which is to supply the input data for macro 0103 may suddenly require 10 more clock cycles. For this reason, the cell in macro 0103 sends a trigger signal to counter 0101, causing the result of the calculation to be sent to another macro. At the same time, processing of macro 0103 by the same cell is stopped. This cell “knows” exactly that the condition for termination of a calculation has been reached.

In this case the trigger signal sent is a STEP trigger, causing counter 0101 to execute its configured function once. The counter decrements its count by one and compares whether it has reached a value of 0. If this is not the case, a GO trigger is sent to macro 0103. This GO trigger signal causes macro 0103 to resume its function.

This process is repeated until counter 0101 has reached a value of 0. In this case, a trigger signal is sent to macro 0102, where it triggers a function.

A very fine synchronization can be achieved due to this interaction of triggers.

FIG. 2 shows how a comparison construct can be implemented by using multiple triggers. FIG. 2 corresponds to the basic idea of FIG. 1. However, in this case the function in element 0202 is not a counter but a comparator. Macro 0201 also sends a comparison value to comparator 0202 after each processing run. Depending on the output of the comparison, different triggers are again driven to prompt an action in macros 0203, for example. The construct implemented in FIG. 2 corresponds to that of an IF query in a programming language.

FIG. 3 shows how a comparison construct with multiple outputs can be implemented by using multiple triggers and interleaving them. Here, as in FIG. 2, several comparators 0301, 0302 are used here to implement construction of an IF-ELSE-ELSE construct (or multiple choice). Due to the use of a wide variety of types of triggers and connections of these triggers to macros 0303, 0304, very complex sequences can be implemented easily.

FIG. 4 shows an example of some of the differences between the present invention and, for example, conventional FPGAs and DFPs. Additional configuration register 0401 and additional status register 0402 are connected to the SM UNIT over bus 0407. Registers 0401, 0402, F-PLUREG and M-PLUREG are connected to a gate 0403 by an internal bus 0206. Depending on position, this gate connects internal bus 0406 to PLU bus 0405 to permit configuration by the PLU or to the BM UNIT by a bus 0408. Depending on the address on data bus 0404, the BM UNIT relays the data to the O-REG or to addressed register 0401, 0402, F-PLUREG or M-PLUREG.

BM UNIT 0411 sends trigger signals over 0415 to SYNC UNIT 0412. 0411 receives results from the EALU over 0414 (“equal,” “greater,” “less,” “result=0,” “result positive,” “result negative,” carry-over (positive and negative), etc.) to convert the results into trigger vectors. As an alternative, states generated by the SYNC UNIT or the STATE MACHINE can be relayed to the BM UNIT over 0415.

The trigger signals transmitted by the BM UNIT to bus 0404 can be used there as STEP/STOP/GO triggers, RECONFIG triggers or for selecting a configuration register, depending on the configuration of the configurable elements to be analyzed. Which function a generated trigger will execute in the configurable elements to be analyzed is determined by interconnection 0404 and the configuration of the respective configurable element. One and the same trigger may have different functions with different configurable elements. 0416 is the result output of R-REGsft to bus system 0404 and the following configurable elements.

FIG. 5 shows the time response between generated triggers and the configuration registers selected by the triggers as an example. 0501 generates by comparison a trigger vector TRIGV, which can assume values “equal,” “greater,” or “less.” Configurable elements 0502-0504 process data independently of comparison 0501. Processing depends on comparison values “equal,” “greater” and “less.” Processing is pipelined, i.e., a data word is modified first by 0502, then by 0503 and finally by 0504. 0505 also processes data as a function of 0501. However, this is limited to the dependence on the comparison values “less”; “greater” and “equal” cause the same function to be carried out. Thus, a distinction is made between the values “less” and “greater than or equal to.” 0506 is connected downstream in pipeline 0505. 0506 reacts differently to “equal,” “greater” and “less” (see 0503). 0507 also depends on 0501, but a distinction is made between the values “equal” and “not equal (less or greater).” This embodiment begins at time t (FIG. 5a) and ends at time t+3. If the data passes through one of pipelines 0502, 0503, 0504 or 0505, 0506, it is delayed by one clock cycle in each execution in one of macros 0502-0506. Longer and especially different delays may also occur. Since there is a handshake mechanism between the data and trigger signals for automatic synchronization (according to the related art or this application (TRIGACK/TRIGRDY)), this case need not be discussed separately.

Due to the delays, data and trigger signals of the earlier time t−2 are available at time t between the second and third pipeline steps, for example.

FIGS. 5a through 5d show the sequence of three clock cycles t through t+2.

The trigger vectors (i.e., the results of the comparison) generated by 0501 look as follows over t:

Time t Result of comparison
t − 2 less
t − 1 greater
t equal
t + 1 greater
t + 2 equal

FIG. 6 shows the integration of several configuration registers into one configurable element. In this embodiment there are three configuration registers 0409 according to FIG. 4. These are configured over bus 0406. A control unit 0601 (which may also be designed as a state machine) receives signals TRIGV and TRIGRDY over bus system 0411. Depending on TRIGV, the control unit switches one of the configuration registers over multiplexer 0602 to bus system 0401 leading to the control mechanisms of the configurable element. For synchronization of the trigger signals with the internal sequences of the configurable element, 0601 has a synchronization output leading to synchronization unit 0412 or to state machine 0413. For synchronization of the trigger sources, 0601 generates handshake signal TRIGACK after processing the incoming trigger. In this embodiment, each configuration register 0409 is assigned to one TRIGV of the type “equal,” “greater,” “less.” If other operations are executed with each type of trigger, then each configuration register is occupied differently. For example, if a distinction is made only between “equal” and “not equal” then the configuration registers are occupied equally for the types “less” and “greater,” namely with the configuration for “not equal.” The configuration register for “equal” is occupied differently. This means that the comparison can be made more specific on the basis of the occupancy of the configuration registers, each configurable element being able to design this specification differently.

TRIGV is relayed together with the result over register 0603 to the downstream configurable elements to permit pipelining according to FIGS. 5a-d. The register and the handshake signals are controlled by 0412 or 0413. Trigger information together with the result from R-REGsft or with a time offset, i.e., before the result, can be sent over interface 0416 to downstream configurable elements.

A time-offset transfer offers the advantage that no additional time is necessary for setting the configuration registers in the downstream configurable elements, because the setting is made before receiving the data (simultaneously with the release of the result). FIG. 6a shows a corresponding timing (based on sequences conventional for DFP). Trigger vectors 0615 are generated at rising edge 0613 of module clock 0614. Triggers are analyzed in the configurable elements at trailing edge 0612. Data is phase shifted, i.e., released at 0612 and entered at 0613. The trigger vectors are transferred over the bus and data is calculated during 0610. Data is transferred over the bus and triggers are calculated during 0611, or configuration registers of the configurable elements are selected according to data stored at 0613 and the configuration is set accordingly.

FIG. 7a shows the management of jumps according to the predicate/NOP method of the related art. In execution of a comparison, an entry is made in predicate register 0704. This entry is queried during the execution of commands, determining whether a command is being executed (the command is inside the code sequence addressed by the conditional jump) or is replaced by an NOP (the command is in a different code sequence from that addressed by the conditional jump). The command is in comma id register 0701. The predicate register contains a plurality of entries allocated to a plurality of operations and/or a plurality of processors. This allocation is issued at the compile time of the program of the compiler. Allocation information 0707 is allocated to the command entered into the command register, so that a unique entry is referenced by the respective command.

0703 selects whether the command from 0701 or an NOP is to be executed. In execution of an NOP, one clock cycle is lost. 0703 has a symbolic character, because executing unit 0702 could also in principle be controlled directly by 0704.

In FIG. 7b there are n command registers (0701: Func 1 . . . Func n). In executing a comparison/conditional jump, the command register to be addressed, i.e., the result of the comparison, is deposited as an entry 0708 in predicate register 0706, where 0706 has a plurality of such entries. Respective entry 0708 in 0706 is so wide that all possible command registers of an executing unit 0702 can be addressed by it, which means that the width of an entry is log2(n) with n command registers. The predicate register contains a plurality of entries allocated to a plurality of operations and/or a plurality of processors. This allocation is issued by the compiler at the compile time of the program. Allocation information 0707 is allocated to the quantity of commands entered into the command registers, so that an unambiguous entry is referenced by the respective commands.

The multiplexer selects which command register supplies the code for the instantaneous execution.

Due to this technology, a valid command is executed instead of an NOP even in the worst case with conditional jumps, so no clock cycle is wasted.

The following provides an explanation of various names, functions and terms described above.

Name Convention

Assembly group UNIT
Type of operation MODE
Multiplexer MUX
Negated signal not
Register for PLU visible PLUREG
Register internal REG
Shift register sft

Function Convention

NOT Function!

0 1
1 0

AND Function &

0 0 0
0 1 0
1 0 0
1 1 1

OR Function #

0 0 0
0 1 1
1 0 1
1 1 1

GATE Function G

0 0
0 1
1 0 0
1 1 1


BM UNIT: Unit for switching data to the bus systems outside the PAE. Switching is done over multiplexers for the data inputs and gates for the data outputs. OACK lines are implemented as open collector drivers. The BM UNIT is controlled by the M-PLUREG.

Data receiver: The unit(s) that process(es) the results of the PAE further.

Data transmitter: The unit(s) that make(s) available the data for the PAE as operands.

Data word: A data word consists of a bit series of any desired length. This bit series represents a processing unit for a system. Commands for processors or similar modules as well as pure data can be coded in a data word.

DFP: Data flow processor according to German Patent/Unexamined Patent No. 44 16 881.

DPGA: Dynamically configurable FPGAs. Related art.

EALU: Expanded arithmetic logic unit. ALU which has been expanded by special functions which are needed or appropriate for operation of a data processing system according to German Patent No. 441 16 881 A1. These are counters in particular.

Elements: Collective term for all types of self-contained units which can be used as part of an electronic module. Elements thus include:

    • configurable cells of all types
    • clusters
    • blocks of RAM
    • logic
    • processors
    • registers
    • multiplexers
    • I/O pins of a chip

Event: An event can be analyzed by a hardware element of any type suitable for use and can prompt a conditional action as a reaction to this analysis. Events thus include, for example:

    • clock cycle of a computer
    • internal or external interrupt signal
    • trigger signal from other elements within the module
    • comparison of a data stream and/or a command stream with a value
    • input/output events
    • sequencing, carry-over, reset, etc. of a counter
    • analysis of a comparison

FPGA: Programmable logic module. Related art.

F-PLUREG: Register in which the function of the PAE is set. Likewise, the one shot and sleep mode are also set. The register is written by the PLU.

H level: Logic 1 level, depending on the technology used.

Configurable element: A configurable element is a unit of a logic module which can be set for a special function by a configuration word. Configurable elements are thus all types of RAM cells, multiplexers, arithmetic logic units, registers and all types of internal and external network writing, etc.

Configurable cell: See logic cells.

Configure: Setting the function and interconnecting a logic unit, an (FPGA) cell or a PAE (see: Reconfigure).

Configuration data: Any quantity of configuration words.

Configuration memory: The configuration memory contains one or more configuration words.

Configuration word: A configuration word consists of a bit series of any desired length. This bit series represents a valid setting for the element to be configured, so that a functional unit is obtained.

Load logic: Unit for configuring and reconfiguring the PAE. Embodied by a microcontroller specifically adapted to its function.

Logic cells: Configurable cells used in DFPs, FPGAs, DPGAs, fulfilling simple logic or arithmetic functions according to their configuration.

L level: Logic 0 level, depending on the technology used.

M-PLUREG: Register in which the interconnection of the PAE is set. The register is written by the PLU.

O-REG: Operand register for storing the operands of the EALU. Permits independence of the PAE of the data transmitters in time and function. This simplifies the transfer of data because it can take place in an asynchronous or package-oriented manner. At the same time, the possibility of reconfiguring the data transmitters independently of the PAE or reconfiguring the PAE independently of the data transmitters is created.

PLU: Unit for configuring and reconfiguring the PAE. Embodied by a microcontroller specifically adapted to its function.

Propagate: Controlled relaying of a received signal.

RECONFIG: Reconfigurable state of a PAE.

RECONFIG trigger. Setting a PAE in the reconfigurable state.

SM UNIT: State machine UNIT. State machine controlling the EALU.

Switching table: A switching table is a ring memory which is addressed by a control. The entries in a switching table may accommodate any desired configuration words. The control can execute commands. The switching table reacts to trigger signals and reconfigures configurable elements on the basis of an entry in a ring memory.

Synchronization signals: Status signals generated by a configurable element or a processor and relayed to other configurable elements or processors to control and synchronize the data processing. It is also possible to return a synchronization signal with a time lag (stored) to one and the same configurable element or processor.

TRIGACK/TRIGRDY: Handshake of the triggers.

Trigger: Synonymous with synchronization signals.

Reconfigure: Configuring any desired quantity of PAEs again while any desired remaining quantity of PAEs continue their own function (see: Configure).

Processing cycle: A processing cycle describes the period of time needed by a unit to go from one defined and/or valid state into the next defined and/or valid state.

VLIW: Very large instruction word. Coding of microprocessors, prior art method.

Cells: Synonymous with configurable elements.

Citas de patentes
Patente citada Fecha de presentación Fecha de publicación Solicitante Título
US206747720 Mar 193112 Ene 1937Allis Chalmers Mfg CoGearing
US324299823 May 196329 Mar 1966Wolf Electric Tools LtdElectrically driven equipment
US368157813 Nov 19701 Ago 1972Marconi Co LtdFault location and reconfiguration in redundant data processors
US375300814 Jun 197114 Ago 1973Honeywell Inf SystemsMemory pre-driver circuit
US375760822 Nov 197111 Sep 1973Bhs Bayerische BergSolar and planetary gear system with load pressure compensation
US385557711 Jun 197317 Dic 1974Texas Instruments IncPower saving circuit for calculator system
US415161128 Mar 197724 Abr 1979Tokyo Shibaura Electric Co., Ltd.Power supply control system for memory systems
US449813426 Ene 19825 Feb 1985Hughes Aircraft CompanySegregator functional plane for use in a modular array processor
US449817226 Jul 19825 Feb 1985General Electric CompanySystem for polynomial division self-testing of digital networks
US456610218 Abr 198321 Ene 1986International Business Machines CorporationParallel-shift error reconfiguration
US457173631 Oct 198318 Feb 1986University Of Southwestern LouisianaDigital communication system employing differential coding and sample robbing
US459197925 Ago 198327 May 1986Nec CorporationData-flow-type digital processing apparatus
US459468222 Dic 198210 Jun 1986Ibm CorporationVector processing
US462399713 Dic 198418 Nov 1986United Technologies CorporationCoherent interface with wraparound receive and transmit memories
US466370614 Oct 19835 May 1987Tandem Computers IncorporatedMultiprocessor multisystem communications network
US46822846 Dic 198421 Jul 1987American Telephone & Telegraph Co., At&T Bell Lab.Queue administration method and apparatus
US468638618 Mar 198511 Ago 1987Oki Electric Industry Co., Ltd.Power-down circuits for dynamic MOS integrated circuits
US470621627 Feb 198510 Nov 1987Xilinx, Inc.Configurable logic element
US472078017 Sep 198519 Ene 1988The Johns Hopkins UniversityMemory-linked wavefront array processor
US473947410 Mar 198319 Abr 1988Martin Marietta CorporationGeometric-arithmetic parallel processor
US476175511 Jul 19842 Ago 1988Prime Computer, Inc.Data processing system and method having an improved arithmetic unit
US479160318 Jul 198613 Dic 1988Honeywell Inc.Dynamically reconfigurable array logic
US481121414 Nov 19867 Mar 1989Princeton UniversityMultinode reconfigurable pipeline computer
US485204320 May 198725 Jul 1989Hewlett-Packard CompanyDaisy-chain bus system with truncation circuitry for failsoft bypass of defective sub-bus subsystem
US485204812 Dic 198525 Jul 1989Itt CorporationSingle instruction multiple data (SIMD) cellular array processing apparatus employing a common bus where a first number of bits manifest a first bus portion and a second number of bits manifest a second bus portion
US48602012 Sep 198622 Ago 1989The Trustees Of Columbia University In The City Of New YorkBinary tree parallel processor
US487030219 Feb 198826 Sep 1989Xilinx, Inc.Configurable electrical circuit having configurable logic elements and configurable interconnects
US488423126 Sep 198628 Nov 1989Performance Semiconductor CorporationMicroprocessor system with extended arithmetic logic unit
US489181027 Oct 19872 Ene 1990Thomson-CsfReconfigurable computing device
US490126819 Ago 198813 Feb 1990General Electric CompanyMultiple function data processor
US49106652 Sep 198620 Mar 1990General Electric CompanyDistributed processing system including reconfigurable elements
US495978116 May 198825 Sep 1990Stardent Computer, Inc.System for assigning interrupts to least busy processor that already loaded same class of interrupt routines
US496734018 Nov 198830 Oct 1990E-Systems, Inc.Adaptive processing system having an array of individually configurable processing components
US49929334 May 199012 Feb 1991International Business Machines CorporationSIMD array processor with global instruction control and reprogrammable instruction decoders
US501419314 Oct 19887 May 1991Compaq Computer CorporationDynamically configurable portable computer system
US50158847 Mar 199014 May 1991Advanced Micro Devices, Inc.Multiple array high performance programmable logic device family
US502194730 Ene 19904 Jun 1991Hughes Aircraft CompanyData-flow multiprocessor architecture with three dimensional multistage interconnection network for efficient signal and data processing
US502377515 Oct 199011 Jun 1991Intel CorporationSoftware programmable logic array utilizing "and" and "or" gates
US50364734 Oct 198930 Jul 1991Mentor Graphics CorporationMethod of using electronically reconfigurable logic circuits
US503649315 Mar 199030 Jul 1991Digital Equipment CorporationSystem and method for reducing power usage by multiple memory modules
US504397821 Sep 198927 Ago 1991Siemens AktiengesellschaftCircuit arrangement for telecommunications exchanges
US50479242 Dic 198810 Sep 1991Mitsubishi Denki Kabushiki KaishaMicrocomputer
US50559979 Oct 19908 Oct 1991U.S. Philips CorporationSystem with plurality of processing elememts each generates respective instruction based upon portions of individual word received from a crossbar switch
US506530822 Feb 199112 Nov 1991The Secretary Of State For Defence In Her Britannic Magesty's Government Of The United Kingdom Of Great Britain And Northern IrelandProcessing cell for fault tolerant arrays
US50721784 Jun 199010 Dic 1991Hitachi, Ltd.Method and apparatus for testing logic circuitry by applying a logical test pattern
US50813752 Ene 199114 Ene 1992National Semiconductor Corp.Method for operating a multiple page programmable logic device
US51033111 Oct 19907 Abr 1992U.S. Philips CorporationData processing module and video processing system incorporating same
US510950322 May 198928 Abr 1992Ge Fanuc Automation North America, Inc.Apparatus with reconfigurable counter includes memory for storing plurality of counter configuration files which respectively define plurality of predetermined counters
US51134984 Jun 199012 May 1992Echelon CorporationInput/output section for an intelligent cell which provides sensing, bidirectional communications and control
US511551019 Oct 198819 May 1992Sharp Kabushiki KaishaMultistage data flow processor with instruction packet, fetch, storage transmission and address generation controlled by destination information
US51231095 Mar 199016 Jun 1992Thinking Machines CorporationParallel processor including a processor array with plural data transfer arrangements including (1) a global router and (2) a proximate-neighbor transfer system
US51258012 Feb 199030 Jun 1992Isco, Inc.Pumping system
US51285598 Ago 19917 Jul 1992Sgs-Thomson Microelectronics, Inc.Logic block for programmable logic devices
US514246929 Mar 199025 Ago 1992Ge Fanuc Automation North America, Inc.Method for converting a programmable logic controller hardware configuration and corresponding control program for use on a first programmable logic controller to use on a second programmable logic controller
US51441662 Nov 19901 Sep 1992Concurrent Logic, Inc.Programmable logic cell and array
US519320229 May 19909 Mar 1993Wavetracer, Inc.Processor array with relocated operand physical address generator capable of data transfer to distant physical processor for each virtual processor while simulating dimensionally larger array processor
US52030052 May 198913 Abr 1993Horst Robert WCell structure for linear array wafer scale integration architecture with capability to open boundary i/o bus without neighbor acknowledgement
US520493510 Abr 199220 Abr 1993Fuji Xerox Co., Ltd.Programmable fuzzy logic circuits
US52084917 Ene 19924 May 1993Washington Research FoundationField programmable gate array
US521277717 Nov 198918 May 1993Texas Instruments IncorporatedMulti-processor reconfigurable in single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD) modes and method of operation
US522612221 Ago 19876 Jul 1993Compaq Computer Corp.Programmable logic system for filtering commands to a microprocessor
US523353930 Oct 19893 Ago 1993Advanced Micro Devices, Inc.Programmable gate array with improved interconnect structure, input/output structure and configurable logic block
US524323817 Mar 19907 Sep 1993Algotronix LimitedConfigurable cellular array
US52476899 Feb 199021 Sep 1993Ewert Alfred PParallel digital processor including lateral transfer buses with interrupt switches to form bus interconnection segments
US527459328 Sep 199028 Dic 1993Intergraph CorporationHigh speed redundant rows and columns for semiconductor memories
US528747222 Ago 199015 Feb 1994Tandem Computers IncorporatedMemory system using linear array wafer scale integration architecture
US528751115 Oct 199115 Feb 1994Star Semiconductor CorporationArchitectures and methods for dividing processing tasks into tasks for a programmable real time signal processor and tasks for a decision making microprocessor interfacing therewith
US528753214 Nov 199015 Feb 1994Amt (Holdings) LimitedProcessor elements having multi-byte structure shift register for shifting data either byte wise or bit wise with single-bit output formed at bit positions thereof spaced by one byte
US529411928 Sep 199215 Mar 1994Taylor Made Golf Company, Inc.Vibration-damping device for a golf club
US530128416 Ene 19915 Abr 1994Walker-Estes CorporationMixed-resolution, N-dimensional object space method and apparatus
US530134429 Ene 19915 Abr 1994Analogic CorporationMultibus sequential processor to perform in parallel a plurality of reconfigurable logic operations on a plurality of data sets
US530317216 Feb 198812 Abr 1994Array MicrosystemsPipelined combination and vector signal processor
US53369508 Feb 19939 Ago 1994National Semiconductor CorporationConfiguration features in a configurable logic array
US534340628 Jul 198930 Ago 1994Xilinx, Inc.Distributed memory architecture for a configurable logic array and method for using distributed memory
US534763915 Jul 199113 Sep 1994International Business Machines CorporationSelf-parallelizing computer system and method
US534919320 May 199320 Sep 1994Princeton Gamma Tech, Inc.Highly sensitive nuclear spectrometer apparatus and method
US535343223 Abr 19914 Oct 1994Compaq Computer CorporationInteractive method for configuration of computer system and circuit boards with user specification of system resources and computer resolution of resource conflicts
US53555087 May 199111 Oct 1994Mitsubishi Denki Kabushiki KaishaParallel data processing system combining a SIMD unit with a MIMD unit and sharing a common bus, memory, and system controller
US536137311 Dic 19921 Nov 1994Gilson Kent LIntegrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
US536512523 Jul 199215 Nov 1994Xilinx, Inc.Logic cell for field programmable gate array having optional internal feedback and optional cascade
US53794447 Jun 19943 Ene 1995Hughes Aircraft CompanyArray of one-bit processors each having only one bit of memory
US538615423 Jul 199231 Ene 1995Xilinx, Inc.Compact logic cell for field programmable gate array chip
US538651812 Feb 199331 Ene 1995Hughes Aircraft CompanyReconfigurable computer interface and method
US54086433 Feb 199218 Abr 1995Nec CorporationWatchdog timer with a non-masked interrupt masked only when a watchdog timer has been cleared
US541072321 May 199325 Abr 1995Deutsche Itt Industries GmbhWavefront array processor for blocking the issuance of first handshake signal (req) by the presence of second handshake signal (ack) which indicates the readyness of the receiving cell
US541279525 Feb 19922 May 1995Micral, Inc.State machine having a variable timing mechanism for varying the duration of logical output states of the state machine based on variation in the clock frequency
US541895211 Jun 199223 May 1995Flavors Technology Inc.Parallel processor cell computer system
US542101923 Sep 199230 May 1995Martin Marietta CorporationParallel data processor
US54228237 Jul 19946 Jun 1995Advanced Micro Devices, Inc.Programmable gate array device having cascaded means for function definition
US542503618 Sep 199213 Jun 1995Quickturn Design Systems, Inc.Method and apparatus for debugging reconfigurable emulation systems
US542637820 Abr 199420 Jun 1995Xilinx, Inc.Programmable logic device which stores more than one configuration and means for switching configurations
US54285263 Feb 199327 Jun 1995Flood; Mark A.Programmable controller with time periodic communication
US54306871 Abr 19944 Jul 1995Xilinx, Inc.Programmable logic device including a parallel input device for loading memory cells
US54402459 Mar 19938 Ago 1995Actel CorporationLogic module with configurable combinational and sequential blocks
US544053823 Sep 19938 Ago 1995Massachusetts Institute Of TechnologyCommunication system with redundant links and data bit time multiplexing
US54427909 Mar 199415 Ago 1995The Trustees Of Princeton UniversityOptimizing compiler for computers
US54443948 Jul 199322 Ago 1995Altera CorporationPLD with selective inputs from local and global conductors
US544818616 Mar 19945 Sep 1995Fuji Xerox Co., Ltd.Field-programmable gate array
US54500227 Oct 199412 Sep 1995Xilinx Inc.Structure and method for configuration of a field programmable gate array
US54555256 Dic 19933 Oct 1995Intelligent Logic Systems, Inc.Hierarchically-structured programmable logic array and system for interconnecting logic elements in the logic array
US545764420 Ago 199310 Oct 1995Actel CorporationField programmable digital signal processing array integrated circuit
US546537514 Ene 19937 Nov 1995France TelecomMultiprocessor system with cascaded modules combining processors through a programmable logic cell array
US547326618 Oct 19945 Dic 1995Altera CorporationProgrammable logic device having fast programmable logic array blocks and a central global interconnect array
US54732673 Feb 19955 Dic 1995Sgs-Thomson Microelectronics LimitedProgrammable logic device with memory that can store routing data of logic data
US547558324 Feb 199212 Dic 1995Siemens AktiengesellschaftProgrammable control system including a logic module and a method for programming
US547580310 Jul 199212 Dic 1995Lsi Logic CorporationMethod for 2-D affine transformation of images
US547585617 Oct 199412 Dic 1995International Business Machines CorporationDynamic multi-mode parallel processing array
US547752531 Ago 199319 Dic 1995Sony CorporationData destruction preventing method, recording apparatus provided with data destruction preventing capability, and disc recorded with guard band
US54836209 Mar 19959 Ene 1996International Business Machines Corp.Learning machine synapse processor system apparatus
US548510315 Dic 199416 Ene 1996Altera CorporationProgrammable logic array with local and global conductors
US548510418 Ene 199516 Ene 1996Advanced Micro Devices, Inc.Logic allocator for a programmable logic device
US54898573 Ago 19926 Feb 1996Advanced Micro Devices, Inc.Flexible synchronous/asynchronous cell structure for a high density programmable logic device
US549135331 Mar 199513 Feb 1996Xilinx, Inc.Configurable cellular array
US549323931 Ene 199520 Feb 1996Motorola, Inc.Circuit and method of configuring a field programmable gate array
US549749828 Sep 19935 Mar 1996Giga Operations CorporationVideo processing module using a second programmable logic device which reconfigures a first programmable logic device for data transformation
US55044396 Jun 19952 Abr 1996Xilinx, Inc.I/O interface cell for use with optional pad
US550699817 Jun 19949 Abr 1996Fujitsu LimitedParallel data processing system using a plurality of processing elements to process data and a plurality of trays connected to some of the processing elements to store and transfer data
US551073021 Jun 199523 Abr 1996Actel CorporationReconfigurable programmable interconnect architecture
US55111735 Ene 199423 Abr 1996Ricoh Co., Ltd.Programmable logic array and data processing unit using the same
US551336628 Sep 199430 Abr 1996International Business Machines CorporationMethod and system for dynamically reconfiguring a register file in a vector processor
US552183719 Ene 199528 May 1996Xilinx, Inc.Timing driven method for laying out a user's circuit onto a programmable integrated circuit device
US552208322 Jun 199428 May 1996Texas Instruments IncorporatedReconfigurable multi-processor operating in SIMD mode with one processor fetching instructions for use by remaining processors
US552597125 Ago 199411 Jun 1996Advanced Risc Machines LimitedIntegrated circuit
US55308732 Ago 199325 Jun 1996Hudson Soft Co. Ltd.Method and apparatus for processing interruption
US553094628 Oct 199425 Jun 1996Dell Usa, L.P.Processor failure detection and recovery circuit in a dual processor computer system and method of operation thereof
US553269313 Jun 19942 Jul 1996Advanced Hardware ArchitecturesAdaptive data compression system with systolic string matching logic
US553295731 Ene 19952 Jul 1996Texas Instruments IncorporatedField reconfigurable logic/memory array
US553540629 Dic 19939 Jul 1996Kolchinsky; AlexanderVirtual processor module including a reconfigurable programmable matrix
US553705714 Feb 199516 Jul 1996Altera CorporationProgrammable logic array device with grouped logic regions and three types of conductors
US553760111 Jul 199416 Jul 1996Hitachi, Ltd.Programmable digital signal processor for performing a plurality of signal processings
US554153017 May 199530 Jul 1996Altera CorporationProgrammable logic array integrated circuits with blocks of logic regions grouped into super-blocks
US554433611 Abr 19956 Ago 1996Fujitsu LimitedParallel data processing system which efficiently performs matrix and neurocomputer operations, in a negligible data transmission time
US554877330 Mar 199320 Ago 1996The United States Of America As Represented By The Administrator Of The National Aeronautics And Space AdministrationDigital parallel processor array for optimum path planning
US555078218 May 199427 Ago 1996Altera CorporationProgrammable logic array integrated circuits
US555543414 Mar 199410 Sep 1996Carlstedt Elektronik AbComputing device employing a reduction processor and implementing a declarative language
US555945027 Jul 199524 Sep 1996Lucent Technologies Inc.Field programmable gate array with multi-port RAM
US556173825 Mar 19941 Oct 1996Motorola, Inc.Data processor for executing a fuzzy logic operation and method therefor
US556862413 Ago 199322 Oct 1996Digital Equipment CorporationByte-compare operation for high-performance processor
US557004022 Mar 199529 Oct 1996Altera CorporationProgrammable logic array integrated circuit incorporating a first-in first-out memory
US557271013 Sep 19935 Nov 1996Kabushiki Kaisha ToshibaHigh speed logic simulation system using time division emulation suitable for large scale logic circuits
US557493012 Ago 199412 Nov 1996University Of HawaiiComputer system and method using functional memory
US558173114 Oct 19943 Dic 1996King; Edward C.Method and apparatus for managing video data for faster access by selectively caching video data
US55817342 Ago 19933 Dic 1996International Business Machines CorporationMultiprocessor system with shared cache and data input/output circuitry for transferring data amount greater than system bus capacity
US558345018 Ago 199510 Dic 1996Xilinx, Inc.Sequencer for a time multiplexed programmable logic device
US55860445 Jun 199517 Dic 1996Advanced Micro Devices, Inc.Array of configurable logic blocks including cascadable lookup tables
US558792120 Nov 199524 Dic 1996Advanced Micro Devices, Inc.Array of configurable logic blocks each including a look up table having inputs coupled to a first multiplexer and having outputs coupled to a second multiplexer
US558815225 Ago 199524 Dic 1996International Business Machines CorporationAdvanced parallel processor including advanced support hardware
US559034522 May 199231 Dic 1996International Business Machines CorporationAdvanced parallel array processor(APAP)
US559034828 Jul 199231 Dic 1996International Business Machines CorporationStatus predictor for combined shifter-rotate/merge unit
US55967422 Abr 199321 Ene 1997Massachusetts Institute Of TechnologyVirtual interconnections for reconfigurable logic systems
US560026520 Dic 19954 Feb 1997Actel CorporationProgrammable interconnect architecture
US56005976 Jun 19954 Feb 1997Xilinx, Inc.Register protection structure for FPGA
US560084527 Jul 19944 Feb 1997Metalithic Systems IncorporatedIntegrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
US56066987 Mar 199525 Feb 1997Cadence Design Systems, Inc.Method for deriving optimal code schedule sequences from synchronous dataflow graphs
US560834223 Oct 19954 Mar 1997Xilinx, Inc.Hierarchical programming of electrically configurable integrated circuits
US56110493 Jun 199211 Mar 1997Pitts; William M.System for accessing distributed data cache channel at each network node to pass requests and data
US561754730 Abr 19961 Abr 1997International Business Machines CorporationSwitch network extension of bus architecture
US56175778 Mar 19951 Abr 1997International Business Machines CorporationAdvanced parallel array processor I/O connection
US561972029 Jul 19968 Abr 1997Analog Devices, Inc.Digital signal processor having link ports for point-to-point communication
US56258068 Ago 199629 Abr 1997Advanced Micro Devices, Inc.Self configuring speed path in a microprocessor with multiple clock option
US56258362 Jun 199529 Abr 1997International Business Machines CorporationSIMD/MIMD processing memory element (PME)
US56279924 May 19956 May 1997Advanced Micro DevicesOrganization of an integrated cache unit for flexible usage in supporting microprocessor operations
US563413126 Oct 199427 May 1997Intel CorporationMethod and apparatus for independently stopping and restarting functional units
US56358512 Feb 19963 Jun 1997Xilinx, Inc.Read and writable data bus particularly for programmable logic devices
US564205816 Oct 199524 Jun 1997Xilinx , Inc.Periphery input/output interconnect structure
US56465445 Jun 19958 Jul 1997International Business Machines CorporationSystem and method for dynamically reconfiguring a programmable gate array
US564654518 Ago 19958 Jul 1997Xilinx, Inc.Time multiplexed programmable logic device
US564917610 Ago 199515 Jul 1997Virtual Machine Works, Inc.Transition analysis and circuit resynthesis method and device for digital circuit modeling
US564917919 May 199515 Jul 1997Motorola, Inc.Dynamic instruction allocation for a SIMD processor
US565289429 Sep 199529 Jul 1997Intel CorporationMethod and apparatus for providing power saving modes to a pipelined processor
US56550697 Ago 19965 Ago 1997Fujitsu LimitedApparatus having a plurality of programmable logic processing units for self-repair
US56551247 Jun 19955 Ago 1997Seiko Epson CorporationSelective power-down for high performance CPU/system
US565695026 Oct 199512 Ago 1997Xilinx, Inc.Interconnect lines including tri-directional buffer circuits
US565733015 Jun 199512 Ago 1997Mitsubishi Denki Kabushiki KaishaSingle-chip microprocessor with built-in self-testing function
US565978510 Feb 199519 Ago 1997International Business Machines CorporationArray processor communication architecture with broadcast processor instructions
US56597979 Jun 199219 Ago 1997U.S. Philips CorporationSparc RISC based computer system including a single chip processor with memory management and DMA units coupled to a DRAM interface
US567526226 Oct 19957 Oct 1997Xilinx, Inc.Fast carry-out scheme in a field programmable gate array
US567574322 Feb 19957 Oct 1997Callisto Media Systems Inc.Multi-media server
US567575714 Mar 19957 Oct 1997Davidson; George S.Direct match data flow memory for data driven computing
US568058316 Feb 199421 Oct 1997Arkos Design, Inc.Method and apparatus for a trace buffer in an emulation system
US568249129 Dic 199428 Oct 1997International Business Machines CorporationSelective processing and routing of results among processors controlled by decoding instructions using mask value derived from instruction tag and processor identifier
US568732519 Abr 199611 Nov 1997Chang; WebApplication specific field programmable gate array
US56946021 Oct 19962 Dic 1997The United States Of America As Represented By The Secretary Of The Air ForceWeighted system and method for spatial allocation of a parallel load
US569679117 Ene 19959 Dic 1997Vtech Industries, Inc.Apparatus and method for decoding a sequence of digitally encoded data
US569697617 Sep 19969 Dic 1997Intel CorporationProtocol for interrupt bus arbitration in a multi-processor system
US57010916 Jun 199523 Dic 1997Xilinx, Inc.Routing resources for hierarchical FPGA
US57059385 Sep 19956 Ene 1998Xilinx, Inc.Programmable switch for FPGA input/output signals
US570648229 May 19966 Ene 1998Nec CorporationMemory access controller
US57130377 Jun 199527 Ene 1998International Business Machines CorporationSlide bus communication functions for SIMD/MIMD array processor
US57179435 Jun 199510 Feb 1998International Business Machines CorporationAdvanced parallel array processor (APAP)
US573220914 May 199624 Mar 1998Exponential Technology, Inc.Self-testing multi-processor die with internal compare points
US57348696 Sep 199531 Mar 1998Chen; Duan-PingHigh speed logic circuit simulator
US573492130 Sep 199631 Mar 1998International Business Machines CorporationAdvanced parallel array processor computer package
US5742180 *10 Feb 199521 Abr 1998Massachusetts Institute Of TechnologyDynamically programmable gate array with multiple contexts
US574573429 Sep 199528 Abr 1998International Business Machines CorporationMethod and system for programming a gate array using a compressed configuration bit stream
US574887219 Mar 19965 May 1998Norman; Richard S.Direct replacement cell fault tolerant architecture
US57544598 Feb 199619 May 1998Xilinx, Inc.Multiplier circuit design for a programmable logic device
US575482713 Oct 199519 May 1998Mentor Graphics CorporationMethod and apparatus for performing fully visible tracing of an emulation
US57548717 Jun 199519 May 1998International Business Machines CorporationParallel processing system having asynchronous SIMD processing
US576060217 Ene 19962 Jun 1998Hewlett-Packard CompanyTime multiplexing a plurality of configuration settings of a programmable switch element in a FPGA
US57614841 Abr 19942 Jun 1998Massachusetts Institute Of TechnologyVirtual interconnections for reconfigurable logic systems
US577399415 Dic 199530 Jun 1998Cypress Semiconductor Corp.Method and apparatus for implementing an internal tri-state bus within a programmable logic circuit
US577843918 Ago 19957 Jul 1998Xilinx, Inc.Programmable logic device with hierarchical confiquration and state storage
US57817561 Abr 199414 Jul 1998Xilinx, Inc.Programmable logic device with partially configurable memory cells and a method for configuration
US578463628 May 199621 Jul 1998National Semiconductor CorporationReconfigurable computer architecture for use in signal processing applications
US579405928 Jul 199411 Ago 1998International Business Machines CorporationN-dimensional modified hypercube
US579406217 Abr 199511 Ago 1998Ricoh Company Ltd.System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization
US580154723 Oct 19961 Sep 1998Xilinx, Inc.Embedded memory for field programmable gate array
US580171517 Oct 19941 Sep 1998Norman; Richard S.Massively-parallel processor array with outputs from individual processors directly to an external device without involving other processors or a common physical carrier
US580195810 Sep 19961 Sep 1998Lsi Logic CorporationMethod and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information
US580229012 Dic 19961 Sep 1998Virtual Computer CorporationComputer network of distributed virtual computers which are EAC reconfigurable in response to instruction to be executed
US580498629 Dic 19958 Sep 1998Cypress Semiconductor Corp.Memory in a programmable logic device
US581500416 Oct 199529 Sep 1998Xilinx, Inc.Multi-buffered configurable logic block output lines in a field programmable gate array
US58157155 Jun 199529 Sep 1998Motorola, Inc.Method for designing a product having hardware and software components and product therefor
US58157267 Jun 199529 Sep 1998Altera CorporationCoarse-grained look-up table architecture
US58282291 May 199727 Oct 1998Altera CorporationProgrammable logic array integrated circuits
US582885816 Sep 199627 Oct 1998Virginia Tech Intellectual Properties, Inc.Worm-hole run-time reconfigurable processor field programmable gate array (FPGA)
US583144827 Ago 19963 Nov 1998Xilinx, Inc.Function unit for fine-gained FPGA
US583816521 Ago 199617 Nov 1998Chatter; MukeshHigh performance self modifying on-the-fly alterable logic FPGA, architecture and method
US58448887 Jun 19951 Dic 1998Echelon CorporationNetwork and intelligent cell for providing sensing, bidirectional communications and control
US58482383 Ene 19978 Dic 1998Hitachi, Ltd.Information processing system and logic LSI, detecting a fault in the system or the LSI, by using internal data processed in each of them
US585491824 Ene 199629 Dic 1998Ricoh Company Ltd.Apparatus and method for self-timed algorithmic execution
US585710911 Abr 19955 Ene 1999Giga Operations CorporationProgrammable logic device for real time video processing
US58595445 Sep 199612 Ene 1999Altera CorporationDynamic configurable elements for programmable logic devices
US586011925 Nov 199612 Ene 1999Vlsi Technology, Inc.Data-packet fifo buffer system with end-of-packet flags
US58652395 Feb 19972 Feb 1999Micropump, Inc.Method for making herringbone gears
US5867691 *15 Mar 19932 Feb 1999Kabushiki Kaisha ToshibaSynchronizing system between function blocks arranged in hierarchical structures and large scale integrated circuit using the same
US58677235 Ago 19962 Feb 1999Sarnoff CorporationAdvanced massively parallel computer with a secondary storage device coupled through a secondary storage interface
US587062030 May 19969 Feb 1999Sharp Kabushiki KaishaData driven type information processor with reduced instruction execution requirements
US588407510 Mar 199716 Mar 1999Compaq Computer CorporationConflict resolution using self-contained virtual devices
US588716213 Ene 199723 Mar 1999Micron Technology, Inc.Memory device having circuitry for initializing and reprogramming a control operation feature
US588953314 Feb 199730 Mar 1999Samsung Electronics Co., Ltd.First-in-first-out device for graphic drawing engine
US58899821 Jul 199530 Mar 1999Intel CorporationMethod and apparatus for generating event handler vectors based on both operating mode and event type
US58923703 Ene 19976 Abr 1999Quicklogic CorporationClock network for field programmable gate array
US589296129 Ago 19976 Abr 1999Xilinx, Inc.Field programmable gate array having programming instructions in the configuration bitstream
US589456520 May 199613 Abr 1999Atmel CorporationField programmable gate array with distributed RAM and increased cell utilization
US590127918 Oct 19964 May 1999Hughes Electronics CorporationConnection of spares between multiple programmable devices
US591512331 Oct 199722 Jun 1999Silicon SpiceMethod and apparatus for controlling configuration memory contexts of processing elements in a network of multiple context processing elements
US592411927 Ene 199413 Jul 1999Xerox CorporationConsistent packet switched memory bus for shared memory multiprocessors
US59274235 Mar 199827 Jul 1999Massachusetts Institute Of TechnologyReconfigurable footprint mechanism for omnidirectional vehicles
US59330233 Sep 19963 Ago 1999Xilinx, Inc.FPGA architecture having RAM blocks with programmable word length and width and dedicated address and data lines
US59336429 Abr 19973 Ago 1999Ricoh CorporationCompiling system and method for reconfigurable computing
US593642414 Oct 199710 Ago 1999Xilinx, Inc.High speed bus with tree structure for selecting bus driver
US594324217 Nov 199524 Ago 1999Pact GmbhDynamically reconfigurable data processing system
US5956518 *11 Abr 199621 Sep 1999Massachusetts Institute Of TechnologyIntermediate-grain reconfigurable processing device
US596614314 Oct 199712 Oct 1999Motorola, Inc.Data allocation into multiple memories for concurrent access
US596653427 Jun 199712 Oct 1999Cooke; Laurence H.Method for compiling high level programming languages into an integrated processor with reconfigurable logic
US597025427 Jun 199719 Oct 1999Cooke; Laurence H.Integrated processor and programmable data path chip for reconfigurable computing
US597826020 Jul 19982 Nov 1999Xilinx, Inc.Method of time multiplexing a programmable logic device
US599604820 Jun 199730 Nov 1999Sun Microsystems, Inc.Inclusion vector architecture for a level two cache
US601140713 Jun 19974 Ene 2000Xilinx, Inc.Field programmable gate array with dedicated computer bus interface and method for configuring both
US601450924 Sep 199711 Ene 2000Atmel CorporationField programmable gate array having access to orthogonal and diagonal adjacent neighboring cells
US602075811 Mar 19961 Feb 2000Altera CorporationPartially reconfigurable programmable logic device
US60214908 Oct 19971 Feb 2000Pact GmbhRun-time reconfiguration method for programmable units
US602356419 Jul 19968 Feb 2000Xilinx, Inc.Data processing system using a flash reconfigurable logic device as a dynamic execution unit for a sequence of instructions
US602374218 Jul 19978 Feb 2000University Of WashingtonReconfigurable computing architecture for providing pipelined data paths
US603453821 Ene 19987 Mar 2000Lucent Technologies Inc.Virtual logic system for reconfigurable hardware
US603537128 May 19977 Mar 20003Com CorporationMethod and apparatus for addressing a static random access memory device based on signals for addressing a dynamic memory access device
US60386508 Oct 199714 Mar 2000PactgmbhMethod for the automatic address generation of modules within clusters comprised of a plurality of these modules
US603865611 Sep 199814 Mar 2000California Institute Of TechnologyPipelined completion for asynchronous communication
US604403021 Dic 199828 Mar 2000Philips Electronics North America CorporationFIFO unit with single pointer
US604711529 May 19974 Abr 2000Xilinx, Inc.Method for configuring FPGA memory planes for virtual hardware computation
US604922230 Dic 199711 Abr 2000Xilinx, IncConfiguring an FPGA using embedded memory
US60498666 Sep 199611 Abr 2000Silicon Graphics, Inc.Method and system for an efficient user mode cache manipulation using a simulated instruction
US60527736 Jun 199518 Abr 2000Massachusetts Institute Of TechnologyDPGA-coupled microprocessors
US605487323 Jun 199925 Abr 2000International Business Machines CorporationInterconnect structure between heterogeneous core regions in a programmable array
US60556197 Feb 199725 Abr 2000Cirrus Logic, Inc.Circuits, system, and methods for processing multiple data streams
US605846911 May 19982 May 2000Ricoh CorporationSystem and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization
US607615723 Oct 199713 Jun 2000International Business Machines CorporationMethod and apparatus to force a thread switch in a multithreaded processor
US607873628 Ago 199720 Jun 2000Xilinx, Inc.Method of designing FPGAs for dynamically reconfigurable computing
US60819038 Oct 199727 Jun 2000Pact GmbhMethod of the self-synchronization of configurable elements of a programmable unit
US608531715 Ago 19974 Jul 2000Altera CorporationReconfigurable computer architecture using programmable logic devices
US608662817 Feb 199811 Jul 2000Lucent Technologies Inc.Power-related hardware-software co-synthesis of heterogeneous distributed embedded systems
US60887958 Oct 199711 Jul 2000Pact GmbhProcess for automatic dynamic reloading of data flow processors (DFPs) and units with two or three-dimensional programmable cell architectures (FPGAs, DPGAs and the like)
US60921741 Jun 199818 Jul 2000Context, Inc.Dynamically reconfigurable distributed integrated circuit processor and method
US61051054 May 199915 Ago 2000Xilinx, Inc.Data processing system using configuration select logic, an instruction store, and sequencing logic during instruction execution
US610510631 Dic 199715 Ago 2000Micron Technology, Inc.Computer system, memory device and shift register including a balanced switching circuit with series connected transfer gates which are selectively clocked for fast switching times
US610876031 Oct 199722 Ago 2000Silicon SpiceMethod and apparatus for position independent reconfiguration in a network of multiple context processing elements
US611872418 Feb 199812 Sep 2000Canon Kabushiki KaishaMemory controller architecture
US61191818 Oct 199712 Sep 2000Pact GmbhI/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures
US612271931 Oct 199719 Sep 2000Silicon SpiceMethod and apparatus for retiming in a network of multiple context processing elements
US612540810 Mar 199726 Sep 2000Compaq Computer CorporationResource type prioritization in generating a device configuration
US612790817 Nov 19973 Oct 2000Massachusetts Institute Of TechnologyMicroelectro-mechanical system actuator device and reconfigurable circuits utilizing same
US612872010 Abr 19973 Oct 2000International Business Machines CorporationDistributed processing array with component processors performing customized interpretation of instructions
US614507220 Sep 19947 Nov 2000Hughes Electronics CorporationIndependently non-homogeneously dynamically reconfigurable two dimensional interprocessor communication topology for SIMD multi-processors and apparatus for implementing same
US615083728 Feb 199721 Nov 2000Actel CorporationEnhanced field programmable gate array
US615083916 Feb 200021 Nov 2000Xilinx, Inc.Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM
US615404927 Mar 199828 Nov 2000Xilinx, Inc.Multiplier fabric for use in field programmable gate arrays
US617252012 Feb 19999 Ene 2001Xilinx, Inc.FPGA system with user-programmable configuration ports and method for reconfiguring the FPGA
US617341914 May 19989 Ene 2001Advanced Technology Materials, Inc.Field programmable gate array (FPGA) emulator for debugging software
US617343422 Ene 19979 Ene 2001Brigham Young UniversityDynamically-configurable digital processor using method for relocating logic array modules
US617849423 Sep 199623 Ene 2001Virtual Computer CorporationModular, hybrid processor and method for producing a modular, hybrid processor
US618865019 Oct 199813 Feb 2001Sony CorporationRecording and reproducing system having resume function
US620218230 Jun 199813 Mar 2001Lucent Technologies Inc.Method and apparatus for testing field programmable gate arrays
US621254423 Oct 19973 Abr 2001International Business Machines CorporationAltering thread priorities in a multithreaded processor
US621983311 Dic 199817 Abr 2001Hewlett-Packard CompanyMethod of using primary and secondary processors
US623030726 Ene 19988 May 2001Xilinx, Inc.System and method for programming the hardware of field programmable gate arrays (FPGAs) and related reconfiguration resources as if they were software by creating hardware objects
US624050225 Jun 199729 May 2001Sun Microsystems, Inc.Apparatus for dynamically reconfiguring a processor
US62438088 Mar 19995 Jun 2001Chameleon Systems, Inc.Digital data bit order conversion using universal switch matrix comprising rows of bit swapping selector groups
US62471476 Nov 199812 Jun 2001Altera CorporationEnhanced embedded logic analyzer
US625279228 Ene 199826 Jun 2001Elixent LimitedField programmable processor arrays
US626011430 Dic 199710 Jul 2001Mcmz Technology Innovations, LlcComputer cache memory windowing
US62601795 May 199810 Jul 2001Fujitsu LimitedCell arrangement evaluating method, storage medium storing cell arrangement evaluating program, cell arranging apparatus and method, and storage medium storing cell arranging program
US626290828 Ene 199817 Jul 2001Elixent LimitedField programmable processor devices
US626343029 Jul 199917 Jul 2001Xilinx, Inc.Method of time multiplexing a programmable logic device
US626676015 Abr 199924 Jul 2001Massachusetts Institute Of TechnologyIntermediate-grain reconfigurable processing device
US627907721 Mar 199721 Ago 2001Texas Instruments IncorporatedBus interface buffer control in a microprocessor
US628262729 Jun 199828 Ago 2001Chameleon Systems, Inc.Integrated processor and programmable data path chip for reconfigurable computing
US628856623 Sep 199911 Sep 2001Chameleon Systems, Inc.Configuration state memory for functional blocks on a reconfigurable chip
US628944014 Jul 199911 Sep 2001Virtual Computer CorporationVirtual computer of plural FPG's successively reconfigured in response to a succession of inputs
US62983961 Jun 19982 Oct 2001Advanced Micro Devices, Inc.System for loading a current buffer desciptor register with a value different from current value to cause a previously read buffer descriptor to be read again
US62984727 May 19992 Oct 2001Chameleon Systems, Inc.Behavioral silicon construct architecture and mapping
US631120023 Sep 199930 Oct 2001Chameleon Systems, Inc.Reconfigurable program sum of products generator
US632136631 Ago 199820 Nov 2001Axis Systems, Inc.Timing-insensitive glitch-free logic system and method
US632137330 Oct 199920 Nov 2001International Business Machines CorporationMethod for resource control in parallel environments using program organization and run-time support
US633810618 Jun 19998 Ene 2002Pact GmbhI/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures
US634131810 Ago 199922 Ene 2002Chameleon Systems, Inc.DMA data streaming
US634734630 Jun 199912 Feb 2002Chameleon Systems, Inc.Local memory unit system with global access for use on reconfigurable chips
US634934623 Sep 199919 Feb 2002Chameleon Systems, Inc.Control fabric unit including associated configuration memory and PSOP state machine adapted to provide configuration address to reconfigurable functional unit
US636265018 May 200026 Mar 2002Xilinx, Inc.Method and apparatus for incorporating a multiplier into an FPGA
US63705963 Ago 19999 Abr 2002Chameleon Systems, Inc.Logic flag registers for monitoring processing system events
US637377919 May 200016 Abr 2002Xilinx, Inc.Block RAM having multiple configurable write modes for use in a field programmable gate array
US63742866 Abr 199816 Abr 2002Rockwell Collins, Inc.Real time processor capable of concurrently running multiple independent JAVA machines
US63780681 Jun 199523 Abr 2002Nec CorporationSuspend/resume capability for a protected mode microprocesser
US638937912 Jun 199814 May 2002Axis Systems, Inc.Converification system and method
US638957926 Ene 199914 May 2002Chameleon SystemsReconfigurable logic for table lookup
US639291210 Ene 200121 May 2002Chameleon Systems, Inc.Loading data plane on reconfigurable chip
US640422423 Jun 199911 Jun 2002Fujitsu LimitedChain-connected shift register and programmable logic circuit whose logic function is changeable in real time
US640518523 Mar 199511 Jun 2002International Business Machines CorporationMassively parallel array processor
US640529928 Ago 199811 Jun 2002Pact GmbhInternal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity
US642180822 Abr 199916 Jul 2002Cadance Design Systems, Inc.Hardware design language for the design of integrated circuits
US64218173 Abr 200016 Jul 2002Xilinx, Inc.System and method of computation in a programmable logic device using virtual instructions
US64250688 Oct 199723 Jul 2002Pact GmbhUnit for processing numeric and logic operations for use in central processing units (cpus), multiprocessor systems, data-flow processors (dsps), systolic processors and field programmable gate arrays (epgas)
US642664929 Dic 200030 Jul 2002Quicklogic CorporationArchitecture for field programmable gate array
US642715621 Ene 199730 Jul 2002Xilinx, Inc.Configurable logic block with AND gate for efficient multiplication in FPGAS
US64346427 Oct 199913 Ago 2002Xilinx, Inc.FIFO memory system and method with improved determination of full and empty conditions and amount of data stored
US643467229 Feb 200013 Ago 2002Hewlett-Packard CompanyMethods and apparatus for improving system performance with a shared cache memory
US645711628 May 199924 Sep 2002Broadcom CorporationMethod and apparatus for controlling contexts of multiple context processing elements in a network of multiple context processing elements
US647764310 Jul 20005 Nov 2002Pact GmbhProcess for automatic dynamic reloading of data flow processors (dfps) and units with two-or-three-dimensional programmable cell architectures (fpgas, dpgas, and the like)
US648093725 Feb 199912 Nov 2002Pact Informationstechnologie GmbhMethod for hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)--
US64809546 Jun 200112 Nov 2002Xilinx Inc.Method of time multiplexing a programmable logic device
US648334329 Dic 200019 Nov 2002Quicklogic CorporationConfigurable computational unit embedded in a programmable device
US649690231 Dic 199817 Dic 2002Cray Inc.Vector and scalar data cache for a vector multiprocessor
US64969717 Feb 200017 Dic 2002Xilinx, Inc.Supporting multiple FPGA configuration modes using dedicated on-chip processor
US650789818 Feb 199814 Ene 2003Canon Kabushiki KaishaReconfigurable data cache controller
US650794720 Ago 199914 Ene 2003Hewlett-Packard CompanyProgrammatic synthesis of processor element arrays
US65128047 Abr 199928 Ene 2003Applied Micro Circuits CorporationApparatus and method for multiple serial data synchronization using channel-lock FIFO buffers optimized for jitter
US651307725 Jul 200128 Ene 2003Pact GmbhI/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures
US651967418 Feb 200011 Feb 2003Chameleon Systems, Inc.Configuration bits layout
US652652029 Mar 200025 Feb 2003Pact GmbhMethod of self-synchronization of configurable elements of a programmable unit
US653846831 Jul 200025 Mar 2003Cypress Semiconductor CorporationMethod and apparatus for multiple boot-up functionalities for a programmable logic device (PLD)
US653847018 Sep 200125 Mar 2003Altera CorporationDevices and methods with programmable logic and digital signal processing regions
US653941524 Sep 199725 Mar 2003Sony CorporationMethod and apparatus for the allocation of audio/video tasks in a network system
US653943815 Ene 199925 Mar 2003Quickflex Inc.Reconfigurable computing system and method and apparatus employing same
US65394773 Mar 200025 Mar 2003Chameleon Systems, Inc.System and method for control synthesis using a reachable states look-up table
US65429986 Ago 19991 Abr 2003Pact GmbhMethod of self-synchronization of configurable elements of a programmable module
US655347931 Jul 200222 Abr 2003Broadcom CorporationLocal control of multiple context processing elements with major contexts and minor contexts
US657138125 Feb 199927 May 2003Pact Xpp Technologies AgMethod for deadlock-free configuration of dataflow processors and modules with a two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)
US658793913 Ene 20001 Jul 2003Kabushiki Kaisha ToshibaInformation processing apparatus provided with an optimized executable instruction extracting unit for extending compressed instructions
US65981281 Oct 199922 Jul 2003Hitachi, Ltd.Microprocessor having improved memory management unit and cache memory
US660670431 Ago 199912 Ago 2003Intel CorporationParallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode
US66248198 Jun 200023 Sep 2003Broadcom CorporationMethod and system for providing a flexible and efficient processor for use in a graphics processing system
US665745715 Mar 20002 Dic 2003Intel CorporationData transfer on reconfigurable chip
US66657584 Oct 199916 Dic 2003Ncr CorporationSoftware sanity monitor
US666823717 Ene 200223 Dic 2003Xilinx, Inc.Run-time reconfigurable testing of programmable logic devices
US66877889 Jul 20023 Feb 2004Pact Xpp Technologies AgMethod of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs , etc.)
US669797921 Jun 200024 Feb 2004Pact Xpp Technologies AgMethod of repairing integrated circuits
US670481625 Jul 20009 Mar 2004Sun Microsystems, Inc.Method and apparatus for executing standard functions in a computer system using a field programmable gate array
US671743628 Mar 20026 Abr 2004Infineon Technologies AgReconfigurable gate array
US67253348 Jun 200120 Abr 2004Hewlett-Packard Development Company, L.P.Method and system for exclusive two-level caching in a chip-multiprocessor
US67288719 Jun 199927 Abr 2004Pact Xpp Technologies AgRuntime configurable arithmetic and logic cell
US674531730 Jul 19991 Jun 2004Broadcom CorporationThree level direct communication connections between neighboring multiple context processing elements
US674844012 May 19998 Jun 2004Microsoft CorporationFlow of streaming data through multiple processing modules
US675172227 Feb 200315 Jun 2004Broadcom CorporationLocal control of multiple context processing elements with configuration contexts
US680220611 Oct 200212 Oct 2004American Axle & Manufacturing, Inc.Torsional actuation NVH test method
US68296976 Sep 20007 Dic 2004International Business Machines CorporationMultiple logical interfaces to a shared coprocessor resource
US683684224 Abr 200128 Dic 2004Xilinx, Inc.Method of partial reconfiguration of a PLD in which only updated portions of configuration data are selected for reconfiguring the PLD
US68684765 Ago 200215 Mar 2005Intel CorporationSoftware controlled content addressable memory in a general purpose execution datapath
US697513825 Mar 200413 Dic 2005Advantage Logic, Inc.Method and apparatus for universal program controlled bus architecture
US700016111 Oct 200214 Feb 2006Altera CorporationReconfigurable programmable logic system with configuration recovery mode
US70281077 Oct 200211 Abr 2006Pact Xpp Technologies AgProcess for automatic dynamic reloading of data flow processors (DFPS) and units with two- or three- dimensional programmable cell architectures (FPGAS, DPGAS, and the like)
US70389524 May 20042 May 2006Xilinx, Inc.Block RAM with embedded FIFO buffer
US704341627 Jul 20019 May 2006Lsi Logic CorporationSystem and method for state restoration in a diagnostic module for a high-speed microprocessor
US72162045 Ago 20028 May 2007Intel CorporationMechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment
US734059612 Jun 20014 Mar 2008Altera CorporationEmbedded processor with watchdog timer for programmable logic
US734664417 Ago 200618 Mar 2008Altera CorporationDevices and methods with programmable logic and digital signal processing regions
US735017827 Ago 200425 Mar 2008Altera CorporationEmbedded processor with watchdog timer for programmable logic
US73821561 Sep 20053 Jun 2008Actel CorporationMethod and apparatus for universal program controlled bus architecture
US75956598 Oct 200129 Sep 2009Pact Xpp Technologies AgLogic cell array and bus system
US765044810 Ene 200819 Ene 2010Pact Xpp Technologies AgI/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures
US775996827 Sep 200620 Jul 2010Xilinx, Inc.Method of and system for verifying configuration data
US200100038347 Dic 200014 Jun 2001Nec CorporationInterprocessor communication method and multiprocessor
US2001001873323 Feb 200130 Ago 2001Taro FujiiArray-type processor
US200200108536 Jun 200124 Ene 2002Xilinx, Inc.Method of time multiplexing a programmable logic device
US2002001386129 May 200131 Ene 2002Intel CorporationMethod and apparatus for low overhead multithreaded communication in a parallel processing environment
US2002003841428 Sep 200128 Mar 2002Taylor Bradley L.Address generator for local system memory in reconfigurable logic chip
US2002004595212 Oct 200118 Abr 2002Blemel Kenneth G.High performance hybrid micro-computer
US2002007328217 Ago 200113 Jun 2002Gerard ChauvelMultiple microprocessors with a shared cache
US2002009975924 Ene 200125 Jul 2002Gootherts Paul DavidLoad balancer with starvation avoidance
US200201242387 Ago 20015 Sep 2002Paul MetzgenSoftware-to-hardware compiler
US200201435052 Abr 20013 Oct 2002Doron DrusinskyImplementing a finite state machine using concurrent finite state machines with delayed communications and no shared control signals
US200201442292 Abr 20013 Oct 2002Shaila HanrahanFaster scalable floorplan which enables easier data control flow
US200201520606 Jul 200117 Oct 2002Tseng Ping-ShengInter-chip communication system
US2002015696210 Jun 200224 Oct 2002Rajesh ChopraMicroprocessor having improved memory management unit and cache memory
US2002016588621 Nov 20017 Nov 2002Lam Peter Shing FaiModification to reconfigurable functional unit in a reconfigurable chip to perform linear feedback shift register function
US2003001474329 Jun 199816 Ene 2003Cooke Laurence H.Method for compiling high level programming languages
US2003004660728 Sep 20016 Mar 2003Frank MayMethod for debugging reconfigurable architectures
US2003005271119 Sep 200120 Mar 2003Taylor Bradley L.Despreader/correlator unit for use in reconfigurable chip
US2003005586118 Sep 200120 Mar 2003Lai Gary N.Multipler unit in reconfigurable chip
US2003005608528 May 200220 Mar 2003Entire InterestUnit for processing numeric and logic operations for use in central processing units (CPUS), multiprocessor systems, data-flow processors (DSPS), systolic processors and field programmable gate arrays (FPGAS)
US2003005609114 Sep 200120 Mar 2003Greenberg Craig B.Method of scheduling in a reconfigurable hardware architecture with multiple hardware configurations
US2003005620228 Sep 200120 Mar 2003Frank MayMethod for translating programs for reconfigurable architectures
US2003006154225 Sep 200127 Mar 2003International Business Machines CorporationDebugger program time monitor
US2003006292228 Sep 20013 Abr 2003Xilinx, Inc.Programmable gate array having interconnecting logic to support embedded fixed logic circuitry
US2003007005930 May 200110 Abr 2003Dally William J.System and method for performing efficient conditional vector operations for data parallel architectures
US200300936627 Oct 200215 May 2003Pact GmbhProcess for automatic dynamic reloading of data flow processors (DFPS) and units with two- or three-dimensional programmable cell architectures (FPGAS, DPGAS, and the like)
US2003009751326 Nov 200222 May 2003Martin Vorbachl/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures
US2003012357915 Nov 20023 Jul 2003Saeid SafaviViterbi convolutional coding method and apparatus
US200301356865 Abr 200217 Jul 2003Martin VorbachInternal bus system for DFPs and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity
US2003015434924 Ene 200214 Ago 2003Berg Stefan G.Program-directed cache prefetching for media processors
US2004001589928 Sep 200122 Ene 2004Frank MayMethod for processing data
US2004002500513 Jun 20015 Feb 2004Martin VorbachPipeline configuration unit protocols and communication
US2004003988023 Ago 200226 Feb 2004Vladimir PentkovskiMethod and apparatus for shared cache coherency for a chip multiprocessor or multiprocessor system
US2004007854819 Oct 200122 Abr 2004Claydon Anthony Peter JohnProcessor architecture
US200401680991 Mar 200426 Ago 2004Martin VorbachUnit for processing numeric and logic operations for use in central processing units (CPUs), multiprocessor systems
US200500662135 Mar 200224 Mar 2005Martin VorbachMethods and devices for treating and processing data
US2005009146828 Oct 200328 Abr 2005Renesas Technology America, Inc.Processor for virtual machines and method therefor
US2005014421021 Dic 200430 Jun 2005Xilinx, Inc.Programmable logic device with dynamic DSP architecture
US2005014421221 Dic 200430 Jun 2005Xilinx, Inc.Programmable logic device with cascading DSP slices
US2005014421521 Dic 200430 Jun 2005Xilinx, Inc.Applications of cascading DSP slices
US2006023009412 May 200612 Oct 2006Xilinx, Inc.Digital signal processing circuit having input register blocks
US2006023009612 May 200612 Oct 2006Xilinx, Inc.Digital signal processing circuit having an adder circuit with carry-outs
US2007008373017 Jun 200412 Abr 2007Martin VorbachData processing device and method
US200803133836 Ago 200818 Dic 2008Renesas Technology America, Inc.Processor for Virtual Machines and Method Therefor
US2009008560327 Sep 20072 Abr 2009Fujitsu Network Communications, Inc.FPGA configuration protection and control using hardware watchdog timer
USRE3436324 Jun 199131 Ago 1993Xilinx, Inc.Configurable electrical circuit having configurable logic elements and configurable interconnects
DE3855673T24 Ago 19887 May 1997IbmVon Peripheriegeräten ausgelöste Systemsteilrekonfiguration
DE4221278C229 Jun 199229 Feb 1996Martin VorbachBusgekoppeltes Mehrrechnersystem
DE10028397A113 Jun 200020 Dic 2001Pact Inf Tech GmbhRegistration method in operating a reconfigurable unit, involves evaluating acknowledgement signals of configurable cells with time offset to configuration
DE10036627A127 Jul 200014 Feb 2002Pact Inf Tech GmbhIntegrated cell matrix circuit has at least 2 different types of cells with interconnection terminals positioned to allow mixing of different cell types within matrix circuit
DE10129237A120 Jun 200118 Abr 2002Pact Inf Tech GmbhIntegrated cell matrix circuit has at least 2 different types of cells with interconnection terminals positioned to allow mixing of different cell types within matrix circuit
DE10204044A11 Feb 200214 Ago 2003Tridonicatco Gmbh & Co KgElektronisches Vorschaltgerät für Gasentladungslampe
DE19651075A19 Dic 199610 Jun 1998Pact Inf Tech GmbhEinheit zur Verarbeitung von numerischen und logischen Operationen, zum Einsatz in Prozessoren (CPU's), Mehrrechnersystemen, Datenflußprozessoren (DFP's), digitalen Signal Prozessoren (DSP's) oder dergleichen
DE19654595A120 Dic 19962 Jul 1998Pact Inf Tech GmbhI0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen
DE19654846A127 Dic 19969 Jul 1998Pact Inf Tech GmbhVerfahren zum selbständigen dynamischen Umladen von Datenflußprozessoren (DFPs) sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen (FPGAs, DPGAs, o. dgl.)
DE19704044A14 Feb 199713 Ago 1998Pact Inf Tech GmbhAddress generation with systems having programmable modules
DE19704728A18 Feb 199713 Ago 1998Pact Inf Tech GmbhVerfahren zur Selbstsynchronisation von konfigurierbaren Elementen eines programmierbaren Bausteines
DE19704742A111 Feb 199724 Sep 1998Pact Inf Tech GmbhInternes Bussystem für DFPs, sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen, zur Bewältigung großer Datenmengen mit hohem Vernetzungsaufwand
DE19807872A125 Feb 199826 Ago 1999Pact Inf Tech GmbhMethod of managing configuration data in data flow processors
DE19822776A120 May 199825 Mar 1999Mitsubishi Electric CorpData processing arrangement
DE19861088A130 Nov 199810 Feb 2000Pact Inf Tech GmbhRepairing integrated circuits by replacing subassemblies with substitutes
DE19926538A110 Jun 199914 Dic 2000Pact Inf Tech GmbhHardware with decoupled configuration register partitions data flow or control flow graphs into time-separated sub-graphs and forms and implements them sequentially on a component
EP0208457A324 Jun 19862 Nov 1988National Research Development CorporationA processor array
EP0221360B13 Oct 198630 Dic 1992International Business Machines CorporationDigital data message transmission networks and the establishing of communication paths therein
EP0428327A18 Nov 199022 May 1991Amt(Holdings) LimitedProcessor array system
EP0463721A326 Abr 199116 Jun 1993Gennum CorporationDigital signal processing device
EP0477809B121 Sep 199117 Dic 1997Intergraph CorporationHigh speed redundant rows and columns for semiconductor memories
EP0485690B115 Jun 199126 May 1999International Business Machines CorporationParallel associative processor system
EP0497029A328 May 199119 Ene 1994Analogic CorpReconfigurable sequential processor
EP0539595A19 Abr 19925 May 1993Fujitsu LimitedData processor and data processing method
EP0628917B19 Jun 19943 May 2000Elsag SpaMultiprocessor system
EP0638867A211 Ago 199415 Feb 1995Hughes Aircraft CompanyDynamically reconfigurable interprocessor communication network for SIMD multi-processors and apparatus implementing same
EP0678985B122 Abr 19951 Mar 2006Xilinx, Inc.A programmable logic device which stores more than one configuration and means for switching configurations
EP0686915B124 May 19958 Ago 2001Nec CorporationHierarchical resource management method
EP0726532B16 Feb 199626 Jul 2000International Business Machines CorporationArray processor communication architecture with broadcast instructions
EP748051A2 Título no disponible
EP0835685B111 Oct 199718 Sep 2002Mitsubishi Gas Chemical Company, Inc.Oxygen absorption composition
EP1102674B113 Jul 199919 Jun 2002UNICOR GmbH Rahn PlastmaschinenDevice for continuously producing seamless plastic tubes
EP1115204B13 Ene 200122 Abr 2009Nippon Telegraph and Telephone CorporationFunction reconfigurable semiconductor device and integrated circuit configuring the semiconductor device
EP1146432B122 Dic 19979 Jun 2010Richter, ThomasReconfiguration method for programmable components during runtime
EP1669885A27 Feb 199814 Jun 2006PACT XPP Technologies AGMethod for self-synchronization of configurable elements of a programmable component
GB2304438A Título no disponible
WO2003032975A116 Oct 200224 Abr 2003The Trustees Of The University Of PennsylvaniaModulation of ocular growth and myopia by gaba drugs
WO2007007269A Título no disponible
Otras citas
1"BlueGene/L: the next generation of scalable supercomputer," Kissel et al., Lawrence Livermore National Laboratory, Livermore, California, Nov. 18, 2002, 29 pages.
2"BlueGene/L—Hardware Architecture Overview," BlueGene/L design team, IBM Research, Oct. 17, 2003 slide presentation, pp. 1-23.
3"IEEE Standard Test Access Port and Boundary-Scan Architecture," IEEE Std. 1149.1-1990, pp. 1-127 (1993).
4"The Programmable Logic Data Book," XILINX, Inc., Section 2, pp. 1-240, Section 8, pp. 1, 23-25, 29, 45-52, 169-172 (1994).
5Abnous et al., "The Pleiades Architecture," U.C. Berkeley, Chapter I of the Application of Programmable DSPs in Mobile Communications, A. Gatherer and A. Auslander, Ed., Wiley, 2002, pp. 1-33.
6Abnous et al., "Ultra-Low-Power Domain-Specific Multimedia Processors," U.C. Berkeley, 1996 IEEE, pp. 461-470.
7Ade, et al., "Minimum Memory Buffers in DSP Applications," Electronics Letters, vol. 30, No. 6, Mar. 17, 1994, pp. 469-471.
8Advanced RISC Machines Ltd (ARM), "AMBA-Advanced Microcontroller Bus Architecture Specification," (Document No. ARM IHI 0001C), Sep. 1995, 72 pages.
9Advanced RISC Machines Ltd (ARM), "AMBA—Advanced Microcontroller Bus Architecture Specification," (Document No. ARM IHI 0001C), Sep. 1995, 72 pages.
10Advanced RISC Machines, "Introduction to AMBA," Section 1, pp. 1-1 to 1-7 (Oct. 1996).
11Agarwal, A., et al., "APRIL: A Processor Architecture for Multiprocessing," Laboratory for Computer Science, MIT, Cambridge, MA, IEEE 1990, pp. 104-114.
12Alfke, Peter, Xilinx Application Note, "Dynamic Reconfiguration," XAPP 093, Nov. 10, 1997, pp. 13-45 through 13-46.
13Alfke, Peter, Xilinx Application Note, "Megabit FIFO in Two Chips: One LCA Device and One DRAM," XAPP 030.000, 1994, pp. 8-148 through 8-150.
14Alfke, Peter; New, Bernie, Xilinx Application Note, "Adders, Subtracters and Accumulators in XC3000," XAPP 022.000, 1994, pp. 8-98 through 8-104.
15Alfke, Peter; New, Bernie, Xilinx Application Note, "Additional XC3000 Data," XAPP 024.000, 1994, pp. 8-11 through 8-20.
16Alfke, Peter; New, Bernie, Xilinx Application Note, "Implementing State Machines in LCA Devices," XAPP 027.001, 1994, pp. 8-169 through 8-172.
17Algotronix, Ltd., CAL4096 Datasheet, 1992, pp. 1-53.
18Algotronix, Ltd., CAL64K Preliminary Data Sheet, Apr. 1989, pp. 1-24.
19Algotronix, Ltd., CHS2x4 User Manual, "CHA2x4 Custom Computer," 1991, pp. 1-38.
20Alippi, C., et al., Determining the Optimum Extended Instruction Set Architecture for Application Specific Reconfigurable VLIW CPUs, IEEE, 2001, pp. 50-56.
21Allaire, Bill; Fischer, Bud, Xilinx Application Note, "Block Adaptive Filter," XAPP 055, Aug. 15, 1996 (Version 1.0), pp. 1-10.
22Almasi and Gottlieb, Highly Parallel Computing, The Benjamin/Cummings Publishing Company, Inc., Redwood City, CA, 1989, 3 pages (Fig. 4.1).
23Altera Application Note (73), "Implementing FIR Filters in Flex Devices," Altera Corporation, Feb. 1998, ver. 1.01, pp. 1-23.
24Altera Corporation product description, Flex 10K Embedded Programmable Logic Device Family, Jan. 2003, Ver. 4.2, pp. 1-128.
25Altera Corporation product description, Flex 8000 Programmable Logic Device Family, Jan. 2003, Ver. 11.1, pp. 1-62.
26Altera, "2. TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices," Altera Corporation, Jul. 2005, 28 pages.
27Altera, "APEX 20K Programmable Logic Device Family," Altera Corporation Data Sheet, Mar. 2004, ver. 5.1, pp. 1-117.
28Altera, "Apex II Programmable Logic Device Family," Altera Corporation Data Sheet, Aug. 2002, Ver. 3.0, 99 pages.
29Arabi et al., "PLD Integrates Dedicated High-speed Data Buffering, Complex State Machine, and Fast Decode Array," conference record on WESCON '93, Sep. 28, 1993, pp. 432-436.
30ARM Limited, "ARM Architecture Reference Manual," Dec. 6, 2000, pp. A10-6-A10-7.
31ARM, "The Architecture for the Digital World," http://www.arm.com/products, 3 pages (Mar. 18, 2009).
32ARM, "The Architecture for the Digital World; Milestones," http://www.arm.com/aboutarm/milestones.html, 5 pages (Mar. 18, 2009).
33Asari, et al., "FeRAM circuit technology for system on a chip," Proceedings First NASA/DoD Workshop on Evolvable Hardware, pp. 193-197 (1999).
34Athanas P. "A Functional Reconfigurable Architecture and Compiler for Adoptive Computing,", IEEE, pp. 49-55.
35Athanas, P. (Thesis), "An adaptive machine architecture and compiler for dynamic processor reconfiguration," Brown University 1992, pp. 1-157.
36Athanas, P. et al., "An Adaptive Hardware Machine Architecture and Compiler for Dynamic Processor Reconfiguration", IEEE, Laboratory for Engineering Man/Machine Systems Divsion of Engineering, Box D, Brown University Providence, Rhode Island, 1991, pp. 397-400.
37Athanas, Peter, et al., "IEEE Symposium on FPGAs For Custom Computing Machines," IEEE Computer Society Press, Apr. 19-21, 1995, pp. i-vii, 1-222.
38Atmel, "An Introduction to DSP Applications using the AT40K FPGA," FPGA Application Engineering, San Jose, CA, Apr. 2004, 15 pages.
39Atmel, 5-K-50K Gates Coprocessor FPGA with Free Ram, Data Sheet, Jul. 2006, 55 pages.
40Atmel, Configurable Logic Design & Application Book, Atmel Corporation, 1995, pp. 2-19 through 2-25.
41Atmel, Field Programmable Gate Array Configuration Guide, AT6000 Series Configuration Data Sheet, Sep. 1999, pp. 1-20.
42Atmel, FPGA-based FIR Filter Application Note, Sep. 1999, 10 pages.
43Ballagh et al., "Java Debug Hardware Models Using JBits," 8th Reconfigurable Architectures Workshop, 2001, 8 pages.
44Baumgarte, et al., PACT XPP"A Self-reconfigurable Data Processing Architecture," PACT Info. GMBH, Munchen Germany 2001.
45Becker et al., "Automatic Parallelism Exploitation for FPL-Based Accelerators," 1998, Proc. 31st Annual Hawaii International Conference on System Sciences, pp. 169-178.
46Becker, et al., "Parallelization in Co-compilation for Configurable Accelerators—a Host/accelerator Partitioning Compilation Method," proceedings of Asia and South Pacific Design Automation Conference, Yokohama, Japan, Feb. 10-13, 1998.
47Becker, J., "A Partitioning Compiler for Computers with Xputer-based Accelerators," 1997, Kaiserslautern University, 326 pp.
48Bellows et al., "Designing Run-Time Reconfigurable Systems with JHDL," Journal of VLSI Signal Processing, vol. 28, Kluwer Academic Publishers, The Netherlands, 2001, pp. 29-45.
49Berkeley Design Technology, Inc., Buyer's Guide to DSP Processors, 1995, Fremont, CA., pp. 673-698.
50Bittner, R. et al., "Colt: An Experiment in Wormhole Run-Time Reconfiguration," Bradley Department of Electrical and Computer Engineering, Blacksburg, VA, SPIE-International Society for Optical Engineering, vol. 2914/187, Nov. 1996, Boston, MA, pp. 187-194.
51Bittner, R. et al., "Colt: An Experiment in Wormhole Run-Time Reconfiguration," Bradley Department of Electrical and Computer Engineering, Blacksburg, VA, SPIE—International Society for Optical Engineering, vol. 2914/187, Nov. 1996, Boston, MA, pp. 187-194.
52Bittner, Ray, A., Jr., "Wormhole Run-Time Reconfiguration: Conceptualization and VLSI Design of a High Performance Computing system," Dissertation, Jan. 23, 1997, pp. i-xx, 1-415.
53BlueGene Project Update, Jan. 2002, IBM slide presentation, 20 pages.
54BlueGene/L, "An Overview of the BlueGene/L Supercomputer," The BlueGene/L Team, IBM and Lawrence Livermore National Laboratory, 2002 IEEE. pp. 1-22.
55Cadambi, et al., "Management Pipeline-reconfigurable FPGAs," ACM, 1998, pp. 55-64.
56Callahan, T. et al. "The Garp Architerchture and C Copiler," Computer, Apr. 2000, pp. 62-69.
57Camilleri, Nick; Lockhard, Chris, Xilinx Application Note, "Improving XC4000 Design Performance," XAPP 043.000, 1994, pp. 8-21 through 8-35.
58Cardoso, "Compilation of Java™ Algorithms onto Reconfigurable Computing Systems with Exploitation of Operation-Level Parallelism," Ph.D. Thesis, Universidade Technica de Lisboa (UTL), Lisbon, Portugal Oct. 2000 (English Abstract included).
59Cardoso, J.M.P. et al., "Compilation and Temporal Partitioning for a Coarse-Grain Reconfigurable Architecture," Lysacht, P. & Rosentiel, W. eds., "New Algorithms, Architectures and Applications for Reconfigurable Computing," (2005) pp. 105-115.
60Cardoso, J.M.P. et al., "Macro-Based Hardware Compilation of Javan(TM) Bytecodes into a Dynamic Reconfigurable Computing System," Field-Programmable Custom Computing Machines (1999) FCCM '99. Proceedings. Seventh Annual IEEE Symposium on Napa Valley, CA, USA, Apr. 21-23, 1999, IEEE Comput. Soc, US, (Apr. 21, 1999) pp. 2-11.
61Cardoso, J.M.P. et al., "Macro-Based Hardware Compilation of Javan™ Bytecodes into a Dynamic Reconfigurable Computing System," Field-Programmable Custom Computing Machines (1999) FCCM '99. Proceedings. Seventh Annual IEEE Symposium on Napa Valley, CA, USA, Apr. 21-23, 1999, IEEE Comput. Soc, US, (Apr. 21, 1999) pp. 2-11.
62Cartier, Lois, Xilinx Application Note, "System Design with New XC4000EX I/O Features," Feb. 21, 1996, pp. 1-8.
63Chaudhry, G.M. et al., "Separated caches and buses for multiprocessor system," Circuits and Systems, 1993; Proceedings of the 36th Midwest Symposium on Detroit, MI, USA, Aug. 16-18, 1993, New York, NY IEEE, Aug. 16, 1993, pp. 1113-1116, XP010119918 ISBN: 0-7803-1760-2.
64Chen et al., "A Reconfigurable Multiprocessor IC for Rapid Prototyping of Algorithmic-Specific High-Speed DSP Data Paths," 1992 IEEE, pp. 1895-1904.
65Chen, D., (Thesis) "Programmable arithmetic devices for high speed digital signal processing," U. California Berkeley 1992, pp. 1-175.
66Churcher, S., et al., "The XC6200 FastMap TM Processor Interface," Xilinx, Inc., Aug. 1995, pp. 1-8.
67Clearspeed, CSX Processor Architecture, Whitepaper, PN-1110-0306, 2006, pp. 1-14, www.clearspeed.com.
68Clearspeed, CSX Processor Architecture, Whitepaper, PN-1110-0702, 2007, pp. 1-15, www.clearspeed.com.
69Cook, Jeffrey J., "The Amalgam Compiler Infrastructure," Thesis at the University of Illinois at Urbana-Champaign (2004) Chapter 7 & Appendix G.
70Cowie, Beth, Xilinx Application Note, "High Performance, Low Area, Interpolator Design for the XC6200," XAPP 081, May 7, 1997 (version 1.0), pp. 1-10.
71Cronquist, D. et al., Architecture Design of Reconfigurable Pipelined Datapaths, Department of Computer Science and Engineering, University of Washington, Seattle, WA, Proceedings of the 20th Anniversary Conference on Advanced Research in VSLI, 1999, pp. 1-15.
72Culler, D.E; Singh, J.P., "Parallel Computer Architecture," p. 17, 1999, Morgan Kaufmann, San Francisco, CA USA, XP002477559.
73Culler, D.E; Singh, J.P., "Parallel Computer Architecture," pp. 434-437, 1999, Morgan Kaufmann, San Francisco, CA USA, XP002477559.
74Defendant's Claim Construction Chart for P.R 4-2 Constructions and Extrinsic Evidence for Terms Proposed by Defendants, PACT XPP Technologies, AG. v. Xilinx, Inc. and Avnet, Inc., Case No. 2:07-cv-00563-TJW-CE, U.S. District Court for the Eastern District of Texas, Dec. 28, 2007, pp. 1-19.
75Defendants' Invalidity Contentions in PACT XPP Technologies, AG v. Xilinx, Inc., et al., (E.D. Texas Dec. 28, 2007) (No. 2:07cv563)., including Exhibits a through K in separate PDF files.
76DeHon, Andre, "Reconfigurable Architectures for General-Purpose Computing," Massachusetts Institute of Technology, Technical Report AITR-1586, Oct. 1996, XP002445054, Cambridge, MA, pp. 1-353.
77Del Corso, et al., "Microcomputer Buses and Links," Academic Press Inc. Ltd., pp. 138-143, 277-285 (1986).
78Diniz et al., "Automatic Synthesis of Data Storage and Control Structures for FPGA-based Computing Engines", 2000, IEEE, pp. 91-100.
79Donandt, "Improving Response Time of Programmable Logic Controllers by Use of a Boolean Coprocessor", AEG Research Institute Berlin, IEEE,1989, pp. 4-167-4-169.
80Duncan, Ann, Xilinx Application Note, "A32x16 Reconfigurable Correlator for the XC6200," XAPP 084, Jul. 25, 1997 (Version 1.0), pp. 1-14.
81Dutt, et al., "If Software is King for Systems-on-Silicon, What's New in Compiler," IEEE, pp. 322-325.
82Ebeling, C. et al., "Mapping Applications to the RaPiD Configurable Architecture," Department of Computer Science and Engineering, University of Washington, Seattle, WA, FPGAs for Custom Computing Machines, 1997. Proceedings., The 5th Annual IEEE Symposium, Publication Date: Apr. 16-18, 1997, 10 pages.
83Ebeling, C., et al., "RaPiD-Reconfigurable Pipelined Datapath," Dept. Of Computer Science and Engineering, U. Washington, 1996, pp. 126-135.
84Ebeling, C., et al., "RaPiD—Reconfigurable Pipelined Datapath," Dept. Of Computer Science and Engineering, U. Washington, 1996, pp. 126-135.
85Epstein, D., "IBM Extends DSP Performance with Mfast-Powerful Chip Uses Mesh Architecture to Accelerate Graphics, Video," 1995 MicroDesign Resources, vol. 9, No. 16, Dec. 4, 1995, pp. 231-236.
86Epstein, D., "IBM Extends DSP Performance with Mfast—Powerful Chip Uses Mesh Architecture to Accelerate Graphics, Video," 1995 MicroDesign Resources, vol. 9, No. 16, Dec. 4, 1995, pp. 231-236.
87Epstein, Dave, "IBM Extends DSP Performance with Mfaxt," Microprocessor Report, vol. 9, No. 16 (MicroDesign Resources), Dec. 4, 1995, pp. 1-4 [XL0029013].
88Equator, Pixels to Packets, Enabling Multi-Format High Definition Video, Equator Technologies BSP-15 Product Brief, www.equator.com, 2001, 4 pages.
89Fawcett, B., "New SRAM-Based FPGA Architectures Address New Applications," Xilinx, Inc. San Jose, CA, Nov. 1995, pp. 231-236.
90Fawcett, B.K., "Map, Place and Route: The Key to High-Density PLD Implementation," Wescon Conference, IEEE Center (Nov. 7, 1995) pp. 292-297.
91Ferrante, et al., "The Program Dependence Graph and its Use in Optimization ACM Transactions on Programming Languages and Systems," Jul. 1987, USA, [online] Bd. 9, Nr., 3, pp. 319-349, XP0021156651 ISSN: 0164-0935 ACM Digital Library.
92Fineberg, et al., "Experimental Analysis of a Mixed-Mode Parallel Architecture Using Bitonic Sequence Sorting", vol. 11. No. 3, Mar. 1991, pp. 239-251.
93Fornaciari, et al., System-level power evaluation metrics, 1997 Proceedings of the 2nd Annual IEEE International Conference on Innovative Systems in Silicon, New York, NY, Oct. 1997, pp. 323-330.
94Forstner, "Wer Zuerst Kommt, Mahlt Zuerst!: Teil 3: Einsatzgebiete und Anwendungsbeispiele von FIFO-Speichern", Elecktronik, Aug. 2000, pp. 104-109.
95Freescale Slide Presentation, An Introduction to Motorola's RCF (Reconfigurable Compute Fabric) Technology, Presented by Frank David, Launched by Freescale Semiconductor, Inc., 2004, 39 pages.
96Galanis, M.D. et al., "Accelerating Applications by Mapping Critical Kernels on Coarse-Grain Reconfigurable Hardware in Hybrid Systems," Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2005, 2 pages.
97Gokhale, et al., "Automatic Allocation of Arrays to Memories in FPGA processors with Multiple Memory Banks", Field-Programmable Custom Computing Machines, 1999, IEEE, pp. 63-67.
98Goslin, G; Newgard, B, Xilinx Application Note, "16-Tap, 8-Bit FIR Filter Applications Guide," Nov. 21, 1994, pp. 1-5.
99Guccione et al., "JBits: Java based interface for reconfigurable computing," Xilinx, Inc., San Jose, CA, 1999, 9 pages.
100Guo, Z. et al., "A Compiler Intermediate Representation for Reconfigurable Fabrics," University of California, Riverside, Dept. of Electrical Engineering, IEEE 2006, 4 pages.
101Gwennap, Linley, "Intel's P6 Bus Designed for Multiprocessing," Microprocessor Report, vol. 9, No. 7 (MicroDesign Resources), May 30, 1995, p. 1 and pp. 6-10.
102Gwennap, Linley, "P6 Underscores Intel's Lead," Microprocessor Report, vol. 9., No. 2, Feb. 16, 1995 (MicroDesign Resources), p. 1 and pp. 6-15.
103Hammes, et al., "Cameron: High Level Language Compilation for Reconfigurable Systems," Department of Computer Science, Colorado State University, Conference on Parallel Architectures and Compilation Techniques, Oct. 12-16, 1999.
104Hartenstein et al., "A Two-Level Co-Design Framework for Xputer-based Data-driven Reconfigurable Accelerators," 1997, Proceedings of the Thirtieth Annual Hawaii International Conference on System Sciences, 10 pp.
105Hartenstein et al., "Parallelizing Compilation for a Novel Data-Parallel Architecture," 1995, PCAT-94, Parallel Computing: Technology and Practice, 13 pp.
106Hauck, "The Roles of FPGA's in Reprogrammable Systems," IEEE, Apr. 1998, pp. 615-638.
107Hauser, et al., "Garp: A MIPS Processor with a Reconfigurable Coprocessor", University of California, Berkeley, IEEE, 1997, pp. 12-21.
108Hauser, John R., "The Garp Architecture," University of California at Berkeley, Computer Science Division, Oct. 1997, pp. 1-55.
109Hauser, John Reid, (Dissertation) "Augmenting A Microprocessor with Reconfigurable Hardware," University of California, Berkeley, Fall 2000, 255 pages. (submitted in 3 PDFs, Parts 1-3).
110Hedge, 3D WASP Devices for On-line Signal and Data Processing, 1994, International Conference on Wafer Scale Integration, pp. 11-21.
111Hendrich, N., et al., "Silicon Compilation and Rapid Prototyping of Microprogrammed VLSI-Circuits with Mimola and Solo 1400," Microprocessing & Microprogramming (Sep. 1992) vol. 35(1-5), pp. 287-294.
112Huang, Libo et al., "A New Architecture for Multiple-Precision Floating-Point Multiply-Add Fused Unit Design," School of Computer National University of Defense Technology, China, IEEE 2007, 8 pages.
113Hwang, et al., "Min-cut Replication in Partitioned Networks" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, [online] Bd. 14, Nr. 1, Jan. 1995, pp. 96-106, XP00053228 USA ISSN: 0278-0070 IEEE Xplore.
114Hwang, K., "Computer Architecture and Parallel Processing," Data Flow Computers and VLSI Computations, XP-002418655, 1985 McGraw-Hill, Chapter 10, pp. 732-807.
115IMEC, "ADRES multimedia processor & 3MF multimedia platform," Transferable IP, IMEC Technology Description, (Applicants believe the date to be Oct. 2005), 3 pages.
116Inside DSP, "Ambric Discloses Massively Parallel Architecture," Aug. 23, 2006, HTTP://insidedsp.com/tabid/64/articleType/ArticleView/articleId/l55/Defa . . . , 2 pages.
117Intel, "Pentium Pro Family Developer's Manual , vol. 3: Operating System Writer's Guide," Intel Corporation, Dec. 1995, [submitted in 4 PDF files: Part I, Part II, Part III and Part IV], 458 pages.
118Intel, Intel MXP5800/MXP5400 Digital Media Processors, Architecture Overview, Jun. 2004, Revision 2.4, pp. 1-24.
119Iseli, et al. "A C++ Compiler for FPGA Custom Execution Units Synthesis," IEEE. 1995, pp. 173-179.
120Isshiki, et al., "Bit-Serial Pipeline Synthesis for Multi-FPGA Systems with C++ Design Capture," 1996 IEEE, pp. 38-47.
121Iwanczuk, Roman, Xilinx Application Note, "Using the XC4000 RAM Capability," XAPP 031.000, 1994, pp. 8-127 through 8-138.
122Jacob, et al., "Memory Interfacing and Instruction Specification for Reconfigurable Processors", ACM 1999, pp. 145-154.
123Jantsch, Axel et al., "Hardware/Software Partitioning and Minimizing Memory Interface Traffic," Electronic System Design Laboratory, Royal Institute of Technology, ESDLab, Electrum 229, S-16440 Kista, Sweden (Apr. 1994), pp. 226-231.
124Jantsch, et al., "A Case Study on Hardware/software Partitioning," Royal Institute of Technology, Kista, Sweden, Apr. 10, 1994 IEEE, pp. 111-118.
125Jo, Manhwee et al., "Implementation of Floating-Point Operations for 3D Graphics on a Coarse-Grained Reconfigurable Architecture," Design Automation Laboratory, School of EE/CS, Seoul National University, Korea, IEEE 2007, pp. 127-130.
126John, et al., "A Dynamically Reconfigurable Interconnect for Array Processors", vol. 6, No. 1, Mar. 1998, IEEE, pp. 150-157.
127Kanter, David, "NVIDIA's GT200: Inside a Parallel Processor," http://www.realworldtech.com/page.cfm?ArticleID=RWT090989195242&p=1, Sep. 8, 2008, 27 pages.
128Kean, T., et al., "A Fast Constant Coefficient Multiplier for the XC6200," Xilinx, Inc., Lecture Notes in Computer Science, vol. 1142, Proceedings of the 6th International Workshop of Field-Programmable Logic, 1996, 7 pages.
129Kean, T.A., "Configurable Logic: A Dynamically Programmable Cellular Architecture and its VLSI Implementation," University of Edinburgh (Dissertation) 1988, pp. 1-286.
130Kim et al., "A Reconfigurable Multifunction Computing Cache Architecture," IEEE Transactions on Very Large Scale Integration (VLSI) Systems vol. 9, Issue 4, Aug 2001 pp. 509-523.
131Knapp, Steven, "Using Programmable Logic to Accelerate DSP Functions," Xilinx, Inc., 1995, pp. 1-8.
132Koch, Andreas et al., "High-Level-Language Compilation for Reconfigurable Computers," Proceedings of European Workshop on Reconfigurable Communication-Centric SOCS (Jun. 2005) 8 pages.
133Koch, et al, "Practical Experiences with the SPARXIL Co-Processor", 1998, IEEE, pp. 394-398.
134Kung, "Deadlock Avoidance for Systolic Communication", 1988 Conference Proceedings of 15th Annual International Symposium on Computer Architecture, May 30, 1988, pp. 252-260.
135Lange, H. et al., "Memory access schemes for configurable processors," Field-Programmable Logic and Applications, International Workshop, FPL, Aug. 27, 2000, pp. 615-625, XP02283963.
136Lee, et al., "Multimedia extensions for general-purpose processors," IEEE Workshop on Signal Processing Systems, SIPS 97—Design and Implementation, pp. 9-23 (1997).
137Lee, Ming-Hau et al., "Designs and Implementation of the MorphoSys Reconfigurable Computing Processors," The Journal of VLSI Signal Processing, Kluwer Academic Publishers, BO, vol. 24, No. 2-3, Mar. 2, 2000, pp. 1-29.
138Li, Zhiyuan, et al., "Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation," International Symposium on Field Programmable Gate Arrays, Feb. 1, 2002, pp. 187-195.
139Ling, "WASMII: An MPLD with Data-Driven Control on a Virtual Hardware," Journal of Supercomputing, Kluwer Acdemic Publishers, Dordrecht, Netherlands, 1995, pp. 253-276.
140M. Morris Mano, "Digital Design," by Prentice Hall, Inc., Englewood Cliffs, New Jersey 07632, 1984, pp. 119-125, 154-161.
141M. Saleeba, "A Self-Contained Dynamically Reconfigurable Processor Architecture", Sixteenth Australian Computer Science Conference, ASCS-16, QLD, Australia, Feb. 1993.
142Maxfield, C. "Logic that Mutates While-U-Wait" EDN (Bur. Ed) (USA), EDN (European Edition), Nov. 7, 1996, Cahners Publishing, USA.
143Maxfield,C., "Logic that Mutates While-U-Wait," EDN (Bur. Ed) (USA), EDN (European Edition), Nov. 7, 1996, Cahners Publishing, USA, pp. 137-140, 142.
144Mei, Bingfeng et al., "Adres: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix," Proc. Field-Programmable Logic and Applications (FPL 03), Springer, 2003, pp. 61-70.
145Mei, Bingfeng, "A Coarse-Grained Reconfigurable Architecture Template and Its Compilation Techniques," Katholeike Universiteit Leuven, PhD Thesis, Jan. 2005, IMEC vzw, Universitair Micro-Electronica Centrum, Belgium, pp. 1-195 (and Table of Contents).
146Mei, Bingfeng, et al., "Design and Optimization of Dynamically Reconfigurable Embedded Systems," IMEC vzw, 2003, Belgium, 7 pages, http://www.imec.be/reconfigurable/pdf/ICERSA-01-design.pdf.
147Mei, Bingfeng, et al., "Design and Optimization of Dynamically Reconfigurable Embedded Systems," IMEC vzw, 2003, Belgium, 7 pages, http://www.imec.be/reconfigurable/pdf/ICERSA—01—design.pdf.
148Melvin, Stephen et al., "Hardware Support for Large Atomic Units in Dynamically Scheduled Machines," Computer Science Division, University of Califormia, Berkeley, IEEE (1988), pp. 60-63.
149Miller, et al., "High-Speed FIFOs Contend with Widely Differing Data Rates: Dual-port RAM Buffer and Dual-pointer System Provide Rapid, High-density Data Storage and Reduce Overhead", Computer Design, Sep. 1, 1985, pp. 83-86.
150Mirsky, "MATRIX: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources," Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, 1996, pp. 157-1666.
151Miyamori, T. et al., "REMARC: Reconfigurable Multimedia Array Coprocessor," Computer Systems Laboratory, Stanford University, IEICE Transactions on Information and Systems E Series D, 1999; (abstract): Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p. 261, Feb. 22-25, 1998, Monterey, California, United States, pp. 1-12.
152Moraes, F., et al., "A Physical Synthesis Design Flow Based on Virtual Components," XV Conference on Design of Circuits and Integrated Systems (Nov. 2000) 6 pages.
153Murphy, C., "Virtual Hardware Using Dynamic Reconfigurable Field Programmable Gate Arrays," Engineering Development Centre, Liverpool John Moores University, UK, GERI Annual Research Symposium 2005, 8 pages.
154Myers, G., Advances in Computer Architecture, Wiley-Interscience Publication, 2nd ed., John Wiley & Sons, Inc. pp. 463-494, 1978.
155Nageldinger, U., "Design-Space Exploration for Coarse Grained Reconfigurable Architectures," (Dissertation) Universitaet Kaiserslautern, 2000, Chapter 2, pp. 19-45.
156Neumann, T., et al., "A Generic Library for Adaptive Computing Environments," Field Programmable Logic and Applications, 11th International Conference, FPL 2001, Proceedings (Lecture Notes in Computer Science, vol. 2147) (2001) pp. 503-512.
157New, Bernie, Xilinx Application Note, "Accelerating Loadable Counters in SC4000," XAPP 023.001, 1994, pp. 8-82 through 8-85.
158New, Bernie, Xilinx Application Note, "Boundary Scan Emulator for XC3000," XAPP 007.001, 1994, pp. 8-53 through 8-59.
159New, Bernie, Xilinx Application Note, "Bus-Structured Serial Input-Output Device," XAPP 010.001, 1994, pp. 8-181 through 8-182.
160New, Bernie, Xilinx Application Note, "Complex Digital Waveform Generator," XAPP 008.002, 1994, pp. 8-163 through 8-164.
161New, Bernie, Xilinx Application Note, "Ultra-Fast Synchronous Counters," XAPP 014.001, 1994, pp. 8-78 through 8-81.
162New, Bernie, Xilinx Application Note, "Using the Dedicated Carry Logic in XC4000," XAPP 013.001, 1994, pp. 8-105 through 8-115.
163Nilsson, et al., "The Scalable Tree Protocol—A Cache Coherence Approaches for Large-Scale Multiprocessors" IEEE, pp. 498-506 Dec. 1992.
164Norman, Richard S., Hyperchip Business Summary, The Opportunity, Jan. 31, 2000, pp. 1-3.
165Ohmsha, "Information Processing Handbook," edited by the Information Processing Society of Japan, pp. 376, Dec. 21, 1998.
166Olukotun, K., "The Case for a Single-Chip Microprocessor," ACM Sigplan Notices, ACM, Association for Computing Machinery, New York, vol. 31, No. 9, Sep. 1996 pp. 2-11.
167PACT Corporation, "The XPP Communication System," Technical Report 15 (2000), pp. 1-16.
168PACT's P.R. 4-1 List of Claim Terms for Construction, PACT XPP Technologies, AG. v. Xilinx, Inc. and Avnet, Inc., Case No. 2:07-cv-00563-TJW-CE, U.S. District Court for the Eastern District of Texas, Dec. 28, 2007, pp. 1-7.
169PACT's P.R. 4-2 Preliminary Claim Constructions and Extrinsic Evidence, PACT XPP Technologies, AG. v. Xilinx, Inc. and Avnet, Inc., Case No. 2:07-cv-00563-TJW-CE, U.S. District Court for the Eastern District of Texas, Dec. 28, 2007, pp. 1-16, and Exhibits re Extrinsic Evidence Parts in seven (7) separate additional PDF files (Parts 1-7).
170Parhami, B., "Parallel Counters for Signed Binary Signals," Signals, Systems and Computers, 1989, Twenty-Third Asilomar Conference, vol. 1, pp. 513-516.
171PCI Local Bus Specification, Production Version, Revision 2.1, Portland, OR, pp. 1-281 (Jun. 1, 1995).
172Piotrowski, "IEC-BUS, Die Funktionsweise des IEC-Bus und seine Anwendung in Geräten und Systemen", 1987, Franzis-Verlag GmbH, München, pp. 20-25.
173Pirsch, et al., "VLSI implementations of image and video multimedia processing systems," IEEE Transactions on Circuits and Systems for Video Technology 8(7): 878-891 (Nov. 1998).
174Price et al., "Debug ofReconfigurable Systems," Xilinx, Inc., San Jose, CA, Proceedings of SPIE, 2000, pp. 181-187.
175Ridgeway, David, Xilinx Application Note, "Designing Complex 2-Dimensional Convolution Filters," XAPP 037.000, 1994, pp. 8-175 through 8-177.
176Roterberg, Eric., et al., "Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching," Proceedings of the 29th Annual Internatinoal Symposium on Michoarchitecture, Paris, France, IEEE (1996), 12 pages.
177Rowson, J., et al., "Second-generation compilers optimize semicustom circuits," Electronic Design, Feb. 19, 1987, pp. 92-96.
178Saleeba, Z.M.G., "A Self-Reconfiguring Computer System," Department of Computer Science, Monash University (Dissertation) 1998, pp. 1-306.
179Salefski, et al., "Re-configurable computing in wireless," Annual ACM IEEE Design Automation Conference: Proceedings of the 38th conference on Design automation, pp. 178-183 (2001).
180Schewel, J., "A Hardware/Software Co-Design System using Configurable Computing Technology," Virtual Computer Corporation, Reseda, CA, IEEE 1998, pp. 620-625.
181Schmidt, et al., "Datawave: A Single-Chip Multiprocessor for Video Applications," IEEE Micro11(3): 22-25 and 88-94 (Jun. 1991).
182Schmidt, H. et al., "Behavioral synthesis for FGPA-based computing," Carnegie Mellon University, Pittsburgh, PA, 1994 IEEE, pp. 125-132.
183Schmit, et al., Hidden Markov Modeling and Fuzzy Controllers in FPGAs, FPGAs for Custom Computing Machined, 1995; Proceedings, IEEE Symposium on Napa Valley, CA, Apr. 1995, pp. 214-221.
184Schönfeld, M., et al., "The LISA Design Environment for the Synthesis of Array Processors Including Memories for the Data Transfer and Fault Tolerance by Reconfiguration and Coding Techniques," J. VLSI Signal Processing Systems for Signal, Image, and Video Technology, ( Oct. 1, 1995) vol. 11(1/2), pp. 51-74.
185Segers, Dennis, Xilinx Memorandum, "MIKE-Product Description and MRD," Jun. 8, 1994, pp. 1-29.
186Segers, Dennis, Xilinx Memorandum, "MIKE—Product Description and MRD," Jun. 8, 1994, pp. 1-29.
187Shin, D., et al., "C-based Interactive RTL Design Methodology," Technical Report CECS-03-42 (Dec. 2003) pp. 1-16.
188Short, Kenneth L., Microprocessors and Programmed Logic, Prentice Hall, Inc., New Jersey 1981, p. 34.
189Siemers, "Rechenfabrik Ansaetze Fuer Extrem Parallele Prozessoren", Verlag Heinze Heise GmbH., Hannover, DE No. 15, Jul. 16, 2001, pp. 170-179.
190Simunic, et al., Source Code Optimization and Profiling of Energy Consumation in Embedded Systems, Proceedings of the 13th International Symposium on System Synthesis, Sep. 2000, pp. 193-198.
191Singh, H. et al., "MorphoSys: An Integrated Reconfigurable System for Data-Parallel Computation-Intensive Applications," University of California, Irvine, CA. And Federal University of Rio de Janeiro, Brazil, 2000, IEEE Transactions on Computers, pp. 1-35.
192Sondervan, J., "Retiming and logic synthesis," Electronic Engineering (Jan. 1993) vol. 65(793), pp. 33, 35-36.
193Soni, M., "VLSI Implementation of a Wormhole Run-time Reconfigurable Processor," Jun. 2001, (Masters Thesis)Virginia Polytechnic Institute and State University, 88 pages.
194Sundararajan et al., "Testing FPGA Devices Using JBits," Proc. MAPLD 2001, Maryland, USA, Katz (ed.), NASA, CA, 8 pages.
195Sutton et al., "A Multiprocessor DSP System Using PADDI-2," U.C. Berkeley, 1998 ACM, pp. 62-65.
196Tau, Edward, et al., "A First Generation DPGA Implementation," FPD'95, pp. 138-143.
197Tenca, et al., "A Variable Long-Precision Arithmetric Unit Design for Reconfigurable Copressor Architectures", University of California, Los Angeles, 1998, pp. 216-225.
198Texas Instruments, "TMS320C80 (MVP) Parallel Processor," User's Guide, Digital Signal Processing Products 1995, 73 pages.
199Texas Instruments, "TMS320C80 Digital Signal Processor," Data Sheet, Digital Signal Processing Solutions 1997, 171 pages.
200Texas Instruments, "TMS320C8x System-Level Synopsis," Sep. 1995, 75 pages.
201The XPP White Paper, Release 2.1, PACT—A Technical Perspective, Mar. 27, 2002, pp. 1-27.
202TMS320C54X DSP: CPU and Peripherals, Texas Instruments, 1996, pp. 6-26 to 6-46.
203TMS320C54x DSP: Mnemonic Instruction Set, Texas Instruments, 1996, p. 4-64.
204Trainor, D.W., et al., "Implementation of the 2D DCT Using A Xilinx XC6264 FPGA," 1997, IEEE Workshop of Signal Processing Systems SiPS 97, pp. 541-550.
205Trimberger, S, (Ed.) et al., "Field-Programmable Gate Array Technology," 1994, Kluwer Academic Press, pp. 1-258 (and the Title Page, Table of Contents, and Preface) [274 pages total].
206Trimberger, S., "A Reprogrammable Gate Array and Applications," IEEE 1993, Proceedings of the IEEE, vol. 81, No. 7, Jul. 1993, pp. 1030-1041.
207Trimberger, S., et al., "A Time-Multiplexed FPGA," Xilinx, Inc., 1997 IEEE, pp. 22-28.
208U.S. Appl. No. 60/109,417, filed Nov. 18, 1998, Jefferson et al.
209U.S. Appl. No. 90/010,979, filed May 4, 2010, Vorbach et al.
210U.S. Appl. No. 90/011,087, filed Jul. 8, 2010, Vorbach et al.
211Ujvari, Dan, Xilinx Application Note, "Digital Mixer in an XC7272," XAPP 035.002, 1994, p. 1.
212Vasell et al., "The Function Processor: A Data-Driven Processor Array for Irregular Computations," Chalmers University of Technology, Sweden, 1992, pp. 1-21.
213Veendrick, H., et al., "A 1.5 GIPS video signal processor (VSP)," Philips Research Laboratories, The Netherlands, IEEE 1994 Custom Integrated Circuits Conference, pp. 95-98.
214Venkatachalam et al., "A highly flexible, distributed multiprocessor architecture for network processing," Computer Networks, The International Journal of Computer and Telecommunications Networking, vol. 41, No. 5, Apr. 5, 2003, pp. 563-568.
215Villasenor, John, et al., "Configurable Computing Solutions for Automatic Target Recognition," IEEE, 1996 pp. 70-79.
216Villasenor, John, et al., "Configurable Computing," Scientific American, vol. 276, No. 6, Jun. 1997, pp. 66-71.
217Villasensor, et al., "Express Letters Video Communications Using Rapidly Reconfigurable Hardware," IEEE Transactions on Circuits and Systems for Video Technology, IEEE, Inc. NY, Dec. 1995, pp. 565-567.
218Wada, et al., "A Performance Evaluation of Tree-based Coherent Distributed Shared Memory" Proceedings of the Pacific RIM Conference on Communications, Comput and Signal Proceesing, Victoria, May 19-21, 1993.
219Waingold, E., et al., "Baring it all to software: Raw machines," IEEE Computer, Sep. 1997, at 86-93.
220Webster's Ninth New Collegiate Dictionary, Merriam-Webster, Inc., 1990, p. 332 (definition of "dedicated").
221Weinhardt, "Compilation Methods for Structure-programmable Computers", dissertation, ISBN 3-89722-011-3, 1997.
222Weinhardt, "Ubersetzingsmethoden fur strukturprogrammierbare rechner," Dissertation for Doktors der Ingenieurwissenschaften der Universitat Karlsruhe; Jul. 1, 1997.
223Weinhardt, et al., "Pipeline Vectorization for Reconfigurable Systems", 1999, IEEE, pp. 52-60.
224Weinhardt, Markus et al., "Memory Access Optimization for Reconfigurable Systems," IEEE Proceedings Computers and Digital Techniques, 48(3) (May 2001) pp. 1-16.
225Wilkie, Bill, Xilinx Application Note, "Interfacing XC6200 to Microprocessors (MC68020 Example)," XAPP 063, Oct. 9, 1996 (Version 1.1), pp. 1-8.
226Wilkie, Bill, Xilinx Application Note, "Interfacing XC6200 to Microprocessors (TMS320C50 Example)," XAPP 064, Oct. 9, 1996 (Version 1.1), pp. 1-9.
227Witig, et al., "OneChip: An FPGA Processor with Reconfigurable Logic" IEEE, 1996 pp. 126-135.
228Wolfe, M. et al., "High Performance Compilers for Parallel Computing" (Addison-Wesley 1996) Table of Contents, 11 pages.
229Wu, et al., "A New Cache Directory Scheme", IEEE, pp. 466-472, Jun. 1996.
230XCELL, Issue 18, Third Quarter 1995, "Introducing three new FPGA Families!"; "Introducing the XC6200 FPGA Architecture: The First FPGA Architecture Optimized for Coprocessing in Embedded System Applications," 40 pages.
231Xilinx Application Note, A Fast Constant Coefficient Multiplier for the XC6200, XAPP 082, Aug. 24, 1997 (Version 1.0), pp. 1-5.
232Xilinx Application Note, Advanced Product Specification, "XC6200 Field Programmable Gate Arrays," Jun. 1, 1996 (Version 1.0), pp. 4-253-4-286.
233Xilinx Data Book, "The Programmable Logic Data Book," 1996, 909 pages.
234Xilinx product description, XC3000 Series Field Programmable Gate Arrays (XC3000A/L, XC3100A/L), Ver. 3.1, Nov. 9, 1998, pp. 1-76.
235Xilinx product description, XC4000E and XC4000X Series Field Programmable Gate Arrays, Ver. 1.6, May 14, 1999, pp. 1-68.
236Xilinx product description, XC6200 Field Programmable Gate Arrays, Ver. 1.10, Apr. 24, 1997, pp. 1-73.
237Xilinx Technical Data, "XC5200 Logic Cell Array Family," Preliminary (v1.0), Apr. 1995, pp. 1-43.
238Xilinx, "Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays," (v2.2) Sep. 10, 2002, Xilinx Production Product Specification, pp. 1-52.
239Xilinx, "Virtex-II and Virtex-II Pro X FPGA Platform FPGAs: Complete Data Sheet," (v4.6) Mar. 5, 2007, pp. 1-302.
240Xilinx, "Virtex-II and Virtex-II Pro X FPGA User Guide," Mar. 28, 2007, Xilinx user guide, pp. 1-559.
241Xilinx, "Virtex-II Platform FPGAs: Complete Data Sheet," (v3.5) Nov. 5, 2007, pp. 1-226.
242Xilinx, Inc.'s and Avnet, Inc.'s Disclosure Pursuant to P.R. 4-1; PACT XPP Technologies, AG. v. Xilinx, Inc. and Avnet, Inc., Case No. 2:07-cv-00563-TJW-CE, U.S. District Court for the Eastern District of Texas, Dec. 28, 2007, 9 pages.
243Xilinx, Inc.'s and Avnet, Inc.'s Disclosure Pursuant to P.R. 4-2; PACT XPP Technologies, AG. v. Xilinx, Inc. and Avnet, Inc., Case No. 2:07-cv-00563-TJW-CE, U.S. District Court for the Eastern District of Texas, Dec. 28, 2007, 4 pages.
244Xilinx, Series 6000 User's Guide, Jun. 26, 1997, 223 pages.
245Xilinx, White Paper 298: (Spartan-6 and Virtex-6 Devices) "Power Consumption at 40 and 50 nm," Matt Klein, Apr. 13, 2009, pp. 1-21.
246Xilinx, White Paper 370: (Virtex-6 and Spartan-6 FPGA Families) "Reducing Switching Power with Intelligent Clock Gating," Frederic Rivoallon, May 3, 2010, pp. 1-5.
247XLINX, "Logic Cell Array Families: XC4000, XC4000A and XC4000H", product description, pp. 2-7 to 2-15, Additional XC3000, XC31000 and XC3100A Data, pp. 8-16 and 9-14.
248Xu, et al., "Parallel QR Factorization on a Block Data Flow Architecture" Conference Proceeding Article, Mar. 1, 1992, pp. 332-336 XPO10255276, p. 333, Abstract 2.2, 2.3, 2.4-p. 334.
249Ye, et al., "A Compiler for a Processor With A Reconfigurable Functional Unit," FPGA 2000 ACM/SIGNA International Symposium on Field Programmable Gate Arrays, Monterey, CA Feb. 9-11, 2000, pp. 95-100.
250Yeung et al., "A Data-Driven Architecture for Rapid Prototyping of High Throughput DSP Algorithms," U.C. Berkeley, 1993 IEEE, pp. 225-234.
251Yeung et al., "A Reconfigurable Data-driven Multiprocessor Architecture for Rapid Prototyping of High Throughput DSP Algorithms," U.C. Berkeley, 1993 IEEE, pp. 169-178.
252Yeung, K., (Thesis) "A Data-Driven Multiprocessor Architecture for High Throughput Digital Signal Processing," Electronics Research Laboratory, U. California Berkeley, Jul. 10, 1995, pp. 1-153.
253Yeung, L., et al., "A 2.4GOPS Data-Driven Reconfigurable Multiprocessor IC for DSP," Dept. of EECS, U. California Berkeley, 1995 IEEE International Solid State Circuits Conference, pp. 108-110.
254Zhang et al., "Abstract: Low-Power Heterogeneous Reconfigurable Digital Signal Processors with Energy-Efficient Interconnect Network," U.C. Berkeley, pp. 1-120.
255Zhang, et al., "A 1V Heterogeneous Reconfigurable Processor IC for Baseband Wireless Applications." U.C. Berkeley, 2000 IEEE, 12 pages.
256Zhang, et al., Architectural Evaluation of Flexible Digital Signal Proceesing for Wireless Receivers, Signals, Systems and Computers, 2000; Conference Record of the Thirty-Fourth Asilomar Conference, Bd. 1, Oct. 29, 2000, pp. 78-83.
257Zilog Preliminary Product Specification, "Z86C95 CMOS Z8 Digital Signal Processor," 1992, pp. 1-82.
258Zilog Preliminary Product Specification, "Z89120 Z89920 (ROMless) 16-Bit Mixed Signal Processor," 1992, pp. 1-82.
259Zima, H. et al., "Supercompilers for parallel and vector computers" (Addison-Wesley 1991) Table of Contents, 5 pages.
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