|Número de publicación||USRE45232 E1|
|Tipo de publicación||Concesión|
|Número de solicitud||US 13/568,920|
|Fecha de publicación||4 Nov 2014|
|Fecha de presentación||7 Ago 2012|
|Fecha de prioridad||8 Oct 2001|
|También publicado como||US6472303|
|Número de publicación||13568920, 568920, US RE45232 E1, US RE45232E1, US-E1-RE45232, USRE45232 E1, USRE45232E1|
|Inventores||Dae Hee Weon, Seok Kiu Lee|
|Cesionario original||Conversant Ip N.B. 868 Inc.|
|Exportar cita||BiBTeX, EndNote, RefMan|
|Citas de patentes (39), Otras citas (2), Clasificaciones (20), Eventos legales (3)|
|Enlaces externos: USPTO, Cesión de USPTO, Espacenet|
1. Field of the Invention
The present invention generally relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device with an improved contact plug suitable for highly integrated semiconductor devices.
2. Description of the Related Art
As is well known, it is essential to reduce the contact resistance in a circuit line width to below 0.16 μm.
According to a recent method of forming a silicon contact plug, a contact hole is first formed and then, polycrystalline silicon is deposited therein. This method is performed by using a Chemical Mechanical Polishing (CMP) process.
Generally, it is desirable to apply selective epitaxial growth (SEG) during the manufacturing process of semiconductor devices since it is possible to reduce cell size, simplify manufacturing processes and improve electrical properties by using SEG.
Therefore, a plug using SEG can solve the problems of gap-fill and of undesirable increase of contact resistance.
Furthermore, it is possible to simplify the manufacturing process by using SEG since it does not require performing CMP and silicon recess etching for plug isolation.
However, there are several problems in applying SEG during plug manufacture.
First, there is a problem with the selectivity of the pattern material, that is, a material to form a window for growing the SEG.
Also, the surface of the nitride layer is exposed when the self-aligned contact (SAC) etch is applied to cell activation regions. The SEG has a different facet generation depending on the selectivity and the thermal stress of the pattern material.
Generally, in a low pressure chemical vapor deposition (LPCVD) process, the nitride materials have difficulty in achieving selectivity at a temperature below 850° C., as compared with oxide materials.
Therefore, the growth speed is lowered in order to have selectivity, thereby increasing the thermal budget on device.
The conventional method for manufacturing a semiconductor device will be described in more detail with reference to accompanying drawings.
Although it is not shown in the drawings, impurity junction regions (not shown) are formed by impurities implanted in the silicon substrate 1 on the lower part of both sides of the sidewall spacer 5.
Subsequently, an interlayer insulating layer 7 is deposited by using an oxide layer material on the silicon substrate 1, including the gate electrode structure 3 and the sidewall spacer 5, in order to prevent the generation of short-circuits between adjacent cells.
However, the conventional method has several problems in forming a contact hole and a contact plug having a high aspect ratio, wherein the circuit line width is below 0.16 μm.
In particular, one problem in the conventional contact formation process is to have a sufficient plug formation area by using a landing plug contact mask. That is, in the etching process to form a landing plug contact through SAC by a nitride layer spacer of the nitride layer barrier, the problem is that it is difficult to have a sufficient landing plug contact hole area due to the etching grade necessarily generated to have the etching selectivity ratio between the nitride layer of the gate spacer and the oxide layer of the interlayer insulating layer.
In order to solve the problem, SAC of selective single crystal silicon has been proposed as shown in
Then, a selective episilicon layer is grown over the height of the gate on the surface of the exposed silicon substrate 21, thereby forming a contact plug 33.
Afterwards, an interlayer insulating layer (not shown) is formed to electrically insulate the contact plug and then, additional processes (not shown) are performed.
However, this embodiment of the conventional method has several problems.
First, the allowable margin of the side is very low in the-episilicon growth process.
Therefore, as the device is formed having fine features, the distance between adjacent activation regions becomes shorter. The adhering episilicon layers thereby grow to the side from the adjacent activation regions.
In order to solve this problem, a method has been proposed whereby the episilicon layer is grown by using processes without side growth.
However, there are also several problems in applying the process without side growth.
When the episilicon is applied without side growth, the silicon of the activation region is formed in the shape of a “T” in order to form the contact plug, as shown in
However, it is very difficult to form activation regions in the shape of a “T” since the distance between the adjacent activation regions becomes shorter by the protruding part of the “T” and it is also difficult to form the cell in the shape of a “T” by using a photolithography process.
Furthermore, it is also difficult to obtain episilicon growth in a curved line.
In order to solve the above problems, a method is proposed whereby a contact is formed by a protruding part of a bit line. However, this is also very difficult to successfully perform.
Therefore, the present invention has been made to solve the above problems of the conventional method. The object of the present invention is to provide a method of manufacturing a semiconductor device capable of forming an improved contact plug suitable for highly integrated semiconductor devices.
Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of simplifying the manufacturing process by applying episilicon growth during plug formation.
Yet another object of the present invention is to provide a method of manufacturing a semiconductor device capable of having a sufficient gap fill margin due to the low step in the deposition of the interlayer insulating layer and the margin due to the reduction of target in the contact etch processes.
Still another object of the present invention is to provide a method of manufacturing a semiconductor device capable of having a maximum allowable margin of side growth in the episilicon growth process.
In order to accomplish the above objects, the present invention comprises the steps of: forming an insulating layer on a silicon substrate; forming a contact hole on the insulating layer; forming a selective silicon layer in the contact hole; and selectively forming a conductive plug on the selective silicon layer.
The above objects, and other features and advantages of the present invention will become more apparent after a complete understanding of the following detailed description is achieved when taken in conjunction with the accompanying drawings.
Although not shown in the drawings, an isolation layer (not shown) is first formed to define the device formation region and device isolation region on a silicon substrate 41.
Then, as shown in
In the above process, the hard mask 45 and the insulating layer spacer 47 are formed as nitrides on the gate 43, in order to prevent damage to each layer during the etch process to form the landing plug contact hole.
The height of the activation regions is increased by between 1500 and 2000 Å after the first episilicon layer 49 is formed. Therefore, the area of the activation region is increased to have a sufficient etching margin in the landing plug etch process in consideration of the angle in landing plug contact etch process.
When the first episilicon layer 49 is grown by a LPCVD process, the H bake process is performed at a temperature of between 800 and 1000° C. for between 1 and 5 minutes and then, SiH2Cl2 gas and HCl gas are supplied at a rate of between 10 and 500 sccm at a pressure of between 5 and 300 Torr.
When the first episilicon layer 49 is grown by a UHVCVD process, the H bake process is performed at a temperature of between 400 and 800° C. and at a pressure of between 0.1 mTorr and 20 mTorr and, Si2H6 gas and Cl2 gas are then supplied at a temperature of between 400 and 800° C. and at a pressure of between 0.1 mTorr and 100 Torr.
Although it is not shown in the drawings, a sensitive film (not shown) is applied on the interlayer insulating layer 51 and then, a sensitive film pattern for the landing plug contact mask (not shown) is formed by performing exposure and development processes using photolithography.
The polycrystalline silicon layer is formed by using a furnace or LPCVD of a single wafer. When the polycrystalline silicon layer is employed, a contact plug may be formed by performing planation on the polycrystalline silicon layer by CMP processes.
As described above, according to the present invention, a contact is easily formed by having a sufficient processing margin in the formation of a fine contact plug. That is, it is possible to have a sufficiently allowable margin of side growth in the episilicon growth process and to have a gap fill margin generated by the low step in the deposition of the interlayer insulating layer.
It is also possible to have a sufficient margin due to the reduction of target in etch processes to form the landing plug contact.
Although the preferred embodiment of this invention has been disclosed for illustrative purpose, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention.
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|Clasificación de EE.UU.||438/597, 438/675, 438/680, 257/E21.166, 438/637, 438/607, 257/E21.507|
|Clasificación internacional||H01L21/8234, H01L21/3205, H01L21/28, H01L21/285, H01L21/60, H01L21/44, H01L27/088, H01L21/205, H01L21/768, H01L23/52|
|Clasificación cooperativa||H01L21/28525, H01L21/76897, H01L21/76895|
|17 Mar 2014||AS||Assignment|
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|22 Jul 2015||AS||Assignment|
Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.,
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