UST887018I4 - Fabrication of integrated circuit gate field effect transistors - Google Patents
Fabrication of integrated circuit gate field effect transistors Download PDFInfo
- Publication number
- UST887018I4 UST887018I4 US887018DH UST887018I4 US T887018 I4 UST887018 I4 US T887018I4 US 887018D H US887018D H US 887018DH US T887018 I4 UST887018 I4 US T887018I4
- Authority
- US
- United States
- Prior art keywords
- gate
- gate insulator
- integrated circuit
- deposited
- effect transistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title abstract description 5
- 238000004519 manufacturing process Methods 0.000 title description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 8
- 239000010408 film Substances 0.000 abstract description 7
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 6
- 239000012212 insulator Substances 0.000 abstract description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 6
- 239000012190 activator Substances 0.000 abstract description 5
- 239000003870 refractory metal Substances 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 5
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 abstract description 4
- 239000011248 coating agent Substances 0.000 abstract description 4
- 238000000576 coating method Methods 0.000 abstract description 4
- 238000000151 deposition Methods 0.000 abstract description 4
- 239000011521 glass Substances 0.000 abstract description 4
- 229910052750 molybdenum Inorganic materials 0.000 abstract description 4
- 239000011733 molybdenum Substances 0.000 abstract description 4
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 4
- 239000000377 silicon dioxide Substances 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 239000012535 impurity Substances 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 239000010409 thin film Substances 0.000 abstract description 2
- MYZAXBZLEILEBR-RVFOSREFSA-N (2S)-1-[(2S,3R)-2-[[(2R)-2-[[2-[[(2S)-2-[(2-aminoacetyl)amino]-5-(diaminomethylideneamino)pentanoyl]amino]acetyl]amino]-3-sulfopropanoyl]amino]-3-hydroxybutanoyl]pyrrolidine-2-carboxylic acid Chemical compound C[C@@H](O)[C@H](NC(=O)[C@H](CS(O)(=O)=O)NC(=O)CNC(=O)[C@H](CCCN=C(N)N)NC(=O)CN)C(=O)N1CCC[C@H]1C(O)=O MYZAXBZLEILEBR-RVFOSREFSA-N 0.000 abstract 1
- SNSBQRXQYMXFJZ-MOKYGWKMSA-N (2s)-6-amino-n-[(2s,3s)-1-amino-3-methyl-1-oxopentan-2-yl]-2-[[(2s)-2-[[(2s)-2-[[(2s)-2-[[(2s)-2-[[(2s)-2-[[(2s)-2-[[(2s)-2-amino-3-phenylpropanoyl]amino]-3-hydroxypropanoyl]amino]propanoyl]amino]-3-hydroxypropanoyl]amino]propanoyl]amino]-4-methylpentanoy Chemical compound CC[C@H](C)[C@@H](C(N)=O)NC(=O)[C@H](CCCCN)NC(=O)[C@H](C)NC(=O)[C@H](CC(C)C)NC(=O)[C@H](C)NC(=O)[C@H](CO)NC(=O)[C@H](C)NC(=O)[C@H](CO)NC(=O)[C@@H](N)CC1=CC=CC=C1 SNSBQRXQYMXFJZ-MOKYGWKMSA-N 0.000 abstract 1
- 108700002400 risuteganib Proteins 0.000 abstract 1
- IAKOZHOLGAGEJT-UHFFFAOYSA-N 1,1,1-trichloro-2,2-bis(p-methoxyphenyl)-Ethane Chemical compound C1=CC(OC)=CC=C1C(C(Cl)(Cl)Cl)C1=CC=C(OC)C=C1 IAKOZHOLGAGEJT-UHFFFAOYSA-N 0.000 description 1
- WUPRYUDHUFLKFL-UHFFFAOYSA-N 4-[3-(4-aminophenoxy)phenoxy]aniline Chemical compound C1=CC(N)=CC=C1OC1=CC=CC(OC=2C=CC(N)=CC=2)=C1 WUPRYUDHUFLKFL-UHFFFAOYSA-N 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 125000002924 primary amino group Chemical group [H]N([H])* 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/043—Dual dielectric
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/053—Field effect transistors fets
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/106—Masks, special
Definitions
- oEPosu' u: LCDNYAC 9 in cart, 50 EJND mum A low cost optimum process for fabricating monolithic integrated circuit insulated gate field effect transistors which utilize a refractory metal diffusion mask.
- a thin layer of gate insulator preferably a laminate of grown silicon dioxide and silicon nitride, and a thick pyrolytically deposited field oxide.
- This includes forming drain and source openings through the refractory metal film and gate insulator layers, depositing an activator impurity-doped glass coating over the entire processed substrate, and dilfusing the activator impurity into the substrate using the patterned molybdenum film as a diifusion mask. Contact holes are then made through the glass coating, and contact metallizations are applied.
Abstract
A LOW COST OPTIMUM PROCESS FOR FABRICATING MONOLITHIC INTEGRATED CIRCUIT INSULATED GATE FIELD EFFECT TRANSISTORS WHICH UTILIZE A REFRACTORY METAL DIFFUSION MASK. AS THE FIRST STEP, THERE IS DEPOSITED ON THE SEMICONDUCTOR SUBSTRATE A THIN LAYER OF GATE INSULATOR, PREFERABLY A LUMINATE OF GROWN SILICON DIOXIDE AND SILICON NITRIDE, AND A THICK PYROLYTICALLY DEPOSITED FIELD OXIDE. AFTER FORMING A SINGLE OPENING DOWN TO THE SILICON NITRIDE FOR SOURCE, GATE, AND DRAIN REGIONS, AND DEPOSITING A THIN FILM OF MOLYBDENUM, SUBSEQUENT PROCESSING IS COMPLETED WITHOUT REMOVING THE INITIALLY DEPOSITED GATE INSULATOR. THIS INCLUDES FORMING DRAIN AND SOURCE OPENING THROUGH THE REFRACTORY METAL FILM AND GATE INSULATOR LAYERS, DEPOSITING AN ACTIVATOR IMPURITY-DOPED GLASS COATING OVER THE ENTIRE PROCESSED SUBSTRATE, AND DIFFUSING THE ACTIVATOR IMPURITY INTO THE SUBSTRATE USING THE PATTERNED MOLYBDENUM FILM AS A DIFFUSION MASK. CONTACT HOLES ARE THEN MADE THROUGH THE GLASS COATING, AND CONTACT METALLIZATIONS ARE APPLIED.
Description
DEFENSIVE PUBLICATION UNITED STATES PATENT OFFICE Published at the request of the applicant or owner in accordance with the Notice of Dec. 16, 1969, 869 0.G. 687. The abstracts of Defensive Publication applications are identified by distinctly numbered series and are arranged chronologically. The heading of each abstract indicates the number of pages of specification, including claims and sheets of drawings contained in the application as originally filed. The files of these applications are available to the public for inspection and reproduction may be purchased for 30 cents a sheet.
Defensive Publication applications have not been examined as to the merits of alleged invention. The Patent Oilice makes no assertion as to the novelty of the disclosed subject matter.
PUBLISHED JUNE 22, 1971 news on N-I'VPE sl WAFER LAVERS or n snow SILICUN moxie: s: on mime: mo
mlqu Flew siuoou amino:
new SINGLE OPEMNG F0 souncz, GATEJND DRAIN no re SILICUN NJIRIBE LAYER no n REFRACTORY a MUM. We) HUI PM? H UTE, ITC" ovzm ion source Aun DRAIN omen TB ll VAFKR one!" Acnv Ion-com GU55 FILM DIFF E AUIVATUR iwimm/ 1n ram MYPE sonnet mm mm nzcmoozs :rcu carrier HOLE! oEPosu' u: LCDNYAC 9 in cart, 50 EJND mum A low cost optimum process for fabricating monolithic integrated circuit insulated gate field effect transistors which utilize a refractory metal diffusion mask. As the first step, there is deposited on the semiconductor substrate a thin layer of gate insulator, preferably a laminate of grown silicon dioxide and silicon nitride, and a thick pyrolytically deposited field oxide. After forming a single opening down to the silicon nitride for source, gate, and drain regions, and depositing a thin film of molybdenum, subsequent processing is completed without removing the initially deposited gate insulator. This includes forming drain and source openings through the refractory metal film and gate insulator layers, depositing an activator impurity-doped glass coating over the entire processed substrate, and dilfusing the activator impurity into the substrate using the patterned molybdenum film as a diifusion mask. Contact holes are then made through the glass coating, and contact metallizations are applied.
June 22, IN
G. S. RODARI FABRICATION OF INTEGRATED CIRCUIT GATE FIELD EFFECT TRANSISTORS Filed March 17, 1970 DEPOSIT ON N-TYPE Si WAFER LAYERS OF THIN GROWN SILICON DIOXIDE, SILICON NITRIDE AND THICK FIELD SILICON DIOXIDE ETCH SINGLE OPENING FOR SOURCE, GATE, AND DRAIN DOWN TO SILICON NITRIDE LAYER DEPOSIT REFRACTORY METAL (M0) FILM PATTERN GATE, ETCH OPENINGS FOR SOURCE AND DRAIN DOWN TO Si WAFER DEPOSIT ACTlVATOR-DOPED GLASS FILM, DIFFUSE ACTIVATOR IMPURITY TO FORM P-TYPE SOURCE AND DRAIN ELECTRODES ETCH CONTACT HOLES; DEPOSIT METAL CONTACTS TO GATE, SOURCE, AND DRAIN 2 Sheets-Sheet 1 (fig 2a) (fig 219) (fig 20) (fig .20)
(fig 2a) //I/ I/E/I/ TOR.- v G/A/VP/ERO s. RODA/W,
June 22, 1971 RODAR] FABRICATION OF INTEGRATED CIRCUIT GATE FIELD EFFECT TRANSISTORS Filed March 17, 1970 2 Sheets-Sheet a lA/ VE/V TOR: 6/4 IVP/ERO s. Rom/w,
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US2030170A | 1970-03-17 | 1970-03-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| UST887018I4 true UST887018I4 (en) | 1971-06-22 |
Family
ID=21797847
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US887018D Pending UST887018I4 (en) | 1970-03-17 | 1970-03-17 | Fabrication of integrated circuit gate field effect transistors |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | UST887018I4 (en) |
| DE (1) | DE2112779A1 (en) |
| FR (1) | FR2083357A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5756397A (en) * | 1993-12-28 | 1998-05-26 | Lg Semicon Co., Ltd. | Method of fabricating a wiring in a semiconductor device |
-
1970
- 1970-03-17 US US887018D patent/UST887018I4/en active Pending
-
1971
- 1971-03-17 FR FR7109393A patent/FR2083357A1/en not_active Withdrawn
- 1971-03-17 DE DE19712112779 patent/DE2112779A1/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5756397A (en) * | 1993-12-28 | 1998-05-26 | Lg Semicon Co., Ltd. | Method of fabricating a wiring in a semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2083357A1 (en) | 1971-12-17 |
| DE2112779A1 (en) | 1971-10-07 |
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