UST944001I4 - - Google Patents
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- Publication number
- UST944001I4 UST944001I4 US50847174A UST944001I4 US T944001 I4 UST944001 I4 US T944001I4 US 50847174 A US50847174 A US 50847174A US T944001 I4 UST944001 I4 US T944001I4
- Authority
- US
- United States
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US50847174 UST944001I4 (en) | 1974-06-13 | 1974-09-23 |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US47906974A | 1974-06-13 | 1974-06-13 | |
| US50847174 UST944001I4 (en) | 1974-06-13 | 1974-09-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| UST944001I4 true UST944001I4 (en) | 1976-03-02 |
Family
ID=27046117
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US50847174 Pending UST944001I4 (en) | 1974-06-13 | 1974-09-23 |
Country Status (1)
| Country | Link |
|---|---|
| US (1) | UST944001I4 (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4263651A (en) | 1979-05-21 | 1981-04-21 | International Business Machines Corporation | Method for determining the characteristics of a logic block graph diagram to provide an indication of path delays between the blocks |
| US4593363A (en) | 1983-08-12 | 1986-06-03 | International Business Machines Corporation | Simultaneous placement and wiring for VLSI chips |
| US5113352A (en) * | 1989-06-20 | 1992-05-12 | Digital Equipment Corporation | Integrating the logical and physical design of electronically linked objects |
| US5187671A (en) * | 1990-08-24 | 1993-02-16 | Microelectronics And Computer Technology Corporation | Automated interconnect routing system |
| US5202840A (en) * | 1990-12-19 | 1993-04-13 | Vlsi Technology, Inc. | Method for partitioning of connected circuit components before placement in one or more integrated circuits |
| US5229953A (en) * | 1989-10-13 | 1993-07-20 | Hitachi, Ltd. | Method of and apparatus for assigning logic gates to a plurality of hardware components |
| US5251147A (en) * | 1989-06-20 | 1993-10-05 | Digital Equipment Corporation | Minimizing the interconnection cost of electronically linked objects |
| US5282148A (en) * | 1989-05-23 | 1994-01-25 | Vlsi Technology, Inc. | Method and apparatus for the design and fabrication of integrated circuits employing logic decomposition algorithms for the timing optimization of multilevel logic |
| US5406497A (en) * | 1990-09-05 | 1995-04-11 | Vlsi Technology, Inc. | Methods of operating cell libraries and of realizing large scale integrated circuits using a programmed compiler including a cell library |
| US5416717A (en) * | 1989-09-06 | 1995-05-16 | Hitachi, Ltd. | Circuit simulation method for a circuit realized by an LSI layout pattern based upon a circuit of a logic gate level realized by the layout pattern |
| US5461577A (en) * | 1987-08-04 | 1995-10-24 | Texas Instruments Incorporated | Comprehensive logic circuit layout system |
| US6345378B1 (en) * | 1995-03-23 | 2002-02-05 | Lsi Logic Corporation | Synthesis shell generation and use in ASIC design |
-
1974
- 1974-09-23 US US50847174 patent/UST944001I4/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4263651A (en) | 1979-05-21 | 1981-04-21 | International Business Machines Corporation | Method for determining the characteristics of a logic block graph diagram to provide an indication of path delays between the blocks |
| US4593363A (en) | 1983-08-12 | 1986-06-03 | International Business Machines Corporation | Simultaneous placement and wiring for VLSI chips |
| US5461577A (en) * | 1987-08-04 | 1995-10-24 | Texas Instruments Incorporated | Comprehensive logic circuit layout system |
| US5282148A (en) * | 1989-05-23 | 1994-01-25 | Vlsi Technology, Inc. | Method and apparatus for the design and fabrication of integrated circuits employing logic decomposition algorithms for the timing optimization of multilevel logic |
| US5113352A (en) * | 1989-06-20 | 1992-05-12 | Digital Equipment Corporation | Integrating the logical and physical design of electronically linked objects |
| US5251147A (en) * | 1989-06-20 | 1993-10-05 | Digital Equipment Corporation | Minimizing the interconnection cost of electronically linked objects |
| US5416717A (en) * | 1989-09-06 | 1995-05-16 | Hitachi, Ltd. | Circuit simulation method for a circuit realized by an LSI layout pattern based upon a circuit of a logic gate level realized by the layout pattern |
| US5229953A (en) * | 1989-10-13 | 1993-07-20 | Hitachi, Ltd. | Method of and apparatus for assigning logic gates to a plurality of hardware components |
| US5187671A (en) * | 1990-08-24 | 1993-02-16 | Microelectronics And Computer Technology Corporation | Automated interconnect routing system |
| US5406497A (en) * | 1990-09-05 | 1995-04-11 | Vlsi Technology, Inc. | Methods of operating cell libraries and of realizing large scale integrated circuits using a programmed compiler including a cell library |
| US5202840A (en) * | 1990-12-19 | 1993-04-13 | Vlsi Technology, Inc. | Method for partitioning of connected circuit components before placement in one or more integrated circuits |
| US6345378B1 (en) * | 1995-03-23 | 2002-02-05 | Lsi Logic Corporation | Synthesis shell generation and use in ASIC design |