WO1981000167A1

WO1981000167A1 - Magnetic bubble package with chips mounted face-to-face

Info

Publication number: WO1981000167A1
Application number: PCT/US1980/000746
Authority: WO
Inventors: W Layton
Original assignee: Burroughs Corp
Priority date: 1979-06-29
Filing date: 1980-06-19
Publication date: 1981-01-22
Also published as: EP0031373A1

Abstract

A magnetic bubble memory package comprising bubble memory chips (26A, 26B) arranged in pairs, with the propagate and functional elements for bubble manipulation, one of each pair being the mirror image of the other, and mounted on a printed circuit board assembly (30A, 30B) face-to-face and surrounded by spaced orthogonally oriented drive coils (22, 24) and bias magnets (14, 16) for the support and propagation of the bubbles. Each chip of each pair may be connected in series and in parallel by the printed circuit board assembly so that individual chips or a series of chips can be selectively accessed. Two embodiments of interconnections between such circuit boards are disclosed to meet the series and parallel connection requirements for the package selected.

Description

MAGNETIC BUBBLE PACKAGE WITH CHIPS MOUNTED PACE-TO-FACE

BACKGROUND OF THE INVENTION

This invention relates to magnetic bubble (domain) assemblies and more particularly to a new and improved bubble memory package arrangement with increased chip density.

A magnetic bubble memory package comprises one or more chips or modules containing a thin layer of garnet-like material formed on a substrate and disposed between bias magnets to provide a bias field, normal to the plane of the substrate, to establish and maintain bubbles in the garnet-like material. For bubble propagation in the plane of garnet-like material, sinusoidal type, for example, field drive coils provide rotational in-plane magnetic fields and surround the substrate. Means are provided to interconnect chips to one another, if there is more than one chip in the package, to control circuitry for performing various bubble manipulations in the chips, and to connect the chips to the outside world.

In the prior art, a plurality of chips, -2-

mounted on a printed circuit board, had suitable conductors for connecting the chips to each other and to pins or other connectors for interconnection to the control circuitry. If more than one chip was mounted on the printed circuit board, all chips were arranged such that the propagate and functional elements faced in the same direction with a space being provided on the side of the chip opposite the printed circuit boards so that the thin layer of magnetically active garnet-like material containing the propagate and functional elements are centered within the drive coils. This prior art arrangement left space, between the top of the chip, (i.e., the side of the chip opposite the printed circuit board), unused and represented waste space in the prior art packages. Attempts were made to fill the space with additional packages mounted in parallel in the wasted space but this was found to interfere with the operation of the packages since they were driven by the same field coils and maintained by the same bias magnets.

It has been found, however, as shown in U.S. Patent No. 4,027,295 to Maegawa et al, that this space can be utilized with the same drive coils and bias magnets by making the propagate and functional elements of one of a pair of bubble memory chips the mirror image of the other chip of the pair and mounting the pair face-to-face on a pair of printed circuit boards in the package. With this arrangement the package chip density, and thus the bubble density, of the bubble memory package can be increased twice the normal over prior art chip packages.

Another matter that arose in the prior art, was the difficulty of interconnecting the "normal" -3-

chips mounted on the printed circuit board with the mirror image chips on the oppositely facing printed circuit board, but it has been found that by selectively arranging conductors on the printed circuit boards on v/hich the chips are mounted and selectively connecting these conductors by package leads, the chips can be connected in series or in parallel so that individual chips and/or series of chips can be selectively accessed. And as will be clear from the detailed description hereafter, depending on selected package size needs, in two embodiments disclosed, the printed circuit boards are interconnected differently.

Accordingly, the primary object of this invention is to provide a technique for interconnecting chips on oppositely facing substrates.

Another object of this invention is to provide a new and improved bubble memory package having increased chip density and increased bubble density over prior art packages. Still another object of this invention is to provide a unique arrangement of substrates on which magnetic bubble memory chips are mounted with selectively arranged conductors and package leads so that individual magnetic memory chips or a series of such chips can be selectively accessed.

Still another object is to provide a package in which the memory capacity can be doubled by adding mirror image chips in pairs with already existing "normal" chips without increasing drive coil volume (and thus inductance).

SUMMARY OF THE INVENTION

The package which accomplishes the foregoing objects comprises an assembly of bubble memory chips arranged in pairs one of each of the pairs having its propagation and functional elements for the -4-

manipulation of bubbles in the form of a mirror image of the other of the pair and mounted face-to-face between orthagonally oriented drive coils and bias magnets so that the pairs of chips share the same field drive coils and bias magnets for domain manipulation and propagation. The printed circuit boards which mount the pairs of chips will have its own interconnect conductors for interchip connection and connection to the outside world. Interconnection between the printed circuit boards is made with the leads or pins that provide interconnection to the outside world. Two embodiments of such interconnections are disclosed. BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a perspective view of one embodiment of a bubble memory package constructed according to the teachings of this invention and partially broken away to illustrate the inner details thereof.

Figure 2 is an exploded view of the package of Figure 1,

Figure 3 is a partial view of the printed circuit board and chips, enlarged over Figures 1 and 2, to show the details of the boards and the interconnect conductors of the first embodiment, Figures 4 and 5 are cross-sectional views taken along lines 4-4 and 5-5, respectively, of Figure 1 and looking in the direction of the arrows.

Figure 6 is a perspective exploded view of the second embodiment of the invention having shorter printed circuit boards, and

Figure 7 is a cross-sectional view illustrating the connection of the printed circuit boards of Figure 6. BRIEF DESCRIPTION OF THE PREFERRED EMBODIMENTS The drawings disclose a bubble memory package

'B -5-

10 having a yoke 12 which encloses bias magnets 14 and 16 and an innerassembly 18. Bias magnets 14 and 16 are connected to the yoke by an adhesive 20. The yoke 12 forms the housing for the package and also forms a

5 closed magnetic path and the bias magnetics 14 and 16 are disposed on both sides of the innerassembly 18. This innerassembly includes orthagonally oriented drive coils 22 and 24 encompassing a plurality of magnetic bubble chips 26A and 26B disposed in cavities 28A and

10 26B (Figures 3, 4 and 5) formed in a pair of printed circuit boards 30A and 30B and spacers 32A and 32B. The chips 26A are generally considered the "normal" or "normally mounted" chips in the art.

The printed circuit boards 30A and 30B are

15 essentially E-shaped which is defined by two slots 34 and 36 separating a midportion 38 on which the chips are mounted and the spacers 32A, 32B are of the same shape to overlay the printed circuit boards and space the boards from each other to accommodate the thickness

20 of the bubble memory chips and to define the aforesaid cavities 28A and 28B.

The bubble memory chips 26A and 26B, under the influence of the magnetic field provided by the bias magnets, form and maintain bubbles in the magnetic

^l⁾ materials, usually a garnet, within the chips. The innerassembly 18 is canted with respect to the bias magnets 14 and 16 to provide a magnetic gradient (see Figures 4 and 5) and, on the garnet materials, are propagate elements and functional elements for

30 generating, storing, accessing and detecting bubbles. As shown in Figure 2, bubble chips 26A mounted on the lower printed circuit board 30A have storage loop architecture which is the mirror image of the architecture of the chips on the top printed circuit

35 board 28B. Thus, when sandwiched between the two -6-

printed circuit boards and in the cavities, the bubbles formed in the chips, are maintained and manipulated by the single bias field provided by the bias magnets 14, 16 and the rotating in-plane drive field formed by the application of pulses to the drive coils 22 and 24. The drawings also show that the printed circuit boards 30A and 30B are made in three layers 40, 42 and 44 by a conventional process (although additional layers could be used), with suitable plated throughholes 46 and conductors 48 which terminate at one end in throughholes 50. The latter are adjacent the cavities 28A, 28B so that wires 52 from the pads of the bubble memory chips can be connected to the selected printed circuit board conductors. On the outer edge of the printed circuit boards are conductive pads 54, only a few of which are shown, which contain the plated throughholes 46 to receive one leg of L-shaped package lead pins 56 (Figures 2, 5 and 7). These lead pins 56 connect the chips to the outside world for suitable controls and for the insertion and retrieval of data from the chips. These package lead pins extend through the holes 46 and are connected, as by soldering, as shown at 60, to selected pads so that the lower circuit board 30A may be electrically connected to the upper circuit board

30B and thus the lead pins permit accessing of both the chips 26A on the lower printed circuit board as well as the chips 26B on the upper printed circuit board. Selected ones of the package leads can also be used for connecting the upper chips 26B to the lower chips 26A for interchip communication.

In the embodiment thus described, with the package pins 56, whose leg is long enough to span the two printed circuit boards, it is clear that for the case where separate communication to each chip is

-_BUR

Oft- -7-

required separate, additional pads 54 are required since the package lead pins 56 are, by necessity, connected to both the upper circuit board 30B and the lower circuit board 30A. This may impose a limitation on the minimum size of package because more throughholes are necessary. In other words, the size of the package in this embodiment may be determined by the number and distance between the pads 46.

On the other hand, while the embodiment shown in Figures 6 and 7 require two package lead pins 56A' and 56B', one for each of the printed circuit boards, the chips of either circuit board 30A' and 30B' can be accessed separately. Thus, in this embodiment the size of the package may be determined by the number of chips rather than by the number of plated throughholes.

Note, in this embodiment, too, the lead pins 56 of the first embodiment can be connected to both printed circuit boards if it is desired to access both the normal chip and its mirror image in the embodiment together with the separate lead pins 56A' and 56B¹.

Note, that lead pin 56' can be added to connect a chip on substrate 30A' with its mirror chip on the substrate 30B' without an additional pad being added and not already required of the configuration. Thus, as mentioned above, an important feature of this invention is that by selecting the dimensions and configuration of-the package leads the bubble memory chips can be accessed, individually, or in series, or in parallel, as the case may be. The conductor lines in the printed circuit boards in combination with the package leads permit this function.

It is to be understood that while the bias magnets and yoke are not shown in Figures 6 and 7, they were omitted for clarity of disclosure and where

0KP1 components, etc., have the same function in Figures 6 and 7 as Figures 1-5, they are given the same reference identification plus an apostrophe to represent a prime number. In summary, also from the foregoing, it can be seen that a bubble memory package has been disclosed in which there is interconnection by package lead pins between chips mounted face-to-face on a suitable substrate and chip density and thus bubble density has been increased by mounting the chips face-to-face utilizing common drive coils and bias magnets. Also, by selection of the printed circuit board and package lead pins, the size of the package can be selected to meet the needs of the user.

Claims

WHAT IS CLAIMED IS:

1. A magnetic bubble package having an assembly of magentic bubble components including a plurality of drive coils for providing a magnetic field rotating in the plane of a plurality of magnetic bubble chip means and yoke means with bias magnets located with respect to said drive coils and said chip means for providing a magnetic field normal to the plane of said chip means, the improvement comprising: said bubble memory chip means being arranged in pairs one of which is the mirror image of the other, a pair of substrate means, said bubble memory chip means being mounted on one of said pair of said substrate means in such a manner that the mirror image memory chip means faces its counterpart on the other of said pair of said substrate means, characterized by said substrate means containing electrical conductor means for interchip communication and for communication to external devices, apertures located along the edges of said substrate means connected to said electrical conductor means, connector pin means extending through said apertures in said substrate means for connecting said chips to external devices and for connecting chips to each other.

2. The magnetic bubble memory package as claimed in Claim 1, wherein said substrate means comprises printed circuit boards.

3. The magnetic bubble package as claimed in ' Claim 2, wherein said printed circuit boards are multilayer and are arranged so as to mount said chip means in the plane of said printed circuit board and centrally located between the said bias magnets and drive coils.

4. A bubble memory package as claimed in Claim 3, wherein said connector pin means engage said printed circuit board means containing said mirror image chip means only while other connector means connect said other chip means only and connect to outside of package.

5. The magnetic bubble memory package as claimed in Claim 4, wherein said pin means extends through said printed circuit boards to connect both said printed circuit boards for connecting said mirror image chip means and said other chips in series or in parallel.

6. A magnetic bubble package having an assembly of magnetic bubble memory components including a plurality of drive coils for providing a magnetic field, yoke means with bias magnetic means located with respect to said drive coils to provide a magnetic field normal to the plane of said yoke means, magnetic bubble memory chip means, some of which are the mirror image of others, printed circuit board means arranged in pairs, one of said pairs containing said mirror image chip means and the other of said pair containing the other chip means, said printed circuit board means arranging said chips facing each other and located in the plane of said rotating in-plane magnetic field, and connector means some of which are electrically connected to only one of said pair of printed circuit board means while other connector means electrically connect said pairs of printed circuit board means to each other.