WO1981001066A1 - Systeme de traitement de donnees - Google Patents

Systeme de traitement de donnees Download PDF

Info

Publication number
WO1981001066A1
WO1981001066A1 PCT/US1980/001314 US8001314W WO8101066A1 WO 1981001066 A1 WO1981001066 A1 WO 1981001066A1 US 8001314 W US8001314 W US 8001314W WO 8101066 A1 WO8101066 A1 WO 8101066A1
Authority
WO
WIPO (PCT)
Prior art keywords
bus
processor
main store
processors
data
Prior art date
Application number
PCT/US1980/001314
Other languages
English (en)
Inventor
G Frieder
D Hughes
M Kline
J Liebel
D Meier
E Wolff
Original Assignee
Nanodata Computer Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US06/083,648 external-priority patent/US4354225A/en
Application filed by Nanodata Computer Corp filed Critical Nanodata Computer Corp
Priority to AU64888/80A priority Critical patent/AU6488880A/en
Publication of WO1981001066A1 publication Critical patent/WO1981001066A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G06F11/2736—Tester hardware, i.e. output processing circuits using a dedicated service processor for test
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/161—Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Computing Systems (AREA)
  • Quality & Reliability (AREA)
  • Multi Processors (AREA)

Abstract

Un systeme de traitement de donnees comprend un magasin principal actif et d'intelligence (12) consistant en une memoire principale (34), une unite principale de controle de magasin (36) pour l'acces a la memoire principale de maniere a permettre differentes structures d'adresses et de donnees, et un bus de magasin principal (14) connecte a l'unite de controle (36). Au moins un processeur d'un premier type est connecte au bus de magasin principal, celui-ci etant un processeur auxiliaire (16) pour effectuer des operations d'entree/sortie et autres. Au moins un processeur du second type est egalement connecte au bus de magasin principal, celui-ci etant un processeur d'execution (18) pour extraire decoder et executer des instructions. Tous ou certains des processeurs d'execution (18) et l'un ou l'autre ou les deux processeurs auxiliaires (16) peuvent etre differents. Un processeur de supervision (20) pour initier la configuration et la surveillance du systeme est connecte au bus de magasin principal. Un bus de communication (22) est connecte aux processeurs du premier et du second types et au processeur de supervision (20). Un bus de diagnostic (24) connecte le processeur de supervision (20) a chacun des processeurs du premier et du second types. Un ensemble de bus d'entree/sortie (28) est connecte au processeur de supervision (20) et a chaque processeur auxiliaire (16). Au moins un dispositif (112) et un controleur de dispositif associe (106) peuvent etre connectes a l'ensemble de bus d'entree-sortie (28). Au moins une unite de controle d'acces direct a la memoire (30) peut etre connectee entre le bus de magasin principal (14) et l'ensemble de bus entree-sortie (28).
PCT/US1980/001314 1979-10-11 1980-10-06 Systeme de traitement de donnees WO1981001066A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU64888/80A AU6488880A (en) 1979-10-11 1980-10-06 Data processing system

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US8367779A 1979-10-11 1979-10-11
US06/083,648 US4354225A (en) 1979-10-11 1979-10-11 Intelligent main store for data processing systems
US83677 1979-10-11

Publications (1)

Publication Number Publication Date
WO1981001066A1 true WO1981001066A1 (fr) 1981-04-16

Family

ID=26769550

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1980/001314 WO1981001066A1 (fr) 1979-10-11 1980-10-06 Systeme de traitement de donnees

Country Status (2)

Country Link
EP (1) EP0037424A1 (fr)
WO (1) WO1981001066A1 (fr)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0075713A2 (fr) * 1981-09-30 1983-04-06 Siemens Aktiengesellschaft Unité fonctionnelle additionnelle dans un microprocesseur, système à microprocesseur et méthode pour son fonctionnement
GB2156550A (en) * 1984-03-28 1985-10-09 Daisy Systems Corp Digital computer for implementing event driven simulation algorithm
EP0184657A2 (fr) * 1984-10-31 1986-06-18 Flexible Computer Corporation Système de traitement numérique à multi-ordinateur
EP0204827A1 (fr) * 1984-12-10 1986-12-17 Advanced Computer Communications Controleur de communication utilisant une memoire a acces aleatoire a connexions multiples
EP0141445B1 (fr) * 1983-09-14 1989-03-15 Koninklijke Philips Electronics N.V. Dispositif fonctionnel isolé comprenant un micro-ordinateur
US4814983A (en) * 1984-03-28 1989-03-21 Daisy Systems Corporation Digital computer for implementing event driven simulation algorithm
WO1989003574A1 (fr) * 1987-10-06 1989-04-20 Fraunhofer Gesellschaft Zur Förderung Der Angewand Procede de codage numerique adaptatif par transformees
US4872125A (en) * 1987-06-26 1989-10-03 Daisy Systems Corporation Multiple processor accelerator for logic simulation
US4873656A (en) * 1987-06-26 1989-10-10 Daisy Systems Corporation Multiple processor accelerator for logic simulation
US4916647A (en) * 1987-06-26 1990-04-10 Daisy Systems Corporation Hardwired pipeline processor for logic simulation
EP0426156A2 (fr) * 1989-11-03 1991-05-08 Compaq Computer Corporation Commande de disque souple avec vérification des opérations DMA

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3893084A (en) * 1973-05-01 1975-07-01 Digital Equipment Corp Memory access control system
US3905023A (en) * 1973-08-15 1975-09-09 Burroughs Corp Large scale multi-level information processing system employing improved failsaft techniques
US4015243A (en) * 1975-06-02 1977-03-29 Kurpanek Horst G Multi-processing computer system
US4032899A (en) * 1975-05-05 1977-06-28 International Business Machines Corporation Apparatus and method for switching of data
US4034347A (en) * 1975-08-08 1977-07-05 Bell Telephone Laboratories, Incorporated Method and apparatus for controlling a multiprocessor system
US4035777A (en) * 1973-12-14 1977-07-12 Derek Vidion Moreton Data processing system including parallel bus transfer control port
US4038645A (en) * 1976-04-30 1977-07-26 International Business Machines Corporation Non-translatable storage protection control system
US4065809A (en) * 1976-05-27 1977-12-27 Tokyo Shibaura Electric Co., Ltd. Multi-processing system for controlling microcomputers and memories
US4084230A (en) * 1976-11-29 1978-04-11 International Business Machines Corporation Hybrid semiconductor memory with on-chip associative page addressing, page replacement and control
US4107773A (en) * 1974-05-13 1978-08-15 Texas Instruments Incorporated Advanced array transform processor with fixed/floating point formats
US4130865A (en) * 1974-06-05 1978-12-19 Bolt Beranek And Newman Inc. Multiprocessor computer apparatus employing distributed communications paths and a passive task register
US4133030A (en) * 1977-01-19 1979-01-02 Honeywell Information Systems Inc. Control system providing for the transfer of data in a communications processing system employing channel dedicated control blocks
US4149239A (en) * 1976-02-13 1979-04-10 Digital Equipment Corporation Secondary storage facility for connecting to a digital data processing system by separate control information and data transfer paths
US4200930A (en) * 1977-05-23 1980-04-29 Burroughs Corporation Adapter cluster module for data communications subsystem
US4228496A (en) * 1976-09-07 1980-10-14 Tandem Computers Incorporated Multiprocessor system

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3893084A (en) * 1973-05-01 1975-07-01 Digital Equipment Corp Memory access control system
US3905023A (en) * 1973-08-15 1975-09-09 Burroughs Corp Large scale multi-level information processing system employing improved failsaft techniques
US4035777A (en) * 1973-12-14 1977-07-12 Derek Vidion Moreton Data processing system including parallel bus transfer control port
US4107773A (en) * 1974-05-13 1978-08-15 Texas Instruments Incorporated Advanced array transform processor with fixed/floating point formats
US4130865A (en) * 1974-06-05 1978-12-19 Bolt Beranek And Newman Inc. Multiprocessor computer apparatus employing distributed communications paths and a passive task register
US4032899A (en) * 1975-05-05 1977-06-28 International Business Machines Corporation Apparatus and method for switching of data
US4015243A (en) * 1975-06-02 1977-03-29 Kurpanek Horst G Multi-processing computer system
US4034347A (en) * 1975-08-08 1977-07-05 Bell Telephone Laboratories, Incorporated Method and apparatus for controlling a multiprocessor system
US4149239A (en) * 1976-02-13 1979-04-10 Digital Equipment Corporation Secondary storage facility for connecting to a digital data processing system by separate control information and data transfer paths
US4038645A (en) * 1976-04-30 1977-07-26 International Business Machines Corporation Non-translatable storage protection control system
US4065809A (en) * 1976-05-27 1977-12-27 Tokyo Shibaura Electric Co., Ltd. Multi-processing system for controlling microcomputers and memories
US4228496A (en) * 1976-09-07 1980-10-14 Tandem Computers Incorporated Multiprocessor system
US4084230A (en) * 1976-11-29 1978-04-11 International Business Machines Corporation Hybrid semiconductor memory with on-chip associative page addressing, page replacement and control
US4133030A (en) * 1977-01-19 1979-01-02 Honeywell Information Systems Inc. Control system providing for the transfer of data in a communications processing system employing channel dedicated control blocks
US4200930A (en) * 1977-05-23 1980-04-29 Burroughs Corporation Adapter cluster module for data communications subsystem

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0075713A3 (fr) * 1981-09-30 1986-02-19 Siemens Aktiengesellschaft Unité fonctionnelle additionnelle dans un microprocesseur, système à microprocesseur et méthode pour son fonctionnement
EP0075713A2 (fr) * 1981-09-30 1983-04-06 Siemens Aktiengesellschaft Unité fonctionnelle additionnelle dans un microprocesseur, système à microprocesseur et méthode pour son fonctionnement
EP0141445B1 (fr) * 1983-09-14 1989-03-15 Koninklijke Philips Electronics N.V. Dispositif fonctionnel isolé comprenant un micro-ordinateur
GB2156550A (en) * 1984-03-28 1985-10-09 Daisy Systems Corp Digital computer for implementing event driven simulation algorithm
US4751637A (en) * 1984-03-28 1988-06-14 Daisy Systems Corporation Digital computer for implementing event driven simulation algorithm
US4814983A (en) * 1984-03-28 1989-03-21 Daisy Systems Corporation Digital computer for implementing event driven simulation algorithm
EP0184657A2 (fr) * 1984-10-31 1986-06-18 Flexible Computer Corporation Système de traitement numérique à multi-ordinateur
EP0184657A3 (fr) * 1984-10-31 1987-02-04 Flexible Computer Corporation Système de traitement numérique à multi-ordinateur
EP0204827A1 (fr) * 1984-12-10 1986-12-17 Advanced Computer Communications Controleur de communication utilisant une memoire a acces aleatoire a connexions multiples
EP0204827A4 (fr) * 1984-12-10 1989-02-13 Advanced Comp Comm Controleur de communication utilisant une memoire a acces aleatoire a connexions multiples.
US4872125A (en) * 1987-06-26 1989-10-03 Daisy Systems Corporation Multiple processor accelerator for logic simulation
US4873656A (en) * 1987-06-26 1989-10-10 Daisy Systems Corporation Multiple processor accelerator for logic simulation
US4916647A (en) * 1987-06-26 1990-04-10 Daisy Systems Corporation Hardwired pipeline processor for logic simulation
WO1989003574A1 (fr) * 1987-10-06 1989-04-20 Fraunhofer Gesellschaft Zur Förderung Der Angewand Procede de codage numerique adaptatif par transformees
EP0426156A2 (fr) * 1989-11-03 1991-05-08 Compaq Computer Corporation Commande de disque souple avec vérification des opérations DMA
EP0426156A3 (en) * 1989-11-03 1995-03-15 Compaq Computer Corp Floppy disk controller with dma verify operations
US5442753A (en) * 1989-11-03 1995-08-15 Compaq Computer Corp. Circuitry for providing replica data transfer signal during DMA verify operations

Also Published As

Publication number Publication date
EP0037424A1 (fr) 1981-10-14

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