WO1981002362A1

WO1981002362A1 - Multiplexed operation of write enable terminal of a memory circuit for control and backup power functions

Info

Publication number: WO1981002362A1
Application number: PCT/US1981/000149
Authority: WO
Inventors: W Parkinson
Original assignee: Mostek Corp
Priority date: 1980-02-08
Filing date: 1981-02-04
Publication date: 1981-08-20
Also published as: CA1162647A; FR2475777B1; FR2475777A1

Abstract

A computer system (10) includes a memory (28) which receives primary power from a power supply (24). A control circuit (14) generates a write enable signal which is provided to a first input line (16) of a switch (58). A secondary power source (54) provides backup power through a line (56) to the switch (58). The power supply (24) generates a primary power warning signal on a line (62) which is connected to control the operation of switch (58). The ouptut line (60) of the switch (58) is connected to each of the write enable terminals of memory circuits (30-44) in the memori (28). Upon detection of failure of the primary power for the computer (10), the switch (58) is activated to disconnect the write enable signal on the input line (16) from the output line (60) of switch (58). The switch (58) is further caused to connect line (56) of the secondary power source (54) to the output line (60) of switch (58) to supply backup power to each of the memory circuits (30-44) in the memory (28).

Description

MULTIPLEXED OPERATION OF WRITE ENABLE TERMINAL OF A MEMORY CIRCUIT FOR CONTROL AND BACKUP POWER FUNCTIONS

TECHNICAL FIELD

This invention relates generally to integrated semiconductor memory circuits and more particularly pertains to the multiplexed use of the write enable terminal of a semiconductor memory circuit to provide backup power to the memory circuit.

BACKGROUND ART

Semiconductor memories have come into increasingly wide use in medium and large scale computer systems and have largely replaced magnetic core type memories. This change has occurred because semiconductor memories are

_* faster, have lower power consumption, and occupy less space. However, a serious problem with semiconductor memories is that each of the memory cells is volatile, that is, upon removal of power from the memory the information stored in the memory cell is lost. Although loss of power does not cause damage to the memory circuit the loss of the bit pattern stored in the memory can result in serious inconvenience to the user as well as the loss of valuable computer processing time when programs and data must be reloaded into the computer memory. In many smaller applications, there is no backup storage, such as a magnetic disk, provided for rapid loading of programs. In this case, the programming information must be manually entered into the system by a process which is quite slow.

It has been proposed to supply a backup power source for a semiconductor memory to supply sufficient power to the memory to maintain the bit pattern therein after a failure of the primary power source. In applying this concept directly, it is required that a dedicated termina on each integrated circuit memory be connected to the backup power source. This is impractical since the semiconductor memory circuits now in common use have each of the pin terminals dedicated for a specific function and the pin assignments have become standardized in the industry. The addition of such an additional pin would upset the standardized terminal assignments for memory circuits.

Oλ' In view of the above considerations, there exists a need for a method and apparatus for supplying backup power to a semiconductor integrated memory circuit in such a manner that no additional. pin terminals are required and the existing pin assignments are not changed.

DISCLOSURE OF THE INVENTION

The present invention is an apparatus for providing backup power to a semiconductor memory circuit for preserving the bit pattern stored therein upon -failure of the memory circuit primary power. The memory circuit has a write enable control terminal for receiving a write enable signal from a write enable output terminal of a control circuit wherein the memory circuit is set up in a read mode when the write enable signal is in a first state and the memory circuit is set up in a write mode - when the write enable signal is in a second state. The apparatus includes a backup power source and a circuit connected to monitor the memory circuit primary power for generating an active state of a primary power warning signal upon failure of the memory circuit primary power. The apparatus further includes circuitry connected to receive the primary power warning signal for connecting the write enable output terminal to the write enable 'control terminal for transferring the write enable signal to the memory circuit when the primary power warning signal is not in the active state. The switch circuit further provides for disconnecting the write enable output terminal from the write enable control terminal and connecting the backup power source to the write enable control terminal when the primary power warning signal is in the active state.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taking.in conjunction with the accompanying drawings in which the FIGURE is a schematic illustration of a computer system which includes the backup power apparatus of the present invention.

DETAILED DESCRIPTION

Referring to the FIGURE, a computer system 10 includes a central processing unit 12 which has a control circuit 14 that generates a plurality of memory..control signals. A WE (Write Enable) signal is generated at a WE output terminal 16 by the control circuit 14. A plurality of C^"5 (chip select) signals are generated on a plurality of C^~S terminals 18 by the control circuit 14. A primary line power source 20, such as a commercial power line, is connected through a conductor 22 to a computer power supply 24. DC power V is generated by power supply 24 and is transmitted through a line 26 to the central processing unit 12. The output of power supply 24 is also connected to a computer memory 28 which includes, among others, individual memory circuits 30-44. Each of the memory circuits 30-44 has a power terminal which is marked _cc« Each of the V_cc terminals is connected to a power bus 46 that is in turn connected to the output line 26 of power supply 24. But in certain applications the memory 28 can be powered from a separate source from that of the central processing unit 12.

In the memory 28 each of the memory circuits 30-44 further has a WE control terminal for receiving the write enable signal generated by the control circuit 14. Each of the WE terminals of the memory circuits is connected to a line 48 which serves as a memory control node for memory 28. Each of the memory circuits 30-44 further includes a CS terminal for receiving a chip select signal. The memory circuits 30-36 are connected to a chip select line 50 which is connected to one of the chip select output terminals 18. The memory circuits 38-44 have the CS terminals thereof connected to a chip select line 52 which is connected to another one of the chip select output terminals 18 from control circuit 14. Additional sections of the memory 28 have CS terminals for each of

OM the memory circuits in a section connected to a different one of the chip select terminals 18.

Referring further to the FIGURE, a secondary power source 54, such as a battery, is connected through a line 56 to a switch 58. The output of switch 58 is a line 60 which is connected to the memory control node 48. A control signal for switch 58 is transmitted from power supply 24 through a line 62 to switch 58.

The functional operation of switch 58 is illustrated by a two position switch 64 which has the switch arm thereof controlled by the signal received on line 62. In a first position, switch 64 connects input line 16 to output line 60, while in a second position switch 64 connects input line 56 to output line 60. Operation of the apparatus of the present invention is now described in reference to the FIGURE. As discussed above, a serious drawback to the use of semiconductor memories in a computer system is that such memories are volatile, that is, the bit pattern stored in the memory is lost when power for the memory is terminated. The present invention provides a method and apparatus for supplying backup power to each of the individual memory cells in the memory upon failure of the memory primary power.

The primary power supply 24 generates the primary power for the memories 30-44 and this power is transmitted through line 26 to power bus 46 in memory 28. The power is distributed from bus 46 to each of the individual memory circuits. But, upon loss of primary power, generally through failure of the primary line power source 20, memory power will be lost on line 46.

A backup power circuit for inclusion in the memory circuits 30-44 is described in copending application Serial No. ! / ^ , I^'Λ "> filed ^~^*J^~- £, / ^'1 ?° by

Andrew C. Graham and assigned to the assignee of the present invention. The circuit described in the copending application monitors the V and WE terminals and powers the memory arra therein from the V_cc terminal when the main power is within an acceptable range but transfers the internal memory array power node to the WE terminal when the main power voltage is outside of the normal range.

Computer power supply 24 includes circuitry for monitoring the AC power received on line 22. Upon detection of a failure of that power, a primary power warning signal is driven to an active state and this signal is transmitted over line 62 to switch 58. Compute power supplies which provide such a warning signal are in common use and an example of such a power supply is a model H7100 manufactured by Digital Equipment Corporation.

Under normal operating conditions, the primary power warning signal transmitted through line 62 is in the inactive state. In this state, switch 58 is set so that the input line 16 is connected to the output line 60 for transmitting the WE^~ signal from control circuit 14 to each of the memory circuits of the memory 28, including circuits 30-44. The power supply 24 has sufficiently large storage capacitors such that the power signal V is provided for a period of a few milliseconds following loss of input power on line 22. Upon loss of main power, the primary power warning signal is driven to the active state which causes switch 58 to disconnect line 16 from line 60 and connect line 56 to line 60. This action disconnects the WE signal from the memory circuit and connects the secondary power source 54 to the WE control terminal of each of the memory circuits. As noted above each of the memory circuits is provided with an internal circuit for receiving the power transmitted to the WE terminal.

Although switch 58 is shown functionally as a mechanical embodiment 64, it is preferrably implemented

OM as a logic circuit having no mechanical parts. Switch 58 can optionally be implemented as a solid state, switch.

The write enable signal transmitted on line 16 selects the read and write modes for the memory_^ 28. When the write enable signal is at a high state, the memory circuits are set up in a read mode to permit reading of information from the memory cells therein. When the write enable signal is at a low state the memory circuits are set up in a write mode to permit writing new data into the memory cells. When the memory circuits 30-44 are set up in the read mode, the memory cells therein are protected from having information written therein. During loss of main pov/er, spurious signals could be generated on the various control lines and these spurious signals may inadvertently attempt to write new data into the memory cells in memory 28. If this should occur, the desired information previously stored in the memory cells would be lost. Therefore, in the event of ah imminent power failure, it is the safe course to apply a high level signal to each of the WE terminals of the memory circuits to place these circuits in a read mode to protect the information stored therein.

In the present invention the WE terminal has been selected for multiplex operation to supply backup power because it is the most commonly connected pin within the memories 28. Other control pins such as, for example, the CS pin are connected in common only to a subgroup of memory circuits within memory 28. As shown in the FIGURE, the memory circuits 30-36 are connected to the chip select line 50 while the memory circuits 38-44 are connected to the separate chip select line 52. If it were attempted to route the backup pov/er to the CS terminal a separate switch, such as 58, would have to be supplied for each of the chip select lines. In summary, the present invention provides a method and apparatus for supplying backup power to a semiconductor memory wherein the write enable terminal of each- of the memory circuits within the memory is operated in a multiplex fashion. During routine operation, the write enable terminal receives the write enable signal from a control circuit, but upon detection of a failure of the primary power, a secondary pov/er source is connected to a line which is in turn connected to each of the write enable terminals of the memory circuits within the memory. A circuit internal to each of the memory circuits detects loss of primary power and connects the memory arrays therein to receive power from the write enable terminal.

Although only one embodiment of the present invention has been illustrated in the accompanying drawing and described in the foregoing detailed description, it will be understood that the' invention ' is not limited to the embodiment disclosed, but is capable of numerous rearrangements, modifications and substitutions without departing from the scope of the invention.

Claims

1. Apparatus for providing backup power to a semiconductor memory circuit for preserving the bit pattern stored therein upon failure of the memory circuit primary power, the memory circuit having a write enable control terminal for receiving a write enable signal from a write enable output terminal of a control* circuit wherein the memory circuit is set up in a read mode when the write enable signal is at a first state and the memory circuit is set up in a write mode when the write enable signal is at a second state comprising: a backup power source; means connected to monitor the memory circuit primary power for generating an active state of a primary power warning signal upon failure of the memory circuit primary power; and switch means connected to receive the primary power warning signal for connecting the write enable output terminal to the write enable control terminal to transfer the write enable signal to the memory circuit-when said primary pov/er warning signal is not in the active state and, said switch means further for disconnecting the write enable output terminal from the v/rite enable control terminal and connecting said backup power source to the v/rite enable control terminal when said primary power warning signal is in the active state.

2. The apparatus recited in Claim 1 wherein said backup power source is a battery.

3. The apparatus recited in Claim 1 wherein said backup pov/er source is a battery driven power supply.

4. The apparatus recited in Claim 1, where said switch means is a solid state switch having the control terminal thereof connected to receive said primary power warning signal, a first input^" terminal connected to the v/rite enable output terminal, a second inpu^'t terminal connected to said backup power source and the output terminal thereof connected to the write enable control terminal.

5. The apparatus recited in Claim 1 wherein said backup power source provides a voltage that corresponds to the first state of the write enable signal to limit the memory circuit to operation in the read mode following failure of the primary pov/er thereby protecting the bit pattern stored in the memory circuit.

6. Apparatus for providing backup power to a semiconductor memory circuit for preserving the bit pattern stored therein upon failure of the memory circuit primary power, the memory circuit having a write enable control terminal for receiving a write- enable signal from a control circuit wherein the memory circuit is set up in a read mode when the write enable signal is at a first state and the memory circuit is set up in a write mode when the write enable signal is at a second state comprising: a backup power source; means connected to monitor said memory circuit primary power for generating an active state of a primary power warning signal upon failure of the memory circuit primary power; and means for transmitting the write enable signal from the control circuit to the write enable control terminal of the memory circuit when the primary power warning signal is not in the active state and for providing power from said backup pov/er source to the memory circuit through the write enable control terminal when said primary pov/er warning signal is in the active state.

OHFI

7. Apparatus for providing backup power to a semiconductor memory for preserving the bit pattern stored therein upon failure of the memory primary power, the memory including a plurality of individual memory circuits each having a write enable control terminal that is connected to a memory control node which receives a write enable signal from a write enable output terminal of a control circuit wherein the memory is se-t up in a read mode when the write enable signal is in a first state and the memory is set up in a write mode when the write enable signal is in a second state, comprising: a backup power source; means connected to the memory primary power for generating an active state of a primary pov/er warning signal upon failure of the memory primary power; and switch means connected to receive said primary power warning signal for connecting the write enable output terminal to the memory control node when said primary power warning signal is not in said active state, said switch means further for disconnecting the write enable output terminal from the memory control node and connecting said backup power source to the memory control node when said primary power warning signal is in said active state.

8. The apparatus recited on Claim 7 wherein said backup power source provides a voltage that corresponds to the first state of the write enable signal to limit the memory to operation in the read mode following failure of the primary power thereby protecting the bit pattern stored in the memory.

9. A method for providing backup power to preserve the bit pattern stored in a semiconductor memory circuit upon failure of the memory circuit primary power, the memory circuit having a write enable control terminal for receiving -a write enable signal from a write enable output terminal of a control circuit wherein the memory circuit is set up in a read mode when the write enable signal is in a first state and the memory circuit is set up in a write mode when the write enable signal is in a second state, comprising the steps of: monitoring the memory circuit primary power to detect a failure of the primary power; driving a primary power warning signal from an inactive state to an active state v/hen a failure of the primary power is detected; transmitting the write enable signal from the control circuit to the write enable control terminal of the memory circuit when said primary pov/er v/arning signal is not in the active state; and providing power from a backup power source to the memory circuit through the write enable control terminal when said primary power warning signal is in the active state.

10. A method for providing backup power to preserve the bit pattern stored in a semiconductor memory circuit upon failure of the memory circuit primary power, the memory circuit having a write enable control terminal for receiving a write enable signal from a write enable ouput terminal of a control circuit wherein the memory circuit is set up in a read mode when the write enable signal is in a first state and the memory circuit is set up in a write mode when the write enable signal is in a second state, comprising the steps of: monitoring the memory circuit primary pov/er to detect a failure of the primary power; driving a primary power warning signal from an inactive state to an active state when a failure of the primary power is detected; connecting the write enable output terminal of the control circuit to the write enable control terminal of the memory circuit when said primary power warning signal is at said inactive state; disconnecting the v/rite enable output terminal of the control circuit from the write enable control terminal of the memory circuit when said primary power warning signal is in said active state; and connecting a backup power source to said write enable control terminal when said primary power warning signal is in said active state.

11. A method for providing backup power to a semiconductor memory for preserving the bit pattern stored therein upon failure of the memory primary power, the memory including a plurality of individual_^memory circuits each having a write enable control terminal that is connected to a memory ^'control node which receives a v/rite enable signal from a write enable output terminal of a control circuit wherein the memory is set up in a read mode when the write enable signal is at a first state and the memory is set up in a write mode when the v/rite enable signal is in a second state, comprising the steps of: monitoring the memory primary power to detect a failure of the primary power; driving a primary power warning signal from an inactive state to an active state when a failure of the primary power is detected; connecting the write enable output terminal of the control circuit to the memory control node of the memory. when said primary pov/er warning signal is in said inactive state; disconnecting the write enable output terminal of the control circuit from the memory control node of the memory when said primary pov/er warning signal is at said active state; and connecting a backup pov/er source to the memory control node when said primary power warning signal is in said active state.