WO1983001153A1 - Integrated protection device against overvoltages in an electronic circuit and electronic circuit protected by such device - Google Patents

Integrated protection device against overvoltages in an electronic circuit and electronic circuit protected by such device Download PDF

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Publication number
WO1983001153A1
WO1983001153A1 PCT/FR1982/000134 FR8200134W WO8301153A1 WO 1983001153 A1 WO1983001153 A1 WO 1983001153A1 FR 8200134 W FR8200134 W FR 8200134W WO 8301153 A1 WO8301153 A1 WO 8301153A1
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WO
WIPO (PCT)
Prior art keywords
varistor
connection
external access
connections
protection device
Prior art date
Application number
PCT/FR1982/000134
Other languages
French (fr)
Inventor
15 Interfaces
Original Assignee
Carreras, Michelle
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Carreras, Michelle filed Critical Carreras, Michelle
Publication of WO1983001153A1 publication Critical patent/WO1983001153A1/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01CRESISTORS
    • H01C7/00Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/10Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material voltage responsive, i.e. varistors
    • H01C7/1006Thick film varistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01CRESISTORS
    • H01C7/00Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/10Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material voltage responsive, i.e. varistors
    • H01C7/1013Thin film varistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/62Protection against overvoltage, e.g. fuses, shunts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12044OLED

Definitions

  • the present invention relates to an integrated protection device for electronic circuits and semiconductors against electrical overvoltages of static or dynamic origin. It applies to the 5 circuits and semiconductors known to be particularly fragile with overvoltages, such as for example MOS or field effect transistors, these being further encapsulated in housings made of insulating material such as ceramics. 0
  • the protective device according to the invention is applicable to any existing insulating package, such as, for example, discrete semiconductors in TO 220 * or TO 126 type plastics, which often replace, for reasons of economy, the 5 metal boxes of type TO 3. It is also applicable to mounted integrated circuits .
  • the object of the invention must be realized before the plastic encapsulation.
  • the device according to the invention applies to any discrete, integrated or hybrid electronic component mounted in a housing the surfaces of which, internal or external, poorly flow electrical charges.
  • an operator seated at a work station creates static voltages between 500 and 3,000 volts, while walking on an insulating mat, he creates static voltages compri ⁇ * between 12,000 and 40,000 volts.
  • the MOS and FET circuits are sensitive to electrostatic discharges from 100 to 200 volts and the bipolar transistors to electrostatic discharges from 380 to 7000 volts.
  • connections are metal strips deposited on and under a ceramic plate, it is no longer possible to prick them in a conductive material.
  • the connections being very generally on, the sides of the plate located at the bottom of a protective groove, it is difficult to take the plate with a clamp which short-circuits all the connections.
  • the device according to the invention provides a continuous, rather than a temporary, solution to the protection against overvoltages, whatever the forms of the external connections.
  • the protection device consists in bringing together the external connections, taken two by. two, by a non-linear resistance element with a • low voltage varistor whose resistance is very high at normal operating voltages of the component and becomes low or very low as soon as the so-called varistor threshold voltage, short-circuiting the connections and - protecting the component since a short-circuit is established between its external connections.
  • the non-linear resistance element or varistor consists of a ring which covers all the output metallizations, or by a localized deposit which joins them two by two.
  • a metallization which covers the non-linear resistance makes it possible to drain the overvoltages to ground.
  • the invention relates to an integrated protection device against surten ⁇ sions of an electronic circuit mounted on a support made of insulating material * and provided with at least one external access connection secured to the support, this device , protective being - characterized in that it is constituted by a resistor with a non-linear effect, called a low-voltage varistor - of threshold (V), of which o a first terminal is in ohimic contact with a metal electrode for setting the mass, the thickness of the varistor material between the connection and the grounding electrode being such that, for any overvoltage (U) (dangerous for the electronic circuit and greater than the threshold voltage
  • FIG. 1 curves of current-voltage characteristics of varistors according to known art
  • FIG. 2 diagram of the protection device according to the invention, in a first type
  • FIG. 3 diagram of the device according to the invention, in a second type
  • FIG. 6 a third embodiment example according to the second type
  • Figure 1 recalls the current characteristics as a function of the voltage for the varistan ⁇ these in the general case of the known art.
  • the varistors are, quite generally, obtained from mixtures of powders based on zinc oxide, the structure of which has defects and to which various oxides of bismuth chromium, manganese, cobalt have been added. .., the oxide Bi203 being found essential for the development of the non-linearity of the varistor.
  • V across a varistor can therefore be expressed as being equal to:
  • V - n.
  • V g g with n 'number of grains in series in the g varistor
  • V the tension per grain,. this voltage per grain being between 2 and 4 volts approximately for the varistors currently known. Consequently, if it is desired to protect a circuit against a given voltage, it suffices to lay down a deposit thickness determined by the number of grains.
  • the protective device according to the invention therefore consists of having a given thickness of varistor between an access electrode to a circuit or a semiconductor and an electrode that is grounded, this varistor being considered to have a very high resistance. high at voltages below the threshold voltage V of the varistor, o
  • _OAÎPI while it becomes almost conductive at voltages higher than the threshold voltage, thus passing the overvoltages of static or dynamic origin to ground via the ground electrode.
  • FIG. 2 represents the diagram of the protection device according to the invention, in a first type of operation.
  • the thickness "e" of the varistor is partly determined by the diameter of the grains with which the varistors are made, and partly by the voltage beyond which the operation of the circuit protection device has been fixed.
  • MOS a deposit thickness of the order of three to five grain diameters can be used, that is to say, with grains whose diameter is between 10 and 20 microns, a thickness of 30 to 100 microns for varistor.
  • the varistor is deposited according to known art processes such as screen printing, vacuum deposition or plasma torch.
  • the material is then annealed by a global or localized annealing treatment, with known means such as the laser, so as to constitute the restoration of the properties of the grain boundaries.
  • the upper electrode 7 can be made of non-noble materials, such as for example bismuth, or aluminum or silver, or nickel, doped with oxides of bismuth, silicon or lead.
  • the varistor 6 is deposited in the form of a ring which surrounds the circuit, soldered in the middle of the substrate 3, and realizes, in the event of overvoltage, a short table. circuit of all external access connections, acting somewhat like a Faraday cage.
  • the presence of a varistor in the region 8 located between two access electrodes such as 4 and 5 plays practically no role since the spacing between the two electrodes considered .e counts rather in fraction of a millimeter and not in microns: there is therefore a transverse operating effect of the varistor 6 and this distance 8 is too high to play a role.
  • the transverse operation between two access electrodes which is implemented in the second type of operation of the invention, that is illustrated in FIG. 3.
  • a ribbon 6 of varis ⁇ tance is deposited on and between the external connections, by a method such as screen printing.
  • the action of the varistor is transverse, that is to say that the thickness of the varistor which will cross its voltage threshold V in the event of a static or dynamic overvoltage that is called the "high speed". you correspond at the distance or at the distance 10 between the metallizations of two connections 4 and 5.
  • This distance "-fc" determines the threshold, for switching of the varistor and it is expressed as has already been said by a thick - grain size of the varistor material. This thickness is therefore counted in a few hundred microns.
  • the safest method for carrying out this second type of protection against voltage overloads consists first of all in making a grid of external connections which are all short-circuited and cut from the same sheet of metal, then separating them by laser cutting or by chemical attack, preceded by photomasking .
  • a continuity solution 10 between two electrodes 4 and 5 it becomes easy to deposit "a" varistor ribbon 6 which fills this inervall 10 with the varistor material over a thickness of a few grains.
  • This second type of embodiment has two advantages: it makes it possible to connect all the external -connections before depositing the varistor, which facilitates the electrolytic deposits of the surface layers such as nickel, gold, silver, etc. etc, and in addition it is only necessary to make a single deposit, that of the varistor since there is no longer any metalization 7 for grounding, as in the first type.
  • FIG. 4 represents a first example of embodiment of the protection device according to the invention, on the base of a micro-housing of the chip-carrier type. Compared to partial figures 2 and 3,
  • igure 4 a ceramic base 3, on which have been deposited a number of metallizations of external connections such as 4 and 5.
  • a number of metallizations of external connections such as 4 and 5.
  • the chip carriers can reach the hundred or so external connections.
  • a ring 6 of varistor has been deposited then, on top of this, an electrode 7 in the form of a ring also, but this electrode is joined together ⁇ to one of the external connections, by a metal bridge II, said external connection being that which corresponds to the ground potential.
  • FIG. 4 and this example of embodiment also remain in the field of the invention.
  • the varistor acts as a sort of Faraday cage ' short-circuiting all the connections and the electrical charges flow through the connection to ground, but this case is of course less favorable than that which provides for metallization 7.
  • FIG. 4 shows the base of a chip-carrier: it is understood that this is only a matter of an example to explain the invention and. that the device according to the invention also applies to any other type of substrate.
  • FIG. 5 represents a second exemplary embodiment according to the first type of the protection device of the invention.
  • the first type of protection acts according to the thickness of the varis ⁇ tance.
  • the varistor is deposited in the form of a ring, consequently having a continuous band, and this varistor band is surmounted by a continuous metallization band which drains the overvoltages to ground.
  • the varistor is produced in the form of a stud, deposited on each external connection, and the upper metallization or ground flow electrode, is a metalli ⁇ tion taken out on the neighboring connection. According to this second type, all the connections act in series.
  • a fragment of substrate 3 has been represented, this fragment supporting a few external connections such as 4 and 5.
  • a varistor block such as 12 on connection 4 and 13 on connection 5.
  • This stud has reduced dimensions but it is important during deposition that it partially covers at least one side ' of the connection in order to avoid short circuits between the elect trode upper '16 with the connection 4, oul7 with the connection 5.
  • This lateral deposition such as 14 and 15 has no role but a varistor insulator.
  • a second localized metallization such as 16 and 17 covers the varistor block 12 or 13 and is in ohmic contact with the connection close to the connection which supports the block:.
  • connection 4 The electrode 16 is in ohmic contact with the connection 5 and the electrode 17 above the connection 5 is in ohmic contact with the neighboring connection, and so on.
  • the varistor therefore acts according to the thickness of the varistor layer between two metal parts which constitute the terminals of the aristor.
  • protection device may concern either one or more connections which are particularly exposed to overvoltages, or all of the external connections.
  • Figure 6 shows a third embodiment of the protection device according to one • in- vention, according to the second type.
  • Figure 6 shows a fragment 3 • substrate supporting at least two external connections 4 and 5.
  • the. external connections 'that they are made in a cut metal plate, as is the case for example for DIL packages, or that they are produced by screen printing of a metal-based paste on a substrate ceramic, as is the case for chip-carrier micro-housings, are all originally joined by a metal bridge 18.
  • metal bridges 18 are cut by any process known to those skilled in the art, such as a chemical attack under mask or a laser beam cutting, so as to leave two arches 9 of the bridge 18, these arches or beaches of .
  • metallization 9 leaving between them a space 10 which corresponds to the thickness "t" of desired varistor, as a function of the composition of the material, of its characteristics and of the tension against which it is sought to protect itself.
  • the varistor 6 is deposited either by screen printing or by spraying and it fills the intervals 10 between the metal areas, also forming incidentally but this is not essential for the operation of the device one. continuous strip as described on the occasion of FIG. 2 or of FIG. 3.
  • the varistor therefore acts transversely between two connections.
  • the protection device can be applied between a connection particularly subjected to external overvoltages, between several or between the all-. connections, at least one of which is grounded.
  • FIG. 7 represents a fourth embodiment of the device for protection against overvoltages, in the case of a metal case, such as for example the boxes T03 for encapsulation of discrete semiconductor.
  • FIG. 7 is shown in 19 a fragment of the metal base of a housing: the external access connection 4 is immobilized and supported on this base by means of a glass bead 3, which fulfills the function of the insulating substrate described on the occasion of. previous examples.
  • the invention provides for depositing a film or a drop of varistor 20 at the foot of the connection 4, and on the base 19.- In this case , the action of the varis ⁇ tance is exerted according to the distance 21 separating the per ⁇ turn of the connection 4 at the edge of the hole in the base 19 which supports the glass bead 3.
  • the overvoltage protection therefore acts according to the second type, that is to say transversely. Given, on the one hand, that this distance 21 is greater than that which separates a connection from its grounding electrode in the examples described above, but that on the other hand the switching voltage of the vaistor 20 is a function of the intergranular tension, it suffices to increase the particle size of the starting material, so as to provide protection through a length 21 of varistor corresponding to a precise number of grains of material.

Abstract

The device is intended for the protection of circuits and semiconductors against static overvoltages or dynamic voltage overloads. The device according to the invention comprises the deposition on the support (3) and on the external access connections (4, 5) to the circuit of a non-linear resistance or varistance (6), of which the composition and the thickness of the deposition are selected so that the threshold voltage (Vo?) of the varistance is lower than the critical overvoltage for the circuit. According to a preferred embodiment of the invention, the varistance (6) is deposited by serigraphy as a ring covering the external access connections (4, 5), and metallization (7) deposited on the varistance (6) provides for the grounding in case of overvoltage. According to another embodiment, the grounding is provided by the access connections themselves. Application to MOS and FET circuits in ceramic micro-packages or to hybrid circuits.

Description

DISPOSITIF DE PROTECTION INTEGRE CONTRE LES SURTENSIONS D'UN CIRCUIT ELECTRONIQUE, ET CIRCUIT ELECTRONIQUE PROTEGE INTEGRATED PROTECTION AGAINST OVERVOLTAGES OF AN ELECTRONIC CIRCUIT, AND PROTECTED ELECTRONIC CIRCUIT
PAR CE DISPOSITIFBY THIS DEVICE
La présente invention concerne un dispositif de protection intégré des circuits électroniques et des semiconducteurs contre les surtensions électriques d'origine statique ou dynamique. Elle s'applique aux 5 circuits et aux semiconducteurs réputés particulière¬ ment fragiles aux surtensions, tels que par exemple les MOS ou les transistors à effet de champ-, ceux-ci étant en outre encapsulés dans des boîtiers en maté¬ riau isolant tel que des céramiques. 0 Le dispositif de protection selon l'invention est applicable à tout boîtier isolant existant, tel que par exemple les semiconducteurs discrets en boîti¬ ers de type TO 220* ou TO 126, plastiques, qui remplacent souvent pour des raisons, d'économie les 5 boîtiers métalliques de type TO 3. Elle est également applicable aux circuits intégrés montés .en boîtiers' de type DIL ou en microboîtiers couramment appelés chip-carriers, céramiques, enfin aux circuits hybri¬ des sur substrats céramiques ou tôle émaillée. Dans 0 le cas de boîtiers d ' encapsulation plastique, l'objet de l'invention doit être réalisé avant l' encapsula¬ tion plastique.The present invention relates to an integrated protection device for electronic circuits and semiconductors against electrical overvoltages of static or dynamic origin. It applies to the 5 circuits and semiconductors known to be particularly fragile with overvoltages, such as for example MOS or field effect transistors, these being further encapsulated in housings made of insulating material such as ceramics. 0 The protective device according to the invention is applicable to any existing insulating package, such as, for example, discrete semiconductors in TO 220 * or TO 126 type plastics, which often replace, for reasons of economy, the 5 metal boxes of type TO 3. It is also applicable to mounted integrated circuits . in housings ' of the DIL type or in micro-housings commonly called chip-carriers, ceramics, finally with hybri¬ circuits on ceramic substrates or enameled sheet. In 0 in the case of plastic encapsulation boxes, the object of the invention must be realized before the plastic encapsulation.
De façon plus générale, le dispositif selon l'in¬ vention s'applique à tout composant électronique dis- 5 cret, intégré ou hybride monté dans un boîtier dont les surfaces, internes ou externes, écoulent mal les charges électriques.More generally, the device according to the invention applies to any discrete, integrated or hybrid electronic component mounted in a housing the surfaces of which, internal or external, poorly flow electrical charges.
Il est connu que les composants électroniques sont calculés pour fonctionner à des tensions relati- 0 vement faibles, telles que par exemple + 5 V pour les circuits TTL , 15V pour les circuits MOS, quelques centaines de volts pour les transistors de puissance, sans que ceci soit limitatif. Ces mêmes composants sont bien entendu réalisés avec un coefficient de sécurité qui permet une certaine marge sur les ten- sions, de quelques dizaines de volts selon les types. Ceci ne met cependant pas ces composants à l'abri des décharges d'électricité statique ou des surchar¬ ges accidentelles de tension, en service. En effet, surtout en ce qui concerne l'électricité statique, les tensions développées sont sans commune mesure avec les tensions admissibles. C'est ainsi que, à titre d'exemple, un opérateur assis à un poste de travail crée des tensions statiques comprises entre 500 et 3 000 volts, tandis qu'en marchant sur un tapis isolant, il crée des tensions statiques compri¬ ses* entre 12 000 et 40 000 volts. A titre de comparaison, les circuits MOS et FET sont sensibles à des décharges électrostatiques de 100 à 200 volts et les transistors bipolaires à des décharges électro- statiques de 380 à 7 000 volts.It is known that electronic components are calculated to operate at relatively low voltages, such as for example + 5 V for TTL circuits, 15 V for MOS circuits, some hundreds of volts for power transistors, without this being limiting. These same components are of course produced with a safety coefficient which allows a certain margin on the voltages, of a few tens of volts depending on the types. This does not, however, protect these components from static electricity discharges or accidental voltage overloads, in service. Indeed, especially with regard to static electricity, the developed voltages are incommensurate with the admissible voltages. Thus, for example, an operator seated at a work station creates static voltages between 500 and 3,000 volts, while walking on an insulating mat, he creates static voltages compri¬ * between 12,000 and 40,000 volts. By way of comparison, the MOS and FET circuits are sensitive to electrostatic discharges from 100 to 200 volts and the bipolar transistors to electrostatic discharges from 380 to 7000 volts.
Il est donc nécessaire de protéger les composants, e*t surtout les plus fragiles tels que les circuits intégrés et les MOS contre toute surtension d'origine statique ou dynamique afin d'éviter leur destruction. Les solutions actuellement connues sont des solu¬ tions - temporaires qui consistent à court-circuiter les connexions externes pend'ant leur stockage, leur manipulation ou leur soudure sur un circuit complexe. C'est ainsi que, à titre d'exemple, les composants encapsulés dans . des boîtiers munis de connexions extérieures embrochables, tels que les boîtiers du type DIL, ou supportés par des substrats également munis de connexions tels que les circuits hybrides, sont piqués pour leur stockage et leur transport, dans des mousses organiques rendues conductrices de l'électricité ou recouvertes d'une feuille métallique qui court-circuite les connexions. Pendant leur mani¬ pulation, ces mêmes boîtiers sont pris par des pinces spéciales qui court-circuitent entre elles les conne¬ xions et les mettent à la masse.It is therefore necessary to protect the components, e * t especially the most vulnerable, such as integrated circuits and MOS against overvoltage static or dynamic origin to prevent their destruction. The currently known solutions are solu¬ tions - which involve temporary bypass external connections hangs' ant storage, handling or welding on a complex circuit. This is how, for example, the components encapsulated in. boxes fitted with plug-in external connections, such as DIL type boxes, or supported by substrates also fitted with connections such as hybrid circuits, are pricked for storage and transport, in organic foams made electrically conductive or covered with a metallic foil which short-circuits the connections. During their handling, these same cases are taken up by special clamps which short-circuit the connections between them and ground them.
• Il n'en est plus de même avec les boîtiers sans connexions embrochables tels que les chip-carriers. D'une part, puisque les connexions sont des bandes métalliques déposées sur et sous une plaquette cérami¬ que., il n'est plus possible de les piquer dans un matériau conducteur. D'autre part, les connexions étant très généralement sur ,les flancs de la plaquet¬ te situées au fond d'une gorge de protection, il est malaisé de prendre la plaquette avec une pince qui court-circuite toutes les connexions.• It is no longer the same with housings without plug-in connections such as chip-carriers. On the one hand, since the connections are metal strips deposited on and under a ceramic plate, it is no longer possible to prick them in a conductive material. On the other hand, the connections being very generally on, the sides of the plate located at the bottom of a protective groove, it is difficult to take the plate with a clamp which short-circuits all the connections.
Dans tous les cas, l'action de court-circuit des connexions externes, que ce soit avec connexions em¬ brochables ou que ce soit en court-circuitant les métallisations d'un chip-carrier, cesse quand la pin¬ ce lâche le composant, ou quand le composant est retiré de la mousse dans laquelle il a été piqué. Enfin cette action n'est valable qu'en cours de monta¬ ge ou de manipulation de composant contre les décharges statiques : il n'y a plus d'action contre les surtensions dynamiques au cours du fonctionnement du semiconducteur ou du circuit électronique.In all cases, the short-circuiting action of the external connections, whether with plug-in em¬ connections or by short-circuiting the metallizations of a chip-carrier, ceases when the pin releases this component. , or when the component is removed from the foam in which it was stuck. Finally, this action is only valid during assembly or manipulation of the component against static discharges: there is no longer any action against dynamic overvoltages during the operation of the semiconductor or the electronic circuit.
Le dispositif selon l'invention apporte une solu¬ tion continue, et non plus temporaire, à la pr.otec- tion contre les surtensions., quelles que soient les formes des connexions extérieures. En effet, le dispo- * sitif de protection consiste à réunir les connexions externes, prises deux par. deux, par un élément de résistance non linéaire à effet varistance à basse tension dont la résistance est très élevée aux tensions de service normales du composant et devient faible ou très faible dès que la tension dite de seuil de la varistance, court-circuitant alors les connexions et - protégeant le composant puisqu'un court-circuit est établi entre ses connexions exter¬ nes. Selon la- con iguration du microboîtier ou du substrat, l'élément de résistance non linéaire ou varistance est constitué par un anneau qui recouvre toutes les métallisations de sortie, ou par un dépôt localisé qui les réunit deux à deux. Selon une forme préférée de l'invention, une métallisation qui recou¬ vre la résistance non linéaire permet d'écouler les surtensions à la masse.The device according to the invention provides a continuous, rather than a temporary, solution to the protection against overvoltages, whatever the forms of the external connections. Indeed, the protection device consists in bringing together the external connections, taken two by. two, by a non-linear resistance element with a low voltage varistor whose resistance is very high at normal operating voltages of the component and becomes low or very low as soon as the so-called varistor threshold voltage, short-circuiting the connections and - protecting the component since a short-circuit is established between its external connections. According to the configuration of the micro-housing or of the substrate, the non-linear resistance element or varistor consists of a ring which covers all the output metallizations, or by a localized deposit which joins them two by two. According to a preferred form of the invention, a metallization which covers the non-linear resistance makes it possible to drain the overvoltages to ground.
De façon plus précise, l'invention concerne un dispositif de protection intégré contre les surten¬ sions d'un circuit électronique monté sur un support en matériau isolant* et muni d'au moins une connexion d'accès extérieur solidaire du support, ce dispositif, de protection étant - caractérisé en ce qu'il est constitué par une .résistance à effet non linéaire, dite varistance à basse tension- de seuil (V ) , dont o une première borne est en contact ohimique avec une électrode métallique de mise à la masse, l'épaisseur du matériau de varistance comprise entre la connexion et l'-électrode de mise à la masse étant telle que, pour toute surtension (U) (dangereuse pour le circuit électronique et supérieure à la tension de seuilMore specifically, the invention relates to an integrated protection device against surten¬ sions of an electronic circuit mounted on a support made of insulating material * and provided with at least one external access connection secured to the support, this device , protective being - characterized in that it is constituted by a resistor with a non-linear effect, called a low-voltage varistor - of threshold (V), of which o a first terminal is in ohimic contact with a metal electrode for setting the mass, the thickness of the varistor material between the connection and the grounding electrode being such that, for any overvoltage (U) (dangerous for the electronic circuit and greater than the threshold voltage
(Vo) de la varistance) , celle-ci franchit .son seuil de basculement et' établit une liaison peu résistive entre la connexion et la masse.(Vo) of the varistor), it crosses its tilting threshold and ' establishes a weak resistive connection between the connection and the ground.
L'invention sera mieux comprise par la description d'exemples de réalisation qui va en être faite, en s ' appuyant sur les figures jointes en annexe et qui représentent : - figure 1 : courbes de caractéristiques courant- tension de varistances selon l'art connu,The invention will be better understood from the description of embodiments which will be made thereof, by relying on the attached figures which represent: FIG. 1: curves of current-voltage characteristics of varistors according to known art,
- figure 2 : schéma du dispositif de protection selon l'invention, dans un premier type, - figure 3 : schéma du dispositif selon l'inven¬ tion, dans un deuxième type,FIG. 2: diagram of the protection device according to the invention, in a first type, FIG. 3: diagram of the device according to the invention, in a second type,
- figure 4 : un premier exemple de réalisation selon le premier type sur un • microboîtier ou chip-carrier, - figure 5 : un second exemple de réalisation selon le premier type,- Figure 4: a first embodiment according to the first type on a • micro-housing or chip-carrier, - Figure 5: a second embodiment according to the first type,
- figure 6 : un troisième exemple de réalisation selon le second type,FIG. 6: a third embodiment example according to the second type,
- figure* 7 : un quatrième exemple de réalisation sur boîtier à socle métallique.- Figure * 7: a fourth embodiment on a metal base housing.
La figure 1 rappelle les caractéristiques de courant en fonction de la tension pour les varistan¬ ces dans le cas général de l'art connu.Figure 1 recalls the current characteristics as a function of the voltage for the varistan¬ these in the general case of the known art.
Les varistances sont, de façon tout à fait généra- le , obtenues à partir de mélanges de poudres à base d'oxyde de zinc dont la structure présente des dé¬ fauts et auxquelles ont été ajoutés différents oxydes de bismuth chrome, manganèse, cobalt ..., l'oxyde Bi203 étant trouvé essentiel pour le développement de la non-linéarité de la varistance. La caractéristi¬ que courant-tension d'une varistance n'est donc pas de la forme linéaire I = V/R.V comme' dans les - résistances classiques, mais est d'une forme non linéaire et suit une relation du type I = Kλ avec k étant une constante et α* un coefficient de non-li¬ néarité dépendant de la microstructure du matériau de fabrication de la variβtance. Par différentes compositions du mélange et différents procédés de fabrication des varistances, qui sortent du domaine de l'invention et appartiennent à l'art connu, on sait réaliser des varistances dont les caractéristi¬ ques sont variables, et illustrées à titre d'exemple sur la figure 1 par deux courbes. La tension étant portée en abscisses et l'intensité . étant portée en ordonnées on voit qu'une varistance correspondant à la courbe 1 a une variation monotone de ses caracté¬ ristiques tandis qu'une autre varistance correspondant à la courbe 2 reste très résistante jusqu'à une cer¬ taine tension de seuil repérée V° , tension au delà de laquelle la varistance devient quasiment conduc¬ trice. C'est ce second type de varistance, qui a une tension de seuil à* basculement brutal, qui est inté¬ ressant pour la mise en oeuvre du dispositif selon l'invention.The varistors are, quite generally, obtained from mixtures of powders based on zinc oxide, the structure of which has defects and to which various oxides of bismuth chromium, manganese, cobalt have been added. .., the oxide Bi203 being found essential for the development of the non-linearity of the varistor. The characteristic current-voltage of a varistor is therefore not of the linear form I = V / RV as ' in the - classic resistors, but is of a non-linear form and follows a relation of the type I = Kλ with k being a constant and α * a coefficient of non-linearity depending on the microstructure of the material for manufacturing the variβtance. By different compositions of the mixture and different methods of manufacturing the varistors, which are outside the scope of the invention and belong to the known art, knows how to make varistors whose characteristics are variable, and illustrated by way of example in FIG. 1 by two curves. The tension being plotted on the abscissa and the intensity. being plotted on the ordinate we see that a varistor corresponding to curve 1 has a monotonous variation of its characteristics while another varistor corresponding to curve 2 remains very resistant up to a certain threshold voltage marked V °, voltage beyond which the varistor becomes almost conductive. It is this second type of varistor, which has a threshold voltage with * sudden tilting, which is of interest for the implementation of the device according to the invention.
On sait d'autre part que l'effet varistance est lié à un effet de champ aux. joints de grains. La tension V aux bornes d'une varistance peut donc être exprimée comme étant égale à :We also know that the varistor effect is linked to an aux field effect. grain boundaries. The voltage V across a varistor can therefore be expressed as being equal to:
V =- n .V g g avec n = 'nombre de grains en série dans la g varistance etV = - n. V g g with n = 'number of grains in series in the g varistor and
V = la tension par grain, . cette tension par grain étant comprise entre 2 et 4 volts environ pour les varistances actuellement con- nues. Par conséquent, si l'on souhaite protéger un circuit contre, une tension donnée, il suffit de dis¬ poser d'une épaisseur de dépôt déterminée par le nom¬ bre de grains. Le dispositif de protection selon l'invention consiste donc à disposer entre une élec- trode d'accès à un circuit ou à un semiconducteur et une électrode dé mise à la masse une épaisseur donnée de varistance, cette varistance étant considérée comme présentant une résistance très élevée aux tensions inférieures à la tensi.on de seuil V de la varistance, oV = the tension per grain,. this voltage per grain being between 2 and 4 volts approximately for the varistors currently known. Consequently, if it is desired to protect a circuit against a given voltage, it suffices to lay down a deposit thickness determined by the number of grains. The protective device according to the invention therefore consists of having a given thickness of varistor between an access electrode to a circuit or a semiconductor and an electrode that is grounded, this varistor being considered to have a very high resistance. high at voltages below the threshold voltage V of the varistor, o
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, _OAÎPI tandis qu'elle devient quasiment conductrice aux tensions supérieures à la tension de seuil, écoulant ainsi les surtensions d'origine statique ou dynamique à la masse par l'intermédiaire de l'électrode de 5 masse., _OAÎPI while it becomes almost conductive at voltages higher than the threshold voltage, thus passing the overvoltages of static or dynamic origin to ground via the ground electrode.
La figure 2 représente le schéma du dispositif de protection selon l'invention, dans un premier type de fonctionnement.FIG. 2 represents the diagram of the protection device according to the invention, in a first type of operation.
En vue de' simplifier la figure et le texte il n'' aIn order to 'simplify the figure and the text it n' has
10 été représentée qu'une partie d'un substrat supportant deux électrodes., Soit 3 un substrat céramique qui dans le cas de figure peut être le substrat d'un phip-car- rier, mais qui pourrait également être l'embase d'un boîtier d 'encapsulation de' type DIL., ce substrat céra-10 has been shown that part of a substrate supporting two electrodes., Let 3 be a ceramic substrate which in the case may be the substrate of a phip-quarry, but which could also be the base of a DIL type encapsulation box, this ceramic substrate
15 mique ' 3 supportant donc les connexions externes 4 et 5, dont il est connu qu'une extrémité sert à fixer le boîtier d' encapsulation sur un support tandis que l'autre extrémité assure les connexions avec la pas¬ tille de semiconducteur. Selon l'invetion, une bande15 mique '3 therefore supporting the external connections 4 and 5, of which it is known that one end is used to fix the encapsulation box on a support while the other end provides connections with the semiconductor pas¬ tille. According to the invention, a band
20 de matériau à effet varistance 6 est déposée entre les connexions, cette bande étant elle-même surmontée par une bande métallique 7 qui est reliée à une connexion de masse. Ainsi l'effet varistance se déve¬ loppe entre chaque connexion d'accès telle que 4 et20 of varistor effect material 6 is deposited between the connections, this strip itself being surmounted by a metal strip 7 which is connected to a ground connection. Thus the varistor effect develops between each access connection such as 4 and
25 -l'électrode de mise à la masse 7 à travers une épaisseur repérée de matériau à effet varistance25 -the grounding electrode 7 through a marked thickness of varistor-effect material
Tant que le semiconducteur est soumis à des tensions d'alimentation normales, la tension existant entre l'électrode d'accès 4 et l'électrode de mise à laAs long as the semiconductor is subjected to normal supply voltages, the voltage existing between the access electrode 4 and the release electrode
30. masse 7 est inférieure à la tension de seuil V o choisie pour la varistance 6 : par conséquent celle- ci se comporte comme un .élément ayant une résistance très élevée quasiment comme un' isolant. Par contre, si une -surtension, telle que par exemple une décharge30. 7 weight is less than the threshold voltage V o selected for the varistor 6: therefore the latter behaves as a .A having a very high resistance almost as insulation. On the other hand, if a surge, such as for example a discharge
Figure imgf000009_0001
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Figure imgf000009_0001
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d'électricité statique, se présente sur la même élec¬ trode d'accès 4 la varistance devient conductrice dans un temps extrêmement bref puisqu'il s'agit d'un phé¬ nomène à effet de . champ, et la surtension, au lieu 8e détériorer le semiconducteur, est écoulée à la masse. L'épaisseur "e" de la varistance est déterminée en partie par le diamètre des grains avec lesquels sont réalisées les varistances, et en partie par la tension au delà de laquelle on a fixé le fonction- nement du dispositif de protection d'un circuit MOS, on pourra utiliser une épaisseur de dépôt de l'ordre de trois à cinq diamètres de grains, c ' est—à-dire , avec des grains dont le diamètre est compris entre 10 et 20 microns une épaisseur de 30, à 100 microns pour la varistance.of static electricity, occurs on the same elec¬ access electrode 4 the varistor becomes conductive in an extremely short time since it is a phene¬ effect. field, and the overvoltage, instead of 8th deteriorating the semiconductor, is drained to ground. The thickness "e" of the varistor is partly determined by the diameter of the grains with which the varistors are made, and partly by the voltage beyond which the operation of the circuit protection device has been fixed. MOS, a deposit thickness of the order of three to five grain diameters can be used, that is to say, with grains whose diameter is between 10 and 20 microns, a thickness of 30 to 100 microns for varistor.
Le dépôt de la varistance se fait selon les pro¬ cédés de l'art 'connu tels que sérigraphie, dépôt sous vide ou chalumeau à plasma. Le matériau est ensuite recuit par un traitement de recuit global ou localisé, avec des moyens connus tels que le laser, de façon à constituer du à restaurer les propriétés des joints de grains.The varistor is deposited according to known art processes such as screen printing, vacuum deposition or plasma torch. The material is then annealed by a global or localized annealing treatment, with known means such as the laser, so as to constitute the restoration of the properties of the grain boundaries.
A titre d'exemple non limitatif, avec les maté¬ riaux de varistance' actuellement connus, il est possi- ble de réaliser des protections des sorties d'un circuit avec des valeurs d'isolement, entre conne¬ xions d'accès externe et électrodes de mise à la masse :By way of example, with varistor rials maté¬ 'currently known, it is possi- ble to achieve protection of outputs of a circuit with insulation values between conne¬ xions external access and grounding electrodes:
- V < 10 Volts, R ≈ 50 à 100 k ohms - V - 5 Volts, R ~ 10 Moh s- V <10 Volts, R ≈ 50 to 100 k ohms - V - 5 Volts, R ~ 10 Moh s
"- V > 10 Volts, R ~ 10 à 100 Mohms De plus, certaines compositions ou des modifi¬ cations d'épaisseur permettent de protéger à des tensions plus élevées que celles citées, par exemple 25 ou 50 Volts. L'électrode supérieure 7 peut être constituée de matériaux non nobles, tels que par exemple le bismuth, ou l'aluminium ou l'argent, ou le nickel, dopés par des oxydes de bismuth, de silicium ou de plomb. Selon une forme préférée du dispositif selon l'in¬ vention, la varistance 6 est déposée sous forme d'un anneau qui entoure le circuit, soudé au milieu du substrat 3, et réalise, en cas de surtension, un véri¬ table court-circuit de toutes les connexions d'accès externe, agissant en quelque sorte comme une cage de Faraday. Dans ce premier type de réalisation de l'in¬ vention, la présence de varistance dans la région 8 située entre deux électrodes d'accès telles que 4 et 5 ne joue pratiquement aucun rôle puisque l'ecartement entre les deux électrodes considérées .e compte plutôt en fraction de millimètre et non pas en microns : il y a donc un effet de fonctionnement transversal de la varistance 6 et cette distance 8 est trop élevée pour jouer un rôle. Par contre, c'est le fonctionnement transversal entre deux électrodes d'accès, qui est mis en oeuvre dans le second type de fonctionnement de l'invention, qu'illustre la figure 3. " - V> 10 Volts, R ~ 10 to 100 Mohms In addition, certain compositions or changes in thickness make it possible to protect at higher voltages than those mentioned, for example 25 or 50 Volts. The upper electrode 7 can be made of non-noble materials, such as for example bismuth, or aluminum or silver, or nickel, doped with oxides of bismuth, silicon or lead. According to a preferred form of the device according to the invention, the varistor 6 is deposited in the form of a ring which surrounds the circuit, soldered in the middle of the substrate 3, and realizes, in the event of overvoltage, a short table. circuit of all external access connections, acting somewhat like a Faraday cage. In this first type of embodiment of the invention, the presence of a varistor in the region 8 located between two access electrodes such as 4 and 5 plays practically no role since the spacing between the two electrodes considered .e counts rather in fraction of a millimeter and not in microns: there is therefore a transverse operating effect of the varistor 6 and this distance 8 is too high to play a role. On the other hand, it is the transverse operation between two access electrodes, which is implemented in the second type of operation of the invention, that is illustrated in FIG. 3.
De même que pour la figure 1, et afin de simpli- fier les dessins et le texte, seul un fragment de substrat 3 a été représenté ainsi que deux électrodes d ' accès 4 et 5.As in FIG. 1, and in order to simplify the drawings and the text, only a fragment of substrate 3 has been represented as well as two access electrodes 4 and 5.
Comme dans le cas précédent, un ruban 6 de varis¬ tance est déposé sur et entre les connexions externes, par une méthode telle que la sérigraphie. Cependant l'action de la varistance est transversale, c'est-à- dire que l'épaisseur de la varistance qui va franchir son seuil de tension V en cas de surtension statiαue o ou dynami que es t l ' p ai sseur app elée " t" correspon dant à la distance ou à 1 ' éloignement 10 entre les métal- lisations de deux connexions 4 et 5. Cette distance "-fc" détermine le seuil, de basculement de la varistance et il s'exprime comme il a déjà été dit par une épais- seur des grains du matériau de la varistance. Cette épaisseur se compte par conséquent en quelques cen¬ taines de microns.As in the previous case, a ribbon 6 of varis¬ tance is deposited on and between the external connections, by a method such as screen printing. However, the action of the varistor is transverse, that is to say that the thickness of the varistor which will cross its voltage threshold V in the event of a static or dynamic overvoltage that is called the "high speed". you correspond at the distance or at the distance 10 between the metallizations of two connections 4 and 5. This distance "-fc" determines the threshold, for switching of the varistor and it is expressed as has already been said by a thick - grain size of the varistor material. This thickness is therefore counted in a few hundred microns.
Etant donné qu'il n'est pas possible de réaliser une grille de connexion externe dont chaque connexion est séparée de sa voisine par un intervalle 10 de l'ordre de 100 ou 200 microns, le procédé le plus sûr pour réaliser ce second type de protection contre les surcharges en tension consiste à réaliser d'abord une grille de connexions externes qui sont toutes court- circuitées et découpées dans la même feuille de métal, puis à les séparer par une découpe laser ou par une attaque chimique, précédée par un photomasquage. Dans ce cas ayant réalisé une solution de continuité 10 entre deux électrodes 4 et 5, il devient facile de déposer "un "ruban de varistance 6 qui remplit cet in¬ tervalle 10 avec le matériau de varistance sur une épaisseur de quelques grains.Since it is not possible to produce an external connection grid, each connection of which is separated from its neighbor by an interval 10 of the order of 100 or 200 microns, the safest method for carrying out this second type of protection against voltage overloads consists first of all in making a grid of external connections which are all short-circuited and cut from the same sheet of metal, then separating them by laser cutting or by chemical attack, preceded by photomasking . In this case having produced a continuity solution 10 between two electrodes 4 and 5, it becomes easy to deposit "a" varistor ribbon 6 which fills this inervall 10 with the varistor material over a thickness of a few grains.
Ce second type de réalisation .présente deux avan¬ tages : il permet de connecter toutes les -connexions ' extérieures, avant dépôt de la varistance, ce qui facilite les dépôts électrolytiques des couches super¬ ficielles telles que nickel, or, argent ... etc , et en outre il n'est nécessaire de faire qu'un seul dépôt, celui de la varistance puisqu'il n'y a plus de métal- lisation 7 de mise à la masse, comme dans le premier type.This second type of embodiment has two advantages: it makes it possible to connect all the external -connections before depositing the varistor, which facilitates the electrolytic deposits of the surface layers such as nickel, gold, silver, etc. etc, and in addition it is only necessary to make a single deposit, that of the varistor since there is no longer any metalization 7 for grounding, as in the first type.
La figure 4 représente un premier exemple de réa¬ lisation du dispositif de protection selon l'inven¬ tion, sur l'embase d'un microboîtier de type chip- carrier. Par rapport aux figures partielles 2 et 3,FIG. 4 represents a first example of embodiment of the protection device according to the invention, on the base of a micro-housing of the chip-carrier type. Compared to partial figures 2 and 3,
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on retrouve sur la igure 4 une embase céramique 3, sur laquelle ont été déposées un certain nombre de metallisations de connexions externes telles que 4 et 5. En vue de ne pas compliquer la figuré, quatre- metallisations seulement ont été représentées sur chacun des quatre côtés du chip-carrier, mais il est connu"*"que les chip-carriers peuvent atteindre la cen¬ taine de connexions extérieures. Sur l'embase de chip- carrier, munie de ses dépôts métalliques de connexions externes, à été déposé un anneau 6 de varistance puis, par dessus celui-ci, une électrode 7 en forme d'anneau également, mais cette électrode est réunie^ à l'une des connexions externes, par un pontet métallique II, ladite connexion externe étant celle qui correspond au potentiel de masse.we find in igure 4 a ceramic base 3, on which have been deposited a number of metallizations of external connections such as 4 and 5. In order not to complicate the figuration, only four metallizations have been shown on each of the four sides of the chip carrier, but it is known "* " that the chip carriers can reach the hundred or so external connections. On the base of the chip carrier, provided with its metallic deposits of external connections, a ring 6 of varistor has been deposited then, on top of this, an electrode 7 in the form of a ring also, but this electrode is joined together ^ to one of the external connections, by a metal bridge II, said external connection being that which corresponds to the ground potential.
La figure 4 et cet exemple de réalisation reste¬ raient également, dans le domaine de l'invention . si la métallisation 7 n'avait pas été réalisée par dessus la varistance 6. Dans ce cas, la varistance agit comme une sorte de cage de Faraday 'court-circuitant toutes les connexions et .les charges électriques s'écoulent par la connexion de mise à la masse, mais ce cas est bien entendu moins favorable que celui qui prévoit une métallisation 7. La figure 4.représente l'embase d'un chip—carrier: il est bien entendu qu'il ne s'agit là que d'un exem¬ ple pour expliquer l'invention et. que le dispositif selon l'invention s'applique également à tout autre type de substrat . isolant écoulant mal les charges - électriques et l'exemple d'application s'applique également, et avec les mêmes avantages, aux plaquettes substrats -céramiques de circuits hybrides, ou aux embases céramiques de circuits- intégrés encapsulés en .boîtiers DIL par exemple, ainsi qu'à tout autre encapsulation connue utilisant des matériaux tels que les céramiques.FIG. 4 and this example of embodiment also remain in the field of the invention. if the metallization 7 had not been carried out over the varistor 6. In this case, the varistor acts as a sort of Faraday cage ' short-circuiting all the connections and the electrical charges flow through the connection to ground, but this case is of course less favorable than that which provides for metallization 7. FIG. 4 shows the base of a chip-carrier: it is understood that this is only a matter of an example to explain the invention and. that the device according to the invention also applies to any other type of substrate. insulator badly draining the charges - electrical and the example of application also applies, and with the same advantages, to the pads -ceramics of hybrid circuits, or to the ceramic bases of encapsulated integrated circuits in DIL boxes for example, as well as any other known encapsulation using materials such as ceramics.
La figure 5 représente un second exemple de réali- sation selon le premier type du dispositif de pro¬ tection de l'invention.FIG. 5 represents a second exemplary embodiment according to the first type of the protection device of the invention.
Le premier type de protection, comme il a été pré¬ cédemment exposé, agit selon l'épaisseur de la varis¬ tance. Dans l'exemple de la figure 4, la varistance est déposée sous forme d'un anneau, présentant par conséquent une bande continue, et cette bande de varistance est surmontée par une bande continue de métallisation qui écoule les surtensions à la masse. Dans ce seond exemple de réalisation, la varistance est réalisée sous forme d'un plot, déposé sur chaque connexion externe, et la métallisation supérieure ou électrode d'écoulement à la masse, est une métalli¬ sation prise en excroissance sur la connexion voisine. Ainsi selon ce second type toutes les connexions agis- sent en série.The first type of protection, as previously described, acts according to the thickness of the varis¬ tance. In the example of FIG. 4, the varistor is deposited in the form of a ring, consequently having a continuous band, and this varistor band is surmounted by a continuous metallization band which drains the overvoltages to ground. In this second embodiment, the varistor is produced in the form of a stud, deposited on each external connection, and the upper metallization or ground flow electrode, is a metalli¬ tion taken out on the neighboring connection. According to this second type, all the connections act in series.
Comme dans- les cas de figures précédents, seul un fragment de substrat 3 a été représenté, ce frag¬ ment supportant quelques connexions extérieures telles que 4 et 5. Sur chaque connexion extérieure est déposé un plot de varistance tel que 12 sur la connexion 4 et 13 sur la connexion 5. Ce plot a des dimensions réduites mais il est important au cours du dépôt qu'il recouvre partiellement au moins un côté' de la conne¬ xion en vue d'éviter les court-circuits entre l'élec- trode supérieure '16 avec la connexion 4, oul7 avec la connexion 5. Ce dépôt latéral tel que 14 et 15 n'a pas de rôle de varistance mais un rôle d'isolant. Lorsque le dépôt des plots 12 et 13 a été effectué, une seconde métallisation localisée telle que 16 et 17 recouvre le plot de varistance 12 ou 13 et est en contact ohmique avec la connexion voisine de la connexion qui supporte le plot : . ainsi si l'on considère la connexion 4 L'électrode 16 est en con- tact ohmique avec la connexion 5 et l'électrode 17 au dessus de la connexion 5 est en contact ohmique avec la connexion voisine, et ainsi de suite. D'ans ce type de protection intégrée, la varistance agit donc selon l'épaisseur de la couche de varistance entre deux parties métalliques qui constituent les bornes de la aristance.As in the cases of the preceding figures, only a fragment of substrate 3 has been represented, this fragment supporting a few external connections such as 4 and 5. On each external connection is deposited a varistor block such as 12 on connection 4 and 13 on connection 5. This stud has reduced dimensions but it is important during deposition that it partially covers at least one side ' of the connection in order to avoid short circuits between the elect trode upper '16 with the connection 4, oul7 with the connection 5. This lateral deposition such as 14 and 15 has no role but a varistor insulator. When the plots 12 and 13 have been deposited, a second localized metallization such as 16 and 17 covers the varistor block 12 or 13 and is in ohmic contact with the connection close to the connection which supports the block:. thus if we consider the connection 4 The electrode 16 is in ohmic contact with the connection 5 and the electrode 17 above the connection 5 is in ohmic contact with the neighboring connection, and so on. In this type of integrated protection, the varistor therefore acts according to the thickness of the varistor layer between two metal parts which constitute the terminals of the aristor.
Sur la figure 5 n'ont été représentées que trois connexions externes, mais il est bien entendu que le dispositif de protection peut concerner soit une ou plusieurs connexions qui sont particulièrement expo¬ sées à des surtensions, soit la totalité des conne¬ xions externes.In FIG. 5, only three external connections have been shown, but it is understood that the protection device may concern either one or more connections which are particularly exposed to overvoltages, or all of the external connections.
La figure 6 représente un troisième exemple de réalisation du dispositif de protection selon 1 in- vention, selon le second type. Pour être homogène avec les figures précédentes, les mêmes indices de repère ont ' été conservés, et la figure 6 représente un fragment de substrat 3 supportant au moins deux connexions externes 4 et 5. * Cependant, dans ce type de réalisation, les. conne¬ xions externes, ' qu'elles soient réalisées dans une plaque métallique découpée, comme c'est le cas par exemple pour , les boîtiers DIL, ou qu'elles soient réalisées par sérigraphie d'une pâte à base de métal sur un substrat céramique, comme .c'est le cas pour les microboîtiers chip-carriers, sont toutes à l'ori¬ gine réunies par un pontet métallique 18. De façon à mettre en évidence cette structure à l'origine, la figure 6 est écorchée et représente dans sa partie gauche la structure des connexions avant le début des opérations destinées à mettre en place le disposi¬ tif de protection contre les surtensions, et, dans sa partie droite, le dispositif achevé. Ainsi donc, à l'origine, les connexions sont réunies par des. ponts métalliques 18 et ceux-ci sont coupés par tout procédé connu de l'homme de l'art, tel qu'une attaque chimique sous masque ou une découpe par faisceau laser, de façon à laisser subsister deux arches 9 du pont 18, ces arches ou plages de. métallisation 9 laissant entre elles un espace 10 qui correspond à l'épaisseur "t" de varistance voulue, en fonction de la composition du matériau, de ses caractéristiques et de la tension contre laquelle on cherche à se protéger. Après découpe des plages métalliques 18, la varistance 6 est déposée soit par sérigraphie, soit par pulvérisation et elle remplit les interval¬ les 10 entre les plages métalliques, formant égale¬ ment accessoirement mais cela n'est pas indispensable au fonctionnement du dispositif une . bande continue telle que décrite à l'occasion de la figure 2 ou de la figure 3.Figure 6 shows a third embodiment of the protection device according to one in- vention, according to the second type. To be consistent with the previous figures, the same reference signs have 'been retained, and Figure 6 shows a fragment 3 substrate supporting at least two external connections 4 and 5. * However, in this type of embodiment, the. external connections, 'that they are made in a cut metal plate, as is the case for example for DIL packages, or that they are produced by screen printing of a metal-based paste on a substrate ceramic, as is the case for chip-carrier micro-housings, are all originally joined by a metal bridge 18. In order to highlight this structure at the origin, FIG. 6 is cut away and represents in its part left the structure of the connections before the start of the operations intended to set up the device for protection against overvoltages, and, in its right part, the completed device. So, originally, the connections are joined by. metal bridges 18 and these are cut by any process known to those skilled in the art, such as a chemical attack under mask or a laser beam cutting, so as to leave two arches 9 of the bridge 18, these arches or beaches of . metallization 9 leaving between them a space 10 which corresponds to the thickness "t" of desired varistor, as a function of the composition of the material, of its characteristics and of the tension against which it is sought to protect itself. After cutting the metal areas 18, the varistor 6 is deposited either by screen printing or by spraying and it fills the intervals 10 between the metal areas, also forming incidentally but this is not essential for the operation of the device one. continuous strip as described on the occasion of FIG. 2 or of FIG. 3.
Dans ce second type de protection contre les surtensions la varistance agit donc transversalement entre deux connexions.. De même que dans les cas précédents, le dispositif de protection peut être appliqué entre -une connexion particulièrement soumise à des surtensions extérieures, entre plusieurs ou entre la totalité-. des connexions, l'une d'elles au moins étant mise à la masse.In this second type of overvoltage protection, the varistor therefore acts transversely between two connections. As in the previous cases, the protection device can be applied between a connection particularly subjected to external overvoltages, between several or between the all-. connections, at least one of which is grounded.
La figure 7 représente un quatrième exemple de réalisation du dispositif de protection contre les surtensions, dans le cas d'un boîtier métallique, tels que par exemple les boîtiers T03 d' encapsulation de semiconducteur discret.FIG. 7 represents a fourth embodiment of the device for protection against overvoltages, in the case of a metal case, such as for example the boxes T03 for encapsulation of discrete semiconductor.
-BU EAU Sur cette figure 7 est représenté en 19 un frag¬ ment de l'embase métallique d'un boîtier : la conne¬ xion d'accès extérieur 4 est immobilisée et supportée sur cette embase par l'intermédiaire d'une perle de verre 3, qui remplit, la fonction du substrat isolant décrite à l'occasion des. exemples précédents. Si le semiconducteur encapsulé dans ce boîtier métallique est sensible et peut être détruit par des surtensions, l'invention prévoit de déposer une pellicule ou une goutte de varistance 20 au pied de la connexion 4, et sur l'embase 19.- Dans ce cas, l'action de la varis¬ tance s'exerce selon la distance 21 séparant le pour¬ tour de la connexion 4 au bord du trou dans l'embase 19 qui supporte la perle de verre 3. La protection contre la surtension agit donc selon le second type, c'est-à-dire transversalement. Etant donné, d'une part, que cette distance 21 est supérieure à celle qui sépare une connexion de son électrode de mise à la masse dans les exemples précédemment décrits, mais que d'autre part la tension de basculement de la va¬ ristance 20 est fonction de la tension .intergranulaire, il suffit d'augmenter la granulométrie du matériau de départ, de façon à assurer la protection à travers une longueur 21 de varistance correspondant à un nom- bre précis de grains de matériau.- WATER BU In this FIG. 7 is shown in 19 a fragment of the metal base of a housing: the external access connection 4 is immobilized and supported on this base by means of a glass bead 3, which fulfills the function of the insulating substrate described on the occasion of. previous examples. If the semiconductor encapsulated in this metal case is sensitive and can be destroyed by overvoltages, the invention provides for depositing a film or a drop of varistor 20 at the foot of the connection 4, and on the base 19.- In this case , the action of the varis¬ tance is exerted according to the distance 21 separating the per¬ turn of the connection 4 at the edge of the hole in the base 19 which supports the glass bead 3. The overvoltage protection therefore acts according to the second type, that is to say transversely. Given, on the one hand, that this distance 21 is greater than that which separates a connection from its grounding electrode in the examples described above, but that on the other hand the switching voltage of the vaistor 20 is a function of the intergranular tension, it suffices to increase the particle size of the starting material, so as to provide protection through a length 21 of varistor corresponding to a precise number of grains of material.
L'invention a été décrite, en l'appuyant sur quel- quelques exemples de réalisation , mais elle recouvre toutes les variantes que l'homme de l'art trouvera évident d'y apporter sur boîtiers ou substrats cérarni- ques ou plastiques, la cuisson de "la varistance étant, dans ce dernier cas, réalisée avant l'enrobage plas¬ tique .The invention has been described, based on a few examples of embodiments, but it covers all the variants that a person skilled in the art will find it obvious to make thereon on ceramic or plastic housings or substrates, the cooking of the " varistor being, in the latter case, carried out before the plastic coating.
Elle est précisée par les revendications ci-après.It is specified by the claims below.
- UREA - UREA

Claims

REVENDICATION CLAIM
1. Dispositif de protection intégré contre les surtensions d'un circuit électronique monté sur un support (3) en matériau isolant, et muni d'au moins une connexion (4) d'accès extérieur solidaire du sup- port (3), ce dispositif de protection étant caracté¬ risé en ce qu'il est constitué par une résistance à effet non linéaire (6), dite varistance, à basse ten¬ sion de seuil (V ) , dont une première borne est en o contact ohmique avec la connexion {4) d'accès exté— rieur et dont l'autre borne est en contact ohmique avec une . électrode métallique (7) de mise à la masse, l'épaisseur du* matériau de varistance (6) comprise entre la connexion (4) et l'électrode (7) de mise à la masse étant telle que "pour toute surtension (U) dangereuse pour le circuit électronique et supérieure à la tension de seuil (Vo) de la varistance (6), celle- ci franchit son seuil de basculement et établit une liaison peu résistive entre la connexion (4) et la masse (7) . 1. Integrated protection device against overvoltages of an electronic circuit mounted on a support (3) made of insulating material, and provided with at least one connection (4) of external access secured to the support (3), protection device being caracté¬ ized in that it is constituted by a resistor with non-linear effect (6), called varistor, with low threshold voltage (V), a first terminal of which is in ohmic contact with the connection (4) for external access and the other terminal of which is in ohmic contact with one. metal grounding electrode (7), the thickness of the * varistor material (6) between the connection (4) and the grounding electrode (7) being such that " for any overvoltage (U ) dangerous for the electronic circuit and higher than the threshold voltage (Vo) of the varistor (6), the latter crosses its tilting threshold and establishes a somewhat resistive connection between the connection (4) and earth (7).
2. Dispositif de protection selon la revendica¬ tion 1, caractérisé en ce que, le circuit étant monté sur un support (3) muni d'une pluralité de connexions (4, 5) d'accès extérieur, la varistance (6) est dé¬ posée sur le support (3) et sur les connexions (4, 5) d'accès extérieur sous forme' d'un ruban en anneau qui réunit entre elles toutes les connexions exté¬ rieures. * 2. Protection device according to claim 1, characterized in that, the circuit being mounted on a support (3) provided with a plurality of connections (4, 5) for external access, the varistor (6) is placed on the support (3) and on the external access connections (4, 5) in the form of a ring ribbon which joins together all the external connections. *
3. Dispositif de protection selon la revendication 2 caractérisé en ce que l'électrode métallique (7) de mise à la masse est constituée par une métallisa¬ tion déposée sur la face "libre de l'anneau de varis¬ tance (6), cette métallisation étant réunie électri-3. Protection device according to claim 2, characterized in that the metal electrode (7) for grounding is constituted by a metallization deposited on the " free " face of the varis¬ tance ring (6), this metallization being electrically combined
Figure imgf000018_0001
quement (11) à au moins une connexion extérieure de mise à la masse.
Figure imgf000018_0001
(11) at least one external earth connection.
4. Dispositif de protection selon la revendication 1, caractérisé en ce que, le circuit étant monté sur un support (3) muni d'une pluralité de connexions, (4, 5) d'accès extérieur, celles-ci sont munies de plages (9) distantes entre elles d'un intervalle (10) à l'intérieur duquel la varistance (6) est déposée sur le support (3) , la mise à la masse d'une surten- sion sur une première connexion (4) d'accès extérieur étant assurée- par au moins une -seconde connexion (5) d'accès extérieur.4. Protection device according to claim 1, characterized in that, the circuit being mounted on a support (3) provided with a plurality of connections, (4, 5) of external access, these are provided with pads (9) distant from each other by an interval (10) within which the varistor (6) is deposited on the support (3), the grounding of a surge on a first connection (4) of external access being ensured by at least one second connection (5) of external access.
5.' Dispositif de protection selon la revendication 1, caractérisé en ce que la varistance est déposée sur une première connexion (4) d'accès extérieur sous forme, d'un dépôt localisé (12) , qui recouvre' en (14) au moins un flanc de la dite connexion (4) et en ce que la métallisation (16) de mise à la masse est dépo¬ sée sur la varistance (12 et 14) et sur le support (3) et est électriquement réunie à une seconde conne¬ xion (5) d'accès extérieur.5. ' Protection device according to claim 1, characterized in that the varistor is deposited on a first connection (4) of external access in the form of a localized deposit (12), which covers' at (14) at at least one side of said connection (4) and in that the grounding metallization (16) is deposed on the varistor (12 and 14) and on the support (3) and is electrically joined at one second external access connection (5).
6. Dispositif de protection selon la revendication 1, caractérisé en ce que la varistance (6 ou 12) et l'électrode métallique (7 ou 16) sont déposées sous forme de pâtes pour sérigraphie.6. Protective device according to claim 1, characterized in that the varistor (6 or 12) and the metal electrode (7 or 16) are deposited in the form of pastes for screen printing.
7. Dispositif de protection selon la revendicatio 1, caractérisé en ce que la varistance (6 ou 12) et l'électrode métallique (7 ou 16) de mise à la masse sont déposées sous . forme solide, par pulvérisation cathodique ou projection plasma. 7. Protective device according to claim 1, characterized in that the varistor (6 or 12) and the metal electrode (7 or 16) for grounding are deposited under. solid form, by sputtering or plasma spraying.
8. Dispositif de protection selon la revendication8. Protective device according to claim
1, caractérisé en ce que la composition et la granulo- métrie du matériau de la varistance (6) sont choisies pour que ladite varistance ait une tension de seuil1, characterized in that the composition and the particle size of the varistor material (6) are chosen so that said varistor has a threshold voltage
(Vo) supérieure de quelques volts à la tension de service normal du circuit électronique, et ait un seuil de basculement brutal.(Vo) a few volts higher than the normal operating voltage of the electronic circuit, and has a sudden tilting threshold.
Figure imgf000020_0001
Figure imgf000020_0001
PCT/FR1982/000134 1981-09-14 1982-08-13 Integrated protection device against overvoltages in an electronic circuit and electronic circuit protected by such device WO1983001153A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8117293A FR2513032B1 (en) 1981-09-14 1981-09-14 INTEGRATED PROTECTION AGAINST OVERVOLTAGES OF AN ELECTRONIC CIRCUIT, AND ELECTRONIC CIRCUIT PROTECTED BY THIS DEVICE
FR81/17293810914 1981-09-14

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Publication Number Publication Date
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FR (1) FR2513032B1 (en)
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EP0269225A2 (en) * 1986-11-26 1988-06-01 Energy Conversion Devices, Inc. Thin film electrical devices with amorphous carbon electrodes and method of making same
EP0269224A2 (en) * 1986-11-26 1988-06-01 Energy Conversion Devices, Inc. Thin film overvoltage protection device
EP0431586A2 (en) * 1989-12-07 1991-06-12 Kabushiki Kaisha Toshiba High-power semiconductor device
WO1996041356A2 (en) * 1995-06-07 1996-12-19 Littelfuse, Inc. Method and apparatus for a surface-mountable device for protection against electrostatic damage to electronic components
US5943764A (en) * 1994-05-27 1999-08-31 Littelfuse, Inc. Method of manufacturing a surface-mounted fuse device
US5974661A (en) * 1994-05-27 1999-11-02 Littelfuse, Inc. Method of manufacturing a surface-mountable device for protection against electrostatic damage to electronic components
CN102754204A (en) * 2009-12-17 2012-10-24 Abb技术有限公司 Power electronic module with non-linear resistive field grading and method for its manufacturing

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EP0171642B1 (en) * 1984-07-31 1988-05-18 Siemens Aktiengesellschaft Chip varistor for use in printed circits, and method of producing it
FR2590421A1 (en) * 1985-11-15 1987-05-22 Thomson Csf Device for protection from lightning by fusible and screen-printed resistor, method of manufacture and application to computers on board aircraft
EP0269775A1 (en) * 1986-12-02 1988-06-08 Thomson-Csf Protection device against lightning by means of a fusible resistance made by screening, production method and use in board calculators in aircraft
EP1494284A1 (en) * 2003-06-30 2005-01-05 Freescale Semiconductor, Inc. Overvoltage protection device

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EP0269225A2 (en) * 1986-11-26 1988-06-01 Energy Conversion Devices, Inc. Thin film electrical devices with amorphous carbon electrodes and method of making same
EP0269224A2 (en) * 1986-11-26 1988-06-01 Energy Conversion Devices, Inc. Thin film overvoltage protection device
EP0269225A3 (en) * 1986-11-26 1989-10-11 Energy Conversion Devices, Inc. Thin film electrical devices with amorphous carbon electrodes and method of making same
EP0269224A3 (en) * 1986-11-26 1989-10-11 Energy Conversion Devices, Inc. Thin film overvoltage protection device
EP0431586A2 (en) * 1989-12-07 1991-06-12 Kabushiki Kaisha Toshiba High-power semiconductor device
EP0431586A3 (en) * 1989-12-07 1992-06-03 Kabushiki Kaisha Toshiba High-power semiconductor device
US5943764A (en) * 1994-05-27 1999-08-31 Littelfuse, Inc. Method of manufacturing a surface-mounted fuse device
US5974661A (en) * 1994-05-27 1999-11-02 Littelfuse, Inc. Method of manufacturing a surface-mountable device for protection against electrostatic damage to electronic components
US6023028A (en) * 1994-05-27 2000-02-08 Littelfuse, Inc. Surface-mountable device having a voltage variable polgmeric material for protection against electrostatic damage to electronic components
WO1996041356A2 (en) * 1995-06-07 1996-12-19 Littelfuse, Inc. Method and apparatus for a surface-mountable device for protection against electrostatic damage to electronic components
WO1996041356A3 (en) * 1995-06-07 1997-01-30 Littelfuse Inc Method and apparatus for a surface-mountable device for protection against electrostatic damage to electronic components
CN102754204A (en) * 2009-12-17 2012-10-24 Abb技术有限公司 Power electronic module with non-linear resistive field grading and method for its manufacturing

Also Published As

Publication number Publication date
FR2513032B1 (en) 1985-12-13
FR2513032A1 (en) 1983-03-18
EP0088081A1 (en) 1983-09-14

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