WO1984004628A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO1984004628A1
WO1984004628A1 PCT/JP1984/000243 JP8400243W WO8404628A1 WO 1984004628 A1 WO1984004628 A1 WO 1984004628A1 JP 8400243 W JP8400243 W JP 8400243W WO 8404628 A1 WO8404628 A1 WO 8404628A1
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WIPO (PCT)
Prior art keywords
layer
arsenic
oxide layer
hydrogen
semiconductor substrate
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PCT/JP1984/000243
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French (fr)
Japanese (ja)
Inventor
Hisao Hayashi
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Sony Corp
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Publication of WO1984004628A1 publication Critical patent/WO1984004628A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors with potential-jump barrier or surface barrier
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]

Definitions

  • the present invention relates to a semiconductor device, particularly for a passivation thereof.
  • a complementary M0S integrated circuit has a portion having a cross-sectional structure as shown in FIG. That is, the figure shows a so-called field portion between the MOS element of one channel and the M0S element of another channel adjacent to the MOS element.
  • a field insulating layer (4) is formed by sequentially laminating a Zuma CVD type silicon nitride layer (3).
  • (5) is, for example, an N-type semiconductor substrate,
  • (7) is one N-type diffusion region serving as the source or the drain. (8) configures the M0S element of another channel.
  • the P + channel diffusion area is one of the source or drain of a P-channel MOS transistor.
  • (9) and CO) are ⁇ electrodes that are in ohmic contact with the respective diffusion regions (7) and (8). Therefore, in this case, the field insulating layer (4) straddles the rectangular semiconductor substrate (5) and the rectangular island region (6).
  • the arsenic silicate glass layer (21 is used for lowering the leveling technology, and the plasma CVD type
  • the silicon nitride layer is used to prevent the A electrode from hitching and to prevent external impurities.
  • Hydrogen H in the 20 layer (3) diffuses through the arsenic silicate glass layer (2) and reaches the As transition layer. Then, hydrogen H bonds with oxygen 0 in the glass to form an O H group. As a result, As, which was present between the meshes in the force glass, can no longer bond with oxygen 0 and becomes ionized.
  • the present invention provides a semiconductor device which solves the above-described problem based on the generation of a positive charge.
  • the present invention is a semiconductor device in which an arsenic diffusion blocking layer is formed between an oxide layer on one main surface of a semiconductor substrate and an arsenic-containing layer on which hydrogen can diffuse.
  • FIG. 1 is a cross-sectional view of a field portion of a conventional complementary MOS integrated circuit
  • FIG. 2 is a cross-sectional view of a field portion of a complementary MOS integrated circuit showing one embodiment of the present invention. is there.
  • FIG. 2 shows an embodiment of the present invention, which is the same as FIG. 1 and shows the relationship between each MOS element in a complementary MOS integrated circuit. When applied to the field part.
  • parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted.
  • the N-type semiconductor substrate (5) and the P-type semiconductor substrate were placed on the main surface of the semiconductor substrate corresponding to the field between the complementary MOS elements.
  • the silicon oxide layer (1), the arsenic diffusion blocking layer (11), the arsenic silica glass layer (2), and the plasma CVD type A field insulating layer (12) is formed by laminating a silicon nitride layer (3).
  • the arsenic diffusion blocking layer ( ⁇ ) a plasma CVD type silicon nitride or CVD silicon nitride having a small diffusion coefficient of As may be used.
  • M 0 S preparative run-Shi Li co down gate of Soo data in particular S i 0 of As contained on by that gate insulation ⁇ two polycrystalline sheet Li Silicone with cone layer
  • the arsenic diffusion blocking layer described above is interposed between the gate insulating layer and the As-containing polycrystalline silicon layer.
  • the polycrystalline sheet re co down layer is diffused Sarezu the S i 0 2-layer Ru Goo gate insulating layer der. Positive charge even come hydrogen after therefore does not occur. For this reason, the surface level of the channel portion is stable, and fluctuations in the threshold voltage and the like are avoided.
  • the present invention was applied to the field insulating layer and the silicon gate portion.
  • the present invention forms an arsenic diffusion blocking layer between the oxide layer and the arsenic containing layer.
  • the arsenic diffusion blocking layer the above-mentioned plasma CVD type silicon nitride or CVD silicon nitride is used.
  • the arsenic-containing layer is, for example, As SCl (arsenic silicate glass) or As-doped polycrystalline silicon.
  • the diffusion of hydrogen is caused by the presence of hydrogen during the formation of a CVD film (Si 3 N 4 , amorphous silicon Si, etc.) on a hydrogen arsenic-containing layer. is there.
  • a hydrogen diffusion preventing layer for preventing diffusion of hydrogen may be provided on the arsenic-containing layer. In this case, since the hydrogen that contributes to the generation of the positive charge is not diffused into the arsenic-containing layer, the generation of the positive charge can be more reliably prevented.
  • the oxidation on the main surface of the semiconductor substrate is achieved.
  • an arsenic diffusion blocking layer between the material layer and the arsenic-containing layer where hydrogen can diffuse, As in the arsenic-containing layer diffuses into the oxide layer during annealing.
  • the generation of positive charges is prevented. Therefore, a highly reliable semiconductor device can be obtained.

Abstract

A semiconductor device is designed to solve the problem of the instability of the surface state of a semiconductor substrate below an oxide layer, based on the generation of a positive charge. According to the invention, an arsenic diffusion-blocking layer (11) is formed between an oxide layer (1) which is formed over one main surface of a semiconductor substrate and an arsenic-containing layer (2) which is formed over the oxide layer (1), and into which hydrogen is diffused in order to block the diffusion of the arsenic contained in the arsenic-containing layer (2) into the oxide layer (1) when annealing is effected, thereby preventing the generation of a positive charge. The invention is applicable to, for example, the field-insulating layer of a complementary MOS integrated circuit or the silicon gate portion of a MOS transistor.

Description

明 細 書  Specification
発明の名称 半導体装置  Title of the invention Semiconductor device
技術分野  Technical field
本発明は、 半導体装置特に そのパ ッ シ ベ ー シ ヨ ン用 The present invention relates to a semiconductor device, particularly for a passivation thereof.
, ,
絶縁層等の改良に 関す る。 .  It relates to improvement of insulation layers. .
背景技術  Background art
例えば相補形 M 0 S 集積回路 においては、 第 1 図 に 示す よ う な断面構造を有する個所があ る。 即ち、 同図 は一のチャ ン ネ ルの M O S 素子 と 之に隣接す る他のチ ヤ ン ネ ル の M 0 S 素子間の所謂 フ ィ — ル ド部分を示す も ので、 両素子間の フ ィ ー ル ド部分に対応する半導体 基体の主面上に、 酸化 シ リ コ ン （S i 02 ) 層（1)、 砒素 シ リ ケ 一 ト · カ ラ ス層（2)及び プ ラ ズマ C V D形窒化 シ リ コ ン層（3)を順次積層 し て成る フ ィ ー ル ド絶緣層（4)が形 成 され てい る。 なお、 （5)は例えば N形の半導体基体、For example, a complementary M0S integrated circuit has a portion having a cross-sectional structure as shown in FIG. That is, the figure shows a so-called field portion between the MOS element of one channel and the M0S element of another channel adjacent to the MOS element. on the main surface of the semiconductor substrate corresponding to the full i Lumpur head portion, oxidized Li co down (S i 0 2) layer (1), arsenic Li Ke one preparative Ka La scan layer (2) and up La A field insulating layer (4) is formed by sequentially laminating a Zuma CVD type silicon nitride layer (3). (5) is, for example, an N-type semiconductor substrate,
(6)は一のチ ャ ン ネ ルの M 0 S 素子の所言胃 N チャ ン ネ ル (6) is the statement of the M0S element of one channel.
M O S ト ラ ン ジ ス タ を構成する P 形の島領域であ り 、This is a P-type island region that constitutes a MOS transistor.
(7)はその ソ ー ス又は ド レ イ ン と な る一方の N 形拡散 領域であ る。 （8)は他の チ ャ ン ネ ルの M 0 S 素子を構成 (7) is one N-type diffusion region serving as the source or the drain. (8) configures the M0S element of another channel.
2 0 する所詣 P チ ャ ン ネ ル M O S ト ラ ン ジ ス タ の ソ ー ス 又 は ド レ イ ン と な る一方の P+ 形拡散領域 であ る。 ま た、 (9)及び C O)は夫 々 の拡散領域（7)及び（8)にォー ミ ッ ク 接 された Αβ 電極であ る。 従って こ の場合 フ ィ ー ル ド絶 緣層（4)は Ν形の半導体基体（5) と Ρ 形の島領域（6)に跨つ  The P + channel diffusion area is one of the source or drain of a P-channel MOS transistor. (9) and CO) are Αβ electrodes that are in ohmic contact with the respective diffusion regions (7) and (8). Therefore, in this case, the field insulating layer (4) straddles the rectangular semiconductor substrate (5) and the rectangular island region (6).
OMPI WIPO WAT10 て形成され る。 こ の フ ィ ー ル ド絶緣層（4)において、 砒 素 シ リ ケ一 ト · ガ ラ ス層（21は平担化技術の低温化で使 われ る も のであ り 、 プ ラ ズマ C V D形窒化 シ リ コ ン層 ）は A£ 電極の ヒ π ッ ク防止及び外部不純物防止のた めに用いら れてい る。 OMPI WIPO WAT10 Formed. In this field insulating layer (4), the arsenic silicate glass layer (21 is used for lowering the leveling technology, and the plasma CVD type The silicon nitride layer) is used to prevent the A electrode from hitching and to prevent external impurities.
と ころが、 こ のよ う な フ ィ ー ル ド絶緣層（4)の構造に おいては、 低温 （ 例えば 400 °C ) のァニ ー ル処理を施 すと、 絶緣層中 に正電荷が発生 し、 フ ィ ー ル ド絶緣層 (4)下の P 形島領域（6)の表面が N形に反転し、 リ ー ク 電 i o 流が増大する と い う 現象が生 じた。 こ の正電荷の発生 は、 実験の結果砒素シ リ ケ一 ト · ガ ラ ス層（2! と酸化 シ リ コ ン層（1)の界面 に起 り 、 また プ ラ ズマ C V D形窒化 シ リ コ ン層（3)中の水素が関与し てい る こ とが判明 した。 即ち、 砒素 シ リ ケ一 ト · ガ ラ ス層（2)を流動化するため にァニ ー ル し た時、 As が酸化 シ リ コ ン層（1)中 に拡散 し、 砒素 シ リ ケ一 ト · ガ ラ ス層（2! と 酸化 シ リ コ ン層（1) の界面で As の濃度分布 を も った所謂 As 遷移層が形成 され る。 こ の後、 プ ラ ズマ C V D に よ る窒化 シ リ コ ン 層（3)を被着 し 40 0 °Cのァ二一ルを行 う と、 窒化 シ リ コ However, in such a structure of the field insulating layer (4), if annealing at a low temperature (for example, 400 ° C.) is performed, a positive charge is formed in the insulating layer. Occurred, the surface of the P-type island region (6) under the field insulating layer (4) was inverted to N-type, and a phenomenon occurred in which leak current and io current increased. As a result of the experiment, this positive charge was generated at the interface between the arsenic silicon glass layer (2! And the silicon oxide layer (1), and the plasma CVD type silicon nitride). It was found that the hydrogen in the cone layer (3) was involved, that is, when the arsenic silica glass layer (2) was annealed for fluidization, As diffuses into the silicon oxide layer (1) and has an As concentration distribution at the interface between the arsenic silicon / glass layer (2!) And the silicon oxide layer (1). After that, a so-called As transition layer is formed.After that, a silicon nitride layer (3) is deposited by plasma CVD, and the silicon nitride layer is formed at 400 ° C. Rico
2 0 ン層（3)中の水素 Hが砒素 シ リ ケ一 ト · カ ラ ス層（2)を拡 散して As 遷移層へ達する。 そ こ で水素 Hはガ ラ ス中 で酸素 0 と 結合 し O H基を形成する。 こ れ に よ つて 力' ラ ス 中の網 目 間 に入っていた As は酸素 0 と の結合が で きな く な り 、 イ オ ン化 して存在する よ う にな る。 こ Hydrogen H in the 20 layer (3) diffuses through the arsenic silicate glass layer (2) and reaches the As transition layer. Then, hydrogen H bonds with oxygen 0 in the glass to form an O H group. As a result, As, which was present between the meshes in the force glass, can no longer bond with oxygen 0 and becomes ionized. This
O PI れが正電荷の発生 と な る。 O PI This results in the generation of a positive charge.
こ の メ カ ニ ズ ム に よ れば、 正電荷の発生はその他、 例えば S i 02 に よ る ゲー ト 絶縁膜上に As ドー ブの多結 晶 シ リ コ ン層を形成 し た よ う な所謂 シ リ コ ン ゲー ト 部 分にお いて も起 り 得る も の であ り 、 こ の と き には閾値 電圧の変動等が起 る。 By the this main crab's arm lever, the generation of positive charges others such to form a multi-crystal Shi Li co down layer of As dough blanking to S i 0 2 by that gate insulating film on the Such a phenomenon can also occur in the so-called silicon gate portion, and in this case, a fluctuation in the threshold voltage occurs.
本発明は、 正電荷の発生に基づ く 上述の問題点を解 消 し た半導体装置を提供する も のであ る。  The present invention provides a semiconductor device which solves the above-described problem based on the generation of a positive charge.
発明の開示 Disclosure of the invention
本発明は、 半導体基体の一主面上にあ る酸化物層 と 、 その上の水素が拡散 され得る砒素含有層 と の間 に砒素 拡散阻止層を形成 し て成 る半導体装置であ る。  The present invention is a semiconductor device in which an arsenic diffusion blocking layer is formed between an oxide layer on one main surface of a semiconductor substrate and an arsenic-containing layer on which hydrogen can diffuse.
こ の構成に よ れば、 砒素含有層か ら酸化物層への A s の拡散が阻止され、 正電荷の発生がな く な る。 従って 酸化物層下の半導体基体の表面進位が安定 し、 リ ー ク 電流の増大あ る いは閾値電圧の変動等が回避 される。 図面の簡単な説明  According to this configuration, the diffusion of As from the arsenic-containing layer to the oxide layer is prevented, and the generation of positive charges is eliminated. Therefore, the surface orientation of the semiconductor substrate under the oxide layer is stabilized, and an increase in leak current or a change in threshold voltage is avoided. BRIEF DESCRIPTION OF THE FIGURES
第 1 図は従来の相補形 M O S 集積回路 の フ ィ ー ル ド 部分の断面図、 第 2 図は本発明の一実施例を示す相補 形 M O S 集積回路の フ ィ ー ル ド部分の断面図 であ る。  FIG. 1 is a cross-sectional view of a field portion of a conventional complementary MOS integrated circuit, and FIG. 2 is a cross-sectional view of a field portion of a complementary MOS integrated circuit showing one embodiment of the present invention. is there.
発明を実施するための最良の形態 BEST MODE FOR CARRYING OUT THE INVENTION
以下、 本発明の実施例 について説明する。  Hereinafter, embodiments of the present invention will be described.
第 2 図は本発明の一実施例であ り 、 こ れは第 1 図 と 同様に相補形 M O S 集積回路 にお け る各 M O S 素子間 の フ ィ ー ル ド部分 に適用した場合であ る。 同図中、 第 1 図 と 対応する部分には同一符号を付 し て重複説明を省略 する。 FIG. 2 shows an embodiment of the present invention, which is the same as FIG. 1 and shows the relationship between each MOS element in a complementary MOS integrated circuit. When applied to the field part. In the figure, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted.
本例にお いては、 第 2 図 に示すよ う に相補形 M O S 素子間の フ ィ 一ル ド部分に対応する半導体基体の主面 上に その N形の半導体基体（5)及び P 形の島領域（6)に跨 る如 く 、 順次酸化 シ リ コ ン層（1)、 砒素拡散阻止層 (11)、 砒素 シ リ ケ一 ト · ガ ラ ス層（2)及びプ ラ ズマ C V D 形窒 化 シ リ コ ン層（3)を積層 し て成る フ ィ ー ル ド絶緣層 (12)を 形成する。 砒素拡散阻止層（ίΰ と し ては As の拡散係数 の小さい プ ラ ズマ C V D 形窒化 シ リ コ ン又は C V D窒化 シ リ コ ンな どを用い得る。  In this example, as shown in FIG. 2, the N-type semiconductor substrate (5) and the P-type semiconductor substrate were placed on the main surface of the semiconductor substrate corresponding to the field between the complementary MOS elements. The silicon oxide layer (1), the arsenic diffusion blocking layer (11), the arsenic silica glass layer (2), and the plasma CVD type A field insulating layer (12) is formed by laminating a silicon nitride layer (3). As the arsenic diffusion blocking layer (ίΰ), a plasma CVD type silicon nitride or CVD silicon nitride having a small diffusion coefficient of As may be used.
こ の よ う な フ ィ ー ル ド絶縁層 (12)の構成に よれば、 砒 素 シ リ ケ ー ト · ガ ラ ス層（2)を ァ ニ ー ル し た と き に、 そ の As は砒素拡散阻止層（LI)に よ ってはば まれ酸化 シ リ コ ン層（1)側に拡散 されない。 こ のため に、 As 遷移層 が作 られないので、 以後、 プ ラ ズマ C V D に よ る窒化 シ リ コ ン層（3)中の水素が来て も正電荷の発生が起らな い。 従って、 P 形島領域（6)の表面 には反転層が形成さ れず、 リ ー ク 電流の増大が阻止 され、 信頼性の高い相 補形 M 0 S 集積回路が得られ る。  According to such a structure of the field insulating layer (12), when the arsenic silicate glass layer (2) is annealed, its As Is spread by the arsenic diffusion blocking layer (LI) and is not diffused to the silicon oxide layer (1) side. As a result, an As transition layer is not formed, and no positive charge is generated even if hydrogen in the silicon nitride layer (3) due to the plasma CVD subsequently comes. Therefore, no inversion layer is formed on the surface of the P-type island region (6), an increase in leak current is prevented, and a highly reliable complementary MOS integrated circuit can be obtained.
本発明の他の実施例 と し ては、 M 0 S ト ラ ン ジス タ の シ リ コ ン ゲー ト 部、 特に S i 02 に よ る ゲー ト 絶緣層 上に As 含有の多結晶 シ リ コ ン層を有する シ リ コ ン ゲ As the other embodiments of the present invention, M 0 S preparative run-Shi Li co down gate of Soo data, in particular S i 0 of As contained on by that gate insulation緣層two polycrystalline sheet Li Silicone with cone layer
、' — ト 部に適用 でき る。 即ち、 こ の場合には、 ゲー ト 絶 緣層 と As 含有の多結晶 シ リ コ ン 層間 に'上述の砒素拡 散阻止層を介在 させ る。 こ の構成では、 多結晶 シ リ コ ン層の As がグー ト 絶縁層であ る S i 02 層 に拡散 されず. 従って後に水素が入って来て も 正電荷は発生 し ない。 こ のため、 チ ャ ン ネ ル部の表面 ¾位は安定 し、 閾値電 圧の変動等.が回避され る。 , ' — Applicable to G That is, in this case, the arsenic diffusion blocking layer described above is interposed between the gate insulating layer and the As-containing polycrystalline silicon layer. In this configuration, As the polycrystalline sheet re co down layer is diffused Sarezu the S i 0 2-layer Ru Goo gate insulating layer der. Positive charge even come hydrogen after therefore does not occur. For this reason, the surface level of the channel portion is stable, and fluctuations in the threshold voltage and the like are avoided.
尚、 上例ではフ ィ ー ル ド絶縁層、 シ リ コ ン ゲー ト 部 に本発明を適用 し たが、 その他構成上、 半導体基体の 主面上に酸化物層及び水素が拡散 され得る砒素含有層 を有 し た積層構造に適用 でき る も の で、 本発明ではそ の酸化物層 と 砒素含有層間 に砒素拡散阻止層を形成す る も の であ る。 砒素拡散阻止層 と し ては前記 し たブ ラ ズマ C V D形窒化 シ リ コ ン又は C V D 窒化 シ リ コ ンな ど を用い う る。 砒素含有層 と し ては As SCl ( 砒素 シ リ ケ ― ト ' ガ ラ ス ） 又は As ド ー ブ多結晶 シ リ コ ン な どで あ る。 ま た、 水素の拡散 と し ては、 水素ァ ニ 一 ルゃ砒 素含有層上への C V D膜形成 （S i 3N4， ァモ ル フ ァ ス S i 等 ） 時の水素の存在であ る。 In the above example, the present invention was applied to the field insulating layer and the silicon gate portion. However, due to other configurations, the oxide layer and the arsenic in which hydrogen can be diffused on the main surface of the semiconductor substrate. Since the present invention can be applied to a laminated structure having a containing layer, the present invention forms an arsenic diffusion blocking layer between the oxide layer and the arsenic containing layer. As the arsenic diffusion blocking layer, the above-mentioned plasma CVD type silicon nitride or CVD silicon nitride is used. The arsenic-containing layer is, for example, As SCl (arsenic silicate glass) or As-doped polycrystalline silicon. In addition, the diffusion of hydrogen is caused by the presence of hydrogen during the formation of a CVD film (Si 3 N 4 , amorphous silicon Si, etc.) on a hydrogen arsenic-containing layer. is there.
なお、 ま た、 砒素含有層上に水素の拡散を阻止する ための水素拡散阻止層を設けて も よ い。 こ の と き には 正電荷の発生 に荅与する水素が砒素含有層 中に拡散さ れな いので、 よ り 確実に正電荷の発生が阻止でき る。  In addition, a hydrogen diffusion preventing layer for preventing diffusion of hydrogen may be provided on the arsenic-containing layer. In this case, since the hydrogen that contributes to the generation of the positive charge is not diffused into the arsenic-containing layer, the generation of the positive charge can be more reliably prevented.
上述の本発明 に よ れば、 半導体基体の主面上の酸化 物層 と水素が拡散され得る砒素含有層 と の間 に砒素拡 散阻止層が設け られ る こ と に よ って、 ァ ニ ー ルの際に 砒素含有層の As が酸化物層 中 に拡散されず、 正電荷 の発生が阻止され る。 従って、 信頼性の高い半導体装 置が得られ る。 According to the above-described present invention, the oxidation on the main surface of the semiconductor substrate is achieved. By providing an arsenic diffusion blocking layer between the material layer and the arsenic-containing layer where hydrogen can diffuse, As in the arsenic-containing layer diffuses into the oxide layer during annealing. However, the generation of positive charges is prevented. Therefore, a highly reliable semiconductor device can be obtained.
OMPI WIPO■ ΛOMPI WIPO ■ Λ
' ΑΤΙΟ  'ΑΤΙΟ

Claims

請 求 の 範 囲 The scope of the claims
1. 半導体基体の一主面 にあ る酸化物層 と 、 該酸化物 層上に あ る砒素拡散阻止層 と、 該砒素拡散阻止層上 にあ り 、 水素が拡散され得 る砒素含有層を有する半 導体装置。  1. An oxide layer on one main surface of a semiconductor substrate, an arsenic diffusion blocking layer on the oxide layer, and an arsenic-containing layer on the arsenic diffusion blocking layer through which hydrogen can be diffused. Semiconductor device.
2. 半導体基体の一主面 に あ る酸化 シ リ コ ン層 と、 該 酸化 シ リ コ ン 層上 に あ る窒化 シ リ コ ン層カゝ らな る砒 素拡散阻止層 と、 該砒素拡散阻止層上にあ り 、 水素 が拡散 され得る砒素 シ リ ケ一 ト · ガ ラ ス層 を有す る o 半導体装置。  2. an arsenic diffusion blocking layer such as a silicon oxide layer on one principal surface of a semiconductor substrate, a silicon nitride layer on the silicon oxide layer, and an arsenic O A semiconductor device having an arsenic silicate glass layer on a diffusion blocking layer and through which hydrogen can be diffused.
3. 相補形 M O S 集積回路 において、 素子間 の フ ィ ー ル ド部分に対応する半導体基体の一主面 に あ る酸化 物層 と、 該酸化物層上に あ る砒素拡散阻止層 と、 該 砒素拡散阻止層上にあ り 、 水 素 が 拡 散 さ れ 得 る 砒素含有層 と を フ ィ ー ル ド絶緣膜 と す る相補形 M O S 集積回路。  3. In a complementary MOS integrated circuit, an oxide layer on one main surface of a semiconductor substrate corresponding to a field portion between elements; an arsenic diffusion blocking layer on the oxide layer; A complementary MOS integrated circuit in which the arsenic-containing layer on the arsenic diffusion blocking layer, into which hydrogen can be diffused, is used as a field insulating film.
RE O PI RE O PI
PCT/JP1984/000243 1983-05-16 1984-05-16 Semiconductor device WO1984004628A1 (en)

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US3700507A (en) * 1969-10-21 1972-10-24 Rca Corp Method of making complementary insulated gate field effect transistors
JPS4964382A (en) * 1972-06-30 1974-06-21

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US3660735A (en) * 1969-09-10 1972-05-02 Sprague Electric Co Complementary metal insulator silicon transistor pairs
US3700507A (en) * 1969-10-21 1972-10-24 Rca Corp Method of making complementary insulated gate field effect transistors
JPS4964382A (en) * 1972-06-30 1974-06-21

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