WO1986000425A1

WO1986000425A1 - Adhesion promoter and process for plasma oxide surfaces

Info

Publication number: WO1986000425A1
Application number: PCT/US1985/000871
Authority: WO
Inventors: John N. Helbert
Original assignee: Motorola, Inc.
Priority date: 1984-06-29
Filing date: 1985-05-10
Publication date: 1986-01-16

Abstract

Adhesion promoter and process for lithographically patterning plasma oxide layers. To promote the adhesion of a lithographic resist to the plasma oxide surface, the surface is first prepared by applying a double adhesion promoter. The adhesion promoter includes individually cured layers of vinyltrichlorosilane (VTS) and 3-chloropropyltrimethoxysilane (Cl(CH2)3Si(OMe)3). A resist layer applied to the adhesion promoter prepared surface can subsequently be used in an optical lithography process, electron beam lithography process, or a hybrid optical/electron beam lithography process.

Description

ADHESION PROMOTER AND PROCESS FOR PLASMA OXIDEJ; SURFACES

Background of the Invention

This invention relates generally to an adhesion promoter and process, and more specifically for an adhesion promoter and process for use in lithographically patterning a plasma oxide layer.

Integrated circuit lithographic design rules have been continuously driven to smaller dimensions as the demand for increased circuit packing density continues. Lines, spaces, and openings in the range of 1.0 micron or less may soon become routine. Fabrication of devices having this critical dimension level will require an extremely high resolution lithographic capability. The required high resolution lithography is probably beyond that achievable with conventional ultraviolet (UV) aligners which are generally incapable of submicron patterning. An alternative for the submicron patterning is electron beam (E-beam) lithography in which a resist layer is exposed by a scanning electron beam. Unfortunately, E-beam lithography is time-consuming and suffers from low wafer throughput.

One solution to the need for high resolution litho- graphy which is also capable of high wafer throughput is the use of an intralevel hybrid optical/E-beam lithography. For example, UV exposure is used to delineate all patterns greater than about one micron and E-beam exposure is used for all patterns less than or equal to about one micron. Intralevel hybrid lithography requires the selection of a resist which will function with reasonable latitude in response to two separate and very different radiation exposures. A number of resist materials, and especially some UV positive photoresists, also function well as E-beam resists. The resist must also be amenable to development in a single developing step after exposure to the two types of radiation. Developer selection and concentration must be optimized to allow for resist clearing for both sets of patterns in a unique and controllable time. Most photoresists require a much more concentrated developer for E-beam pattern development than for normal optical UV processing. This characteristic places severe restrictions on the adherence of the resist to the substrate to be patterned. The resist pattern with very fine geometries must remain adherent to the underlying substrate during long development periods in a concentrated developer solution. More specifically, when isolated islands of unexposed resist smaller than about 2-3 square microns are generated, the resulting adhesion requirements are far more stringent than those normally encountered in routine device production. Conventional adhesion promoters such as hexamethyldisilizane (HMDS) are totally inadequate in providing the required adhesion for images of either lithographic type (i.e., E-beam or UV) created by the hybrid lithography. The problem is exacerbated under the hybrid lithography development conditions.

While adhesion promoter systems have been developed for various applications of hybrid lithography, no adequate adhesion promoter has heretofore been developed for providing the required degree of adhesion of resist to plasma deposited oxides. Since plasma deposited oxides are becoming an important part of fine geometry device processing, a need existed for an adhesion promoter and process which would allow the lithographic patterning of such material. It is therefore an object of this invention to provide an improved adhesion promoter for use with plasma deposited oxides.

It is another object of this invention to provide a process for improving the adhesion of resist layers to plasma deposited oxide. It is yet another object of this invention to provide an improved process for the fabrication of semiconductor devices.

^~ Brief Summary of the Invention

The foregoing and other objects and advantages of the invention are achieved through the use of a double adhesion promoter as herein disclosed. In one embodiment of the invention plasma deposited oxides are patterned by applying to the surface of the oxide a first adhesion promoter comprising a vinyl substituted silane such as vinyltri- chlorosilane (VTS). After curing the first adhesion promoter a second adhesion promoter comprising a halogenated alkyl substituted alkoxy silane such as 3-chloropropyltrimethoxysilane (Cl(CH2)3Si(OMe)3) is applied and cured. A resist material is applied to the oxide surface having the first and second adhesion promoters thereon. The resist is exposed and- developed to provide an etch mask for the subsequent etching of the plasma deposited oxide.

Brief Description of the Drawings

FIG. 1 is a flowchart illustrating practice of the invention in accordance with one embodiment; and

FIG. 2 illustrates a device structure fabricated utilizing the adhesion promoter and process in accordance with the invention.

Detailed Description of Preferred Embodiments

Silicon oxides are used extensively in the processing of semiconductor devices. The silicon oxide is produced, for example, by thermal oxidation of a silicon substrate, chemical vapor deposition, plasma deposition, and the like. -Λ-

Although the oxides produced by these various processes are similar in many respects, they are also different in many other important respects. The plasma deposited silicon oxide, for example, differs from the other oxides in the adhesion properties between resist materials and the oxide surface. Methods which have been found successful in promoting the adhesion between resist and, for example, thermal silicon dioxide are totally unsuccessful in promoting the adhesion of resist to plasma deposited oxide.

FIG. 1 shows a flowchart, in accordance with one specific embodiment of the invention, wherein a double adhesion promoter is utilized to improve the adhesion of resist material to the surface of a plasma deposited oxide. The first adhesion promoter is selected from the vinyl > substituted silanes of the form

Cln

/

CH₂ = CH - Si 4R)m

where R CH₃ or C₂H₅ n 1 - 3 m 0 - 3 and n+M = 3.

A preferred first adhesion promoter is vinyltrichlorosilane (VTS). The second adhesion promoter is selected from the halogenated alkyl substituted alkoxy silanes of the form

X (CH₂) Si _TOR)₃

where p = 1 - 3

R = CH3 or C₂H₅ and X = Cl, Br, or I . A preferred second adhesion promoter is 3-chloropropyiltri- methoxysilane.

As shown in FIG. 1, a plasma oxide substrate to be patterned is provided. The plasma oxide can be deposited directly on a semiconductor wafer, overlying a polycrystalline silicon layer, overlying an organic or inorganic insulater layer, or the like. The surface of the plasma oxide layer is dehydration baked at about 200°C. in a nitrogen ambient to remove water from the surface. After cooling the substrate to room temperature, the surface is immediately flooded with a solution of a first adhesion promoter such as vinyltrichlorosilane and then spun to achieve a uniform application of the VTS on the oxide surface. The VTS is thermally cured by heating to about 90°C. for about ten minutes in a dry nitrogen ambient. After cooling to room temperature again, a second adhesion promoter is applied to the oxide surface by immediately flooding the surface with, for example, a diluted solution of 3-chloropropyltrimethoxysilane (Cl(CH₂)3Si(O e)3) .

The substrate is again spun to achieve a uniform layer of the second adhesion promoter, followed by a thermal cure at about 90°C. in a nitrogen ambient for about ten minutes. After cooling the substrate to room temperature again, the resist solution is applied to the adhesion promoted substrate by spin application to achieve a uniform resist layer and then prebaked in preparation for exposure. In the hybrid lithography process, selected portions of the resist layer are exposed by an electron beam and further portions are exposed by UV exposure. Following the hybrid, intralevel lithographic exposure to actinic radiation, the exposed portions of the resist are post baked and then developed in a single development cycle to leave a patterned etch mask adherent on the plasma oxide surface. The resist patterned substrate is etched by reactive ion etching, plasma etching, or wet chemical etching. The resist selected for the intralevel hybrid lithography process must have a useable response to two separate and very different radiation exposures. Although most E-beam specific resists have no useable response to the UV radiation used for optical exposure, a number of UV positive photoresists also function well as E-beam resists. Suitable resists include, for example. Polychrome (PC) 129 SF (now Allied P 2025) from Allied Chemical, AZ1470 from the American Hoechst Corporation and Hunt 204 from the Philip A. Hunt Chemical Corporation. The resist can be developed, for example, using D-100, AZ MF-312, and Hunt LSI developer for the PC129, AZ1470 and Hunt 204 resist, respectively.

FIG. 2 illustrates a portion of a semiconductor device 10 fabricated by a process in accordance with the invention. Device 10 is shown in an intermediate stage of fabrication and includes a semiconductor substrate 12, a layer 14 overlying the semiconductor substrate, and a patterned layer of plasma deposited oxide 16. Semiconductor substrate 12 may include diffused regions and the like forming device regions, transistors, diodes, and the like. Layer 14 can be, for example, an organic insulating material such as polyimide or photoresist, an inorganic insulator, polycrystalline silicon, or other material. Plasma deposited oxide 16 is formed on the surface of layer 14 in a uniform, integral layer by reacting a silicon bearing reactant and an oxygen bearing reactant in a plasma environment. The plasma deposited oxide layer may be used, for example, as an insulating layer or as a sacrificial layer forming an etch mask for layer 14. Layer 16 may have a thickness from a few tens of nanometers to several hundred nanometers. A pattern is formed in plasma deposited layer 16 as needed for the device being fabricated. The pattern may include, for example, a plurality of fine geometry openings 18, a plurality of. openings of larger size 20, islands 22 of small geometry, and islands 24 of larger geometry. Such a mixture of fine and large openings and islands requires a hybrid optical/electron beam lithography process. Especially in fabricating the fine geometry patterns, an adhesion promoter in accordance with the invention is required to ensure adequate adhesion between plasma deposited oxide layer 16 and the resist layer used for forming the pattern.

The following nonlimiting examples serve to further illustrate best modes contemplated by the inventor for practice of the invention.

Example I

Submicron CMOS devices were fabricated using the adhesion process in accordance with the invention including the following sequence. Wafers were provided which included a silicon substrate, a patterned layer of heavily doped polycrystalline silicon material overlying and insulatively spaced from the silicon substrate, and a plasma oxide layer having a thickness of about 150 nanometer covering the polycrystalline silicon material. The wafers were first dehydrated by baking at about 200°C. in a nitrogen ambient. The wafers were then cooled to room temperature and immediately flooded with a VTS solution comprising 2.5 cc of vinyltrichlorosilane in 50 cc of xylene. To produce a uniform film of VTS, the wafers were spun at 500 rpm for one second and then 5,000 for ten seconds. The VTS was thermally cured at about 90°C. for ten minutes in a nitrogen ambient. After again cooling to room temperature, a second adhesion promoter was applied by immediately flooding the wafers with diluted 3-chloropropyltrimethoxysilane comprised of 2.5 cc of (Cl(CH₂)3Si(OMe)3) in 50 cc of acetone. To achieve a uniform film of the adhesion promoter the wafers were spun at 500 rpm for one second and then 5,000 rpm for ten seconds. The adhesion promoter was then thermally cured by heating to about 90°C. for ten minutes in a nitrogen ambient. After again cooling the wafers to room tempera¬ ture, a resist solution comprising AZ 1470/AZ thinner in a ratio of 2:1 was applied and the wafers were spun for one second at 500 rpm followed by 15-30 seconds at 4,500 rpm. The adhesion promoted wafer surface was thus coated with about 500 nanometer of resist and was ready for hybrid exposure after a 90°C. prebake for 30 minutes in air. The resist was first selectively exposed to an electron beam at doses from about 200-500 microcoulombs/cm^ to expose patterns having a size from about 0.4-1.5 micrometer. After the E-beam exposure, larger patterns of resist were exposed through a patterned photomask using an ultraviolet exposure of about 40

The two exposures together provided a pattern of exposed and unexposed resist. Following the exposure, both E-beam and UV exposed regions were developed in a single development cycle consisting of 20 seconds immersion in a 1:1 AZ MF 312/water developer solution. The resist development was quenched by immersion into pure water followed by a spin/spray rinse with water and spin dry. After development, the resist patterned wafers were post-baked at about 90°C. for 30 minutes and then reactive-ion etched to etch the plasma deposited oxide and underlying polycrystalline silicon using the patterned resist layer as an etch mask. The resist material was then stripped from the substrate in an oxygen plasma to leave the pattern of plasma deposited oxide overlying polycrystalline silicon.

Example II.

In-process CMOS wafers were prepared up through the polycrystalline silicon layer deposition as in Example I. The polycrystalline silicon was covered with a one micron thick layer of Hunt 204 resist material which acted as a planarizing layer. The wafers were then vacuum baked at about 240°C. prior to the deposition of a plasma deposited oxide layer. The double adhesion promoter was applied as in Example 1 and Hunt 204 resist was flooded onto the wafers, and the wafers were spun at 500 rpm for one second, and then ten seconds at 4,500 rpm, followed by oven drying in air at about 90°C. for 30 minutes. The wafers were thus coated with an adhesion promoter and resist layer and were ready for lithographic exposure. The wafers were then exposed, developed, and etched as in Example II except that a 5:4 Hunt LSI/water developer solution was used.

Example III.

Wafers were processed as in Example II, except that a layer of PC 129 SF resist was applied over the adhesion promoter. The resist layer was exposed and developed as in Example I except that a 2:1 D-900/water developer solution was used and the plasma deposited oxide was etched by reactive-ion etching.

In further examples, conventional adhesion promoters were tried, but were not found effective in promoting the adhesion of photoresist to plasma deposited oxides in a degree sufficient to allow hybrid lithography processing. Double promoter processes such as sequential layers of vinyltrichlorosilane (VTS) followed by 1,3-divinyltetra- methyldisilizane which had been found effective in promoting the adhesion of resist to polycrystalline silicon were not effective in promoting the adhesion to plasma deposited oxides. Similarly, multiple application of known adhesion promoters such as HMDS were not successful in this application.

Thus, it is apparent that there has been provided, in accordance with the invention, an improved adhesion promoter and adhesion promotion process which fully meets the objects and advantages set forth above. Although the invention has been described and illustrated with reference to specific embodiments thereof, it is not intended that the invention be limited to these illustrative examples. Those skilled in the art will realize, after review of the foregoing detailed description, that variations and modifications differing from the illustrative examples are possible. For example, other spin speeds, cure times, development methods, device applications, and the like are possible. Further, other adhesion promoters in accordance with the general forms given above may be substituted for the specific examples given. It is intended to include within the spirit of the invention all such variations and modifications as fall within the scope of the appended claims.

Claims

Claims :

1. A process for lithographically patterning a plasma deposited oxide which comprises the steps of: providing a structure including a layer of plasma deposited oxide having a surface; applying to said surface a first adhesion promoter comprising vinyltrichlorosilane; heating said structure a first time to cure said first adhesion promoter; applying a second adhesion promoter comprising 3-chloropropyltrimethoxysilane; heating said structure a second time to cure said second adhesion promoter; applying resist to said surface having said first and second adhesion promoters thereon; exposing said resist to patterned radiation to form a pattern of exposed and unexposed resist; developing said resist to remove selected portions of said resist and to expose portions of said plasma deposited oxide; and etching said portions of plasma deposited oxide exposed through said resist.

2. The process of claim 1 wherein said step of applying resist comprises the step of applying a resist having exposure latitude to both electron beam and ultraviolet radiation.

3. The process of claim 2 wherein said step of exposing said resist comprises: exposing portions of said resist to an electron beam; and exposing other portions of said resist to ultraviolet radiation.

4. A process for lithographically patterning a plasma deposited oxide which comprises the steps of: providing a structure including a layer of plasma deposited oxide having a surface; applying to said surface a first adhesion promoter comprising vinyltrichlorosilane; applying a second adhesion promoter comprising 3-chloropropyltri- ethoxysilane; applying resist to said surface having said first and second adhesion promoters thereon; selectively exposing said resist to actinic radiation; developing said resist to form a pattern; and etching plasma deposited oxide exposed through said pattern. -

5. A process for promoting the adhesion between a lithographic resist material and a plasma deposited oxide to be patterned which comprises the steps of: applying to said oxide a first adhesion promoter comprising a solution of vinyltrichlorosilane; curing said first adhesion promoter; applying to said oxide a second adhesion promoter comprising 3-chloropropyltrimethoxysilane; and curing said second adhesion promoter.

6. A process for fabricating a semiconductor device including the patterning of a plasma deposited oxide used in the fabrication thereof which comprises t «he steps of: applying to said plasma deposited oxide a first adhesion promoter comprising vinyltrichlorosilane; curing said first adhesion promoter; applying a second adhesion promoter comprising 3-chloropropyltrimethoxysilane; curing said second adhesion promoter; and applying a resist to said plasma deposited oxide having said first and second adhesion promoters thereon.

7. An adhesion promoter comprising sequentially applied layers of vinyltrichlorosilane and 3-chloropropylthri- methoxysilane.

8. A process for patterning a plasma deposited oxide which comprises the steps of: providing a structure including a layer of plasma deposited oxide having a surface; applying to said surface a first adhesion promoter comprising Cl_n I

CH = CH - S i _τR)_m

where R = CH3 or C₂H₅, n = 1-3, m = 0-3 and n+m = 3; applying a second adhesion promoter comprising

X (CH₂) Si τOR)₃

where p = 1-3, R = CH3 or C₂H₅, and X = Cl, Br, or I; applying resist to said surface having said first and second adhesion promoters thereon; selectively exposing said resist to radiation to form a pattern of exposed and unexposed resist; developing said resist to remove selected portions of said resist; and etching said plasma deposited oxide exposed through said resist.

9. The process of claim 8 wherein said first adhesion promoter comprises vinyltrichlorosilane.

10. The process of claim 8 wherein said second adhesion promoter comprises 3-chloropropyltrimethoxysilane.