WO1986001660A1

WO1986001660A1 - Data compression and expansion system for the transfer or storage of data

Info

Publication number: WO1986001660A1
Application number: PCT/EP1985/000450
Authority: WO
Inventors: Peter Scheffler; Gerald Knabe
Original assignee: Dr. Gerald Knabe Gmbh
Priority date: 1984-09-06
Filing date: 1985-09-05
Publication date: 1986-03-13
Also published as: DE3432837A1; EP0193553A1; AU4774785A

Abstract

A data compression system (1) for the transfer of data has a register (15) for recording a unit of information from input data, a conversion system for transforming the data and an output (25) for the transformed data, as well as a control system (4, 5). In order to be able to undertake data compression without loss of information, the invention includes a comparator linked with the output of the register (15), and a counter (16) controlled by the comparator. The comparator (17) checks all the data of the information unit, and the control system (4, 5) is so designed that in the event of non-uniformity the content of the register (15) is fed to the output (25) and in the event of uniformity, a marker bit is produced and the counter (16) is advanced by one position, and the counter status is fed, together with the marker bit, to the output (25) if two successive information units do not agree. An associated data expansion system (2) contains the output data of the compressor (1), checks the marker bit and conveys an information unit which has no corresponding marker bit, to its output; on the other hand if a corresponding marker bit is present the information unit is fed into a counter and an information unit whose data are mutually identical and possess a predetermined value is fed to the output, with simultaneous advancing of the counter (16) each time by one position, as many times as is necessary until the counter status acquires a predetermined value.

Description

Data compression and data expansion device for transmitting or storing data

The invention relates to a data compression device for transmitting data with a register for receiving an information unit of input data, a converter device for converting the data and an output for the converted data, a controller, a comparator connected to the output of the register and one controlled by the latter Counter. The invention further relates to an associated data expansion device for transmitting data input via an input, with a register for receiving an information unit of data, a converter device for converting the data and an output for the converted data, and a controller, one connected to the input Counter is provided and the controller is designed such that an information unit input via the input, which has no corresponding identification bit, is fed to the output, and when a corresponding identification bit occurs, the information unit is added to the counter, and so often to the output, while simultaneously advancing an information unit is fed to the counter by one at a time until the counter reading assumes a predetermined count. Finally, the invention relates to a data transmission system with a data converter arranged on the input side, a data converter on the reception side and a transmission link therebetween, and a data transmission system with a data memory having an input and an output.

DE-OS 27 23 523 describes a method and a device for compressing and decompressing digital data to be stored. In the method described there, however, a complicated identification field in the data memory is necessary for compression or decompression.

A data compression device of the type described at the outset is known from European laid-open specification A 1-0012173, in which the resolution of an image to be transmitted is reduced in order to reduce storage or transmission costs. This also reduces the amount of information describing this changed image, so that the storage or transmission costs are reduced due to the smaller amount of data. However, it is not possible to reproduce the image with its original resolution at the receiving end or at the output of the memory.

The object of the invention is to provide a data compression device or an associated data expansion device and an associated data transmission system, with which it is possible not only to reduce the amount of data to be transmitted to save storage or transmission costs, but to change them so that the complete amount of data with its original information content can also be restored from the reduced amount of data at the exit. This object is achieved by a data compression device of the type described at the outset, which is characterized in accordance with the invention in that the comparator checks for the equality of all the data in the information unit, and the control is designed in such a way that the contents of the register are fed to the output and at if they are not equal Equality produces a characteristic bit and the counter is incremented by one, and the counter reading together with the characteristic bit is fed to the output if two successive information units do not match.

According to the invention, the data expansion device is characterized in that the data of the information unit are all identical to one another and that the information unit is supplied by the control when a characteristic bit occurs.

A data transmission system with a data converter arranged on the input side, a data converter on the receiving side and a transmission path between them is characterized in that the input-side converter is a data compression device of the type described above and the data converter is a data expansion device of the type described above.

The data transmission system with a data memory having an input and an output is characterized in that a data compression device of the type described above is provided on the input side and a data expansion device of the type described above is provided on the output side.

Further features and advantages of the invention result from the description of exemplary embodiments with reference to the figures. From the figures show:

1 shows a block diagram of a data compression device according to the invention;

2 shows a block diagram of a data expansion device according to the invention;

3 shows an exemplary embodiment of a circuit of the data compression device according to the invention;

4 shows an exemplary embodiment of a circuit of the data expansion device according to the invention;

5 shows a schematic representation of the data compression and data expansion process using an example; 6 shows a schematic illustration of an initial state of the data compression device according to the invention according to FIG. 3;

FIG. 7 shows a schematic illustration of the state of the data compression device according to the invention according to FIG. 3 in the first period according to FIG. 5;

FIG. 8 shows a schematic illustration of the state of the data compression device according to the invention according to FIG. 3 at the beginning of the second period according to FIG. 5;

FIG. 9 shows a schematic illustration of the state of the data compression device according to the invention according to FIG. 3 at the beginning of the third period according to FIG. 5; 10 shows a schematic representation of the state of the data compression device according to the invention according to FIG. 3 at the beginning of the fourth period in FIG. 5;

11 shows a schematic representation of the state of the data compression device according to the invention

Fig. 3 at the beginning of the fifth period of Fig. 5;

12 shows a schematic representation of the state of the data compression device according to the invention according to FIG. 3 at the beginning of the fifth period according to FIG. 5; 13 shows a schematic representation of the state of the data compression device according to the invention according to FIG. 3 at the beginning of the (5 + 126) th period according to FIG. 5;

14 shows a schematic representation of the state of the data compression device according to the invention

FIG. 3 at the beginning of the (5 + 126 + 1) th period according to FIG. 5;

15 shows a schematic representation of the state of the data compression device according to the invention according to FIG. 3 at the beginning of the (5 + 126 + 2) th period after

Fig. 5; and

Fig. 16 is a schematic representation of the state of the data compression device according to the invention according to Fig. 3 at the beginning of the (5 + 126 + 3) th period of

Example of FIG. 5;

17 shows a block diagram of a further embodiment of a data compressor device according to the invention; and

Fig. 18 block diagram of a further embodiment of a data expansion device according to the invention. FIG. 1 shows a block diagram of the data compressor 1 according to the invention and FIG. 2 shows a block diagram of the data expander 2 according to the invention. The data compressor 1 has four circuit blocks, namely a converter 3, a sequence controller 4, a control input part 5 and a memory 6. The data expander 2 has a comparable structure with likewise four circuit blocks, namely a converter 7, a sequence controller 8, a control input part 9 and a memory 10. The memory 10 can be designed as a memory different from the memory 6 or as the same memory as the memory 6. The data compressor 1 has a first input 11 for the data to be compressed and a second input 12 for the switch-on signal. The data expander 2 has an input 13 for the switch-on signal and an output 14 for the data to be output. The connection of the individual circuit blocks 3, 4, 5, 6 and 7, 8, 9, 10 with one another is shown schematically in FIGS. 1 and 2 and is intended in connection with the detailed description of the structure of the individual blocks in the following in connection with the 3 and 4 are shown.

3 shows the circuit of a data compressor 1 according to the invention. The converter 3 has a shift register 15, a counter 16 and a comparator 17. The shift register 15 is formed by two registers 74 LS 598 and has eight register locations with eight parallel outputs 18, which can be made high-resistance. For this purpose, the register has a first input 19. In addition, the shift register 15 is given a pull-up and pull-down option. The register 15 also has a second input 20 which forms the serial data input of the shift register 15 and forms an input to the first register location 21 which is connected to the first input 11 of the data compressor 1. The shift register 15 also has a clock input 22. Instead of via the serial data input 20, the input data can of course also be supplied via a parallel data input of the register 15. The counter 16 is formed by a component 74 AS 869 and has eight memory locations which can be loaded in parallel. For this purpose, the counter 16 has eight parallel inputs 23, of which the first seven are each connected to corresponding register locations of the shift register 15 via the outputs 18 in such a way that the first register location 21 is connected to a first memory location 24 of the counter 16 which points to the first register location 21 The following second register location is connected to the next storage location following the first storage location 24, etc. The eighth storage location is set to zero. The first seven memory locations of the counter 16 are routed in parallel to the outside and form a data output 25 of the converter 3. The counter 16 also has a charging input 26, counter input 27 and clock input 28, which is led outwards, and an output 29, which is also led out, for displaying the Counting minimum, in this case the counting value zero.

The comparator 17 is formed by a component 74 AS 866 and has nine comparator inputs 30 and an output 31 for the comparison result. The first eight of the inputs 30 are each connected to a corresponding output of the eight parallel outputs 18 of the shift register 15. The rest of the input of the comparator inputs 30 is connected to the output of an EXNOR element 32, one input of which is connected to the output of the second register position of the shift register 15 following the first register position 21 and the other input of which is connected to the sequencer 4 in a manner described later . The exit 31 is also led to the outside.

The output of the first register location 21 is also connected to the output of an open collector NAND element 33, the first input 34 of which is connected to the first input 19 of the shift register 15 is connected and led to the outside and the second input 35 is connected to the sequence control 4 in a manner to be described later.

The memory 6 has eight parallel data inputs 36, of which the first seven are each connected to one of the seven data outputs 25 of the counter 16. The eighth data input is connected to the sequential control system in a manner to be described later. The memory 6 also has a read / write input 37 and an address input 38 for the address trigger signal. The memory has a plurality of addresses, in each of which an information unit, e.g. can be stored in the form of a byte, which is formed by the data at the data inputs 36.

The control input part 5 has a clock generator 39 and a shift register 40. The input 41 of the clock generator 39 is connected to the output of an OR gate 42, one input of which is connected to the second input 12 of the data compressor 1 and the other input of which is connected to the sequencer 4 in a manner to be described later. The output 43 of the clock generator 39 is connected to the clock input 22 of the shift register 15, the clock input 28 of the counter 16 and a clock input 44 of the shift register 40. The clock generator 39 is formed by a component 74 S 132 and is designed such that when a signal with a high level is applied to the input, it outputs 12 clocks of a predetermined controllable frequency, preferably between 7 and 100 MHz and in particular approximately 20 MHz at its output 43 .

The shift register 40 is formed by two registers 74 95 and has seven consecutive register locations, each with one output. The output of the seventh register location is connected via a return line 45 to a data input 46 to the first register location, so that the shift register 40 as

Ring counter is switched. The output 47 of the first register Space, the output 48 of the second register space and the output 49 of the third register space are connected to the sequencer 4 in a manner to be described later. The outputs of the fourth to seventh register locations are each connected to inputs of a NOR gate 50, the output of which is connected via a line 51 to the read / write input 37 of the memory 6. The NOR gate is formed by a 7425 component. Furthermore, the outputs 48 and 49 are each connected to inputs of an OR gate 52, the output of which is connected via a line 53 to the input 19 of the shift register 15 and the first input 34 of the NAND gate 33. The shift register 40 is also connected to a set input 54, by means of which the shift register 40 can be set to 1000000 in parallel or in series.

The sequence control has a start-stop register 55, a zero value register 56 and a characteristic value register 57. The start-stop register 55 is formed by three D flip-flops E, E 'and E' ', which by connecting the Q output of the flip-flop E to the D input of the flip-flop E' and the Q- Output of the flip-flop E 'are connected to the D input of the flip-flop E' '. In a similar manner, the characteristic value register 57 is formed by two D flip-flops K 'and K' ', the Q output of the K' flip-flop being connected to the D input of the K '' flip-flop. The zero value register 56 is formed by a simple D flip-flop.

Registers 55, 56, 57 each have reset inputs CP, data inputs D, preset inputs pr and outputs Q. and Ǭ and are connected as follows:

The D input 58 of the start-stop register 55 is connected to the second input 12 of the data compressor 1 and the CP input 59 of the E flip-flops and the CP input 60 of the zero value register 56 connected to the output of the fifth register position of the shift register 40. The CP inputs 61, 62 of the K'- and K '' flip-flops are both connected to the output of the first register location of the shift register 40. The D input 63 of the zero value register 56 is connected to the output 29 of the counter 16 and the D input 64 of the K 'flip-flop of the characteristic value register 57 together with the pr-E input of the zero value register 56 with the output of a NAND Member 66 connected. The NAND gate 66 has two inputs 67, 68, of which one input 67 is connected to the output 31 of the comparator 17. The other input 68 is connected via an inverter 69 to the output of an AND gate 70 with two inputs, one input of which is connected to the Q output 71 with the interposition of an inverter 72 and the other input of which is connected to the Q output of the E 'flip -Flops is connected. The output of the AND gate 70 is also connected to an input of a further AND gate 73, the other input of which is connected to the output 49 of the third register location of the shift register 40 and the output of which is connected to a first input of an OR gate 74 having three inputs is. The second input of the OR gate 74 is connected to the output of an AND gate 75, one input of which is connected to the output 31 of the comparator 17 or input 67 of the NAND gate 66 and the other input of which is connected to the output 47 of the first register position of the shift register 40 is connected. The third input of the OR gate 74 is connected to the output of an AND gate 76 with three inputs, one input of which is connected to the output 49 of the third register location of the shift register 40, the second input of which is connected to the Q output of the K'-flip Flops of the characteristic value register 57 and its third input with the interposition of an inverter 77 with the output of an AND

Link 78 is connected to two inputs, the first input of which is connected to the Q output of the K ″ flip-flop of the characteristic value register

57 and its second input with the Q output of the zero value registers 56 is connected. The output 79 of the OR gate 74 is connected to the charging input 26 of the counter 16.

Furthermore, an AND gate 80 with four inputs is provided, the first input of which is connected to the Q output of the K 'flip-flop of the characteristic value register 57, the second input of which is connected to the output of the AND gate 78, and the third input of which is connected to the output of a NAND gate 81 and its fourth input is connected to the output 49 of the third register location of the shift register 40. The output 82 of the AND gate 80 is connected to the count input 27 of the shift register 16.

The NAND gate 81 has three inputs, one with the Q output of the E 'flip-flop, the second with the output of the inverter 71 and the third with the Q output of the K' 'flip-flop of the characteristic value register 57 is connected by interposing an inverter 83. The output of the NAND gate 81 is connected to one of four inputs of a NAND gate 84, the further inputs of which are connected to the output of the AND gate 78 or the Q output of the K 'flip-flop and the output of one

NAND gate 85 are connected to two inputs, one input of which is connected to the Q output of the E ″ flip-flop and the other output of which is connected to the Q output of the E ′ flip-flop with the interposition of an inverter 86. The output of the NAND gate 84 is connected to an input of an AND gate 87 with three inputs, the further inputs of which are connected to the output 48 of the second register position of the shift register 40 or to the output of an OR gate 88 with two inputs , one input of which is connected to the Q output of the E '' flip-flop and the other input of which is connected to the Q output of the E 'flip-flop. The output 89 of the AND gate 87 is connected to the address input 38 of the memory 6.

A line 90 is also provided, which is the second input of the EXNOR gate 32 connects to the output of the NAND gate 88, and a line 91 which connects the second input of the open collector NAND gate 33 to the output of the NAND gate 81. Another line 92 connects the second input of the OR gate 42 to the Q output of the E ″ flip-flop. The start-stop register 55 and the characteristic value register 57 also each have clear inputs 93, 94, which are each connected to the output of the OR gate 42.

Finally, a line 92 'is provided which connects the Q output of the K' flip-flop of the characteristic value register 57 to the eighth input of the data inputs 36 of the memory 6.

The OR gates 42, 52 and 88 are preferably each by a component 74 S 32, the inverters 69, 71, 77, 83 and 86 each by a component 74 S 04 and the AND gates 70, 73 and 78 by one Component 74 S 08 realized. A component is preferably found for each of the two NAND elements 66 and 85

74 S 10, for the NAND gate 81 a component 74 S 10, for the NAND gate 84 the component 74 S 20, for the AND gate 87 a component 74 LS 21 and for the AND gate 80 a component 74 ALS 21

Use. The OR gate 74 in conjunction with the AND gates

75 and 76 is preferably realized by a component 74 S 64.

The structure of a data expander 2 according to the invention will be explained in detail below using the exemplary embodiment shown in FIG. 4. Parts that are identical to corresponding parts of the data compressor 1 are provided with the same reference numerals and reference is made to the corresponding description in the data compressor for the description of these parts.

The memory 10, which can be a memory shared by several compressors and expanders and other systems, has eight data outputs 95 connected in parallel. The first seven of these eight outputs 95 are each connected to corresponding register locations 1 to 7 of shift register 15 and to corresponding storage locations 1 to 7 of counter 16. The eighth output is connected to the sequencer 8 in a manner to be described later. The eighth memory location of counter 16 is set to the value 1. The counter 16 is used as an up counter and has an output 96 for displaying the maximum counter status. The second input 20 of the shift register 15 is set to zero. Furthermore, the shift register 15 has two further inputs, namely a shift input 97 for serial shifting and a loading input 98 for parallel loading. Finally, the shift register 15 has an output 99 for outputting the data in serial form.

The control input part 9 differs from the control input part 5 of the data compressor 1 in that the output 47 of the first register location of the shift register 40 is not required. The outputs 48, 49 of the second and third register locations are connected to the sequence controller 8 in a manner to be described later. The register positions 4 to 7 are in turn via the NOR gate 50 and the line 51 with the read input

37 of the memory 10 connected. Furthermore, the OR gate 52 is not provided.

The sequencer 8 has four registers, each of which is formed by a simple D flip-flop: a reload register 100, a characteristic register 101, a load inhibit register 102 and an address control register 103. Each of these registers 100, 102 and 103 has a CP input , a preset input pr, a D input and a Q and a und output. Register 101 has a clear input c1, a CP input, a D input and a Q and Ǭ output. The CP input of the reloading register 100 is connected to the output 48 of the second register location of the shift register 40 and the CP input of the load inhibiting register 102 is connected to the output 49 of the third register location of the shift register 40 connected. The CP input of the characteristic value register 101 is connected via an inverter 104 to the output of an AND gate 105 with two inputs, the first input of which is connected to the Q output of the load inhibit register 102 and the other output of which is connected to the output of the seventh register position of the shift register 40 is.

The pr input of register 100 and the c1 input of register 101 are each connected to input 13 of the data expander. The pr input of the load inhibit register 102 is connected to the output of an AND gate 106 with two inputs, one input of which is connected to the input 13 of the data expander 2 and the other input of which is connected to the output of a NAND gate 107 with two inputs. One input of the NAND gate 107 is connected to the output of the fifth register position of the shift register 15 and the other input is connected to the output 96 of the counter 16 via an inverter 108.

The D input of the reloading register 100 is also connected to the output 96 of the counter 16, the D input of the characteristic value register 101 to the eighth, free output of the data outputs 95 of the memory 10 and the D input of the charge blocking register 102 to the Ǭ output of the Characteristic register 101 connected.

The Ǭ output of the characteristic value register 101 is connected to a first input of an AND gate 109 with two inputs, the other input of which is connected to the Q output of the reload register 100 and the output of which is connected to the shift input 97 of the shift register 15. Furthermore, two AND gates 110, 111 are provided, each with three inputs, the first input of which is connected to the output of the AND gate 105 and the third input of which is connected to the Q output of the reload register 100 is connected. The second input of the AND gate 110 is connected via an inverter 112 and the second input of the AND gate 111 directly to the eighth data output of the data outputs 95 of the memory 10. The output of the AND gate 110 is connected to the load input 98 of the shift register 15 and the output of the AND gate 111 to the load input 26 of the counter 16. Another AND gate 113 with two inputs is connected at its first input to the Q output of the reload register 100, at its second input to the output 49 of the third register location of the shift register 40 and at its output to the counter input 27 of the counter 16.

The address control register 103 has a clear input, a preset input pr and a Ǭ output. The clear input of the register 103 is connected to the output of a NOR gate 114 with two inputs, one input of which is connected to the output 48 of the second register location of the shift register 40 and the other input of which is connected to the input 13 of the data expander via an inverter 115 connected is. The pr input of register 103 is connected to the output of a further two-input NOR gate 116, the first input of which is connected to the output of AND gate 110 and the second input of which is connected to the output of AND gate 111. The Ǭ output of register 103 is connected to address input 38 of memory 10.

The following components are preferably used for the individual circuit parts of the sequence control 8: for the registers 100,

101, 102 and 103 each the component 74 S 74, for the inverter

104, 108, 112 and 115 the component 74 S 04, for the AND gates

105 and 106 the component 74 S 08, for the NAND link 107 the

Component 74 S 00 and the component for NOR gates 114 and 116 74 S 02. The NAND elements 109 and 110 as well as 111 and 113 are each realized together by a component 74 S 15. The same components as for the corresponding circuit parts of the data compressor 1 are used for the other circuit parts of the data expander 2.

The operation of the data compressor 1 and the data expander 2 is to be shown on the basis of a bit pattern for the data to be compressed, as is shown in FIG. 5. The successive data are shown as strips with black and white sections, of which a unit length of the black section should represent a binary zero and a unit length of the white section should represent a binary one. The top line I represents the data stream to be compressed which is fed to the input 11 of the data compressor 1, the middle line II the compressed data record stored or to be transmitted in the memory 6 or 10 and the bottom line III the data expander 2 after the expansion Expanded data stream leaving output 14. The data stream to be compressed in line I is, in accordance with the function of the compressor explained in the following, divided into periods 1, 2 ... with seven data units each, to which reference should be made below. The data stream in line I in FIG. 5 is fed to the data compressor 1 in such a way that the data units reach the input 11 of the data compressor 1 one after the other from the left edge of line I.

The states of the data compressor 1 in the individual periods shown in FIG. 5 are shown in FIGS. 6 to 17, a register content of zero in the registers 15, 16, 55, 56 and 57 being identified by a black circle.

The initial state of the data compressor 1, in the at the input 12 is an "off" signal is shown in Fig. 6. By the "off" signal in the start-stop register 55 and in the characteristic value register 57, the content zero and via the set input 54 in the first register position of the shift register 40 a logical one and in the remaining register positions of the shift register 40 a logical one Set to zero. The content of the shift register 15 and the counter 16 is still arbitrary.

If an "on" signal arrives at the input 12, the clock generator 39 is switched on via the OR gate 42 and supplies synchronous clock pulses to the shift register 15, the counter 16 and the shift register 40 via the clock inputs 22, 28 and 44 In the shift register 15 these clock signals have the effect that with each clock signal a further bit of the data stream present at the input 11 is transferred to the shift register 15 or in the shift register 15 each bit is shifted to the right by one register position in FIG. In shift register 40, this clock causes logic one to move one place up to the higher register locations with each clock signal, i.e. 6 is shifted to the right in FIG. 6, the remaining register locations having logic zeros, since the content of register location 7 determines the content of register location 1 in the subsequent cycle in each case via line 45.

The state after five clock signals from the clock generator 39 is in

Fig. 7 shown. The logical one from register position 1 has moved to register position 5 of shift register 40. As a result, the content of the E flip-flop is set to 1 via the connection of the CP input 59 of the start-stop register 55 to the register location 5. At the same time, the data stream present at input 11 has advanced five places into shift register 15 according to line I in FIG. 5. A write command to the memory occurs via the OR gate 50 and the line 51 6 and the current content of the counter 16 is transferred to the memory 6. However, this content will be overwritten at a later point in time since there is still no signal for changing the address at address input 38.

8 shows the state of the data compressor 1 after the first period with seven clocks, that is to say at the beginning of the second period according to FIG. 5. The first seven bits of the data stream present are in shift register 15. Regardless of whether the bits are the same or different, this first data sequence in the shift register 15 should reach the memory unchanged. This is achieved in that the result of the EXNOR element 32 is fed to the ninth input 30 of the comparator 17. Since there is a zero both in the E ′ and in the E ″ flip-flop of the start-stop register 55, one input of the EXNOR gate 32 is set to zero via the OR gate 88. This means that the output of the EXNOR gate in each case assumes the opposite value of the level at the other input which is connected to the second register location of the shift register 15. It is thus determined in any case in the comparator 17 that not all nine inputs have the same level. Thus, the comparator 17 produces a value K with level 1 at the output 31, which supplies a signal with level 1 to the charging input 26 of the counter 16 via the AND gate 75 and the OR gate 74 in cycle 1, so that the content of the first seven register locations of the shift register 15 are fed to the first seven memory locations of the counter 16. This content also appears at the data outputs 25 of the counter 16. Since the content of the memory locations E 'and E''is zero in each case and thus the output of the OR gate 88 is also at zero, no signal appears at the output 89 in the following cycle 2 , so that the address in the memory is not changed since the value K = 1 is also supplied to the NAND gate 66 and so that the content of the K 'memory was set to zero in cycle 1, no signal reaches output 82 in cycle 3, as a result of which no counting process is started. In cycle 5, the content of the E memory moves to E ', so that now EE' = 1 1. In cycles 4 to 7, a signal is sent to write input 37 of memory '6 via NOR gate 50 and line 51 given, so that the content present at the data inputs 36 is written into the first memory address. Since K '= 0, a zero bit is written into the eighth memory location of this first address as the identification bit via line 92'.

FIG. 9 shows the state of the data compressor 1 after the first two periods shown in FIG. 5, that is to say at the beginning of the third period. During the clocks of the preceding second period, the next seven bits of the incoming data stream, namely seven zeros, have reached positions 1 to 7 of shift register 15. At number 8 there is still the zero of the last bit from the seven-bit sequence before it, which was also a zero. Since all bits in the shift register are identical to one another, the newly entered seven-bit sequence is "reason". This means that there are only zeros in shift register 15 at cycle 1 of the third period. This means that the first eight inputs 30 of the comparator 17 each have the same values. Since now because of E 'E' '= 1 0, a signal with level is present at the first input of the EXNOR element 32

1 so that a signal with the same level as that at the second input is always generated at the output of the EXNOR element. The output of the EXNOR gate 32 is thus also at zero, so that all nine inputs of the comparator 17 display the same values and the comparator outputs a signal with level zero at the output K. The output 79 thus remains at zero, so that the content of the memory 15 is not loaded into the counter 16. Furthermore, with K = 0, a signal with level 1 appears at the output of the NAND gate 66, so that the Ver Binding of the CP input 61 to the output 47 in cycle 1, the content of the K 'memory and in cycle 5 via the connection of the CP input 60 of the zero value register 56 to the fifth register position of the shift register 40, the content of the zero value register 56 made one becomes. Since the output of the NAND gate 84 is at level 1 because of K 'K''= 1 0 and the output of the OR gate 88 is at level 1 because of E' E '' = 1 0, a signal appears in clock 2 Level 1 at output 89, so that the memory address for storing the data present at inputs 36 is changed. The data already saved in the second period are thus obtained.

In clocks 2 and 3 of the third period, the outputs of the shift register are made high-resistance via the OR gate 52 and the line 53. At the same time, the output of the first register location 21 is set to zero via the open collector element 33. In cycle 3, a load command is thus given to the load input 26 of the counter 16 via the AND gate 76 and the OR gate 79, as a result of which the value 0111111 is loaded into the first seven memory locations of the counter 16. The eighth memory location still contains the value zero. These data are thus also present at the data inputs 36 of the memory 6 together with the characteristic bit, which has the value 1 because of K '= 1, and are written together in cycles 4 to 7 into the second memory address. In cycle 5, the content of the memory E 'is shifted to E' 'via the CP input 59, so that now E E' E '' = 1 1 1.

10 shows the state of the data compressor 1 after

End of the third period, i.e. at the beginning of the fourth period. 5, a further seven bits with a value of zero, that is to say "reason", are in the shift register 15 broken in. In the same way as in the previous period, there is no loading into counter 16 in cycle 1; instead, by connecting the CP outputs 61 and 62 of the characteristic value register 57 to the output 47 of the shift register 40, K ″ = 1, so that K 'K''= 1 1. This indicates that matching bits were found in two successive periods. The output of the NAND gate 84 is thus at zero level, so that no signal appears at the output 89 in cycle 2 and the address of the memory is therefore not changed. Since in clock 3 all inputs of AND gate 80 are at level 1, in clock 3 there is a signal at output 82 and thus at counter input 27, so that the value 01111110 loaded in the previous period is counted down by 1 to 10111110. At clocks 4 to 7, a write command is again given to the write input 37 of the memory 6, so that the first seven bits 1011 of the counter 16 together with the characteristic bit corresponding to the value stored in the memory K 'instead of the previously stored values in the second address of the memory 6 can be stored.

11 shows the state of the data compressor 1 after the end of the fourth period shown in FIG. 5, that is to say at the beginning of the fifth period. During the fourth period, seven bits have entered register positions 1 to 7 of shift register 15, which are not all identical to one another. The newly entered seven-bit sequence is thus referred to as a "figure". The comparator 17 thus detects inequality and supplies a signal K = 1 at the output 31. A clock signal is thus sent to the charging input 26 via the AND gate 75 and the OR gate 74, so that the content of the first seven Register positions of the shift register 15 are loaded in cycle 1 onto the first seven storage locations of the counter 16 and the next incoming data can then enter the shift register 15. Furthermore, the content of the The memory K 'is set to zero, so that K' K '' = 0 1. The output of the NAND gate 84 thus becomes 1 and in cycle 2 a signal with level 1 appears at the output 89, so that the address of the memory 6 is changed and the count 10111111 stored in the second address of the memory in the fourth period can no longer be overwritten and thus remains stored. In cycle 3, neither a load signal appears at output 79 nor a count signal at output 82, so that the content loaded in cycle 1 from shift register 15 into counter 16 is retained and is written into address 3 of memory 6 in cycles 4 to 7 can.

FIG. 12 shows the state of the data compressor 1 after the end of the fifth period shown in FIG. 5, that is to say at the beginning of the sixth period. During the preceding fifth period, seven bits with a value of one entered the first seven register locations of the shift register 15. The last bit of the preceding seven-bit sequence, which also represented a one, is still in the eighth register position. The comparator 17 thus determines the equality of all bits in the register 15 and thus "reason" and generates immediately, ie within the first cycle, K = 0 at the output 31. A signal with level 0 thus appears at the output 79 and it can be in cycle 1 the value from register 15 cannot be loaded into counter 16. At the same time, however, in cycle 1, due to the interconnection of the memories K 'and K'', the value zero moves from the memory K' into the memory K '', so that K 'K''= 1 0. This gives the output of the NAND element 84 a high level, so that a signal for changing the address of the memory 6 appears at clock 89 at output 89. This means that the bit sequence saved in the previous period can no longer be overwritten and remains saved. In clock 3 in the same way as in the third period described above, the counter 16 with the Value 01111110 loaded and loaded in cycle 4 to 7 together with the identification bit as value 01111111 into the fourth address of memory 6.

13 shows the state of the data compressor 1 after the expiry of (4 + 126) periods, that is to say at the beginning of the (5 + 126) th period. During the previous 2 ⁷ -2 = 126 periods ran as in

Fig. 5 is shown, each seven-bit sequences in the shift register 15, the bits of which were all the same. Therefore, the count of counter 16 has been reduced by 1 in each period in the manner described above in connection with the third period, so that counter 16 now has the content 00000000. The counter 16 has therefore given a signal at the end of the preceding period at the output 29 which indicates the zero level. This counter reading is now together with the identification bit

1 in memory 6 to prevent further counting to the initial value 11111111 and thus to prevent the counter result from being falsified. For this purpose, the signal from the output 29 is fed to the D input 63 of the zero value register 56 and sets the content of this register to zero. As a result, the value K '' = 0 is simulated via the AND gate 78 and the output of the NAND gate 84 is at level 1, so that a clock level 1 signal appears at output 89 and the address of the memory 6 is changed . This means that the count value 00000001 written in the memory can no longer be overwritten. Since the bits that have entered the shift register 15 in the previous period are also identical to one another and to the last bit of the preceding seven-bit sequence, the comparator 17 continues to determine equality, so that K 'K' continues to be via the NAND gate 66. '= 1 1 is present.

The output of the AND gate 78 is thus at a low level, which is raised to level 1 via the inverter 77. Therefore, in cycle 3, in the same way as in the third period described above, a new initial counter reading 01111110 can be loaded into counter 16, which together with the content of the memory chers K '= 1 is stored in the next address of the memory 6 during the cycles 4 to 7.

The state of the data compressor 1 at the beginning of the following (5 + 126 + 1) th period is shown in FIG. 14. At the beginning of this period, as can be seen from FIG. 5, the “off” signal was received at the input 12. As a result, no further bits run into the shift register 15 and the state of the counter 16 is unchanged from the previous period. However, the clock generator 39 continues to run despite the “off” signal, since the second input of the OR gate 42 is still at level 1 because of E ″ = 1. The ring counter formed by the shift register 40 also continues to run and sets the clock in clock 5 Contents of the memory E of the start-stop register 55 to zero.

To indicate the end of the data stream, a mark must now be set in the memory. This mark consists of a stop byte with the bit sequence 11111111. This bit sequence does not otherwise occur in the memory, since when a seven-bit sequence of unequal bits is stored, the identification bit 0 is stored and when successive seven-bit Following the same bits, a counter reading is stored which has at least one zero. The stop byte is therefore clearly recognizable as a stop mark.

The stop byte is generated in the following way: As shown in FIG. 15, in clock 1 of the next (5 + 126 + 2) th period, the output of the AND gate 70 becomes zero and therefore because of EE '= 0 1 the level at the first input 68 of the NAND gate 66 is set to 1 because of the inverter 69. The second input 67 of the NAND element 66 is at zero at the output 31 of the comparator 17 because of 17C = 0. This is the output of the NAND gate 66 at level 1 and in cycle 1, the value 1 is stored in memory K ', so that a signal with level 1 is present at the Q output of memory K' and at the eighth data input 36 of memory 6 reserved for the identification bit. At the same time, because of EE '= 0 1, the open collector NAND gate 33 is controlled via the NAND gate 81 in such a way that the output of the first register location 21 and thus the value of the first memory location 24 of the memory 16 during clocks 2 and 3 Level 1 is set. The content 11111110 is thus loaded into the memory 16 with the loading signal generated in cycle 3 at the charging input 26. The first seven bits of this memory content are written to the first seven memory locations of the present address of the memory 6 together with the identification bit 1 in the eighth memory location, so that the stop byte 11111111 is now stored there. In bar 5, the

Transported zero from memory E to memory E ', so that E E' = 0 0.

The clock 39 is switched off in the next period of the ring counter 40. The state of the data compressor 1 at the beginning of this period is shown in FIG. 16. Since there is E 'E''= 0 1 in clock 1, a signal with a high level is generated in clock 2 at output 89 and thus the address of the memory is changed so that the data inputs 36 are connected to a new address and thus the stop byte can no longer be overwritten. The information arriving at clock 3 in counter 16 and stored in memory 6 during clocks 4 to 7 will be overwritten by new information which arrives after the next "on" signal. In cycle 5, the content zero is transferred from memory E 'to memory E'', so that a signal with level 0 appears at the Q output of memory E' * and the second input of OR gate 42 is also set to zero . The output of the OR gate is striking Zero and the clock 39 is turned off.

As can be seen from the content of the memory 6 shown in FIG. 16, the entire information arriving within the (5 + 126) th periods of 7 bits is a in five addresses

8 bits of memory 6 stored. This means that 917 bits of the incoming data stream are stored in 40 memory locations, which results in a reduction rate of 23: 1. This is achieved in that whenever the individual bits have a number of successive seven-bit sequences, all one below the other and with the last one Bits of a preceding bit sequence are the same (so-called "reason"), not the individual bits of these bit sequences, but the counter reading obtained at the end of these bit sequences is stored. If the bits of a bit sequence differ from one another (a so-called "figure"), these bits are stored in the usual way. To distinguish the "basic bytes" from the "figure bytes" in the memory, it is only necessary to additionally store an additional bit (the so-called "identification bit") for each seven-bit sequence, which indicates whether it is a "reason" or "figure". However, the memory space required for this additional bit is irrelevant if a larger number of "reason" occurs, so that the memory space saving due to this "reason" far exceeds the additional memory space required because of the "identification bits".

The mode of operation of the data expander 2 will be explained using the circuit diagram in FIG. 4 and the schematic information representation in FIG. 5. The information shown in FIG. 16 is present in the memory.

Before the "on" signal is applied to input 13, the value 1 is in the first memory location of shift register or ring counter 40 and the value 0 is stored in the remaining memory locations. Registers 100 and 102 are also at value 1. Register 101 and address control register 103 are at value 0.

After the "on" signal is applied to the input 13, the clock generator 39 is switched on, which clocks the shift register 15, the counter 16 and the ring counter 40 in the same way as for the data compressor. In cycle 2, the output of the NOR gate 114 drops to zero and the signal at the address input 38 of the memory 10 thus remains at a high level, so that the address has not yet been changed. In cycles 4 to 7 of the first period, the content of address 1 of memory 10 is read from memory 10 and made available at data outputs 95.

In the second period, at the beginning of bar 1, the content read from memory at the end of bar 7 is still available due to the gate runtimes. The bit at the eighth position of the data outputs 95, which corresponds to the eighth bit of the first address, is zero and therefore sets this to K '= 0 via the D input of the register 101. The loading input S8 of the Shift register 15 is set to a high level and the first seven bits are loaded in parallel into shift register 15 at the first seven positions of data outputs 95. Because K '= 0, the seven loaded bits are shifted serially to output 99 and, via this, to output 14 of the expander from the next clock cycle (which previously shifted zeros). During the loading process, the preset 1 input of the address control register 103 is set to zero via the NOR gate 116 and the first address change from address 1 to address 2 is thus prepared. At clock 2, a clear signal is applied to the address control register 103 via the NOR gate 114 and the output Q from A is thus set to 1 again. The address is changed in the memory 10 by the edge from Q = O to Q = 1 at the Q ^ output of the address control register 103. The contents of address 2 are then read in cycles 4 to 7 and made available at the data outputs 95.

At the beginning of the third period, the identification bit 1 of the second address appears at the D input of the characteristic value register 101. This results in K '= 1. The last bit of the first seven bits shifted from the shift register 15 thus remains at the seventh register location of the shift register 15. The output of the AND gate 111 goes high and causes the loading of the first seven bits of the data of the second address at the data outputs 95 into the counter 16. The NOR gate 116 in turn causes the next address Prepared for change, which is carried out in bar 2 in the same way as in the second period. In cycle 3, the output of the AND gate 113 goes high and causes the counter to count up from the previously loaded content 10111111 to the content 01111111. At the same time, a value of zero is added to the CP input of the load inhibit register 102 via the output 49

Load inhibit register 102 is loaded, as a result of which the output Q of the load inhibit register 102 becomes zero and thus the output of the AND gate 111 is kept at a low level via the AND gate 105 and further charging is prevented until the clock 3 in a later period maximum counter reading of counter 16 is reached. In cycles 4 to 7, the content of the next address 3 is again made available at the data outputs 95.

At the beginning of the fourth period, K '= 1 and the output Q of the load inhibit register 102 is at zero. Thus, at clock 1, neither the shift register 15 nor the counter 16 are loaded in parallel. Without a signal with level 1 at the output of the AND- The gate 110 or the AND gate 111, however, cannot prepare the address change of the memory 10 via the address control register 103 and thus the address of the memory 10 cannot be changed either. In cycle 3, the counter input of counter 16 is set to a high level and counter 16 counts up by 1 to the new counter reading 11111111. The maximum counter reading is thus reached and a signal is output at output 96, which is transmitted in cycle 5 via the NAND Gate 107 and the AND gate 106 resets the load lock register 102 and thus releases the load lock. In measures 4 to 7, the content of the present address, that is again address 3, is made available at data outputs 95 in the same way as in the preceding measures.

During the third and fourth period, the output of the AND gate 109 is always at a low level, so that the data in the shift register 15 are not shifted and with each clock signal from the clock generator 39 a bit is output by the shift register 15 which corresponds to the seventh register position of the Shift register corresponds to 15 standing bits. This bit is the last of the figure bytes shifted from register 15 in the second period, namely a zero bit.

At the beginning of the fifth period, during the transition from clock 7 of the fourth period to clock 1 of the fifth period, the content of the first seven bits of address 3 was loaded in parallel into shift register 15. Since the bit at the eighth position of address 3 (identification bit) is zero, K '= 0 and the bit sequence in register 15 is shifted serially to data output 99. The last bit of the previous seven bits is also Waiting place at the last position of the shift register 15 leaves. With the loading, the address change is prepared via the NOR gate 116, which goes through in cycle 2 as above leads. In cycle 3, counter 16 is switched on and counts upwards from 11111111 to 00OOOO0O. In cycle 5, the charge lock 102 is not set because the counter output signal is no longer at 11111111 or 255. In cycles 5 4 to 7, the content of the new address, ie now address 4, is made available at data outputs 95 as above.

At the beginning of the sixth period, the content of the first seven bits of the address 4 is loaded into the counter 16 because the identifier. _Q bit at the eighth position of address 4 = 1. As a result, K ¹ = 1 and thus the serial shifting of the shift register 15 is interrupted, so that the last bit of the preceding figure byte remains in the seventh position of the shift register 15 and is output in each case with the following clock signals from the clock generator 39. Zeros were added via input 20. With the loading, the address change is prepared as above, which is carried out in cycle 2 in the same way as described above. In cycle 3, the counter 16 is increased from the counter reading 20 00000001 loaded at the beginning of the sixth period to the counter reading 10000001. In cycle 5, the charge lock register 102 is switched on because K ¹ = 1 and in cycles 4 to 7, as described above, the content of the subsequent fifth address is made available at the data outputs 95 of the memory 10. 25th

In the subsequent 125 periods, the shift register 15 outputs a bit for each clock of the clock generator 39, which corresponds to the last figure bit of the last preceding figure byte 30 in the seventh register position of the shift register 15. In each period, the counter reading of counter 16 is increased by 1. Since no more loading takes place, the address in cycle 2 is not changed. In the subsequent (6 + 126) th period, the counter reading 11111111 is reached in cycle 3. A signal is thus generated at the output 96 of the counter 16 and the charge lock 102 is switched off at clock 5. However, since this counter reading is only reached in cycle 3, the counter reading in cycle 2 was still unequal

11111111 or 255. In the following (6 + 127) th period the content of address 5, namely 11111111, is loaded into the counter at the beginning due to the identification bit = 1 in address 5 and the previously released load lock, which means that for the first time already the counter maximum signal 255 is emitted at the output 96 at the clock 2 from the counter 16. As a result, the reload register 100 is switched over and the Q output (STOP) becomes zero. The outputs of the AND gates 109, 110, 111 and 113 are thus set to zero and the serial shifting and parallel loading of the shift register 15 and the loading and counting of the counter 16 are switched off. As a result, the address change can no longer be carried out. The clock generator 39 and the ring counter 40 are not switched off if they are used together for a plurality of data expanders 2 or also data compressors 1.

The principle of the data expander 2 is therefore that when a characteristic bit with the value 0 is detected in the eighth place of the data outputs 95 of the memory 10, the information from the first seven positions of the outputs 95 is loaded in parallel with a register (shift register 15) , which supplies this data serially to the data output 14, and that when a characteristic bit with the value 1 is detected, the content of the first seven places of the data outputs 95 of the memory 10 is interpreted as a counter reading and loaded into a counter (counter 16), from which the data are not supplied to data output 14. Rather, the counter is incremented by 1 for each period and seven bits are output by the register (shift register 15), which are each equal to the bit that came from the memory 10 to the register (shift register 15) to the first register position 21 when the data was last loaded in parallel. When a "stop" bit (= 11111111) is detected, the data expander 2 is switched off. The expander thus has a "switch" which directs the data from the data outputs 95 of the memory 10 depending on the identification bit either to the register and from there to the output or to the counter. The identification bits are no longer required from the turnout and are removed from the information flow. In principle, the data compressor 1 also contains one

Output switch which, depending on the output signal of the comparator 17, either passes on the "figure byte" with identification bit or the counter reading + identification bit.

The length of the "Bytes" resp. Bit sequences in a period can of course take any value. In this case, only the size of the register 15, the counter 16 and the memory 6 or 10 has to be adapted to the selected length of the bit sequence. Any number of identification bits can also be selected. With more identification bits, for example, "colors" of the spaces formed by the "basic bytes" can also be represented, for example four "color tones" with two identification bits. In another case, two identification bits can also identify a supplementary byte which, with f bits, identifies a color of an image part that is different from 2 ^f .

Furthermore, the method can in principle not only be applied one-dimensionally, but also to the columns after the data field contained in the memory 6 or 10 has been rotated by 90 °. Further data compression is thus possible through such an n-dimensional application 17 shows a further embodiment of a data compressor according to the invention. The circuit has a converter 3, a controller 200 connected to the converter 3 and a buffer memory 210. The buffer memory 210 is divided into an information data area 212, which is connected to the controller 200 via a line 202, and a control data area 211, which is connected to the controller via a line 201. The buffer memory 210 has an output 213, which is connected to an external memory 6.

The operation of the circuit is described below with reference to FIG. 17. As described above, the converter 3 receives serial data at its data input 11, which it converts into parallel data. The parallel data are present as eight bit-wide information units at the output 25 of the converter 3. The controller 200 receives this information unit via the connection 203. A comparator present in the controller 200 checks whether all data bits of the information unit are the same and correspond to the last data bit of the previous information unit. If this condition is not met, the information unit is written directly into the information data area 212 of the buffer memory 210 via the connection 202. Furthermore, an element counter contained in the controller 200 is increased by one. The controller 200 then sets a bit in the control data area 211 of the buffer memory 210 to one via the connection 201, whose position in the control data area 211 corresponds to the counter reading of the element counter. A repetition counter also present in the controller 200 is set to zero.

The comparator provides the match of all data bits of the information unit and the correspondence with the last data bit of the previous information unit, the repetition counter is increased by one. The next information unit can then be supplied to the controller 200 via the connection 203. If the comparator again determines equality, the counter is increased again by one. If this does not determine equality, the counter reading of the repetition counter is written into the information data area 212. The element counter is incremented by one and the controller 200 sets in the control data area

211 a data bit, whose position corresponds to the counter reading of the element counter, to zero.

This process is repeated until the end of a data record is reached. The length of the data record is dependent on the size of the buffer memory 210. At the end of the data record, the status of the element counter is also written into the control data area 211 via the connection 201. Furthermore, the controller 200 sets a further bit in the control data area 211 to the value one if compression of information units was possible, i.e. , if the comparator found equality while processing a data set, and set it to zero if it was not possible to compress information units. The buffer memory 210 then transfers the entire control data area 211 and information data area in the event that the last bit set has the value one

212 to the memory 6, and in the event that the last bit set has the value zero, only this bit from the control data area 211 and the information data area. The next data record can then be edited.

A compression of the same information units in successive data sets can also be carried out with this circuit. For this purpose, the current information units are compared in controller 200 with the respective information units of the previous data record. If a match is found, the corresponding information unit is not transferred to the information data area 212, and a bit in a corresponding position is set to the value one in a separate area of the control data area 211. In addition, a further bit is also set to one here if a line-by-line compression could take place and to zero if this compression was not possible.

According to yet another embodiment of the invention, the data stored in memory 6 are rotated through 90 ° to compress successive data sets, i.e. the rows and columns of the data stored in matrix form are interchanged. Data compression is then carried out again as described above. In this embodiment, the controller 200 is also designed such that the control data present in the control data area 211 can itself be compressed again at the end of a data record. The compression method described above is used for this, the newly obtained control data being written in a further control data area of the buffer memory 210.

With these embodiments of the invention, a further reduction in the necessary memory area in the memory 6 is thus possible, since no control data or identification bits are output if the compression has not taken place.

The data compressed in this way is converted back into original data using the data expander shown in FIG. The data expander has essentially the same functional blocks as the data compressor of FIG. 17. The circuit of Fig. 18 differs from the circuit in Fig. 17 only in that the directions of the data paths are reversed. The mode of operation of the data expander is described below with reference to FIG. 18.

First of all, a data record is transferred from memory 6 to buffer memory 210. The controller 200 now reads from the control data area 211 the bit that characterizes compression of the data record. If this bit has the value zero, it is, as described above, an uncompressed data record. The information units in the information data area 212 are then output unchanged by the controller 200 to the converter 3, which converts them into a serial data stream and outputs the data at the data output.

If it is a compressed data record, the controller 200 reads the element counter reading from the control data area 211 into the element counter present in the controller 200. The first information unit is then transmitted to the controller 200 from the information data area 212. On the basis of the control data bit in the control data area 211, the position of which corresponds to the position of the information unit in the information data area 212, the controller 200 decides whether the information unit is a compressed data byte or an uncompressed data byte. In the case of an uncompressed

Data bytes, the information unit is output directly to the converter 3 and the element counter is decreased by one. The controller 200 then reads the next information unit. In the case of a compressed data byte, the read-in information unit is interpreted by the controller 200 as a counter reading. The controller 200 outputs a number of data bytes corresponding to this counter reading to the converter 3, the data bits of which are identical to one another and equal to the last data bit of the preceding information unit. After these similar data bytes have been output, the element counter is decreased again by one and the next information unit is transmitted to the controller 200. This process is repeated until the element counter is counted to zero and the entire data set is thus output. The next data record is then transferred from the memory 6 to the buffer memory 210. The compressed information stored in the memory 6 can thus be completely recovered.

The reduction in the amount of data achieved in this way can save a considerable amount of storage space when storing the data, for example when storing matrices with unoccupied fields on magnetic disks, which also increases the access speed accordingly. In practice, the data is reduced or the access speed is increased by at least a factor of 10. The transmission of the compressed data also saves on transmission time. In the "gaps" saved between the data to be transmitted, for example, duplicates of the data to increase the transmission security, parts of other programs in the multiplex process for better channel utilization or, in addition, color information, for example, can also be transmitted.

Claims

PATENT CLAIMS

1. Data compression device for transmitting data with a register for receiving an information unit of input data, a converter device for converting the data and an output for the converted data, a controller, a comparator connected to the output of the register and a counter controlled by the latter, characterized in that the comparator checks for equality of all data of the information unit, and the control is designed such that in the event of non-equality, the contents of the register are fed to the output and, in the event of equality, a characteristic bit is generated and the counter is incremented by one, and the counter reading together with the identification bit is supplied to the output if two successive information units do not match.

2. Data expansion device for transmitting data input via an input with a register for receiving an information unit of data, a converter device for converting the data and an output for the converted data, and a controller, a counter connected to the input being provided and the control is designed such that an information unit input via the input, which has no corresponding identification bit, is fed to the output, and when a corresponding identification bit occurs, the information unit is added to the counter, and so often to the output, while simultaneously advancing the counter by in each case One information unit is supplied until the counter reading assumes a predetermined count value, characterized in that the data of the information unit are all identical to one another and that the information unit is supplied by the controller when a characteristic bit occurs.

3. Data expansion device according to claim 2, characterized in that the value of the last data unit of the preceding information unit is selected as the predetermined value.

4. Device according to one of claims 1 to 3, characterized in that the controller has a clock generator (39), the output (43) of which is connected to an input (22) of the register and clocks a shift of the data in the register.

5. Data transmission system with a data converter arranged on the input side, a data converter on the receiving side and a transmission link therebetween, characterized in that the input-side converter is a data compression device according to one of Claims 1, 3 or 4 and the data converter is a data expansion device according to one of Claims 2, 3 or 4 .

6. Data transmission system with an input and an output data storage, characterized in that on the input side a data compression device according to one of claims 1, 3 or 4 and on the output side a data expansion device according to one of claims 2, 3 or 4 is provided.

7. Data compression device for transmitting data with a register for receiving an information unit of input data, a converter device for converting the data and an output for the converted data, a controller, a comparator connected to the output of the register and a counter controlled by the latter, characterized in that a buffer memory is provided for receiving the converted data and the data of the controller, which has a control data area and an information data area, the comparator checks for equality of all data of the information unit, and the controller is designed so that the content of the Register in the information data area of the buffer memory, and a corresponding identifier is written in the control data area, the counter is incremented by one in the case of equality, and the counter reading in the information data area of the buffer memory and e-ine corresponding ID is written in the control data area if two successive information units do not match.

8. Data compression device according to claim 7, characterized in that for writing the identifier in the control data area of the buffer memory a first control data unit corresponding to the write position of the data in the information data area is brought into one state when the comparator detects non-equality and in another state is brought when the comparator detects equality and the number of data in the information data area of the buffer memory is written in the control data area.

9. Data compression device according to claim 7 or 8, characterized by a device which, after all information units have been written into the buffer memory when all data of the information unit have been detected by the comparator, brings a second control data unit in the control data area of the buffer memory into one state, and if the equality is not recorded, the brings the second control data unit into the other state.

10. Data compression device according to one of claims 7 to 9, characterized in that the control in the presence of one state of the second control data unit outputs the entire control data area and information data area of the buffer memory for output and in the presence of the other state of the second control data unit the second control data unit and the information data area to the exit.

11. Data compression device according to one of the claims

7-10, characterized in that the control is designed such that, after performing a compression of the data of the information units, the control data in the control data area of the buffer memory are compressed and a corresponding identifier is written in a further control data area of the buffer memory.

12. Data compression device according to one of claims 7-11, characterized in that the data output by the buffer feeder at the output are written line by line into a memory and the controller is designed such that at the end of the data output the memory content is rotated by 90 ° and one line-by-line data compression is performed again.

13. Data expansion device for transmitting data input via an input with a register for receiving an information unit of data, a converter device for converting the data and an output for the converted data, and a controller, characterized in that a buffer memory for receiving the am Input input data is provided, which has a control data area and an information data area, and the controller outputs the data in the information area directly when reading a state of a control data unit in the control data area of the buffer memory, and the data when reading another state of the first control data unit in the control data area of the buffer memory reads in the information data area and outputs a number of information units in which all data are the same, the number corresponding to the read data from the information data area.