WO1987002828A1

WO1987002828A1 - Glass intermetal dielectric

Info

Publication number: WO1987002828A1
Application number: PCT/US1986/001733
Authority: WO
Inventors: John F. Teodorski; Terri Jewett-Enzmann
Original assignee: Motorola, Inc.
Priority date: 1985-11-04
Filing date: 1986-08-25
Publication date: 1987-05-07
Also published as: EP0245290A1

Abstract

An improved means and methods for forming multilayer metal electronic devices (10) where the intermetal dielectric (18) is formed of a three layer sandwich. The first metal layer (13) is covered with a dielectric layer (14) formed using plasma assisted oxide deposition or low pressure chemical vapor deposition. This first dielectric layer (14) is covered by a second dielectric layer (15) formed using a spun-on glass. The third dielectric layer (16) is formed by chemical vapor deposition or plasma deposition and is then covered with the second metal layer (17). Substantially improved step coverage is obtained and delamination between the intermetal dielectric (18) and the metal layers (13, 17) is avoided. The dielectric may be tapered-etched for contact holes.

Description

GLASS INTERMETAL DIELECTRIC

BACKGROUND 0£ THE. INVENTION

1. Field of the Invention

This invention relates, in general, to means and methods for improved electronic devices, especially semiconductor devices and integrated circuits, and more particularly to improved manufacturing processes and structures involving multiple conductor layers and circuits made therewith.

2. Background Art

It is common practice in the manufacture of semiconductor devices and integrated circuits, and other electronic devices as well, to use multiple layers of conductors, one crossing over the other and separated by an interlayer dielectric. The interlayer dielectric serves to passivate the first conductor as well as to insulate and separate it from the overlying second conductor. Interlayer connection points are provided through openings formed for that purpose in the interlayer dielectric. With semiconductor and other devices having conductive substrates, a primary dielectric layer is also required between the substrate and any conductive layers. This dielectric serves to passivate the substrate surface as well as insulate it from the overlying conductors. Openings are provided in the primary dielectric layer so that the various conductors may make contact with the device structures in the semiconductor substrate.

Because of the openings which must penetrate through the various layers, the surface topography of the device may be highly irregular. This creates step coverage problems with respect to the various layers, e.g., voids or cracks may occur in the conductor layers where they pass over abrupt steps in the surface topography. Further, the substrate and its various dielectric and conductor layers typically undergo substantial heating and cooling during manufacture and use. Because the coefficients of thermal expansion of the various materials are different, substantial stresses are created in the films. This can result in the formation of voids or the delamination of some or all of the various conductor and dielectric layers.

Delamination often occurs during thermal shock treatment.

Thus a need continues to exist for materials, manufacturing methods and structures which contribute to smoothing out the surface topography and which avoid delamination or void formation problems at the same time. There is a particular need for interlayer dielectrics which have excellent adhesion to metal conductors and which, at the same time, can assist in overcoming the step coverage problems created by uneven surfaces on the device.

Accordingly, it is an object of this invention to provide an improved manufacturing method and structure wherein step coverage and adhesion are simultaneously improved.

It is a further object of this invention to provide an improved means and method for the formation of multiple conductor layers separated by an insulating dielectric wherein the insulating dielectric adheres strongly to the conductor layers and at the same time assists in smoothing out surface irregularities.

It is an additional object of the present invention to provide an improved means and method for electronic devices wherein the interlayer dielectric is readily adapted to permit the formation of tapered through-holes for layer to layer contacts.

It is a further object of the present invention to provide multiple conductor layer structures which do not delaminate under thermal shock.

It is a still further object of the present invention to provide an improved means and methods for electronic devices wherein the foregoing objects can be achieved simultaneously.

As used herein, the word "device" is intended to include both individual devices, portions of devices, and collections of devices, as for example in integrated circuits and the like.

SUMMARY OF THE INVENTION

The foregoing and other 'objects and advantages are achieved by providing a structure comprising: a first conductor layer, a first dielectric adhesion layer on the first conductor layer, of for example, a plasma oxide or low pressure chemical vapor deposited (LPCVD) oxide, a second dielectric layer on the first dielectric layer formed from a spun-on glass layer, a third dielectric layer on the second dielectric layer and which is several times thicker than the first or second dielectric layers and which is formed from a plasma oxide or chemical vapor deposited (CVD) oxide, and a second conductor layer overlying the third dielectric layer. It is desirable that the spun-on glass layer be arsenic doped and that the third dielectric layer be phosphorous doped.

The above described objects and advantages, as well as others, are further achieved by providing a semiconductor substrate, covering the semiconductor substrate with an insulating layer, providing a first conductor layer on the insulating layer, providing a second conductor layer superposed above the first conductor layer and separated therefrom by a three part insulating layer, wherein the three part insulating layer is formed by first providing a dielectric adhesion layer on the first conductor layer, then providing a spun-on glass layer on the first dielectric adhesion layer, and finally providing a second dielectric layer on the spun-on glass layer and in contact with the second conductive layer. It is desirable that the step of providing the first dielectric adhesion layer comprise providing that layer by plasma assisted oxide deposition or low pressure chemical vapor oxide deposition. It is desirable that the step of providing the spun-on glass comprise providing an arsenic doped spun-on glass. It is further desirable that the step of providing the second dielectric layer comprise providing a plasma deposited oxide, a low pressure chemical vapor deposited oxide, and/or a phosphorous doped chemical vapor deposited oxide.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-3 are cross-sectional views in simplified schematic form of a cross-over portion of a multi- conductor electronic device during different stages of fabrication and showing the arrangements of the various layers.

DETAILED DESCRIPTION OF^" THE DRAWINGS

In the description which follows, the structure and materials are illustrated for the case of a silicon semiconductor substrate on which are formed various dielectric and conductor layers. It will be readily apparent to those of skill in the art that other electronic substrate materials could be employed. The described means and methods are particularly suited to situations where extremely fine dimensions are employed, e.g., of the order of a fraction of a micron^' to a few microns in thickness and/or lateral extent.

FIG. 1 is a cross-sectional view in simplified schematic form of portion 10 of an electronic device, for instance a semiconductor integrated circuit, comprising substrate 11 (e.g. silicon) covered by dielectric layer 12 (e.g. silicon oxide or nitride) and first conductor layer 13. For clarity, conductor layers 13 and 17 are stippled. First conductor layer 13 is made of metal, semiconductor, semi-metal, intermetallic, or other conductive means. The means and method of the present invention are particularly useful when conductor 13 is of metal, e.g., aluminum or an aluminum (98%) - copper (1%) - silicon (1%) alloy. Conductor layer 13 is patterned using means well known in the art to remove all except conductor portion 13a (FIG. 2). FIG. 2 shows the cross section of conductor 13a which, in this example, has -its long dimension running perpendicular to the plane of the drawing. Up to this point the structure and method of fabrication are entirely conventional and means for providing such structures are well known in the art. As shown in FIG. 3, conductor 13a is covered by interlayer dielectric 18, composed of a sandwich of three dielectric layers 14-16. Second conductor layer 17 lies on top of interlayer dielectric 18. For the arrangement illustrated in FIG. 3, conductor 17 may be thought of as a conductive stripe having its long dimension running parallel to the plane of the drawing. Thus, conductors 13a and 17 form a multi-conductor insulated cross-over. Such cross-overs are commonly desired in the art. Those of skill in the art will also understand that the multi-conductor structure need not be limited merely to two conductors. By repetition of the basic conductor-insulator sandwich, the final structure can be composed of three, four, five or more conductor layers.

The present invention is concerned particularly with the construction and formation of interlayer dielectric 18. It has been found, that when conventional oxides or nitrides are used to form a dielectric region between two conductors, that substantial loss in manufacturing yield is encountered due to breaks in layer 17 where it passes over conductor 13a and/or adhesion failures between interlayer dielectric 18 and conductors 13a and/or 17. These effects result in opens or shorts in the finished circuit.

It has been discovered that the manufacturing yield is substantially improved by the three layer dielectric sandwich shown in FIG. 3. First dielectric layer 14 is chosen to be a material which adheres tightly to first conductor 13a. Silicon oxide formed by plasma assisted deposition or by low pressure chemical vapor deposition has been found to be suitable. A Plasma-I type deposition reactor made by Applied Materials, Inc. of Santa Clara, California is a suitable plasma assisted oxide deposition apparatus. Typical depositions were performed with the substrate wafer support heated to about 300°C. Thickness 14a of layer 14 in the range 0.05-0.4 microns is useful with 0.1-0.2 microns being preferred. When thickness 14a was above about 0.4 microns, cracking of dielectric layer 14 was observed following a 400°C to room temperature thermal shock test. Second dielectric layer 15 is formed by a different method and material. Dielectric layer 15 is formed using a spun-on glass material. Spun-on glasses consist, typically, of silica bearing glass materials which are suspended in an organic carrier. Where substrate 11 is, for example, a semiconductor or other wafer, a drop of the glass-carrier mixture having a predetermined viscosity is placed on the center of the wafer and the wafer rotated at high speed. This causes the glass-carrier mixture to spread out in a thin film. However, one of the properties of such spun-on materials is that where the surface topography of the substrate is irregular, the spun-on material does not conformally coat the surface, that is, the thickness of the spun-on layer is not uniform. As illustrated in FIG. 3, spun-on glass layer 15 tends to accumulate in regions 15b at the edges of surface discontinuities so that the slope of layer 15 over such surface steps or discontinuities is substantially reduced. This provides a smoothing action which contributes to improved planarization of the surface. Arsenic doped spun-on glass material manufactured by the Allied Chemical Company of

Morristown, New Jersey is suitable. Useful spun-on glass materials and application procedures are also described in U.S. Patents 3,832,202 and 3,789,023 to Kim Richie, which are incorporated herein by reference. It is desirable that the spun-on glass be arsenic doped, however phosphorous doped or undoped spun-on glasses can also be used. The arsenic doped glass shows greater resistance to cracking and better survives thermal shock. In a typical example, a small quantity of the arsenic doped glass-carrier mixture was placed, on a silicon semiconductor wafer and spun at approximately 3000 RPM to form a thin layer. The spun- on layer was baked at about 450°C for one hour to form glass layer 15. Temperatures in the range 400-550°C can also be used. The baking temperature for the spun-on glass should not exceed the melting point of conductor 13a. Thickness 15a of glass layer 15 in the range 0.1- 0.4 microns is suitable, with 0.1-0.25 microns being preferred. When thickness 15a is above about 0.4 microns, cracking of spun-on glass layer 15 is observed after thermal shock. Hence, thicknesses greater than about 0.4 microns are not desirable. ^' As illustrated in FIG. 3, spun-on layer 15 provides a substantial smoothing action in regions 15b even though it amounts to only a relatively small fraction of the total thickness of interlayer 18.

Following the formation of spun-on glass layer 15, additional dielectric layer 16 is applied. Dielectric layer 16 is preferably formed by plasma assisted deposition or chemical vapor deposition. It has been found that deposited silicon dioxide is suitable. Layer 16, when formed of deposited silicon dioxide may be doped with 0-4 percent phosphorous.. It is desirable that layer 16 be formed at a temperature less than that used in the formation of layer 15. A four percent phosphorous doped silicon dioxide layer was typically deposited by LPCVD from a mixture of silane and oxygen at 360°C. Other higher or lower temperatures may be used provided they are less than th-e temperature used for the formation of layer 15. Thickness 16a of layer 16 is desirably several times greater than either thickness 14a or 15a, being adjusted so that total thickness 18a of layer 18 is sufficient to provide the desired degree of electrical isolation. For high density integrated circuits, thickness 18a is conveniently in the range of about 0.8 to 1.6 microns and thickness 16a is typically in the range 0.6-1.0 microns.

Conductor 17 is then applied over the top of dielectric 16. Conductor 17 may be of any suitable conductor material such as, but not limited to, metals, semiconductors, semi-metals, intermetallics, or composites thereof. Aluminum and/or aluminum (98%) - Copper (1%) - Silicon (1%) alloy were used with excellent results.

It has been discovered that adhesion layer 14 is essential to obtaining a high manufacturing yield in forming multi-layer conductor structures employing spun- on glasses. If layer 14 is not used, and spun-on glass layer 15 is located directly on conductor 13a, then a significant manufacturing yield loss due to delamination between conductor 13a and spun-on glass 15 is found to occur. This is particularly severe when conductor 13a is formed of aluminum or Al-Cu-Si alloy. When dielectric layer 14 formed, for example, by plasma deposition or low pressure chemical vapor deposition of silicon oxide, excellent adhesion both to conductor layer 13a and spun-on glass layer 15 is obtained. The completed structure showed no delamination when thermally shocked by heating the wafer to 400°C and then quickly placing it on a room temperature metal block to provide rapid cooling. The delamination effect is entirely overcome and the manufacturing yield is substantially improved.

Layer 16 is also essential. If layer 16 is omitted, then delamination is observed between spun-on glass layer 15 and second conductor layer 17. While dielectric layer 16 may be formed by the same general methods as used for layer 14, it has been found particularly convenient to use low temperature, low pressure chemical vapor deposition (LPCVD) of a phosphorous doped silicon oxide for layer 16. Typical conditions are deposition of a 0-4 percent phosphorous doped silicon oxide at temperatures in the range 300- 400°C from a mixture of silane and oxygen at low pressure. LPCVD is a technique well known in the art. The phosphorous doped silicon oxide may be readily etched using means well known in the art to provide through-holes with tapered sides. Since layers 14-15 are substantially thinner than layer 16, undercutting of layers 14-15 during etching of through-holes through layer 18 is reduced. Reactive ion etching using a thickness tapered resist mask is a preferred method for achieving tapered through-holes. The above-described means and methods provide structures which exhibit excellent step coverage, which are substantially free of delamination between the conductors and the dielectric interlayer, and which permit etching of tapered through- holes.

As used herein the words "plasma deposited oxide" or "plasma oxide" refer to formation methods for dielectric passivation layers which use gas plasma and/or gas discharge reactions to form dielectric films such as, for example, but not limited to, plasma assisted chemical vapor deposition. The invention has been illustrated for the situation where aluminum or aluminum alloy has been used as the metallization. It will be readily apparent to those of skill in the art, that other conductors can also be used. Accordingly it is intended to include these and other variations that are within the spirit and scope of the present invention in the claims which follow.

Claims

1. A semiconductor device having superposed multiple conductor layers, comprising: a semiconductor substrate; an insulating layer on said substrate; a first conductor layer on said insulating layer; a second conductor layer superposed above said first conductor layer and separated therefrom by a second insulating layer; and wherein said second insulating layer comprises a first dielectric adhesion layer on said first conductor layer, a spun-on glass layer on said first dielectric adhesion layer, and a second dielectric layer on said spun-on glass layer and in contact with said second conductor layer.

2. The semiconductor device of claim 1 wherein said first dielectric adhesion layer comprises plasma oxide.

3. The semiconductor device of claim 1 wherein said spun-on glass comprises an arsenic doped spun-on glass.

4. The semiconductor device of claim 1 wherein said first dielectric adhesion layer and said spun-on glass layer have substantially the same first thickness and said second dielectric layer has a second thickness about three to five times said first thickness.

5. A multi-conductor electronic device comprising: a first conductor layer; a first adhesion promoting dielectric layer on said first conductor layer; a spun-on glass layer on said first adhesion promoting layer; a second dielectric layer on said spun-on glass layer; and a second conductor layer on said second dielectric layer.

6. The electronic device of claim 5 wherein said first adhesion promoting dielectric layer and said second dielectric layer are formed by plasma assisted deposition or by chemical vapor deposition.

7. The electronic device of claim 5 wherein said spun- on glass comprises arsenic.

8. A process for forming electronic devices comprising: providing a substrate having a partially insulating surface; providing a first conductor layer on said substrate; covering said first conductor layer with an adhesion promoting dielectric layer; spinning a glass containing layer onto said adhesion promoting layer; heating said spun-on glass containing layer; covering said spun-on glass containing layer with a deposited dielectric layer; and forming a second conductor layer on said deposited dielectric layer.

9. The method of claim 8 wherein said heating step comprises heating to a temperature less than 500°C.

10. The method of claim 8 wherein said first covering step comprises covering said first conductor with an adhesion promoting layer formed by plasma assisted deposition or chemical vapor deposition, and wherein said second covering step comprises covering said spun- on glass containing layer by chemical vapor deposition or plasma assisted deposition.