WO1987006079A1 - Digital analogue signal conversion - Google Patents
Digital analogue signal conversion Download PDFInfo
- Publication number
- WO1987006079A1 WO1987006079A1 PCT/GB1987/000204 GB8700204W WO8706079A1 WO 1987006079 A1 WO1987006079 A1 WO 1987006079A1 GB 8700204 W GB8700204 W GB 8700204W WO 8706079 A1 WO8706079 A1 WO 8706079A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- digital
- analogue
- converter
- signal
- output
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/04—Analogue/digital conversion; Digital/analogue conversion using stochastic techniques
Abstract
A method of conversion of an imput of one of digital and analogue form in a converter (14) adapted to convert the input to the other of digital and analogue form comprises adding to the input a random signal of the one form, converting the summed signal, separately converting the random signal to the other signal form and subtracting it from the converter output of the summed signal, and varying the random signal such that conversion errors become random. Apparatus comprises a converter (4, 13), a random signal generator (7, 8, 14, 15) generating the random signal in each of digital and analogue form, means (3, 11) adding the random signal to the converter input, limiter means to prevent overflow, and means (5, 18) for subtracting the random signal from the converter (4, 13) output.
Description
"DIGITAL ANALOGUE SIGNAL CONVERSION" This invention relates to a method of an apparatus for improving the conversion of continuously varying' signals between digital and analogue forms using digital to analogue or analogue to digital conversion and is particularl but not exclusively useful in connection with audio systems. In conventional systems non-linearities and errors in conversion devices which may result from tolerance variation, ageing or partial failures impair the sound quality of an audio signal due to quant- isation error and irregularities in the conversion transfer characteristic over the range of conversion leading to an objectionable level of harmonic distortion.
It is an object to reduce the cyclic _ effects of quantisation error and irregularities in the conversion characteristic of continuously changing signals. According to the invention a method of operating a digital analogue conversion system comprising a converter adapted to convert a signal from an input of one of a digital and analogue signal to an output of the other of digital and analogue signal form consists in adding to the input signal a random or pseudo random signal of the same form limited to maintain the summ¬ ation of the signals within the capacity of the converter converting the summed signal, and separately converting the random signal to the other signal form and sub¬ tracting the added random signal from the converter output of the summed signal, and varying the random signal such that conversion errors become random.
Digital-analogue conversion apparatus according to the invention comprises a converter adapted to convert an input signal in one of analogue or digital
formto the other signal form,a randomor pseudo-random signal generator adapted to generate a random signal in the one of analogue or digital form, means for summing the input signal and the random signal and limiting the summed signal to the capacity of and supplying it to the convertor, and auxiliary convertor arranged to convert the random signal to the other signal form, and means arranged to subtract the auxiliary convertor output from the converted summed signal whereby the converted input signal includes random conversion error.
In a digital to analogue audio system for example a 16-bit system, an 8-bit random number is obtained from a digital pseudo random source and is added to the least significantbits of a 16-bit number at the begin- ning of a sample period. The result is limited to prevent overflow and is applied to the convertor input. Simultaneously the random number is applied to an auxiliary digital to analogue convertor to obtain the analogue value of the random number. The output of the main convertor is the 16-bit signal number plus the random number divided by 256. The random number output of the auxiliary DAC is inverted and divided by 256, then added to the main convertor output such that the component due to the random number is taken away.
This leaves the analogue conversion of the input 16-bit number plus a voltage due to conversion error. Since errors in the convertor are input dependant and distributed, each new sample gives rise to a different error voltage due to the random number
applied and the resulting different conversion level. This results in the generation of random noise at a peak level equal to the maximum error in the convertor device. When signal is applied to the input of the system, the effect of the changing signal is constantly to modify the distribution of the errors and thus the random noise distribution. Since the errors are random and the range of the noise is "ery large with respect to the error differences (i.e. noise = 256 error<1) the noise remains essent¬ ially incoherent and therefore the changes in distrib¬ ution due to signal are inaudible. The signal is thus relieved of the harmonic distortion that would normally result from the quantisation non-linearity of the conversion.
In this system it is possible to obtain response to signals at levels less than the least significant bit by adding more resolution in bits to the adding stage. Lesser bits will be added to the random number and give a result in the range of the convertor.
Large numbers of error levels of less than one least significant bit (LSB) are being generated and these are effectively modulated by sub LSB values to eliminate the eventual drop-out of reducing signals. If extremely linear convertors are used the nulling effect of injected noise can be in excess of the device's resolution. In this case a dynamic performance in excess of the device's resolution can be achieved. If, for example, device errors are less than 1 LSB then 17-bit performance is possible
from a 16-bit convertor.
When the magnitude of the injected random number is decided consideration has to be given to the quality of the convertor used, the noise modulation tolerable, and the loss of dynamic range as a result of accommodat¬ ing the width of the random value in the total range of the convertor. 8-bits is a suitable compromise with respect to presently available devices.
In an analogue to digital conversion an.equivalent system is employed except that a rand n analogue signalis added to the analogue input to an analogue to digital convertor, and the randan signal is subtracted from the output digitally. The random signal is suitably generated in a pseudb random digital number, generator and converted by a DAC to analogue form. The advantages are the same as in the case of the DAC. In general the ADC suffers more from errors caused by layout and ground loop potentials, and the system offers a vast reduction in problems of this type, bearing in mind however that errors, however caused, will still give rise to increased residual noise in the system output.
As in the DAC a useful output in excess of 16 bits may be produced by adding lesser significant bits of the random number into the adding stage. And the system will resolve coherent signals far below the maximum resolution of the device employed.
The invention will nowbe described, by way of example, with reference to the accompanying partly diagrammatic drawings, in which:- Figure 1 is a block diagram of an analogue to
digital converter (ADC) system according to the invention, *
Figure 2 is a block diagram of a digital to analogue converter (DAC) system according to the invention.
Figure 3 is a circuit diagram of an analogue to digital converter according to the invention, and
Figure 4 is a circuit diagram of a digital to analogue converter according to the invention. In the system of Figure 1 an analogue audio input signal 1 is supplied via an input sampling circuit 2 and an adder unit 3 to an analogue to digital conv¬ enor 4 supplying a 16-bit digital output to the upper bit inputs of an adder unit 5 outputting via a limiter 6. Adigital pseudo randomnumber generator 7 outputs an 8-bit signal to the lower bit inputs of the adder unit 5, bit inputs between the lower 8 and the upper 16 being co moned to logic zero. The output of the random number generator 7 is also via a digital to analogue convertor 8, an invertor 9 and a divider 10 to the adder unit 3 whereby the inverted signal divided by 256 is added to the sampled input signal, and the limiter is arranged to prevent overflow. In use the sampled analogue input signal 1 is reduced by the analogue equivalent of the random number output of the generator 7, divided by 256, and the reduced analogue signal converted to a 16- bit digital signal to which the random number output of generator 7 is added to remove the random number content of the output from the limiter 6.
Due to the random signal content of the input to the convertor 4, conversion errors due to non- linearity or errors in the convertor 4 are varied
« between successive sample signal conversions, and errors in the output are random.
A trimmer is suitably provided at the divider 10 so that the divided analogue noise can be trimmed to null residual noise in the output.
In the digital to analogue system of Figure 2 a 16-bit digital input signal 10 is applied to the upper bit inputs of an adder unit 11 outputting via a limiter 12 to a digital to analogue convertor
13. An 8-bit pseudo-random number generator 14 outputs to the lower bit inputs of the adder unit 11 and via a digital to analogue convertor 15, an invertor 16 and divider 17 to an adder unit 18 where it is added to the output of the convertor 13 and fed to a deglitch and output circuit 19. The limiter 12 is arranged to prevent overflow. Bit inputs of the adder unit 11 between the upper bit and lower bit inputs are connected to logic zero. The divider unit 17 is adapted to divide the inverted random audio signal by 256 so that the output of the adder unit 18 is without the component due to the random number added to the input signal and the output of the adder unit is the audio conversion of the digital input to the convertor 13 plus a voltage due to the error incurred in the convertor 13.
Since the errors of the conversion are input dependant and distributed, each new sample gives rise to a different error voltage due to the random number applied and the resulting different conversion level. When successive signal samples are applied to the input, the effect of the changing signal value is constantly to modify the distribution of the errors and thus the random noise distribution. Since the
errors are random and the range of the noise very large with respect to the error differences, i.e. noise = 256 error 1 , the noise remains essentially incoherent and therefore the changes in distribution due to input signal are inaudible. As a result the output signal is relieved of harmonic distortion that would normally result from quantisation non- linearity of the conversion.
Also it is possible to obtain response to signals at levels less than the least significant bit, by adding more resolution in bits to the adding stage. Lesser bits will be added to the random number and give a result within the range of the convertor 13. Large numbers of error levels of less than 1 LSB (one least significant bit) are being randomly generated and these are effectively modulated by sub LSB values to eliminate the eventual drop-out of reducing signals.
If extremely linear convertors are used the nulling of injected noise can be in excess of the devices resolution, in which case a dynamic perform¬ ance in excess of the device's true resolution can be achieved, e.g. if device errors are less than 0.5 LSB, 17-bit performance is possible from a 16- bit convertor. It will be understood that due to the accommodation of the random number 1 in the convertor there is a loss of dynamic range. Thus in selecting the size of the random number a balance needs to be struck between the quality of the convertors used, the noise modulation tolerable and the potential loss of dynamic range. An 8-bit random number is a reasonable compromise with respect to presently available devices.
The invention is particularly useful in audio systems where randomising conversion errors to produce random noise which is incoherent to and may be ignored by a listener and is more acceptable than the harmonic distortion that would otherwise result. The invention may also be applied in conjunction with time averaging circuitry to produce output signals of improved absolute accuracy.
In the circuit diagram of Figure 3, the random noise generator comprises integrated circuits IC19, IC20 and IC21, suitably 74 HCT164, and IC22 arranged in conventional manner to generate an 8-bit random number which is fed to the lower bit inputs of the adder unit comprising integrated circuits IC9, IC10, IC11 and IC12 arranged in conventional manner and out- putting via overflow limiters IC13 to IC16 to buss registers comprising integrated circuits IC17 and IC18, suitably 74HCT374 outputting to a 16-bit data buss. One input to the integrated circuit IC22 is via a capacitor and is coupled to logic to enable the random number generator to start. The 8-bit output of the random noise generator is supplied to the upper bit inputs of an auxiliary digital to analogue converter comprising an integrated circuit IC24, suitably AD7541, outputting an analogue signal in conventional manner through integrated circuit IC27 suitably LF351, and a variable resistor VRl to the internal comparator input of the analogue to digital converter IC8 where, due to the internal arrangement of IC8 the noise input is added in an inverse sense to the digital output of the convert¬ er IC8. The variable resistor VRl provides for nulling control whereby matching of the inverse of the analogue noise and the digitally added noise may be obtained.
-9-
The audio input to IC8 is via a conventional buffering circuit comprising integrated circuit IC7 outputting through transistors TR11, TR12, suitably BC182LB, and TR15 and TR16 suitably BC212LB. In the circuit diagram of Figure 4, an 8-bit random digital number generator comprising integrated circuits IC19, IC20, IC21 and IC22, suitably 74HCT164 and arrayed, as in the Figure 3 embodiment, outputs to the lower bit inputs of a digital adder unit comprising integrated circuits IC9, IC10, IC11 and IC12, suitably 74HCT283, outputting through overflow limiters IC13, IC14, IC15 and IC16, suitably 54LS32 to the inputs of a 16-bit digital to analogue converter comprising integrated circuit IC8, suitably PCM53JP-V, outputting an analogue signal through integrated circuit IC6, suitably 5534, arranged as an operational amplifier adapted to divide by 2 and provide an inverse adding point for analogue noise.
A data buss inputs through buffering integrated circuits IC27 and IC28, suitably 74HCT374 coupled to an address decoding circuit comprising integrated circuit IC25, suitably 74HCT85 and integrated circuits IC23, suitably 74L508, to buss registers comprisinσ integrated circuits IC17 and IC18, suitably 74HCT374, inputting to the upper bit inputs of the adder unit integrated circuits IC9, IC10, IC11 and IC12.
The output of the random number generator is applied to 8-bit inputs of an auxiliary digital to analogue converter comprising an integrated circuit comprising IC24, suitably AD 7541 ouputting via integrated circuit IC26, suitably LF351 to the inverse adding point of the operational amplifier IC6 whereby the audio equivalent of the random number is removed from the audio output.
Claims
1. A method of operating a digital analogue conversion system comprising a converter (4,13) adapted to convert a signal from an input of one of a digital and analogue signal to an output of the other of digital and analogue form comprising adding to the input signal (1,10) a random or pseudo random signal (7,14) of the same form limited to maintain the summation of the signals within the capacity of the converter (4,13), converting the summed signal, and separately converting (8,15) the random signal to the other signal form and subtracting (5,18) the added random signal from the converter output of the summed signal, and varying the random signal such that conversion errors become random.
2. Digital analogue conversion apparatus comprising a converter (4,13) adapted to convert an input (1,10) in one of analogue or digital signal form to an output of the other signal form, means (7,8,14,15) for generating a variable random or pseudo random signal in each of digital and analogue form, means (3,11) for adding the random signal in the one of analogue or digital form to the input (1,10) , means for maintaining the summation of the signals within the capacity of the converter (4,13), andmeans (5,18) fo subtracting the random signal in the other of analogue and digital form from the output of the converter (4,13) . 3. Apparatus as claimed in claim 2 comprising an analogue to digital converter (4) in which a pseudo random number generator (7) outputs via a digital to analogue converter (8) to an analogue adder unit (.
3) where it is added to an analogue input signal (l) and the added signals supplied to the analogue to digital converter (4) supply¬ ing its output to the upper bit inputs of a digital adder unit (5) outputting via a limiter (6) arranged to prevent overflow, the pseudo random number output (7) being supplied to the lower bit inputs of the digital adder unit (5).
4. Apparatus as claimed in claim 3 in which the input to the analogue to digital converter (4) is via an input and sampling circuit (2) preceding the analogue adder unit ( 3) .
5. Apparatus as claimed in claim 3 or claim 4 in which the pseudo random number generator (7) is an 8- bit number generator, the analogue to digital converter unit (4) supplies a 16-bit digital output, and bit inputs of the digital adder unit (5) between the upper 16 and lower 8 are commoned to logic zero.
6. Apparatus as claimed in any of claims 3-5 in which the output of the auxiliary digital to analogue converter ( 8) is supplied to the analogue adder unit (3 ) via an inverter and divider (9) adapted to divide by 256.
7. Apparatus as claimed in any of claims 3-6 in which the divider (9) is provided with a trimmer (VRl) whereby the divided analogue output may be trimmed to allow for null residual noise in the digital output.
8. Apparatus as claimed in any of claims 3-7 in which the converter (4) has a linearity with errors of less than 0.5 least significant bit.
9. Apparatus as claimed in claim 2 comprising a digital to analogue audio system in which the pseudo random source (14) is a random digital number generator arranged to supply a digital output to an adder unit (11) for addition to the least significant bits of a digital input signal (10) the adder unit (11) outputting to a limiter (12) arranged to prevent overflow and outputting to a digital to analogue converter (13) having an output to an analogue adder unit (18), the pseudo random source (4) also outputting through an auxiliary digital to analogue converter (15) via an inverter and divider unit ("16) to the analogue adder uni t (18) such that the random component is taken away from the analogue output of the converter (13). -12-
10. Apparatus as claimed in claim 9 in which the pseudo random source (14) is adapted to generate a variable 8-bit random number and the input to the_ digital to analogue converter (13) is a 16-bit number whereby the output of the digital to analogue converter (13) is the sum of the 16-bit input number plus the random number divided by 256, the divider unit (17) being adapted to divide the random number by 256.
11. Apparatus as claimed in claim 10 in which the linearity of the digital to analogue converter (13) is such that errors are less than 0.5 least significant bit.
12. Apparatus as claimed in any of claims 9-11 in which bit inputs of the digital adder unit (11) between upper and lower bit inputs are connected to logic zero.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8607553 | 1986-03-26 | ||
| GB868607553A GB8607553D0 (en) | 1986-03-26 | 1986-03-26 | Digital analogue signal conversion |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO1987006079A1 true WO1987006079A1 (en) | 1987-10-08 |
Family
ID=10595294
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/GB1987/000204 WO1987006079A1 (en) | 1986-03-26 | 1987-03-25 | Digital analogue signal conversion |
Country Status (2)
| Country | Link |
|---|---|
| GB (1) | GB8607553D0 (en) |
| WO (1) | WO1987006079A1 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2642589A1 (en) * | 1989-01-28 | 1990-08-03 | Forschungszentrum Juelich Gmbh | ASSEMBLY COMPRISING AN ANALOGUE / DIGITAL DIVIDER CONVERTER |
| GB2227896A (en) * | 1989-02-03 | 1990-08-08 | Standard Telephones Cables Ltd | Analog-to-digital converter |
| EP0430449A2 (en) * | 1989-11-27 | 1991-06-05 | Hewlett-Packard Company | Method and apparatus for linearizing the output of a digital-to-analog converter |
| GB2250148A (en) * | 1990-11-15 | 1992-05-27 | Sony Corp | Conversion between analog and digital signals |
| WO1997040645A1 (en) * | 1996-04-22 | 1997-10-30 | Cardinal Sound Labs, Inc. | A directional hearing system |
| DE19720548A1 (en) * | 1997-05-16 | 1998-11-19 | Rohde & Schwarz | A=D converter esp. for large scale dithering |
-
1986
- 1986-03-26 GB GB868607553A patent/GB8607553D0/en active Pending
-
1987
- 1987-03-25 WO PCT/GB1987/000204 patent/WO1987006079A1/en unknown
Non-Patent Citations (2)
| Title |
|---|
| ELECTRONICS INTERNATIONAL, Volume 53, No. 20, 11 September 1980, (New York, US), L.M. LOWE, "8-Bit a-d Converter Has 12-Bit Linearity", pages 171-172. * |
| THE BELL SYSTEM TECHNICAL JOURNAL, Volume 51, No. 6, July-August 1972, (New York, US), N.S. JAYANT et al., "The Application of Dither to the Quantization of Speech Signals", pages 1293-1304. * |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2642589A1 (en) * | 1989-01-28 | 1990-08-03 | Forschungszentrum Juelich Gmbh | ASSEMBLY COMPRISING AN ANALOGUE / DIGITAL DIVIDER CONVERTER |
| GB2227896B (en) * | 1989-02-03 | 1993-01-13 | Standard Telephones Cables Ltd | Digital converters and methods of reducing conversion errors therein |
| AU623462B2 (en) * | 1989-02-03 | 1992-05-14 | Alcatel Australia Limited | Digital converter |
| GB2227896A (en) * | 1989-02-03 | 1990-08-08 | Standard Telephones Cables Ltd | Analog-to-digital converter |
| EP0430449A2 (en) * | 1989-11-27 | 1991-06-05 | Hewlett-Packard Company | Method and apparatus for linearizing the output of a digital-to-analog converter |
| EP0430449A3 (en) * | 1989-11-27 | 1993-05-12 | Hewlett-Packard Company | Method and apparatus for linearizing the output of a digital-to-analog converter |
| GB2250148A (en) * | 1990-11-15 | 1992-05-27 | Sony Corp | Conversion between analog and digital signals |
| US5148163A (en) * | 1990-11-15 | 1992-09-15 | Sony Corporation | Digital to analog conversion circuit with dither and overflow prevention |
| GB2250148B (en) * | 1990-11-15 | 1994-06-08 | Sony Corp | Conversion between analog and digital signals |
| WO1997040645A1 (en) * | 1996-04-22 | 1997-10-30 | Cardinal Sound Labs, Inc. | A directional hearing system |
| US5793875A (en) * | 1996-04-22 | 1998-08-11 | Cardinal Sound Labs, Inc. | Directional hearing system |
| DE19720548A1 (en) * | 1997-05-16 | 1998-11-19 | Rohde & Schwarz | A=D converter esp. for large scale dithering |
| US6064328A (en) * | 1997-05-16 | 2000-05-16 | Rohde & Schwarz Gmbh & Co. Kg | Analog/digital converter with small crest factor dither signal superposed at an input side |
| DE19720548C2 (en) * | 1997-05-16 | 2003-07-10 | Rohde & Schwarz | Analog / digital converter |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8607553D0 (en) | 1986-04-30 |
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