WO1988008617A1 - Buried well dram - Google Patents

Abstract

A memory storage device comprising a layer of semiconductor material having an access field effect transistor (10) and a storage region (16) formed within the semiconductor. The storage region (16) is electrically isolated from the channel region of the access FET (10) so as not to affect operation of the access FET at normal operating voltages. The storage region of the DRAM is accessed by applying a voltage to the gate (21) of the access FET of a polarity to electrically connect the channel region to the storage region (16).

Description

"BURIED WELL DRAM"

This invention relates, in general, to memory storage devices, and in particular to a single transistor compound semiconductor dynamic random access memory (DRAM) .

Computers and other information processing and control systems depend upon the rapid storage and retrieval of digital information. There are many forms of storage media, including magnetic and optical storage devices. However, the most versatile memory device that is most compatible with other electronic devices in both large and small systems is a semiconductor memory. The most compact semiconductor memory system known comprises a simple one-transistor storage cell that is used to read, write, and hold information: Such one-transistor memories are manufactured in the form of metal oxide field-effect transistors (MOSFET) with an integrated storage capacitor. This MOΞFET technology is implemented using silicon and its oxide, silicon dioxide. Silicon dioxide is an excellent insulator and can also serve as a mask for various processin steps.

The speed of a computer or other semiconductor based processing system is ultimately dependent upon the charge carrier mobility of the devices that comprise the computer or system. Silicon based devices are widely used due to their relative ease in fabrication. However, there are other materials that have inherently higher charge carrier mobility than silicon. These materials include compound semiconductors of III-V and II-VI elements. One such material is gallium arsenide. Gallium arsenide, due to its high carrier mobility,

- L is particularly useful in fabricating integrated circuits that operate in the microwave frequency range. In addition, gallium arsenide devices theoretically require less voltage to achieve saturation, thereby, in principle, requiring less energy for operation. However, gallium arsenide is more brittle than silicon and is otherwise more difficult to process. Gallium arsenide also has no native oxide and so cannot be simply substituted into the MOSFET technology of silicon that allows for one-transistor memory devices. As

10 such, there remains a desire and an unfulfilled need for a one-transistor gallium arsenide dynamic random-access memory.

Another drawback is the number of uncontrollable defects, such as anti-site, defects in current gallium arsenide crystals. Such defects are common to compound

15 semiconductors of groups I I-V and II-VI. These defects in the crystal lattice respond to thermal energy and generate electron-hole pairs. It is thought that the generation of such pairs limit the memory applications of compound semiconductors because storage time is inversely proportioned

20 to such thermal generation. number of prior art devices are described in, "A Survey of High-Density Dynamic RAM Cell Concepts", P. K. Chatterjee, et al. , IEEE Transaction on Electron Devices, Vol. ED-26, No. 6, June, 1979. At pages 830, 831 there is

25 described a punch through RAM cell device. That device appears to be a bipolar device with an n-doped source underneath a p-doped gate. The source is accessed by punch through from the gate and the source and the gate are in contact. The source is contactless and the device has been

30

35 ^' criticized by others for a difficulty in fabrication and reliability. See, "ONE-DEVICE CELLS FOR DYNAMIC RANDOM-ACCESS MEMORIES: A TUTORIAL", IEEE Transaction on Electron Devices, Vol. ED-26, No. 6, June, 1979, Page 849.

Another device, similar to the punch through device discussed above, is shown in U.S. Patent 4,328,511. There is shown an n-channel MESFET with a p-junction substituted for the metal gate. That device provides for a potential well 35 on the upper surface of the device. Holes can be captured or expelled from the surface well. The presence or absence of holes in the well on the surface controls the conductivity of electrons through the channel under the gate. Holes in the surface gate well will increase the current flowing from source to drain for a given voltage. In effect, the device functions like a MESFET device except that the gate is a p-n junction rather than a metal-oxide junction. SUMMARY OF THE INVENTION

The invention provides a one-transistor compound semiconductor dynamic random-access memory device. In its broader aspects, the invention provides a memory device having a single access transistor and a storage region made from a compound semiconductor. Charges are stored in the storage region that is appropriately doped to provide a potential barrier at the boundaries of the storage region.

In one embodiment, the storage region is provided by a buried well that lies close to but out of normal electrical contact with the access field effect transistor (FET) . The buried well has no effect upon the normal operation of the FET. However upon suitable application of a voltage to the designated surface electrode, the buried well can be accessed. Once the buried well is accessed, information stored in the well may be extracted and read or new information may be written. In one version of the

-.1 invention the access voltage is reduced by extending the surface electrode close to but still spaced from the buried well. As such, the necessary voltage for accessing the well is reduced by bringing the electrode physically closer to the well. Further embodiments of the invention provide for adapting the invention to MODFET, JFET and MESFET technologies and to provide nondestructive MODFET, JFET and MESFET DRAMS.

In another embodiment, the storage region is

10 provided by a floating drain region that is charged when the access FET is turned on and stores that charge when the FET is turned off. There is no ohmic contact to the floating drain of the device as the source electrode acts as both the source and drain of the access FET. The storage and

15 discharge of the floating drain is controlled by the gate electrode. The floating drain DRAM may also be implemented in MODFET, MESFET and JFET technologies.

It was expected that anti-site and other electron- hole regeneration defects would reduce memory storage times.

20 In contrast, the inventors found that the storage times of compound semiconductor wells and floating drains match those of silicon based devices. The inventors believe these unexpected results are due to the larger energy bandgap of compound semiconductors. For one compound semiconductor, -^> gallium arsenide, the bandgap is about twenty percent (20%) greater than the bandgap of silicon. However, the generation of electron-hole pairs due to defects is inversely exponentially proportional to the bandgap. So, it is believed the larger bandgap contributes to the suppression of

30 the memory reducing side effects of defects. It appears likely that the suppressive effects of even a slightly larger bandgap far outweigh the thermal generated memory defects.

5 In the buried well embodiment, charge carriers in the well are confined by a potential barrier whose boundaries or depth are controlled. Charge carriers stored in the well are extracted by electrically lowering the potential barrier surrounding the well. The barrier is lowered by adjusting the voltage on an electrode, i.e., a drain, disposed above the well. The voltage on the drain is adjusted to expand the depletion region beneath the drain sufficient to punch through an intermediate layer to access the well. When that occurs, any carriers stored in the well flow out to the drain electrode.

When the well carriers reach the surface or drain electrode, the voltage on the electrode will be changed, thus indicating the presence of carriers in the well. If there are no carriers in the well, the voltage on the electrode after punch through remains unchanged. By designating one condition a binary "1" and the other condition a binary "0", the buried well functions as a memory device accessed by a single transistor.

Still more specificaiiy, the invention provides a gallium arsenide based memory storage device having a MODFET access transistor that includes properly doped layers of gallium arsenide and a layer providing a barrier to charge flow, typically of aluminum gallium arsenide. The AlGaAs barrier layer may be doped or undoped. ' If doped, the transistors so formed are commonly called HEMTs. If undoped, the transistors are commonly called HIGFETs or SISFETs. In this specification, the term MODFET is used as a generic term for all these devices, whether or not the AlGaAs barrier is doped. A first, upper, surface layer comprises a layer of gallium arsenide that is heavily doped with a charge carrier of one polarity, e.g. n-doped. Beneath the surface layer is an insulating layer of aluminum gallium arsenide. Below the aluminum gallium arsenide layer is a third layer of gallium arsenide that is lightly doped with charge carriers of a

-3. polarity opposite to the first layer. Within the third layer is a region, completely surrounded by the third layer, and comprising a buried well of gallium arsenide that is doped the same as the first layer of gallium arsenide. The foregoing layers are all deposited and carried on a substrate of gallium arsenide. Thus, a sectional view of the device reveals a heavily doped surface layer of one polarity that is the same as the polarity of a buried well region. The well is buried in a material that is lightly doped and of an

10 opposite polarity. A barrier layer separates the first layer from the layer that contains the buried well.

In fabricating the invention described above, portions of the top two layers are removed, to form a residual gate electrode from the first layer and provide

15 regions on the third layer for a source and a drain. The latter are formed by suitable n-doping ion implantation. The buried well is formed during epitaxial growth of the second layer. The buried well is laterally defined by either ion implantation or selective etching. The buried well is read 0 or otherwise accessed by taking the gate of the device to a positive voltage sufficient to punch through to the buried well. The punch through is accomplished by expanding the depletion region underneath the gate. Writing or filling the buried well is accomplished by injecting electrons from the -³ n-doped gallium arsenide surface electrode in conjunction with suitable control of the voltage on the gate electrode.

In one of the preferred embodiments of the invention, the buried well is disposed beneath the drain and the drain electrode is disposed deeper in the second layer 0 than is the source. The extra depth of the drain will bring it physically closer to the buried well. Such physical

5 'closeness will reduce the amount of voltage required to

-.1 access the buried well. That reduction in voltage is desirable in order to conform the invention to existing voltage criteria for accessing memory devices. The reading operation is accomplished in the same manner as previously described. Writing in the well is a two-step process. First electrons are allowed to flow from the source into a surface inversion layer beneath the gate. Then the drain is isolated from the source and a further voltage is applied to the drain to inject the surface electrons into the buried well. 0

In further embodiments of the invention, the access transistor is provided as a MESFET or a JFET implementation. In the MESFET device, there is no barrier layer. Instead, the metal electrodes are deposited directly on a doped upper gallium arsenide layer. In the JFET device, the gate 5 electrode is a layer of heavily doped GaAs deposited on the upper GaAs layer and has an opposite conductivity as the upper layer. A metallic oh ic contact is then deposited to the gate electrode layer.

The invention may also be embodied in a 0 nondestructive read MODFET, MESFET or JFET DRAM. In such a device, the surface MODFET, MESFET or JFET includes a single charge carrier transistor of one polarity. That transistor is carried on a layer of gallium arsenide of an opposite polarity. The storage region includes a section within the 5 opposite doped layer of a highly opposite doped region. So, for example, an n-channel MESFET will be mounted on a lightly doped p-channel layer that contains a highly doped p-well.

In equilibrium, the p-well is filled with holes and the channel is filled with electrons. This condition is deemed a "1". A "0" is written by removing holes. from the well. Holes are rendered by applying a negative bias to the gate. That causes holes to flow out of the well onto the gate of the DRAM and leaving fewer holes in the well. The smaller number-of holes in the p-well depletes electrons from the n-channel causing a high resistance between the source and the drain. The presence of this high resistance is sensed and signifies a "0".

Still another embodiment of the invention implements a nondestructive readout DRAM having separate hole source and hole drain contacts.

The invention thus provides a single transistor DRAM of a compound semiconductor material. The material is selected from suitable group III-V or group II-VII combinations, including, but not limited to, gallium arsenide, aluminum gallium arsenide, zinc sellenide, indium gallium arsenide, and others. The invention thus provides a single transistor DRAM without the need for an oxide or insulating layer, as required in the traditional MOSFET technology. Brief Description of the Drawings

Figure 1 is a schematic sectional view of a combined MODFET and buried storage cell;

Figure 2 is a schematic sectional view of a complete MODFET DRAM?

Figure 3 is the embodiment of Fig. 2 in a reading operation;

Figure 4 is the embodiment of Fig. 2 in a writing operation_?

Figure 5a is a sectional material schematic diagram;

Figure 5b - 5f are a series of energy band diagrams;

Figure 6a - 6e are a series of schematic sectional views of a deep drain MODFET DRAM with separate transfer and read/write gates showing equilibrium, read, and write operations; * - Figure 7 is a schematic sectional view of a MESFET

- .1 DRAM;

Figure 8a - 8c are a series of energy band diagrams showing the equilibrium, read and write operations of the MESFET DRAM of Fig. 7;

Figures 9, 9(a), 9(b) and 9(c) are schematic sectional views of floating drain MESFET DRAMS:

Figure 10 is a schematic sectional view of a nondestructive read MESFET DRAM;

Figure 11a - lid are a series of energy band 0 diagrams showing the equilibrium, read and write operations of the MESFET DRAM of Fig. 10;

Figure 12 is a modified version of the MESFET DRAM of Fig. 10; and

Figure 13 is another nondestructive read MESFET 5 DRAM.

Figures 13a and 13b are side and end views of a surface drain nondestructive read MESFET.

Figure 14 is a sectional view of a DRAM having a direct access contact to the buried well. 0 Detailed Descriptions of the Embodiments

With reference to Figure 1 there is generally shown a DRAM 1 having a buried storage well formed under a single gallium arsenide gate heterojunσtion field-effect transistor 10. The transistor 10 is fabricated with an undoped gallium 5 arsenide substrate 14. On top of substrate 14 a layer 15 of lightly p-doped gallium arsenide is grown by molecular beam epitaxy. On top of layer 15 a next layer 16 of heavily n-doped gallium arsenide is formed. Layer 16 is likewise grown by molecular beam epitaxy. On top of layer 16 a next 0 layer 17 of lightly p-doped GaAs is grown by MBE. On top of layer 17 a next layer 20 of AlGaAs is grown by MBE. On top of layer 20 a final layer 21 of heavily n-doped GaAs is grown by MBE. Layers 21 and 20 are subsequently etched to selectively expose the top of layer 17 for further processing.

Using a deep p-type ion implant, regions 18 and 19, the boundaries of layer 16, are well defined and isolated from the surrounding material. Alternatively, layer 16 may be defined and isolated by etching to remove the regions 18 and 19. Heavily doped n-type source and drain regions 11, 13 are formed by ion implantation. Gate contact 12 is affixed to the upper gate layer 21.

As such, the layer 16 forms a buried well under transistor 10. Layer 16 is doped the same as layer 21 of the gate. Layer 16 is surrounded by and completely enclosed in a volume of material of a doping opposite to the buried well layer 16. In transistor 10, the n-doped layer 16 is surrounded by p-doped material in layers 15 and 17 including the p-implant regions 18, 19. The dimensions and the doping of the transistor iθ are similar to the dimensions and doping used or a conventional gallium arsenide gate heterojunction field-effect transistor. Having the buried n-well 16 below the gate 12 will not affect the transistor 10. A typical depth of the n-well 16 is on the order of 0.75 microns. At that depth, the mobility of the electrons at the interface of layers 20 and 17 is not affected. Moreover, the n-well 16 is deep enough so it will not short out the source and drain regions 11, 13.

In the transistor 10, there is thus shown, in effect, a dynamic random-access cell. The buried well 16 is. not in electrical contact with the source, gate or drain electrodes 11, 12, 13 under normal operating voltages. However, by adjusting the voltage on the source or drain, one connects the buried well 16 to the source or drain thereby altering the voltage on the source or drain. - - The transistor 10 functions as a dynamic

-.1 random-access memory in the following manner. Electrons are abundantly present in the highly doped buried well 16. The electrons in well 16 can be read out by taking a surface electrode, e.g., in drain 13 or source 11, sufficiently positive. For high positive values the surface depletion region under the selected electrode will extend through layer 17 beneath the gate and punch through to the buried well 16. Once punched through, the electric field in the well 16 is raised so that it is no longer negative. As such, the 0 barrier on its surface with adjacent layer 17 is removed and electrons are free to flow from the buried well 16 to the surface where they are collected by the selected surface electrode 11 or 13. Thus, by monitoring the voltage on the selected surface electrode one can detect the presence or 5 absence of the charge stored in buried well 16.

The writing function is accomplished by injecting electrons from one of the surface electrodes into layer 17 where they are collected in the buried well 16. Injection is accomplished by applying a negative voltage to a surface 0 electrode 11 or 13.

A problem encountered with dynamic RAMs is the possibility of loss of stored information. Loss may occur through two mechanisms. One is escape or recombination of stored electrons from a full well 16._^ The other is the 5 filling of an empty well 16 by thermal generation of electron-hole pairs in or near the buried well 16. These losses can be controlled by erecting suitable potential barriers. Electrons can be prevented from escaping the well by making the well deep enough in voltage, i.e. 1-2 electron 0 volts. The emission rate of electrons from the buried well 16 goes down exponentially as the potential barrier increases. The loss of electrons by recombination with holes

-.1 in layer 17 and 15 will be small since the hole doping that surrounds layer 16 is relatively light. Likewise, holes are excluded from the region by the potential barrier in the valance band. This barrier is made quite large, 1-2 electron volts. It has been found that the filling of empty wells 16 by thermal generation is a slow process because the band gap of gallium arsenide is 1.4 electron volts.

Another embodiment of the single access transistor DRAM of the invention is shown in Fig. 2 , including a

10 separate read/write gate. There is shown a DRAM 2 that includes an access transistor 10' . The transistor 10' includes a gallium arsenide substrate 34 and a lightly p-doped layer 30. Inside the lightly p-doped layer 30 is a highly n-doped layer or buried well 31. A source region 25

15 of highly n-doped material is formed on the surface of layer 30 by suitable processes, for example, ion implantation. Source contact 22 is in electrical contact with source region 25. It will be understood by those skilled in the art that source region 25 functions both as the source and drain of 0 the access transistor 10' of DRAM 2, depending on the direction of current flow through region 25. There are two gates, a transfer gate 23 and a read/write gate 24. The gates 23, 24 are made of highly n-doped gallium arsenide and have contacts 26 and 27 extending therefrom. Lower layers 5 28, 29 of aluminum gallium arsenide are provided between the gate layer and the layer 30. By suitably adjusting the voltage applied to transfer and read/write gates 23, 24, electrons 32 in a depletion region 33 can be directed laterally between the two gates or to the source 25. A more 0

5 ^•positive voltage on gate 24 than gate 23 will cause electrons

^■J. to travel from the source to gate 24, while a more positive voltage on gate 23 with respect to gate 24 will cause electrons to flow in the opposite direction. The buried well 31 has a large number of charge carriers, electrons, that are retained in the well 31 by the potential barrier provided by the surrounding p-doped volume of layer 30.

Turning to Fig. 3, electrons within the well 31 are extracted ("read") by imposing a high enough positive voltage ( pt) on one of the gates 23, 24 in order to extend the 0 depletion region 33 until it meets the corresponding depletion region 33' associated with the buried well 31. The voltage, pt, is positive and greater than the normal supply voltage. In the illustrative embodiment of Figure 3, Vpt is applied to gate 24 while gate 23 is kept at zero. This 5 meeting of depletion regions is commonly termed "punch through". Upon punch through, electrons stored in the buried well 31 will flow out of the well 31 to the region underneath the read/write gate 24. The lack of potential on gate 23 . isolates the depletion region 33 under the gate 24 from the 0 source region 25 during punch through. After punch through, a voltage is again applied to gate 23 which causes the electrons 32 to travel toward the source to produce a voltage. A separate monitoring circuit (not shown) detects change in source voltage to thereby "read" the DRAM 2. In an 5 integrated DRAM of multiple devices 2, the sources 25 would be connected together to form a common bit line.

With reference to Fig. 4, information is written into the buried well 31 by injecting electrons 32 from underneath the read/write gate 24. To this end, the 0 read/write gate 24, which is normally at a positive value, is driven towards zero. As the voltage on the gate 24 approaches zero, electrons are expelled from underneath the gate and are forced into the buried well 31. Once inside the well 31, the electrons remain trapped there by the surrounding potential barrier of layer 30. It may require several cycles of driving the gate 24 toward zero in order to store sufficient electrons into buried well 31 in order to practically store the charges therein.

The reading and writing operations described above are perhaps better understood with reference to the series of drawings shown in Figs. 5a-5e. Fig. 5a is a schematic cross-sectional view taken along the dashed lines indicated by V in Fig. 3. The Figures 5b-5e are energy band diagrams of that cross-sectional area. In Fig. 5b, the DRAM 2 is shown in its equilibrium condition. The lines E , E_f, and E represent respectively the energy levels of the conduction band, the FERMI level, and the valance band of the electrons in the layers as shown in Fig. 5a. Since these series of figures are energy band diagrams, a positive voltage is indicated by a depression of the bands; negative voltage is indicated by an elevation of the bands. When a positive voltage is applied to the read/write gate 24, the energy bands of the electrons in layer 27 are depressed thereby creating an inversion layer rich in electrons in the region of layer 30 adjacent the interface of layer 30 with the aluminum gallium arsenide layer 29. The creation of this inversion layer is shown in Fig. 5c.

Thus, it will also be seen from Fig. 5c, that the surface transistor comprising source 25 and gates 23, 24 will function without any adverse influence of the buried well. This is so because the electrons stored in the buried well cannot overcome the potential barrier supplied by the p-doped layer 30. - . The access and the reading the buried well 31 is diagrammatically illustrated in Fig. 5d. There, the voltage on the transfer gate 24 has been raised to a voltage pt greater than the normal supply voltage. That large positive voltage greatly depresses the energy bands and the layers underneath the transfer gate 24. The depression is so great that the former boundary supplied by the p-doped layer 30 is now overcome and electrons within the buried well 31 are free to flow up to the inversion layer at the interface of the aluminum gallium arsenide layer 29 and the upper surface of layer 30.

When gate 24 is returned to its normal positive operating voltage, buried well 31 is depleted of electrons, i.e. "empty". This condition is shown in Fig. 5e. Once again, the large energy barrier provided by layer 30 effectively shields the empty well 31 from having any affect upon the electrons 40 at the surface.

As previously mentioned, writing is accomplished by driving the transfer gate 24 towards zero. A writing demonstration is diagrammatically shown in Fig. 5f. There, it will be seen that the energy level of layer 24 of the transfer gate is raised thereby raising the energy of the- electrons in the inversion layer to a level much higher than those in the buried well 31. Accordingly, electrons will flow from the inversion layer into the buried well 31. Upon returning the transfer gate 24 to its normal operating voltage, the electrons in the inversion layer will once become separated from the electrons in the buried well by the potential barrier provided by layer 30. It may be necessary for two or more cyclic operations in order to fill the well 31 with a sufficient number of electrons for suitable storage. Such cyclicable operations are commonly termed "charge pumping." I 5

Memory devices in current commercial usage normally

-1 operate with low read/write voltages, i.e., less than that required to punch through to a buried well. In order to be compatible with standard memory circuits, the invention is modified to have a read/write operating voltage compatible with commercial circuits. Such a version of the invention is shown in Fig. 6a-6e and is a deep drain DRAM.

The deep drain DRAM 3 is similar in construction and operation to the surface DRAM 2. The major difference is the provision of the deep drain 36 between the gates 23, 24. 0 Deep drain 36 includes an n-doped region that extends into the lightly p-doped layer 30 deeper than the source region 25. The drain region 36 extends far enough into layer 30 so that electrons stored in the buried well 31 can be extracted to the depletion region 33 beneath the deep drain 36 upon 5 application of normal operating voltages to the source and gates 25, 23, 24.

With reference to the series of figures, the deep drain device 3 shown in equilibrium in Fig. 6a. The well 31 is accessed by applying a normal operating voltage, +V, to 0 the source and gates 25, 23, 24. Thereupon, as shown in Figure 6 (b) , the depletion region 33 expands and merges with the depletion region 33' surrounding the well 31. Thus, the potential barrier of layer 30 is lowered and electrons stored in the well 31 flow from the well 31 to the drain 36 and onto 5 the source 25. Upon removal of the operating voltage, the residual voltage on source 25 will indicate the presence or absence of electrons 40 in the well 31.

Writing or storing charges in the well 31 is shown in Fig. 6c-6e. First, the two gates 23, 2' are applied with 0 positive voltage, +V, and the source 25 is grounded. Next,

5 ^• it is desired ;to isolate the electrons 40 under one of the gates. To do this, the transfer gate 23 is driven toward zero thereby repelling the electrons underneath that gate to the more positively charged read/write gate 24. During this isolation phase, the read/write gate 24 is maintained at its positive operating voltage, +V. Finally, the source and transfer gate 25, 23 are grounded and the read/write gate 24 is driven toward zero as shown in Fig. 6e. Electrons are driven from underneath the transfer gate 24 to the depletion region below the deep drain 36 where they are expelled into the deep well 31. As with the surface DRAM 2, the deep drain DRAM 3 may also require several repeated operations in order to fill up an empty well 31.

The foregoing embodiments of the invention use modulation doped field effect transistor (MODFET) technology to provide a single transistor gallium arsenide DRAM using a buried well. The single transistor DRAM having a buried well is also applicable^' to a gallium arsenide MESFET and JFET. A preferred embodiment of a single transistor gallium arsenide MESFET DRAM is illustrated in Fig. 7 and is diagrammatically explained in the band diagrams of Figs. 8a-c.

Turning to Fig. 7, there is generally shown a gallium arsenide MESFET DRAM 4 with a buried well 53. The DRAM 4 includes a substrate 54 of p-doped or semi-insulating gallium arsenide. Using molecular beam epitaxy (liquid phase epitaxy or metallo organic chemical vapor deposition is also ^"" possible) , an epitaxial layer 55 of lightly p-doped gallium arsenide is grown on substrate 54. On top of layer 55, a heavily n-doped gallium arsenide layer 53 is grown by epitaxy. Upper layer 51 is epitaxially grown. The surface of layer 51 is selectively treated to form source, channel and -deep drain regions. The source 49 is ion implanted and heavily n-doped. The deep drain 47 is likewise heavily n-doped. Channel regions 43 and 44 are lightly n-doped. Metal electrodes 45 and 46 in the form of Schottky gates are fixed to the surface above the lightly doped regions 43, 44. Source contact 42 is connected to the heavily doped region 49 and gate contacts 45* and 46' are connected to gates 45 and 46 respectively. Outside of the operating MESFET areas described above, a deep recess edge may be provided and regions 56 on either side of the MESFET are heavily p-doped to provide an isolation region deep enough to reach and compensate the buried well 53. An upper depletion region 50 extends into the layer 51 from the n-doped regions 43, 44, 47 and 49. A further depletion region 52 surrounds the buried well 53. The deep drain 47 extends far enough into the region 51 so that the deep well 53 can be accessed using normal operating voltages of the MESFET 4. However, the potential barrier provided by layer 51 between the deep drain 47 and the buried well 53 is sufficient to prevent the deep well from effecting the performance of the surface MESFET.

The operation of the MESFET DRAM 4 is best understood with reference to the series of Figures 8a-c. Those figures represent a series of energy band diagrams as seen in the cross-sectional area underlying the deep drain 471 Figure 8a shows the MESFET ^"4 in its equilibrium condition. As such, deep drain 47 is isolated from buried well 53 by the potential barrier of layer 51. In order to access or read the buried well 53 or write a zero, the gates 45, 46 and the source 49 are given a positive operating voltage. As such, the depletion area 50 underneath the deep drain expands, the potential barrier of layer 51 is lowered, and electrons stored in the buried well 53 flow to the deep drain 47. From there, the presence or absence of electrons is detected by the voltage change, if any, induced on source 49.

A "1" is written by performing a series of voltage changes on the surface electrodes. At first, the three surface electrodes 49, 45, 46 are grounded. That will precharge the region beneath the deep drain 47 to zero along with the channel beneath gate 44. Next, gate 45 is driven to a negative voltage thereby turning off the channel between the source and the deep drain 47. This isolates electrons under gate 46. Next, gate 46 is driven to a negative voltage thereby forcing the electrons underneath the deep drain 47 and expelling them into the substrate 51 where they are captured in buried well 53.

The foregoing operation of the MESFET 4 is described for a depletion mode MESFET. Those skilled in the art will appreciate that the invention may also be operated with enhancement mode MESFETs and JFETs. When operated in the enhancement mode, the three electrodes 49, 45, 46 are set to a positive voltage to read or to write a zero.- Upon application of the positive voltage, the deep drain 47 will punch through to extract electrons from the buried well 53. To write a one into the buried well 53, the source 42 will be grounded and gates 45, 46 will be set to a positive operating voltage. First, gate 45 will be driven to zero to thereby isolate the electron's under the deep drain 47 and gate 2. Next, gate 46 will be driven toward zero whereupon electrons will be expelled from underneath the gate and the deep drain 47 into the buried well 53.

For such enhancement mode devices, typical operating threshold voltages are 0.1 volts and required power su plies are approximately 1.0 volts. The 1.0 volt power supply will be sufficient for the reading and writing operations. Another embodiment of the invention involves the

-.1 use of a floating drain as the storage region in lieu of a buried well. A floating drain MESFET of the invention is shown generally by the device 5 of Fig. 9. In the device, a semi-insulating or p-doped substrate of gallium arsenide 70 is provided with an upper n-doped layer 62. Portions of layer 62 are more heavily n-doped to provide a source region 63 and a floating drain region 65. A gate channel region 64 lies between source and drain 63, 65. The gate is provided with a metal Schottky barrier electrode 67 connected to lead

10 61. The MESFET 5 is isolated laterally by an isolation etch 71. Alternatively, isolation can be accomplished by heavily p-type ion implanting region 71 . Above the floating drain 65 is an optional further barrier to inhibit surface generation. This optional barrier includes an aluminum

15 gallium arsenide barrier layer 73 that is capped by a p-doped gallium arsenide upper isolation layer 72. In another alternative, only the cap p-doped GaAs layer 72 is provided above floating drain 65.

The floating drain 65 is isolated by providing a

20 heavily p-doped isolation region 69 on one end thereof and a metal electrode 68 that connects the upper isolation layer 72 to the isolation region 69. Thus, the floating drain can be surrounded by a high quality p-n junction to provide further isolation. It might be possible to dispense with-the p-doped 5 isolation regions 72 and 69. However, such isolation is useful in case surface generation of the carriers on an exposed upper surface of the floating drain becomes a problem.

In operation, the drain 65 is connected to the 0 source 63 when the gate 67 turns the transistor on. When the gate 67 turns the transistor off, the drain 65 is isolated

5 and charge will be retained therein. Thus, the drain 65 is precharged to the source potential when the transistor 5 is on and holds that potential when the transistor is off, thereby storing data.

It will also be appreciated by those skilled in the , . art that the floating drain 65 can be increased in storage capacity by connecting it directly to a buried n-doped layer

75 using a deep ion-implanted n-type region 74 as shown by device 5' in Fig. 9(a). The buried n-layer and deep implant are formed as described above in connection with the deep drain embodiment of Fig. 7 with the exception that the drain is implanted deep enough to contact the buried well 75. To establish electrical connection between p-doped regions 70' and 70, isolation regions 71 and 69 should be p-doped regions.

Those skilled in the art will appreciate that devices comparable in structure and operation to 5 and 5' can be fabricated in MODFET and JFET technologies. As shown in Fig. 9(b), device 5'' includes a gate layer 76 of gallium arsenide deposited on top of the channel 64'. A metallic ohmic contact 67' is attached to the gate layer 76 to form a JFET. Figure 9(b) also includes a p-doped layer 77 on a doped, insulating or semi-insulating layer 70'. In a MODFET configuration, the layer 76 is a barrier layer of AlGaAs and the layer 67' is a metallic gate attached to the barrier layer 76. Layer 64' is typically p-doped or undoped in the MODFET. Alternatively, a GaAs gate layer can be deposited on barrier layer 76.

Figure 9 (c) illustrates another embodiment of a storage cell in which the N region is brought to the surface and acts as the floating drain of the access transistor. The floating-drain- cell in Figure 9(c) is fabricated on a semi-insulating substrate 70 with a P tub implant 69'

-.1 selectively placed under the storage drain to reduce parasitic capacitances outside the cell area. No buried epitaxial layers are required. The cell is directly compatible with MESFET, MODFET or JFET processes, requiring only the addition of the P implant and the .associated alloy contact.

The increased area of the GaAs free surface with its high density of surface states might be expected to greatly degrade the storage time of such a structure.

10 However, it is believed that surface generation will not play an important role, for the following reason: in order for thermally generated electrons to discharge the N region, the associated holes must diffuse to the junction and be swept into the P region. The discharging process is therefore

15 limited not by the surface generation rate, but by the rate at which minority holes diffuse out. Even if the surface generation rate is infinite, the hole concentration at the surface cannot exceed the equilibrium concentration, n.^ώ/N_. Due to the low intrinsic carrier concentration in GaAs, this 0 number is exceedingly small, and the carrier gradient driving the diffusion process is correspondingly small. For a donor density of 10 18 cm—3 and a 0.25 pm junction depth at room temperature, the surface hole concentration is no greater than 4x10 cm and the diffusion current is approximately 5 one hole per cm2 per second, which should be negligible compared to generation within the depletion region.

In the floating drain embodiments described above, the channel regions 64 become completely depleted upon application of a suitable voltage to the contact 61. As 0 such, the floating drain region 68 is electrically isolated from the source 63. The drain is connected to the source by changing the voltage on the gate.

5 • » The jnvention is further embodied in a non¬ destructive DRAM. It can be implemented in either MODFET, JFET or MESFET configurations. For convenience, the following description of devices 6, 7 and 8 are embodiments in a MESFET configuration. However, those skilled in the art will appreciate that the Schottky gate 84 of Fig. 10 can be replaced with a suitable MODFET gate electrode such as the type shown in device 10 of Fig. 1. For a JFET a heavily p-doped gate region of GaAs is deposited above the layer 85 and a suitable ohmic contact is deposited on the gate region. In addition, other gate electrode configurations are also well known in the art.

A standard transistor used in gallium arsenide logic circuits is n-channel MESFET. It comprises a source, drain, and a Schottky gate. Such a standard gallium arsenide MESFET is included in the device 6 in Fig. 10. The MESFET 80 includes an n-doped channel 85 that has more heavily doped source and drain regions 86a, b. Electrical contacts 81, 82, 83 are respectively connected to the source 86a, a Schottky metal electrode 84 disposed above the channel region and the drain region 86b.

In the above-described MESFET^"80, the current flows between the source 86a and the drain 86b under control of a bias voltage applied to the gate 84. By applying a negative bias to the gate 84, one can^' completely deplete the channel and cut off all current flowing between the source 86a and the drain 86b. Below the MESFET 80 is the buried well storage structure of the device 6. This includes lightly p-doped layers 87, 89. A heavily p-doped layer 88 provides the buried well. The substrate 90 may comprise semi-insulating gallium arsenide or heavily n-doped gallium arsenide. Fabrication of the MESFET device 6 is similar to the fabrication previously described for other MESFET devices including buried wells. Layers 87, 88 and 89 are electrically isolated from adjacent devices on the same substrate 90.

The MESFET DRAM 6 will provide, in operation, a MESFET where the reading of the stored charge on buried well 88 will not result in an erasure from the device 6 of the stored charge. As such, the reading of the device 6 is termed nondestructive. The function and operation of device 6 is more readily understood with reference to the series of Figures lla-d.-

Figure 11a shows a cross-sectional area taken through the device 6 at the gate electrode 84. The device 6 is shown in equilibrium in lib. There, it will be seen that electrons are included in the channel region of layer 85. Likewise, a large number of holes are collected in the buried well 88. Upon application of a large negative voltage to the gate 84, the energy bands of the upper layers in the device will be raised. For a suitable voltage, the elevation will be sufficient to allow holes to escape from the buried p-well 88 and rise to the gate 84 as shown in Fig. lie. The latter is the equivalent of the process of writing a zero into the device 6.

When the voltage on the gate 84 is returned to ground there is a resulting energy band diagram as shown in lid. There are a reduced number of holes in the buried well 88. The smaller number of holes in the p-well 88 will cause the depletion of electrons in the channel 85. Such depletion will result in a higher resistance between the source 86a and the drain 86b. One can assign this high resistance condition a value to signify "zero". In the equilibrium situation Fig. lib there is little or no resistance between the source and the drain when the voltage on the gate is zero. The latter can be designated as a "1". Thus, the device 6 can be used to write or store a zero and thereby have two states 1 or 0 which is the basic condition of the useful memory device.

The device 6 of Fig. 10 has some limitations. The Schottky gate 84 is not especially useful for injecting holes. Thus, it is difficult with the device 6 to change the condition in the buried p-well 88 from a zero to a one.

The MESFET Device 7 shown in Figure 12, includes a hole injector that overcomes these limitations. The device 7 is similar in structure and operation to the device 6 and reference numerals indicate similar structures. The device 7 includes a MESFET 80' having a hole injector comprising electrode 91, a heavily p-doped area 92 surrounded by an n-doped area 93 that extends into layer 87 a depth deeper than the channel region 85. By applying a positive voltage to contact 91, holes will be introduced into the p-doped region 92 where they will in turn be injected into the p-well 88 in order to write a "1" into p-well 88.

A preferred embodiment of a MESFET with nondestructive readout is shown as device 8 in Fig. 13. There a MESFET 80' " is disposed in a lightly p-doped layer 96. The MESFET 80' '' may be any type of MESFET, including the deep drain type of Figure 7. A buried n-doped well 97 lies beneath layer 96 and on top of a substrate 98 of gallium arsenide typically doped p-type or semi-insulating.

The upper surface of layer 96 is provided with a hole source 91' and a hole drain 93*. The hole source 91' is an ohmic contact to the p-doped region 94. The injected holes are received in a hole drain region 95. Buried well 97 is a heavily n-doped layer. Thus, the holes 99 transit from their source 94 to the drain 95 between two n-doped regions, channel 85' of the MESFET and the buried well 97. In effect, the device incjludes a buried junction field effect transistor. In operation, the width of the depletion region surrounding the buried n-doped layer 97 depends upon the amount of charge stored on the buried layer; if the buried layer has less than the equilibrium number of electrons, the depletion region will be wide enough to pinch off the p-doped layer 96 and inhibit current flow between source 94 and drain 95. By detecting this current, it is possible to determine whether the charge is stored on the buried n-well 97.

A nondestructive readout memory device may also be implemented with a surface drain as shown in Figures 13 (a) and 13(b). The device 10 includes an access transistor 130 shown as a MESFET, however, transistor 130 may also be implemented as a JFET or a MODFET. Figure 13a is a side view of the device 10 and Figure 13b is a cross-sectional end view taken along line 13-13. The transistor 130 includes a source 132, channel 134, Schottky gate 136, floating drain 138 and p-tub 140 on an undoped GaAs substrate 142. The p-tub is provided with an ohmic contact 144 as a p-tub drain and -an ohmic contact 146 that is grounded. The operation of the device 10 is similar to the device of Figure 13. A current flow between contacts 144 and 146 will determine whether charge is stored in the drain 138. The depletion region surrounding the drain 138 may be made large enough to pinch-off the p-tub to inhibit the current flow.

One disadvantage of the buried-well configuration is the operating complications introduced by the need for punch through. A more straightforward mode of operation would be possible if the storage region could be brought into direct electrical contact with a surface electrode. Figure 14 shows one possible direct-access configuration. In device 9 of Figure 14, the buried well 102 is brought to the surface by means of an alloy contact 104. Once at the surface, the buried well 102 is connected to the drain 106 of a MODFET, JFET or MΞSFET.;100 which becomes the access transistor for the cell, providing direct electrical connection between the buried well 102 and the associated bit line when the gate 108 of the access transistor is biased above threshold. As in the simple burieά-well structure^", the various layers could be grown by LPE, MBE, or MOCVD, and the N well 102 and adjacent P layers 110, 112 can be AlGaAs, increasing the storage time. Layer 112 also acts as a stop etch layer to define the depth of the etch regions 114. Layer 118 of lightly doped GaAs is an optional layer that functions to lower the parasitic capacitance of the source and drain regions. In the device 9, the distance through which the contact 104 must extend to contact the well 102 is lessened by providing an etch region 114 on either side of the source 116, drain 106 and channel 108 regions. Thus, the contact 104 need only penetrate the layer 112 to contact the well 102. Isolation regions 120 are provided to define the well.

The foregoing preferred embodiments have doping concentrations, depths, thicknesses, and spacings that are readily apparent to those skilled in the art. In general, the concentrations of the heavily n-doped areas are sufficient to hold enough charge carriers for storage and conduction. So, a buried n-well is doped to about 10 18 carrier/cm . Typically, the dopant is silicon. The well is generally 0.2 microns thick and is disposed about 1.0 microns below the surface of the surface of the field effect transistor, i.e., the surface defined by the source, channel and drain regions. The deep drain, e.g., 36 of device 3,

Fig. 6(a) may extend a depth of 0.45 microns. Other shallow drains are typically 0.25 microns deep.

The lightly p-doped regions are commonly doped 5 X

1 fi

10 carriers/cm with beryllium. That concentration may be reduced to 5 X 10 15 carriers/cm3 if the buried well is deeper. However, lowering the well will require further £• 8

fabrication steps including isolation etching. The foregoing embodiments are readily made using ion implantation to establish the well and isolate the well. Of course, other techniques are available and may be used.

The embodiments with shallow drains will require about 5 volts for normal supply operation and 6 volts for punch through. The deep drain I of device 3 will punch through at about 2 volts.

The punch through and operating voltages depend upon the doping of the transistor and the well, the thickness of the well, the depth of the well and the depth of the sources and drains, the doping material and its concentration. These parameters can be varied to achieve desired operating efficiencies and to accommodate manufacturing capabilities. Such variations are considered to be within the expertise of those skilled in the art and are within the spirit and scope of the appended claims.

The foregoing preferred embodiments are illustrative only of some of the many ways of which the buried well technology described above can be combined with group III-V or II-VI compound semiconductor devices to provide one transistor memory devices. A significant feature of the foregoing devices is that they provide practical, useful memory storage at ordinary or room temperatures. In addition, these devices are compatible with existing fabrication techniques. Thus, it will be possible to use these devices in combination with other devices either on or off the same substrate.

Those skilled in the art will appreciate various modifications, additions, substitutions and deletions may be made to the foregoing invention without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

WHAT IS CLAIMED IS

1. A. semiconductor memory storage device comprising: a surface semiconductor electrode of a charge doping of one polarity; a first layer of semiconductor material of a charge doping of a polarity opposite to the polarity of said surface electrode; a second layer of barrier material disposed between said surface electrode and said first layer; a buried well comprising a third layer of semiconductor material disposed within said first layer, electrically isolated by said first layer from said second layer, and having a charge doping so that a charge applied to said buried well shall remain within the buried well.

2. The device of Claim 1 wherein the surface electrode and buried well are n-doped and the first layer is p-doped.

3. The device of Claim 1 wherein the surface electrode and buried well are p-doped and the first layer is n-doped.

4. The device of Claim 1 wherein the surface ^• electrode, the first layer, the second layer and the third layer comprise a semiconductor material fashioned from group III - V or group II-VI elements. *

5. The device of Claim 4 wherein the material for the surface electrode, first layer and third layer comprises gallium arsenide.

6. The device of Claim 5 wherein the barrier material comprises aluminum gallium arsenide.

7. :ffhe device of Claim 1 wherein a heterojunction is formed at the interface of the first and second layers.

8. The device of Claim 7 wherein the buried well is spaced from the heterojunction a sufficient distance to not electrically interfere with the heterojunction.

9. The device of Claim 1 further comprising a voltage means connected to the surface electrode for applying a charge to the surface electrode.

10. The device of Claim 9 wherein the voltage means is of a polarity and of a magnitude for so depleting the first layer of charge carriers that the buried well is electrically connected to said second layer.

11. The device of Claim 9 wherein the voltage means is of a polarity and of a magnitude for enhancing the first layer with charge carriers such that carriers of an opposite polarity are electrically forced into the buried well for storage.

12. A heterojunction device comprising a first conductive layer; a second layer comprising a semiconductor providing a barrier to charge flow, said layer having a first surface in contact with the first layer and a second surface for forming a heterojunction; a third layer of semiconductor, having a surface in contact with said second surface of said second layer to form a heterojunction therebetween; a buried well comprising a fourth layer of semiconductor, disposed within said third layer and spaced from said heterojunction to not interfere with customary operation thereof; said fourth layer doped with charge carriers of the opposite polarity to said third layer; means for applying a voltage of a polarity and magnitude to tile first layer in order to connect the buried well to the heterojunction interface and allow charge carriers in the ^'buried well to flow to said interface.

13. The device of Claim 12 further comprising means for applying a voltage of a polarity and magnitude to the first layer in order to allow charge carriers to flow from the heterojunction interface into the buried well.

14. The device of Claim 12 wherein the first, third and fourth layers comprise a compound semiconductor selected from group III-V or group II-VI elements.

15. The device of Claim 14 wherein the compound semiconductor is gallium arsenide.

16. The device of Claim 12 wherein the barrier comprises a compound semiconductor selected from the group III-V or group II-VI elements.

17. The device of Claim 16 wherein the compound semiconductor comprises aluminum gallium arsenide.

18. A heterojunction field effect transistor comprising: a first layer of semiconductor doped with one polarity of charge carriers, said layer having an upper surface comprising a drain contact spaced from a source contact, and a channel defined by a region in said layer between the source and the drain for carrying charges from the source to the drain at or above a threshold voltage; a second layer of semiconductor disposed above said channel providing a barrier to charge flow; a gate electrode, disposed on top of said second layer of semiconductor, said gate being operable to control the charges passing through the channel; - • a region of high charge carrier mobility disposed beneath said gate electrode, in said channel region at the interface between the second layer and the first layer; a third, buried well layer of semiconductor, disposed within said first layer having a charge carrier doping and opposite to the first layer, located in said first layer at a sufficient distance from the channel region to normally not interfere with charge carriers in said channel when a threshold voltage is applied to said channel and adapted to receive and store charge carriers placed in said buried well.

19. The device of of Claim 18 further comprising means for applying a voltage to said gate sufficient to deplete charge carriers from the first layer and thereby connect the buried well to the channel region.

20. The device of Claim 18 further comprising means for applying a voltage to said gate whereby charge carriers are electrically passed into said buried well.

21. The device of Claim 18 wherein said buried layer is adapted to respond to a voltage applied to said gate by expelling, holding and .receiving charge carriers in accordance with the magnitude and polarity of the voltage applied to said gate.

22. The device of Claim 18 wherein the first and third layers_^comprise a compound semiconductor selected from group III-V or group II-VI elements.

23. The device of Claim 22 wherein the compound semiconductor is gallium arsenide.

24. The device of Claim 18 wherein the barrier comprises a compound semiconductor selected from group III-V or group II-VI elements.

25. The device of Claim 24 wherein the compound semiconductor comprises aluminum gallium arsenide.

26.---_J.A field effect transistor having a source, gate and drain"laterally disposed on the surface of a semiconductor layer with respect to each other and a buried well in the semiconductor layer, said buried well underlying the gate, and adapted to receive, hold and expel charge carriers in accordance with a threshold voltage of one polarity and magnitude applied to said gate.

27. The device of Claim 26 wherein the drain extends below the surface of the semiconductor layer a distance sufficient to establish electrical contact between the buried well and the channel at a voltage less than the normal drain supply voltage of the transistor.

28. The device of Claim 26 comprising a second gate disposed laterally from said drain and means for applying to the two gates a sequence of voltages in order to store charge carriers in said buried well.

29. The device of Claim 28 where the semiconductor layer is p-doped, the buried well is n-doped and the threshold voltage is positive.

30. The device of Claim 29 wherein the voltages on the gates are alternately reduced to zero in order to first isolate electrons under one gate and then force the electrons into the well from the gate.

31. The device of Claim 28 wherein the semiconductor layer is n-doped, the buried well is p-doped, and the threshold voltage is negative.

32. The device of Claim 31 wherein the voltages on the gates are alternately increased to zero in order to isolate holes under one gate and then force the isolated holes into the well from the gate.

33 . The device of Claim 26 wherein the semiconductor layer comprises a compound semiconductor selected from group III-V or II-VI elements.

34..«■ The device of Claim 33 wherein the compound

,1 semiconductor is gallium arsenide.

35. The device of Claim 26 wherein the gate comprises a barrier layer of a compound semiconductor selected from group III-V or group II-VI elements.

36. The device of Claim 35 wherein the compound semiconductor comprises aluminum gallium arsenide.

37. A memory storage device comprising: a MESFET including a source, channel, and drain doped with one type of charge carrier and disposed on a layer 0 of material doped with charge carriers of opposite polarity; a buried well disposed within said layer and more heavily doped than the layer with charge carriers of the same polarity as the layer; means for extracting charge carriers from said 5 buried well and carrying the extracted charges to the gate, thereby causing a depletion of charge carriers from the channel and changing the electrical resistance of current between the source and the drain; and means for electrically isolating the layer and the 0 buried well.

38. The device of Claim 37 further comprising means for injecting charge carriers of the same polarity as the buried well into the buried well and thereby enhance the channel to reduce the resistance between the source and the 5 drain.

39. The device of Claim 38 wherein the charge carrier injection means comprises a shallow surface region in the layer surrounded by a region of oppositely doped material.

40. The device of Claim 37 wherein the layer 0 comprises a compound semiconductor selected from group III-V or group II-VI elements.

5

41. £ The device of Claim 40 wherein the compound semiconductor Is gallium arsenide.

42. A single transistor dynamic random access memory comprising: a first layer of compound semiconductor material including a field effect transistor disposed in said layer and having a plurality of electrodes including a gate disposed adjacent a channel region for accommodating the transit of charge carriers through the channel under the influence of a voltage applied to the gate; a buried well storage region disposed in and substantially enclosed by said first layer to receive charge carriers, said storage region being doped with respect to said first layer to provide a potential barrier around said storage region for retaining said charge carriers in said storage region; means for reducing said potential barrier to allow charges to escape from said storage region to said channel region.

43. The device of Claim 42 wherein the potential barrier reducing means comprises an electrode of the transistor extending into the first layer a depth greater than the other electrodes.

44. The device of Claim 42 wherein the field effect transistor comprises a modulation doped field effect transistor.

45. The device of Claim 42 wherein the field effect transistor comprises a layer providing a barrier to charge flow disposed on said first layer and a gate electrode disposed on said barrier layer.

46. The device of Claim 45 wherein the buried well is of one doping and the first layer is of an opposite doping.

47.,,- The device of Claim 46 wherein the buried well is n-doped and?,the first layer is p-doped.

48. The device of Claim 46 wherein the buried well is p-doped and the first layer is n-doped.

49. The device of Claim 42 wherein the field effect transistor comprises a Schottky barrier metal electrode gate disposed above said channel region.

50. The device of Claim 49 wherein the channel region and the buried well are of one doping and the first layer surrounding the buried well is of an opposite doping to thereby provide a potential barrier between the buried well and the first layer.

51. The device of Claim 49 wherein the means for reducing said potential barrier comprises an electrode of the transistor extending into the first layer a depth greater than the other electrodes.

52. The device of Claim 49 wherein the channel is of one doping and the first layer and the buried well are of an opposite doping whereby the potential barrier around the well will influence charge carrier transiting the channel after charge carriers are removed from the well.

53. The device of Claim 52 wherein the buried well is more heavily doped than the first layer.

54. The device of Claim 53 wherein the buried well and first layer are p-doped and the channel is n-doped.

55. The device of Claim 53 wherein the buried well and first layer are n-doped and the channel is p-doped.

56. The device of Claim 28 wherein the field effect transistor comprises a compound semiconductor selected from group III-V or group II-VI elements.

57. The device of Claim 56 wherein the compound semiconductor is gallium arsenide.

58. - ,The device of_.._.Claim 28 wherein the field effect transistor further comprises a barrier layer of a compound semiconductor selected from group III-V or group II-VI elements.

59. The device of Claim 58 wherein the compound semiconductor comprises aluminum gallium arsenide.

60. A compound semiconductor memory storage device comprising: a first layer of compound semiconductor material; a second layer of compound semiconductor material disposed within said first layer, electrically isolated by said first layer and having a charge doping of a polarity opposite to the polarity of the first layer so that a charge applied to said second layer shall remain within said second layer.

61. The device of Claim 60 wherein the second layer is n-doped and the first layer is p-doped.

62. The device of Claim 60 wherein the second layer is p-doped and the first layer is n-doped.

63. The device of Claim 60 wherein the first layer and the second layer comprise a semiconductor material fashioned from group III-V or group II-VI elements.

64. The device of Claim 63 wherein the material comprises gallium arsenide.

65. A dynamic random access memory device comprising: a first layer of a compound semiconductor of one type of doping; a surface region in said first layer comprising source, channel and drain regions,- all of a doping opposite the first layer with the source and drain regions more heavily doped than the channel region; meang. for applying a potential to the source region; means connected to said channel region for selectively depleting said channel of charge carriers in order to electrically isolate the drain region from the source region and thereby store a charge in the drain region.

66. The device of Claim 65 wherein the doped drain region extends into the first layer and intersects a buried well, disposed in the first layer beneath the surface thereof and of a doping of the same polarity as the drain region.

67. The device of Claim 65 wherein the selective depleting means comprises a Schottky gate.

68. The device of Claim 65 wherein the selective depleting means comprises a first barrier layer disposed on the surface of the channel region and an electrode connected to said barrier layer.

69. The device of Claim 68 wherein the first barrier layer is a compound semiconductor selected from a compound of group III-V elements or group II-VI elements.

70. The device of Claim 69 wherein the barrier layer is aluminum gallium arsenide.

71. The device of Claim 65 wherein the compound semiconductor of the first layer is selected from a compound of group III-V elements or group II-VI elements.

72. The device of Claim 71 wherein the compound semiconductor is gallium arsenide.

73. The device of Claim 65 further comprising a second barrier layer overlaying- the surface of said drain region for preventing generation of undesired charge carriers that would dissipate the potential stored in said drain region.

74.. The device of Claim 73 wherein said second

1 layer comprises a compound semiconductor selected from group III-V or group II-VI compounds.

75. The device of Claim 74 wherein the second barrier layer comprises aluminum gallium arsenide.

76. The device of Claim 73 further comprising a conductive layer overlying the second barrier layer and mean for connecting said conductive layer to the first layer in order to substantially enclose the drain region.

77. The device of Claim 76 further comprising a 0 metal electrode for connecting the conductive layer to the first layer.

78. A memory storage device comprising: a field effect transistor including a first source, a channel, and a first drain with the first source and first 5 drain doped with one type of charge carrier and disposed on a first layer of compound semiconductor material doped with charge carriers of opposite polarity; a buried well disposed within said first layer and more heavily doped than the first layer with charge carriers 0 of opposite polarity to the first layer; means for extracting charge carriers from said buried well to cause a depletion of charge carriers from the first layer and changing the electrical resistance of the first layer. 5 ^J

79. The device"^* of Claim 78 further comprising a second source and a second drain in said first layer for respectively injecting and receiving carriers of the polarity of the first layer.

80. The device of Claim 79 wherein the second source and the second drain are ohmic contacts on said first layer.

81.^'-:. The device of Claim 78 further comprising a Schottky gate connected to said channel for controlling the transit of charge carriers in said channel.

82. The device of Claim 78 further comprising a gate including a barrier layer disposed above said channel and an electrical contact mounted on said barrier layer for providing an electric field and thereby controlling the transit of charge carriers in said channel.

83. The device of Claim 82 wherein the barrier layer is a compound semiconductor selected from group III-V or group II-VI elements.

84. The device of Claim 83 wherein the barrier layer comprises aluminum gallium arsenide.

85. The device of Claim 78 wherein the material of the first layer comprises a compound semiconductor.

86. The device of Claim 85 wherein the compound semiconductor is selected from group III-V or group II-VI elements.

87. The device of Claim 86 wherein the compound semiconductor is gallium arsenide.

88. The device of Claim 65 wherein the surface region further includes an isolation region adjacent said drain region, said isolation region having a doping of the same type as the first layer, said isolation region being more heavily doped than said first layer.

89. The device of Claim 88 wherein the isolation region extends beneath the drain region in contact with said drain region.

90. The device of Claim 89 wherein the isolation region extends beneath substantially the entire drain region.

91. - A dynamic random access memory device comprising: ^*_ a substrate of a compound semiconductor; a surface region in said substrate comprising source, channel and drain regions, the source and drain regions having a first doping type, said surface region further including an isolation region adjacent said drain region of a second doping type; means for applying a potential to the source region; means for selectively depleting said channel of. charge carriers in order to electrically isolate the drain region from the source region and thereby store a charge in the drain region.

92. The device of Claim 91 wherein the isolation region extends beneath the drain region in contact with said drain region.

93. The device of Claim 91 wherein the isolation region -extends beneath substantially the entire drain region.

94. The device of Claim 26 further including a contact extending from said surface to said buried well providing direct electrical access to said buried well.

95. The device of Claim 42 further including a contact extending from said surface to said buried well providing direct electrical access to said buried well.

96. The device of Claim 68 wherein the first barrier layer is one of an insulating layer and a doped layer.

97. -^'-.-The device of Claim 65 further comprising a

-J. conductive layer overlaying the surface of said drain region for preventing generation of undesired charge carriers thereby preventing the dissipation of the potential stored in said drain region.

98. The device of Claim 1 wherein the barrier material is one of an insulating layer and a doped layer.

99. The device of Claim 12 wherein the barrier layer is one of an insulating layer and a doped layer.

100. The device of Claim 18 wherein the barrier

10 layer is one of an insulating material and a doped material.

101. The device of Claim 35 wherein the barrier layer is one of an insulating material and a doped material.

102. The device of Claim 45 wherein the barrier layer is one of an insulating material and a doped material. 5

103. The device of Claim 82 wherein the barrier layer is one of an insulating material and a doped material.

104. A memory storage device comprising:

(a) a layer of compound semiconductor material?.

(b) an access field effect transistor (FET) having 0 at least one electrode formed within said semiconductor material and at least one gate electrode formed in close proximity to said semiconductor material, said access FET having a channel region formed within said semiconductor material near said gate electrode; 5 (c) a storage region formed within said semiconductor material having a doping to electrically isolate said storage region from adjacent semiconductor regions; and

0

5 (d) means for applying voltage to said at least one gate electrode^'fof a polarity and magnitude to selectively transfer charge^' between said at least one electrode and said storage region and selectively isolate said at least one electrode from said storage region,

105. The device of Claim 104 wherein said access FET is one of a MODFET, JFET and MESFET.

106. The device of Claim 105 wherein said storage region comprises a buried well within said semiconductor material spaced from said access FET to not affect operation of the FET at normal operating voltages.

107. The device of Claim 105 wherein said storage region comprises a region within said semiconductor spaced laterally and adjacent to said channel region.

108. The device of Claim 107 wherein the compound semiconductor material is GaAs.

109. The device of Claim 65 wherein the selective depleting means includes a second layer of compound semiconductor material disposed on the first layer and an ohmic contact disposed on said second layer, said second layer of semiconductor material having a doping opposite the first layer.

110. The device of Claim 42 wherein said gate comprises a second layer of compound semiconductor material disposed on said first layer and an ohmic contact disposed on said second layer, said second layer of semiconductor material having a doping opposite the first layer.

111. The device of Claim 78 further comprising a second layer of compound semiconductor material disposed on said first layer and an ohmic contact disposed on said second layer, said second layer of semiconductor material having a doping opposite the first layer.