WO1988010433A1

WO1988010433A1 - Method for transferring a binary code and code carrier for implementing the method

Info

Publication number: WO1988010433A1
Application number: PCT/SE1988/000343
Authority: WO
Inventors: Sten Lundgren
Original assignee: Lundgren & Nordstrand Ab
Priority date: 1987-06-22
Filing date: 1988-06-21
Publication date: 1988-12-29
Also published as: SE8702568L; AU1987188A; SE458564B; SE8702568D0

Abstract

In a method for transferring a binary code consisting of a plurality of bits from a code carrier to a code receiver, a periodic signal is transferred from the code receiver to the code carrier. In each period of the periodic signal supplied, one bit in the code is transferred from the code carrier to the code receiver in that the signal supplied to the code carrier is given an increase depending on the value of said bit. The signal increase is detected in the code receiver. A code carrier for implementing the method has a memory (M) which is sequentially addressable by the periodic signal supplied from the code receiver and has a number of bit cells corresponding to the number of bits in the code, and a pulse generator (P1, P2, T1) connected to an output of the memory and so controlled as to give the periodic signal in each period thereof an increase depending on the bit value on the output of the memory.

Description

METHOD FOR TRANSFERRING A BINARY CODE AND CODE CARRIER FOR IMPLEMENTING THE METHOD

The present invention relates to a method for transferring a binary code consisting of a plurality of bits from a code carrier to a code receiver, and to a code carrier for implementing the method. Code carriers in the form of electronic keys, identification cards and the like, are used to an ever increasing extent. For security and information adequacy, it is desirable that the code stored in the code carrier can comprise a large number of bits. An increased amount of information normally requires an extended time for transfer to a code receiver. How¬ ever, this transfer time must be very short in order that the combination of code carrier and code receiver should be useful in practice. Present-day techniques therefore imply either that the code carrier and/or the transfer procedure must be of complex design, or that the amount of information stored in the code carrier must be limited.

The object of the present invention therefore is to provide a method and a code carrier of the type men¬ tioned by way of introduction, which permit rapid trans¬ fer of a large amount of information from a code carrier to a code receiver, while maintaining a simple transfer procedure and a code carrier of simple design. In the method according to the invention, where a periodic signal is inductively supplied from the code receiver to the code carrier, this object is achieved by the steps, in each period of the inductively sup¬ plied periodic signal, of inductively transferring one bit in the code from the code carrier to the code receiver by addressing, by means of a first portion in each period of the periodic signal, a special memo¬ ry cell which is provided in the code carrier and in which one bit in the code is stored, and giving the signal inductively supplied to the code carrier an increase in a second succeeding portion of the same period depending on the value of said bit, and of inductively detecting the signal increase in the code receiver.

In order to make the code carrier independent of a current source of its own, the periodic signal can also be rectified in the code carrier and used for current supply thereof.

The same object as mentioned above is achieved by means of the inventive code carrier in that it has a memory which is sequentially addressable by a periodic signal supplied from the code receiver and which has a number of bit cells corresponding to the-.number of bits in the code, said memory being addressable by means of a first portion in each pe¬ riod of the periodic signal, and in that a pulse ge¬ nerator connected to an output of the memory is so controlled as to supply the periodic signal in a se¬ cond succeeding portion of the same period of the periodic signal, with an increase depending on the bit value on the output of the memory.

For current supply of the code carrier, this suitably has a rectifier which also receives the pe¬ riodic signal. For the inductive connection between the code carrier and the code receiver, these each have at least one coil.

In the preferred embodiment of the code carrier, the pulse generator comprises a pulse shaper connected to the output of the memory, and a drive circuit con¬ nected to the coil and controlled by the pulse shaper. Further, the code carrier may have a counter for count¬ ing the number of received periods of the periodic signal and generating addresses for addressing the me¬ mory. The memory may also be switchable between reading and writing by means of a circuit for detecting a pre¬ determined pattern in the periodic signal.

Preferred embodiments of the code carrier accord¬ ing to the invention and of the associated code receiver will be described in more detail hereinbelow with refe¬ rence to the accompanying drawings. Fig. 1 is a cir¬ cuit diagram for a first embodiment of a code carrier according to the invention. Fig. 2 is a circuit dia¬ gram for an associated code receiver according to the invention. Fig. 3 is a circuit diagram for a se¬ cond reprogrammable embodiment of the code carrier according to the invention. Fig. 4 is a circuit diagram for a code receiver intended for the code carrier shown in Fig. 3. Figs. 5, 6 and 7 are diagrams showing ave- forms occuring in the circuits shown in Figs. 1-4.

A code carrier shown in Fig. 1 has a coil Ll via which the code carrier inductively receives and emits signals to a code receiver shown in Fig. 2. The coil Ll is connected via a resistor Rl across a network of two capacitors Cl and C2 connected to ground, and two diodes Dl and D2. This network acts as a voltage- doubling and rectifying network and supplies a feed voltage to the code receiver over a voltage-limiting Zener diode Zl. The coil Ll is also connected via the capacitor Cl to a second rectifying network consisting of a diode D3, a capacitor C3 and a resistor R2. On the output of this rectifying network, a Schmitt trigger Si is connected. Via the capacitor Cl, the coil Ll is also con¬ nected to a second Schmitt trigger S2 the output of which is connected both to an input of an AND gate Gl and to the clock input of a counter PR1 whose out¬ put will be high after 16 pulses received on the clock input and is connected to the other input of the gate Gl. The output of the gate Gl is connected to an in¬ put of a NAND gate G2 whose output is connected to an input of a counter PR2. The output of the Schmitt trigger SI is connected to the reset input of the counter PR1, the reset input of the counter PR2, and to the other input of the gate G2. Three of the outputs of the counter PR2 are con¬ nected to inputs of a 1/8 decoder A whose outputs, as well as the other inputs of the counter PR2, constitute address inputs of a memory M having a number of bit cells corresponding to the product of the number of inputs from the counter PR2 and the number of inputs from the decoder A. The bit value in the memory cell of the memory M addressed at each point of time by the counter PR2 and the decoder A appears on an output of the decoder A, which output is connected to an in- put of an AND gate G3 whose other input is connected to the output of the gate G2.

The output of the gate G3 is connected to the in¬ put of a first pulse shaper PI being a monostable circuit and serving as a delay circuit. The output of the pulse shaper Pi is connected to the input of a se¬ cond pulse shaper P2 also being a monostable circuit. The output of the pulse shaper P2 is connected to the base of a transistor Tl connected between the po¬ sitive feed voltage and the connection of the coil Ll to the resistor Rl.

Before a description of the function of the code carrier in Fig. 1, the design of the code receiver in Fig. 2 will first be described.

The code receiver in Fig. 2 consists of an oscil- lator part and a detector part. The oscillator part in¬ cludes an oscillator 0 whose output is connected to a counter PR3 the outputs of which are connected to a co binatory network Kl. Two outputs of the combinatory network, on which outputs inverse signals appear, are connected via drive circuits Fl, F2 to a coil

L2. On a third output of the combinatory network ap¬ pears a clock signal which is used for clocking the signals received from the detector part of the code receiver.

The detector part more specifically consists of a coil L3 with a centre tap connected to ground. One end of the coil L3 is connected via a diode D4 to one input of a comparator Jl, and the other end of the coil L3 is connected via a diode D5 to the other input of the comparator Jl. The first input of the comparator Jl is branched to ground via a resistor R3, while the other input of the comparator Jl is branched to ground via a resistor R4 and a capacitor C4. The output of the comparator Jl is connected to the input of a pulse sha¬ per P3 being a monostable circuit, and the output of the pulse shaper P3 constitutes the data output of the code receiver, on which output data is detected by clocking by means of the clock signal on the clock out¬ put of the combinatory network Kl .

The mode of operation of the circuits shown in Figs. 1 and 2 will now be described, it being under- stood that the memory M contains a binary code which consists of a plurality of bits and which should be detected by the code receiver in Fig. 2. Reference is also made to Figs. 5 and 7.

For carrying out the code transfer, the code carrier, being a separate unit, is placed in such a position relative to the code receiver that the coils Ll, L2 and L3 are inductively connected to each other. The combinatory network Kl generates a train of pulses the number of which is equal to 16 plus the number of bits in the memory M. After this pulse train, an interruption is made, whereupon the same sequence is again repeated. The periodic signal thus induced in the coil Ll substantially has sine shape and charges the capacitors C2 and C3 to positive po- larity, the capacitor C2 ensuring the current supply of the code carrier. During an interruption between the pulse trains, the voltage drops on the capacitor C3, the capacitance of which is substantially lower than the capacitance of the capacitor C2, sufficiently for the output signal on the Schmitt trigger SI to change level, whereby the counter PRl and the counter PR2 are reset. For each pulse in the pulse train following upon the first 16 pulses after the interruption, the counter PR2 is stepped up one step so that all bit cells of the memory M are consecutively addressed by the counter PR2 and the decoder A. The pulses appearing on the out- put of the gate G2 are used for clocking the bit values appearing on the output of the decoder A to the pulse shaper Pi which after a predetermined delay acts on the pulse shaper P2, in turn opening the transistor Tl during a predetermined period of time. Fig. 5, at the top, shows the form of the pulse train PT on the output of the Schmitt trigger S2 and, at the bottom, shows the form of a reset signal RS on the output of the Schmitt trigger SI. It appears that the reset signal RS changes level soon after the start of the interruption between the pulse bursts in the pulse train PT, the delay being dependent upon the discharge of the capacitor C3.

The pulse train induced in the coil Ll substan¬ tially has sine shape, as appears from Fig. 7. Fig. 7 shows the level on which the counters PRl and PR2 are triggered, for instance at a point of time t-. The pulse length or time delay of the pulse shaper PI is indicated as a time interval tl in Fig. 7, and the pulse length of the pulse shaper P2 is indicated as a time interval t2 in Fig. 7. If an addressed bit in the me¬ mory M results in a "1" on the output of the decoder ^'A, the pulse shaper Pi will be triggered, so that the pulse shaper P2 is triggered with the delay time tl after the point of time t„. The pulse shaper P2 will then make the transistor Tl conductive during a time inter¬ val t2, whereby the periodic signal induced in the coil Ll_r via the transistor Tl, is given an increase during said interval t2, which increase is indicated in Fig. 7 by a dashed line. As a result of this increase, the flank concerned of the sine waveform will become steeper, which results in a higher voltage being induced in that half of the coil L3 in the decoder part of the code receiver which is connected between ground and the diode D4. The other positive half-periods of the sine wave in Fig. 7 result in the induction of a voltage in said half of the coil L3, which voltage is approximately as high as or preferably slightly lower than the voltage induced in the lower half of the coil L3 by the negative half-periods of the sine wave in Fig. 7. As a result, the voltage across the capacitor C4 in the decoder will correspond _^to slightly more than half the peak-to-peak value of the sine sig¬ nal in Fig. 7. This voltage on the capacitor C4 consti¬ tutes the reference voltage in the comparator Jl. The higher voltage induced in the upper half of the coil L3 as a result of the conduction of the transistor Tl during the interval t2 will thus be sensed by the comparator Jl whose output signal then triggers the pulse shaper P3 which on the data output emits a pulse which is clocked by means of the clock pulses on the clock output of the combinatory network Kl. It is evident that by the inventive design of the code carrier and the code receiver, where the very clock signal from the code receiver to the code carrier is also used for transferring information from the code carrier to the code receiver, it is possible to achieve a very fast transfer process.

As an example, the pulse frequency in the pulse train PT may be 1 MHz, whereby transfer times of approximate¬ ly 10 μs per 10 bits in the memory M can be achieved. According to the invention, a periodic signal in the form of the pulse train PT is thus supplied from the code receiver to the code carrier and in each period of the periodic signal supplied, one bit in the code is transferred from the code carrier to the code receiver in that the signal supplied to the code carrier is given an increase depending on the value of said bit. The signal increase supplied is then detected in the code receiver. Clocking the coun¬ ters PRl and PR2 at the first point of time t„, while supplying the increase during a later time interval t2, provides the functions of addressing a special memory cell, storing one bit in the code, by means of a first portion in each period of the periodic signal, and of supplying the increase in a second succeeding portion of the same period.

In the variant of the code carrier shown in Fig. 1, the code in the memory M is stationary and non-repro- grammable. The embodiment of a code carrier according to the invention as shown in Fig. 3 contains the same circuits as the code carrier of Fig. 1, as well as additional circuits for making the memory M repro¬ grammable. The additional circuit elements in the code carrier according to Fig. 3 more specifically are three gates G4, G5 and G6, two counters PR4 and PR5, two combinatory networks K2 and K3, a bistable circuit VI and a Schmitt trigger S3. The gate G5 is of the tri-state type. The code carrier in Fig. 3 also contains a decoder part which essentially agrees with the decoder part in the code receiver of Fig. 2. Thus, it comprises a coil L4 with a grounded centre tap, one end of the coil being connected via a network consisting of a diode D6, a resistor R5 and a Zener ^■ diode Z2 to one input of a comparator J2, while the other end of the coil L4 is connected via a network consisting of a diode D7, a resistor R6, a capacitor C5 and a Zener diode Z3 to the other input of the comparator J2. The output of the comparator J2 is connected to the input of a pulse shaper P4 which is a monostable circuit. The code receiver according to Fig. 4 contains the same components as the code receiver according to Fig. 2 and, additionally, a gate G7, two pulse shapers P5 and P6, a transistor T2, and a bistable circuit V2. The detector part of the code receiver is not shown in Fig. 4.

The mode of operation of the code carrier accord¬ ing to Fig. 3 and the code receiver according to Fig. 4 is the same as for the circuits according to Figs. 1 and 2 when a code is read from the memory M in the code carrier. For reading a new code into the memory M, the following sequence is carried out, reference being now also made to Fig. 6. For switching the memory M from reading to writing, a signal should be applied to an input R/ of the memory M. This is achieved by switching the circuit VI. The switching of the circuit VI is achieved by means of such a pulse train PTl as is shown at the top of Fig. 6. More particularly, an interruption is made in the pulse train PTl after the first 30 + 16 pulses therein. The pulse train PTl is generated by the combinatory network Kl after a pulse on the input of the circuit V2 has switched this circuit.

After the first 16 pulses have been counted by the counter PRl, the following 30 pulses will be counted by the counter PR4 which when attaining 30 pulses concurrently with the appearance of the reset signal RSI on the output of the Schmitt trigger SI, emits a set signal to the circuit VI via the combinatory net- work K2. The signal then appearing on the output of the circuit VI is applied to the input R/W of the memory M and switches the memory into writing mode. The signal on the output of the circut VI is also applied to the combinatory network K3, whereby the reset signal from one output of the network K3 to the reset input of the counter PR5 is removed. Further, the signal on the output of the circuit VI is applied to the gate G5 to open it, and finally to a disabling input of the pulse shaper Pi, whereby pulses appearing on the output of the gate G3 during the programming process are not passed on to the resistor Tl. When the counter PR4 has counted 30 pulses, the combinatory network K2 on one of its outputs also generates a signal which is applied to the other in¬ put of the gate G4 and stops further supply of pulses to the counter PR4. In order to prevent the counter PR4 during the continued writing cycle from counting the input pulses to the coil Ll, the output signal of the circuit VI is also applied to an input of the combinatory network K2, whereby the counter PR4 is locked in its position. During the interruption, the counters PRl and PR2 are reset. The first 16 pulses after the interruption are again counted by the coun¬ ter PRl which thereafter opens the gate Gl. The coun¬ ter PR2 is then supplied with an equal amount of pulses as the number of bits in the memory M. The new data are read into the memory M via the output of the deco¬ der A, which output also serves as input. These data are supplied to the code carrier in the following manner. The code which is to be programmed in the memory M is supplied more specifically to the data input in the code receiver of Fig. 4 and is clocked by the clock signals from the combinatory network Kl through the gate G4 via the pulse shapers P5 and P6 corresponding to the pulse shapers PI and P2 in the code carrier, to the transistor T2 corresponding to the transistor Tl in the code carrier. Thus, there is achieved in the substantially sinusoidal signal supplied to the coil L2, an increase in each period of this signal, which increase corresponds, for example, to a binary value "1". The signal through the coil L2 may thus substantially have the shape shown in Fig. 7. The signal is induced in the coil L4 of the code car¬ rier and applied to the comparator J2, such that the pulse shaper P4 generates a pulse sequence which corre¬ sponds to the code and which via the gate G4 and the decoder A is supplied to the memory M for writing the new code therein. During the writing of the new code, the counter PR5 counts the number of clock pulses applied to the counter PR2 and will emit a disabling signal on its output connected to an input of the gate G2, when the number of pulses counted by the counter PR5 is equal to the number of bit cells in the memory M. At the same time, the combinatory network K3 emits an output signal via the gate G6 to a programming voltage input of the memory M.

After a predetermined burn-in time, when the new code in the memory M is permanently stored there¬ in, the circuit V2 in the code receiver is reset. This is carried out more particularly in that the combina¬ tory network Kl on its output, which is connected to the reset input of the circuit V2, emits a signal for resetting the circuit V2. In this way, the code receiver in Fig. 4 is passed to reading mode. A rela¬ tively long interruption in the pulse train transferred via the coil L2 is now also made. The Schmitt trigger SI will then first generate its reset signal RSI, whereupon the Schmitt trigger S3 will generate its reset signal RS2. In this manner, the circuit VI is reset to its initial state, the memory M being passed to reading mode, the gate G5 is locked, the counter PR5 is reset, and the locking of the counter PR4 is suspended.

As appears from the above, the inventive code carrier is advantageous in that it allows a very fast transfer of information, in that it is self-sustaining, and in that it can be made programmable. Finally, it should be pointed out that further modifications of the above-described code carrier are possible within the scope of the invention. Thus, for instance, the signal increase from the transistor Tl or T2 can be made negative or be performed at an¬ other point of the period. Further, the term "code car¬ rier" should be understood in a broad sense, i.e. the invention is applicable to any equipment in which a binary code is stored and should be transferred to a receiver.

Claims

1. Method for transferring a binary code consist¬ ing of a plurality of bits from a code carrier to a code receiver, a periodic signal being inductively supplied from the code receiver to the code carrier, c h a r a c t e r i s e d by the steps, in each period of the inductively supplied periodic signal, of induc¬ tively transferring one bit in the code from the code carrier to the code receiver by addressing, by means of a first portion of each period of the periodic signal, a special memory cell which is provided in the code carrier and in which one bit in the code is stored, and giving the signal inductively supplied to the code carrier an increase in a second succeeding portion of the same period depending on the value of said bit, and of inductively detecting the signal increase in the code receiver.

2. Code carrier for transferring a code stored therein and consisting of a plurality of bits to a code receiver arranged to inductively supply a periodic signal to a sequentially addressable memory (M) provid¬ ed in said code carrier and having a number of bit cells corresponding to the number of bits in said code, c h a r a c t e r i s e d in that the memory (M) is addressable by means of a first portion in each period of the periodic signal, and that a pulse generator (Pi, P2, Tl) connected to an output of said memory is so controlled as to supply the periodic sig¬ nal in a second succeeding portion of the same period of the periodic signal, with an increase depending on the bit value on the output of the memory.

3. Code carrier as claimed in claim 2, c h a ¬ r a c t e r i s e d in that it is inductively con¬ nected to the code receiver via a single coil (Ll).

4. Code carrier as claimed in claim 3, c h a ¬ r a c t e r i s e d in that the pulse generator (Pi, P2, Tl) comprises a pulse shaper (PI, P2) connected to the output of the memory, and a drive circuit (Tl) connected to the coil (Ll) and controlled by the pulse shaper.

5. Code carrier as claimed in any one of claims 2-4, c h a r a c t e r i s e d in that the memory (M) is switchable between reading and writing by means of a circuit (PR4) for detecting a predetermined pat¬ tern in the periodic signal.

6. Code carrier as claimed in claim 5, c h a ¬ r a c t e r i s e d in that the detecting circuit (PR4) is a time circuit for detecting an interruption of predetermined length in the periodic signal.