WO1989001208A1

WO1989001208A1 - Data carrying devices

Info

Publication number: WO1989001208A1
Application number: PCT/GB1988/000644
Authority: WO
Inventors: Andrew Jim Kelley Glasspool; James Joseph Armour
Original assignee: Mars Incorporated
Priority date: 1987-08-04
Filing date: 1988-08-04
Publication date: 1989-02-09
Also published as: GB8718419D0; GB2207790A; JPH03501193A; KR890702158A; EP0378546A1; BR8807629A; GB2207790B

Abstract

A data carrying device (2) communicates in a contactless manner with an interrogator, which transmits data by amplitude modulation of a carrier (Fig. 4c). The device includes a data detection circuit (10) which is synchronized to the carrier and which generates a pulse (T1) of a first length at regular intervals if the carrier remains unmodulated and generates a pulse (T2) of a different length if a modulation of the carrier is detected. An input/output line (16) conveys the pulses to a processor (6). During data transmissions from the interrogator, pulses of both lengths, representing the data, are delivered to the processor. During data transmissions from the device (Fig. 3), pulses (104) of one length act as clock pulses determining the time at which data is applied to the input/output line by the processor. The impedance of the token is modulated, and the carrier thus affected in a detectable fashion, in response to the data placed on the input/output line by the processor.

Description

DATA CARRYING DEVICES

This invention relates to data carrying devices, and is particularly but not exclusively concerned with such devices which communicate in a contactless manner with device readers.

Examples of such devices are described in EP-A-147099, GB-A-2196450 and GB-A-2197107. EP-A-147099 describes an arrangement in which a reader, or interrogator transmits a carrier which is used to power a data carrying device in the form of a token. Data is transmitted to the token by amplitude modulation of the carrier (in particular by- interrupting the carrier at selected timings to produce 100 per cent amplitude modulation) , and data is transmitted by the token to the interrogator by selectively altering the token impedance at predetermined timings so that the effect on the carrier is detectable by the interrogator. The data transmissions from the interrogator and the token are synchronised with clock pulses transmitted by the interrogator.

One problem with this arrangement is the need for the processor in the token to have a crystal for ensuring that it operates at an accurate speed. Another problem is that even a fast processor is capable of only a relatively low communication rate if communication errors are to be avoided.

One proposal to mitigate these problems is disclosed in GB-A-2196450. In the arrangement described in that patent application, the processor is clocked by an oscillator whose frequency is controlled by the processor so that the processor operations are initially synchronised to a carrier received from the interrogator. Although this arrangement represents a substantial improvement, certain problems still remain. Because the frequency of operation of the token processor is not highly accurate, and could vary during a communication operation, and because the processor controls the timing of the communication operations, the speed of communication is still limited to a relatively low value. In addition, the arrangement requires several output lines between the token processor and the variable frequency oscillator. It would in some circumstances be desirable to use a token processor which has only a single input/output line.

In accordance with the present invention there is provided a data carrying device having a data detection circuit for receiving a carrier signal and for deriving data therefrom, the circuit being operable to count carrier pulses and to provide a data pulse of a first type in response to a predetermined count being reached and being operable to detect when no carrier pulses have been received for a predetermined interval (or when the

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characteristics of the carrier have altered for a predetermined interval) and in response thereto to generate a data pulse of a second type.

According to another aspect of the invention there is provided a data carrying device having a data detection circuit for receiving a carrier signal and for deriving data therefrom, the data detection circuit being operable to count carrier pulses so as to operate cyclically in synchronism therewith, and having means for initiating a new cycle of operations in response to detecting that the characteristics of the carrier have changed. Preferably, the new cycle is initiated only if the characteristics have altered for more than a predetermined interval.

Thus, for example, the operation of the data detection circuit and the interrogator can be synchronised using the carrier pulses despite the fact that the carrier is altered, e.g. interrupted, in order to transmit data, by using the altered carrier to restart a cycle of operations of the data detection circuit. Preferably, each cycle of operation is initiated either by a count of carrier pulses reaching a predetermined number, or in response to an alteration of the carrier. Thus, successive bits of data can be transmitted, one bit per cycle, by arranging at regular intervals for the carrier either to be altered or not altered depending upon the logic level of the bit being transmitted. (In an altervative arrangement, different types of carrier alteration are employed depending upon the data bit to be transmitted. Each type of carrier alteration initiates a new cycle of operations.)

If a cycle is to be started in response to the carrier having altered for a predetermined interval, it is preferably started at the time at which the carrier reverts to its normal condition (e.g. the cycle is restarted when the carrier resumes after having been interrupted) .

It is envisaged that the data detection circuit may form an interface between a carrier receiver (e.g. an antenna) and a control circuit (e.g. a processor) of the data carrying device (e.g. a token). The data detection circuit operates in response to counting the carrier pulses so that its operations remain synchronised to the carrier and it can therefore enable reliable communication at a precise data transfer rate without requiring an accurate processor speed, and without requiring the transmission of clock pulses which, for a given bandwidth, would slow the data transfer rate. Synchronization can be maintained in spite of temporary alterations of carrier characteristics or carrier interruptions.

A further aspect of the invention is directed to the communication between a data detection circuit of a data carrying device and a control circuit (e.g. processor) thereof. According to this aspect of the invention, the control circuit is operable to distinguish between data pulses of a first type from the data detection circuit and data pulses of a second type in accordance with the lengths of the pulses. This permits data pulses of both types to be transmitted along a single communication channel at spaced intervals and recognised and distinguished by the control circuit. Furthermore, so long as the difference in durations of the two types of pulses is sufficient, this operation can take place reliably without requiring a precise speed of operation of the control circuit.

According to a still further aspect of the present invention there is provided a data carrying device comprising a control circuit and an interface circuit, the interface circuit being operable to detect data received from an interrogator and transmit the data to the control circuit, and being further operable to receive data from the control circuit and to cause it to be transmitted to the interrogator, the device having an input/output line between the control circuit and the interface circuit, and the control circuit being operable in an output mode to place data pulses on the line in response to clock pulses transmitted along the line by the data detection circuit and in an input mode to sense data transmitted along the line by the interface circuit. Preferably, the data pulses transmitted by the interface circuit along the input/output line have durations dependent upon their logic type. Preferably, the processor alters the logic level on the input/output line when it transmits data pulses of a first type during its output mode and does not affect the logic level on the input/output line when data pulses of another logic type are to be transmitted.

Such an arrangement permits a single input/output line to be used for bi-directional communication between the interface circuit and the control circuit,' and further permits transmission of clock pulses using the same line.

An arrangement embodying the invention will now be described by way of example with reference to the accompanying drawings, in which:

Fig.1 is a schematic block diagram of a data carrying device in accordance with the invention;

Fig.2 is a waveform diagram illustrating the waveform of a carrier transmitted by an interrogator and the waveforms of various signals within the interrogator and the data carrying device at the beginning of a communication operation;

Fig.3 is a waveform diagram similar to that of Fig. but showing the waveforms when data is being transmitted by the token;

Fig.if is a waveform diagram similar to that of Fig.2 but showing the waveforms when data is being transmitted by the interrogator; -?-

Fig.5 is a waveform diagram of signals within an interface circuit of the token; and

Fig.6 is a diagram similar to Fig.5 but showing the waveforms at different times.

Referring to Fig.1 a data carrying device or token 2 has a data transmitting/receiving circuit in the form of a coil 4 and a control circuit in the form of a microprocessor 6. The device also has an interface circuit 8 disposed between the coil 4 and the processor 6. The interface circuit includes a data detection circuit 10 which derives data from a carrier received by the coil 4 and transmits this data to the processor 6, and a data transmission circuit 12 which receives data from the processor 6 and in response thereto alters the impedance across the coil 4 so as to affect the carrier transmitted by the interrogator in a manner which is detectable by the interrogator and therefore which can be interpreted as data. For example, the data transmission circuit 12 may be arranged to connect a low impedance 13 across the ends of the coil 4, or in another embodiment to alter the value of a capacitance connected across the ends of the coil.

In addition the data carrying device 2 has a power storage circuit (not shown) which receives power via a rectifying circuit (not shown) from the coil 4, and which supplies the power for the processor 6 and the rest of the data carrying device 2. -\ The microprocessor 6 has an input/output terminal 14 connected by an input/output line 16 to a buffer/driver circuit 18 of the interface circuit 8. The buffer/driver circuit 18 is coupled to an output 20 from the data detection circuit 10 and an input 22 of the data transmission circuit 12. The buffer/driver circuit 18 and a corresponding interface circuit within the microprocessor 6 at the other end of the input/output line 14 are designed in a well known manner in order that the input/output line 14 is normally held at a predetermined logic level, but can be brought to the other level by a signal on the input/output terminal 14 of the processor 6, and can also be brought to this other level by a signal on the output 20. If desired the circuit 18 can include gates to prevent changes in logic levels on output 20 from appearing at input 22.

The interrogator may be similar to that disclosed in EP-A-147099 or, preferably, that disclosed in GB-A-2197107. The interrogator has a data output line whose logic level determines the amplitude of a carrier transmitted by an antenna of the interrogator, and a data detection circuit which responds to carrier changes produced by alterations of the token impedance to produce data corresponding to that transmitted by the token upon a data input line. T O

Referring to Fig. 2, the waveforms on the interrogator's data output and input lines at the

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beginning of a communication operation are shown at (a) and (b) respectively. With reference to Fig.2(a), once the token has been received by the interrogator, the wave form rises so that the carrier, shown at Fig.2(c), starts to be transmitted. This causes power-up of the token. Shortly afterwards, a reset pulse indicated at 100 causes a brief interruption of the carrier.

Fig.2(d) shows the waveform on the input/output line 16 of the token. As will be explained below, the interruption of the carrier results in a negative-going pulse 102 being placed on the -input/output line 16 by the data detection circuit 10. This pulse is of relatively long duration, corresponding to nine carrier cycles, and is interpreted by the processor 6 to represent a logic level of 1. Thereafter, while the carrier is being transmitted without interruption, the data detection circuit regularly places short negative-going pulses 104 on the line 16, each pulse lasting for three carrier cycles and being interpreted by the processor 6 as representing logic 0's.

With reference to Fig.3, if the token needs to transmit data, the ^"processor waits until a logic 0 has been received along the line 16. Shortly after this pulse has terminated, the processor 6 is operable to apply a negative-going pulse to the line 16. Thus, referring to Fig.3(d), it will be observed that an - n-

initial logic pulse 106 is applied to the line immediately after a logic 0 pulse 104. This forms a start bit. After each successive logic 0 transmitted by the data detection circuit 20, the processor 6 selectively applies a negative-going pulse to line 16 dependent upon whether or not the bit to be transmitted Is a 1 or a 0. Thus, in Fig.3(d), the start bit 106 is followed by a logic 1 pulse 108, a logic 0 (because no pulse is applied after the subsequent pulse 104), a logic 1 pulse 110, a logic 0 and a further logic 1 pulse 112. The start bit and each logic 1 pulse results in the data transmission circuit 12 changing the impedance across the coil 4 and thus altering the waveform of the carrier as indicated at 114. These alterations are detected by the interrogator which thus generates corresponding logic pulses on the data input line as shown at Fig.3(b).

It will be appreciated from Fig.3 that the logic 0 pulses 104 generated by the data detection circuit 10 are used as clock pulses by the processor 6 to determine the timings at which it applies data pulses to the input/output line 16.

Referring to Fig.4, data transmissions by the interrogator are achieved by selectively interrupting the carrier. The carrier is interrupted for a brief period (e.g. 6 carrier cycles) in order to transmit a start bit and to transmit bits of logic 1. No interruptions occur when bits of logic 0 are transmitted. The data detection circuit 10 transmits lengthy pulses 116 representing logic 1 in response to interruptions of the carrier and short pulses 118 representing logic 0 if the interrogation does not interrupt the carrier, as will be explained below. Each of the logic 1 and logic 0 pulses starts a fixed time after the beginning of the preceding pulse.

The detailed operation of the device will be described with reference to Figs.1, 5 and 6.

The carrier received by the coil 4 is transmitted to a detector circuit 24 which compares the carrier with predetermined threshold levels TH thereby to generate pulses TC, each pulse corresponding to a half-cycle of the carrier. The pulses are delivered along line 26 to a modulo 29 counter indicated at 28. This counts the pulses, and when the count exceeds 28 it generates an overflow signal OF on line 30 and starts to count again from zero. The counter 28 also generates timing signals T1 , T2, and T3, which are used in controlling the timing of the operations of the interface circuit 8. Timing signal T1 (Fig.5) is generated when the count reached by counter 28 is 1 and ends as the count changes to 4, signal T2 (Fig.6) is generated for counts 1 to 9 inclusive, and signal T3 (Fig.6) for counts 13 to 18, inclusive.

The clock pulses TC are also delivered to a carrier-absence detector 32. This is formed by a counter - 1 ij~

which counts in response to an internal clock CL of the device, which is derived from the clock of the processor 6. This clock may be formed by a simple R-C oscillator, and need not have an accurate frequency. The detector 32 is reset by each of the carrier pulses TC. If the detector 32 counts up to a preset number, this indicates that no carrier has been received for a relatively long interval, and a carrier-absent signal CA is generated on output line 34. For reliable operation of the circuit It is ensured that all interruptions of the carrier produced by the interrogator are sufficiently long that they will be detected by the carrier-absence detector 32 for all frequencies of the internal clock within the permitted tolerance.

The carrier-absent signal CA^" is delivered to a reset input of the counter 28. The signal is also delivered to a set input of a latch circuit 36 whose reset input is coupled to receive overflow signal OF from counter 28. The output of the latch 36 determines whether timing signal T1 or timing signal T2 is coupled to the output line 20 of the data detection circuit 10.

The operation of the data detection circuit 10 is as follows. As soon as the carrier is being transmitted and the token has powered-up, the counter 28 starts to count. At some stage, the interrogator will interrupt the carrier. This will initially be done when the reset pulse 100 of Fig.2(a) is produced. This will terminate the carrier pulses TC so that the counter 28 will stop counting. After a number of cycles of the internal clock, the carrier-absence detector 32 will generate the carrier-absent signal CA which will reset the counter 28 and set the latch 36. If this is the first time an interruption in the carrier has been detected, then the condition of the counter 28 and thus of the timing signals T1 and T2 is indeterminate, so that the condition of the output signal 20 is not known. However, as soon as the interrogator starts to transmit the carrier once more, the carrier-absence signal CA disappears and the counter 28 begins to count from zero. Accordingly, because the latch 36 is still set, the timing signal T2 is applied to the output 20 and thus to the input/output line 16. Accordingly, a long 9-cycle pulse, representing Token Data In (TDI) logic level 1, is applied to the input/output line 16 as indicated in Fig.6 and at 102 in Fig.2(d).

Thereafter, the counter repeatedly counts from 0 to 28, and then overflows, at the same time resetting the latch 36. Accordingly, timing signal T1 is coupled to the output 20, and short 3-cycle pulses representing Token Data In (TDI) logic 0 are repeatedly applied to the input/output line 16 at regular intervals corresponding to 29 cycles of the carrier, as shown in in Fig.5 and Fig.2(d). - Mo-

It will be appreciated from the above that during data communications from the interrogator, each carrier interruption will result in a nine-cycle logic 1 pulse being applied to input/output line 16 (see Fig.6), and this will be followed by a logic zero pulse (see Fig.5) which will commence 29 cycles from the beginning of the logic 1 pulse unless a further carrier interruption occurs. This will generate the waveform shown in Figure 4(d) on the input/output line 16.

The data transmitted by the interrogator can be detected by the processor 6 without requiring the processor to operate at accurate timings and without requiring the processor to devote a large proportion of its processing operations to the detection of the data.^" In the preferred embodiment this is achieved as follows.

The processor's programme is designed so that during the communication procedure it performs operations in discrete stages, and none of the operations takes longer than a predetermined number of cycles of the carrier. Clearly, this programming must take into account the possible variations in processor speed if the processor's clock has a wide tolerance. After the processor detects a negative-going transition on the input/output line 16, it enters a routine whereby, after a predetermined number of processor cycles, it checks the level on the line 16 once more. If it is still low, then the processor determines that a logic 1 is present. Otherwise the processor determines that a logic 0 is present. The processor can then carry out a sequence of processing operations, which will be completed before the time that a subsequent logic pulse can be present on input/output line 16. When that sequence is completed, the processor repeatedly checks the logic level on line 16 until a low level has ϋeen detected. The operation is then repeated with the processor again checking after a predetermined number of processor cycles to determine whether the logic level represents a 0 or a 1. Such an arrangement enables a substantial amount of processing to take place at the same time as data is being received from the interrogator. In a particularly preferred embodiment of the invention, a de-cryption algorithm is solved between receipt of successive bits of data, so that de-cryption can take place at the same time as data transmission.

When data is to be transmitted by the processor 6, the processor first checks the input/output line 16 until it determines that a logic zero pulse has ended. The processor then applies a pulse 120 to the line 16 (see Fig.5), assuming that a Token Data Out (TDO)bit of logic 1 is to be transmitted. This causes the setting of a latch 38 in the data transmission circuit 12. Subsequently a gate 40 is opened by the timing signal T3 for count periods 13 to 18. The gate 40 thus passes the logic one level to a carrier modulating circuit element - 1 S-

42 in the form of a switch, which is thereby caused to alter the impedance across the coil 4 during the period of signal T3• As shown in Figure 3, this results in data pulses being received by the interrogator. The latch 38 is reset at an early point in each cycle (eg. by the leading edge of pulse T1 ) so that the switch 42 remains unoperated unless a pulse 120 is outputted by the processor 6.

It will be understood that after the period in which the processor can selectively apply a pulse 120 to the input/output line 16, there is an interval before the processor needs to check the line 16 for the presence of a logic zero clock pulse. As in the data receiving procedure, the processor can use this interval to perform other processing operations. In the preferred embodiment, the processor performs an encryption algorithm to determine the logic level to be transmitted following the next clock pulse. This enables extremely rapid performance of the token.

The pulse 120 can be presented on the input/output line 16 at any time after count period 4 until the beginning of the count period 13 to generate an impedance alteration at the correct time and for the correct duration. This is a further factor enabling a wide variation in processor speeds.

In the above embodiment, the processor regularly checked the level on input/output line 16,^* and waited until a logic zero clock pulse occurred. However, this - 1^<

is not essential. For example, the clock pulses could be arranged to produce an interrupt signal which causes the processor temporarily to halt its processing operations in order to carry out a communication operation.

The preferred embodiment of the invention operates at a communication rate of 9_.600 baud, using half duplex techniques. However, full duplex transmissions and other baud rates can be employed. The baud rate could be made programmable by allowing the processor to control the value at which the counter 28 overflows.

In the described embodiment, using the baud rate of 9600, the frequency of operation of the process^'or in the token may for example have an overall tolerance of plus or minus 20$.

It will be appreciated that many modifications to the above arrangement are possible.

The token preferably has a non-volatile memory for storing data, and this may be formed on the same chip as the processor 6, or on a separate chip connected to the processor. The interface circuit 8 may be on the same chip as the processor 6.

Instead of using a processor 6, the control circuit may be a simple logic circuit connected to control the inputting and outputting of data to and from a memory.

In the above embodiment the input/output line 16 carried clock pulses, token data and interrogator data. Instead, these could be carried on two or three separate lines. The clock pulses could be transmitted while the data pulses are present. Instead of representing the different logic values of the interrogator data by pulses of different lengths, the pulses can be presented on different lines. Obviously, the logic values represented by the various signals can be inverted.

In the above embodiment, one type of logic value is represented by the interruption by the carrier, and another logic value is represented by the carrier maintaining its amplitude. Other possibilities include (.a) the carrier being only partially modulated, e.g. so that its amplitude is decreased by half during the transmission of one type of logic value, and (b) one type of logic value being represented by a decrease in amplitude and the other by an increase in amplitude. Instead of amplitude modulation, frequency or phase modulation could be used.

The present invention Is particularly applicable in systems in which a single carrier is used to transmit power to a data carrying device and for bidirectional data communication. However, the invention is applicable also to systems in which power is transmitted using a different signal from the data carrier, although In those systems it may be more appropriate if the power transmissions are continuous to derive clock pulses from those transmissions rather than the data carrier.

Claims

-1\ -CLAIMS :

1. A data-carrying device comprising a control circuit, a receiving circuit for receiving a carrier signal, and a data detection circuit for deriving data from the received carrier and for transmitting the data to the control circuit, the data detection circuit being operable to detect changes in the characteristics of the carrier lasting for more than a predetermined interval and in response thereto to produce a signal indicative of a first logic level, and to produce a signal indicative of a second logic level in response to having detected a predetermined number of carrier cycles without any such alteration of the characteristics having occurred.

2. A device as claimed in claim 1, including a carrier cycle counter for counting carrier cycles, the counter being arranged to cause the second logic level to be produced on reaching a predetermined count value and thereafter being operable to start counting carrier cycles again.

3- A device as claimed in claim 2, including means responsive to the characteristics of the carrier being altered for more than a predetermined interval for resetting the counter so that the counter begins to count again when the carrier resumes its former characteristics.

4. A device as claimed in any preceding claim, Including a data transmission circuit operable to cause token data to be transmitted.

5- A device as claim in claim 4, including means for changing the impedance of the device in response to data to be transmitted by the device, so that data transmissions can be detected by determining changes in the carrier caused by said impedance changes.

6. A device as claimed in claim 4 or 5, wherein the data transmission circuit is operable to cause token data to be transmitted at timings synchronized with the received carrier cycles.

7- A device as claimed in claim 4, 5 or 6, wherein the control circuit is operable to send data pulses to the data transmission circuit at timings determined by one of said first and second logic level signals received from said data detection circuit.

δ. A device as claimed in claim 7, wherein the timings are determined by the second logic level signals received from said data detection circuit.

9- A device as claimed in any one of claims 4 to 8 including an input/output line for conveying first and second logic level signals to the control circuit and for conveying output data from the control circuit to the data transmission circuit.

10. A device as claimed in claim 9, wherein the input/output line is operable in an output mode of the device to convey said output data from the control circuit and to convey timing signals derived by the data detection circuit from the received carrier to the control circuit.

11. A device as claimed in any preceding claim, wherein the first logic level signals have a different duration from the second logic level signals, and wherein the control circuit is operable to determine the logic levels in dependence on the duration of the signals.

12. A device as claimed in any preceding claim, wherein the receiving circuit is operable to receive the carrier in a contactless manner.

13- A device as claimed in any preceding claim, including means for deriving power for the device from the received carrier. -2f-

14. A data carrying device having a data detection circuit for receiving a carrier signal and for deriving data therefrom, the data detection circuit being operable to count carrier pulses so as to operate cyclically in synchronism therewith, and having means for initiating a new cycle of operations in response to detecting that the characteristics of the carrier have changed.

15- A data carrying device comprising a control circuit, a data detection circuit for detecting received data and for delivering the data to the control circuit, and a data transmission circuit for receiving from the control circuit data to be transmitted by the device, the device including an input/output line for conveying the data from the data detection circuit to the control circuit in

•e an input mode of the control circuit, and for conveying clock pulses to the control circuit and data from the control circuit in an output mode of the control circuit.

16. A data carrying device as claimed in claim 15 wherein the data detection circuit is operable to derive the received data and the clock pulses from a received carrier.

17- A device as claimed in claim 15 or 16, wherein the data conveyed to the control circuit during the input mode of the control circuit comprises first and second types of data pulses which are distinguished by the control circuit in dependence on the duration thereof.

18. A device as claimed in claim 15, 16 or 17, wherein the control circuit is operable in its output mode either to alter the logic level on the input/output line or to leave the logic level unaltered during intervals each determined by a respective clock pulse, in dependence upon the data to be transmitted.

19- A data carrying device substantially as herein described with reference to the accompanying drawings.