WO1989001236A1 - A method of providing refilled trenches - Google Patents

A method of providing refilled trenches Download PDF

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Publication number
WO1989001236A1
WO1989001236A1 PCT/GB1988/000597 GB8800597W WO8901236A1 WO 1989001236 A1 WO1989001236 A1 WO 1989001236A1 GB 8800597 W GB8800597 W GB 8800597W WO 8901236 A1 WO8901236 A1 WO 8901236A1
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WO
WIPO (PCT)
Prior art keywords
trench
glass
layer
spin
providing
Prior art date
Application number
PCT/GB1988/000597
Other languages
French (fr)
Inventor
Shane Duncan
Original Assignee
Plessey Overseas Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Plessey Overseas Limited filed Critical Plessey Overseas Limited
Publication of WO1989001236A1 publication Critical patent/WO1989001236A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Definitions

  • the present invention relates to a method of providing refilled trenches and in particular to a method of refilling deep trenches with spin-on glass.
  • trenches in integrated circuit (i.c) technology is a known technique for providing component isolation and mechanical stability.
  • the trenches are formed by etching through the epitaxial layer and buried N+ layer.
  • the trench is then refilled with a refill material which is usually polysilicon.
  • One such method comprises refilling the trench completely with polysilicon.
  • a grain boundary is formed down the middle of the trench since the deposition of polysilicon extends from the side walls of the trench inwards.
  • This grain boundary is fissile such that during field oxidation, the oxide may extend into the trench along the grain boundary.
  • the oxide acts on the polysilicon, creating pressure on the sidewalls of the trench which can result in defects being formed in the epitaxial layer. Attempts have ' been made to reduce this pressure by depositing a thinner layer of polysilicon on the sidewalls. However, it has proven impractical to control the required thickness for minimising pressure on the sidewalls whilst ensuring that the trench is filled.
  • a more preferable refill material is spin-on glass since it can be applied by a less specialised process and is a material which is self-planarising.
  • spin-on glass is a known material in the art and comprises polymethyle syloxane.
  • the present invention seeks to provide a method for refilling deep trenches using spin-on glass whilst substantially eliminating the aforementioned disadvantages.
  • a method of providing refilled trenches comprises: etching a trench; growing a passivating layer for lining the trench: providing fillets along each respective sidewall of the trench contiguous with the passivating layer, having a void therebetween; and filing the said void with spin-on glass.
  • the fillets are provided by depositing a layer of polysilicon and anisotropically etching the said layer.
  • the method may comprise the following steps of curing the spin-on glass and etching the spin-on glass, thereby providing a planarised trench surface.
  • Figures 1, 2, 3, and 4 are schematic cross-sections of trenches at various stages of the method in accordance with a first embodiment
  • Figures 5, 6, and 7 are schematic cross-sections of trenches at various stages of the method in accordance with a second embodiment.
  • a trench 2 is plasma etched through the epitaxial layer 4 and buried N+ layer 6.
  • the dimensions of the trench are typically 5 ⁇ m deep and 2 ⁇ m wide.
  • the trench 2 is introduced to provide component isolation in the integrated circuit, the components (not shown) being disposed in the epitaxial layer 4.
  • a layer of thermal oxide 8 is grown to provide a suitable passivating layer.
  • This layer of thermal oxide 8 typically comprises a homogenous, amorphous material possessing a structure of silicon-oxygen bonds grown at a high temperature.
  • a thick layer of polysilicon 10 is then deposited usually by a low pressure chemical vapour deposition (LPCVD) process.
  • LPCVD low pressure chemical vapour deposition
  • This layer is then anisotropically etched in a vertical direction to form large sidewall fillets 12 running down the sidewalls of the trench 2 as shown in figure 2.
  • the width of the fillets 12 is approximately 0.7 ⁇ m.
  • These fillets 12 leave a void 13 running down the middle of the trench 2, of a width approximately 0.5 ⁇ m.
  • the trench 2 is etched through the epitaxial layer 4 and buried N+ layer 6.
  • a passivating layer is provided by growing the layer of thermal oxide 8.
  • a layer of silicon nitride 16 is then deposited, followed by a thin layer of polysilicon 10.
  • the depth of the polysilicon is approximately 0.3 ⁇ m.
  • This layer of polysilicon 10 is anisotropically etched in a vertical direction, to leave thin sidewall fillets 18 as shown in Figure 6.
  • a void 20 remains therebetween running down the trench 2, of an approximate width 1.4 ⁇ m.
  • the width of this void 20 is too wide to avoid cracking of the spin-on glass during the curing process, if introduced at this stage. Therefore, the fillets 18 are completely oxidised and swell so as to leave a narrower void 20, see Figure 7.
  • the layer of silicon nitride 16 protects the surface and sidewalls of the trench 2 from this oxidation process.
  • the void 20 is then filled with spin- on glass, cured at a high temperature and then etched back to provide a planarised trench 2.
  • spin-on glass as a refill material ensures low isolation capacitance between adjacent buried N+ layers whilst improving surface planarity after refill. Furthermore, the probability of defect formation in the eptaxial layer 4 is reduced.
  • this is due to a reduced exposure area of the polysilicon fillets 12 to any subsequent field oxidation. Also if the top of the fillets 12 do become oxidised, then the resultant pressure tends to act on the spin-on glass 14 rather than the sidewalls of the trench 2.
  • the refill material in the trench namely the fillets 18 and the spin-on glass 20
  • the refill material in the trench namely the fillets 18 and the spin-on glass 20
  • the problem of defect formation is obviated.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

A method of providing refilled trenches, for use in i.c. technology, using spin-on glass (14). The method comprises etching a trench through the substrate, growing a passivating layer (8), providing fillets (12) on the sidewalls of the trench, defining a void (13) therebetween and filling the void with spin-on glass (14). The glass is then cured at a high temperature and etched back to provide a planarised trench. The fillets reduce the effective width of the trench, thereby enabling spin-on glass to be introduced and avoiding the problem of the glass cracking during the curing process.

Description

A METHOD OF P OVIDTNG REFILLED TRENCHES
The present invention relates to a method of providing refilled trenches and in particular to a method of refilling deep trenches with spin-on glass.
The use of trenches in integrated circuit (i.c) technology is a known technique for providing component isolation and mechanical stability. The trenches are formed by etching through the epitaxial layer and buried N+ layer. The trench is then refilled with a refill material which is usually polysilicon.
Previously proposed methods of introducing the refill material have been susceptible to defect generation in the epitaxial layer during the succeeding stages of device processing.
One such method comprises refilling the trench completely with polysilicon. When the trench is completely filled, a grain boundary is formed down the middle of the trench since the deposition of polysilicon extends from the side walls of the trench inwards. This grain boundary is fissile such that during field oxidation, the oxide may extend into the trench along the grain boundary. The oxide acts on the polysilicon, creating pressure on the sidewalls of the trench which can result in defects being formed in the epitaxial layer. Attempts have' been made to reduce this pressure by depositing a thinner layer of polysilicon on the sidewalls. However, it has proven impractical to control the required thickness for minimising pressure on the sidewalls whilst ensuring that the trench is filled. Generally, methods using an oxide as a refill material are restricted to specialised chemical vapour deposition (CVD) processes and require large thicknesses of material to planarise the trench surface. A more preferable refill material is spin-on glass since it can be applied by a less specialised process and is a material which is self-planarising.
However, thick layers or large volumes of spin-on glass are susceptible to cracking at high temperatures during the curing process. Spin-on glass is a known material in the art and comprises polymethyle syloxane.
Hence, the present invention seeks to provide a method for refilling deep trenches using spin-on glass whilst substantially eliminating the aforementioned disadvantages.
According to the present invention there is provided, a method of providing refilled trenches, which method comprises: etching a trench; growing a passivating layer for lining the trench: providing fillets along each respective sidewall of the trench contiguous with the passivating layer, having a void therebetween; and filing the said void with spin-on glass.
Preferably, the fillets are provided by depositing a layer of polysilicon and anisotropically etching the said layer.
Furthermore, the method may comprise the following steps of curing the spin-on glass and etching the spin-on glass, thereby providing a planarised trench surface. Particular embodiments of the present invention will now further be described with reference to the accompanying drawings, of which:
Figures 1, 2, 3, and 4 are schematic cross-sections of trenches at various stages of the method in accordance with a first embodiment; and
Figures 5, 6, and 7 are schematic cross-sections of trenches at various stages of the method in accordance with a second embodiment.
Referring to the drawings there is shown schematic cross- sections of silicon substrate for one micron feature size integrated circuits. A trench 2 is plasma etched through the epitaxial layer 4 and buried N+ layer 6. The dimensions of the trench are typically 5μ m deep and 2μm wide. The trench 2 is introduced to provide component isolation in the integrated circuit, the components (not shown) being disposed in the epitaxial layer 4.
After etching the trench 2, a layer of thermal oxide 8 is grown to provide a suitable passivating layer. This layer of thermal oxide 8 typically comprises a homogenous, amorphous material possessing a structure of silicon-oxygen bonds grown at a high temperature.
In accordance with the first embodiment shown in Figures 1 to 4, a thick layer of polysilicon 10 is then deposited usually by a low pressure chemical vapour deposition (LPCVD) process.
This layer is then anisotropically etched in a vertical direction to form large sidewall fillets 12 running down the sidewalls of the trench 2 as shown in figure 2. The width of the fillets 12 is approximately 0.7μm. These fillets 12 leave a void 13 running down the middle of the trench 2, of a width approximately 0.5μm.
Glass is then spun-on, filling the void 13 and resides above the surface of the trench 2. Since the material spin-on glass is self- planarising, in this application it will tend to form a uniform layer parallel to the thermal oxide layer 8, as shown in Figure 3. The spin- on glass is then cured at a high temperature, forming a stable oxide. The cured glass is then etched to form a planarised trench 2 as shown in Figure 4.
The second embodiment of the present invention will now be described with reference to Figures 5, 6 and 7.
As before, the trench 2 is etched through the epitaxial layer 4 and buried N+ layer 6. A passivating layer is provided by growing the layer of thermal oxide 8.
As shown in Figure 5 a layer of silicon nitride 16 is then deposited, followed by a thin layer of polysilicon 10. The depth of the polysilicon is approximately 0.3μm. This layer of polysilicon 10 is anisotropically etched in a vertical direction, to leave thin sidewall fillets 18 as shown in Figure 6. Thus a void 20 remains therebetween running down the trench 2, of an approximate width 1.4μm. The width of this void 20 is too wide to avoid cracking of the spin-on glass during the curing process, if introduced at this stage. Therefore, the fillets 18 are completely oxidised and swell so as to leave a narrower void 20, see Figure 7. The layer of silicon nitride 16 protects the surface and sidewalls of the trench 2 from this oxidation process. As in the first embodiment, the void 20 is then filled with spin- on glass, cured at a high temperature and then etched back to provide a planarised trench 2.
The use of spin-on glass as a refill material ensures low isolation capacitance between adjacent buried N+ layers whilst improving surface planarity after refill. Furthermore, the probability of defect formation in the eptaxial layer 4 is reduced.
In the first embodiment, this is due to a reduced exposure area of the polysilicon fillets 12 to any subsequent field oxidation. Also if the top of the fillets 12 do become oxidised, then the resultant pressure tends to act on the spin-on glass 14 rather than the sidewalls of the trench 2.
In the second embodiment, the refill material in the trench, namely the fillets 18 and the spin-on glass 20, is already oxidised and therefore not susceptible to further oxidation. Hence, the problem of defect formation is obviated.
It will be readily apparent to a man skilled in the art, that the foregoing description has been given by way of example only and modifications may be made without departing from the scope of the present invention.

Claims

1. A method of providing refilled trenches for use in integrated circuit (i.c) technology, which method comprises: etching a trench; growing a passivating layer for lining the trench; providing fillets along each respective sidewall of the trench contiguous with the passivating layer, having a void therebetween; and filling the said void with spin-on glass.
2. A method as claimed in claim 1, wherein after growing the passivating layer, depositing a layer of silicon nitride.
3. A method as claimed in claim 1 or claim 2, wherein the fillets are provided by depositing a layer of polysilicon and anisotropically etching the said layer of polysilicon.
4. A method as claimed in claims 2 and 3, which method comprises oxidising the fillets.
5. A method as claimed in any one of the preceding claims, wherein the passivating layer is a layer of thermal oxide comprising a structure of silicon-oxygen bonds.
6. A method as claimed in any one of the preceding claims, comprising the further steps of curing the spin-on glass and etching the spin-on glass, thereby providing a planarised trench surface.
7. A method of providing refilled trenches substantially as herein before described with reference to the accompanying drawings.
8. An integrated circuit having at least one refilled trench substantially as provided by the aforegoing method.
PCT/GB1988/000597 1987-07-24 1988-07-22 A method of providing refilled trenches WO1989001236A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8717612A GB2207281B (en) 1987-07-24 1987-07-24 A method of providing refilled trenches
GB8717612 1987-07-24

Publications (1)

Publication Number Publication Date
WO1989001236A1 true WO1989001236A1 (en) 1989-02-09

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EP (1) EP0324020A1 (en)
JP (1) JPH02500153A (en)
GB (1) GB2207281B (en)
WO (1) WO1989001236A1 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2207281B (en) * 1987-07-24 1992-02-05 Plessey Co Plc A method of providing refilled trenches
EP0657925A1 (en) * 1993-12-06 1995-06-14 STMicroelectronics, Inc. Enhanced planarization technique for an integrated circuit
US5472022A (en) * 1993-11-02 1995-12-05 Genentech, Inc. Injection pen solution transfer apparatus and method
US5793114A (en) * 1993-12-17 1998-08-11 Sgs-Thomson Microelectronics, Inc. Self-aligned method for forming contact with zero offset to gate
US6051864A (en) * 1993-12-17 2000-04-18 Stmicroelectronics, Inc. Memory masking for periphery salicidation of active regions
US6107194A (en) * 1993-12-17 2000-08-22 Stmicroelectronics, Inc. Method of fabricating an integrated circuit
US11342441B2 (en) 2012-07-17 2022-05-24 Unm Rainforest Innovations Method of forming a seed area and growing a heteroepitaxial layer on the seed area

Families Citing this family (4)

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DE3902701A1 (en) * 1988-01-30 1989-08-10 Toshiba Kawasaki Kk METHOD FOR PRODUCING A SEMICONDUCTOR ARRANGEMENT
US5244827A (en) * 1991-10-31 1993-09-14 Sgs-Thomson Microelectronics, Inc. Method for planarized isolation for cmos devices
SE520115C2 (en) * 1997-03-26 2003-05-27 Ericsson Telefon Ab L M The ditch with flat top
US6063693A (en) * 1998-03-23 2000-05-16 Telefonaktiebolaget Lm Ericsson Planar trenches

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EP0084635A2 (en) * 1981-12-30 1983-08-03 International Business Machines Corporation Method of forming a wide deep dielectric filled isolation trench in the surface of a silicon semiconductor substrate
JPS60121737A (en) * 1983-12-06 1985-06-29 Nec Corp Element isolating method for semiconductor device

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US4571819A (en) * 1984-11-01 1986-02-25 Ncr Corporation Method for forming trench isolation structures
GB2207281B (en) * 1987-07-24 1992-02-05 Plessey Co Plc A method of providing refilled trenches

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EP0084635A2 (en) * 1981-12-30 1983-08-03 International Business Machines Corporation Method of forming a wide deep dielectric filled isolation trench in the surface of a silicon semiconductor substrate
JPS60121737A (en) * 1983-12-06 1985-06-29 Nec Corp Element isolating method for semiconductor device

Non-Patent Citations (6)

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Title
IBM Technical Disclosure Bulletin, vol. 26, no. 7A, December 1983 (New York, US) K.D. Beyer et al.: "Lead silicate glass isolation technology", pages 3194-3197 *
IBM Technical Disclosure Bulletin, vol. 27, no. 11, April 1985 (New York, US) "Isolation trench filling", page 6524 *
IBM Technical Disclosure Bulletin, vol. 27, no. 2, July 1984 (New York, US) K.D. Beyer et al.: "Borosilicate glass trench fill", pages 1245-1247 *
IBM Technical Disclosure Bulletin, vol. 28, no. 6, November 1985 (New York, US) "Trench filling process", pages 2583-2584 *
IBM Technical Disclosure Bulletin, vol. 29, no. 3, August 1986 (New York, US) "Bird's beak-free recessed oxide isolation process", pages 1215-1216 *
Patent Abstracts of Japan, vol. 9, no. 277, (E-355)(2000) & JP-A-60121737 (NIPPON DENKI K.K.) 29 June 1985 *

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2207281B (en) * 1987-07-24 1992-02-05 Plessey Co Plc A method of providing refilled trenches
US5472022A (en) * 1993-11-02 1995-12-05 Genentech, Inc. Injection pen solution transfer apparatus and method
US5986330A (en) * 1993-12-06 1999-11-16 Stmicroelectronics, Inc. Enhanced planarization technique for an integrated circuit
EP0657925A1 (en) * 1993-12-06 1995-06-14 STMicroelectronics, Inc. Enhanced planarization technique for an integrated circuit
US5633534A (en) * 1993-12-06 1997-05-27 Sgs-Thomson Microelectronics, Inc. Integrated circuit with enhanced planarization
US5837613A (en) * 1993-12-06 1998-11-17 Stmicroelectronics, Inc. Enhanced planarization technique for an integrated circuit
US6107194A (en) * 1993-12-17 2000-08-22 Stmicroelectronics, Inc. Method of fabricating an integrated circuit
US6051864A (en) * 1993-12-17 2000-04-18 Stmicroelectronics, Inc. Memory masking for periphery salicidation of active regions
US5793114A (en) * 1993-12-17 1998-08-11 Sgs-Thomson Microelectronics, Inc. Self-aligned method for forming contact with zero offset to gate
US6284584B1 (en) 1993-12-17 2001-09-04 Stmicroelectronics, Inc. Method of masking for periphery salicidation of active regions
US11342441B2 (en) 2012-07-17 2022-05-24 Unm Rainforest Innovations Method of forming a seed area and growing a heteroepitaxial layer on the seed area
US11342438B1 (en) 2012-07-17 2022-05-24 Unm Rainforest Innovations Device with heteroepitaxial structure made using a growth mask
US11342442B2 (en) 2012-07-17 2022-05-24 Unm Rainforest Innovations Semiconductor product comprising a heteroepitaxial layer grown on a seed area of a nanostructured pedestal
US11349011B2 (en) 2012-07-17 2022-05-31 Unm Rainforest Innovations Method of making heteroepitaxial structures and device formed by the method
US11374106B2 (en) 2012-07-17 2022-06-28 Unm Rainforest Innovations Method of making heteroepitaxial structures and device formed by the method
US11456370B2 (en) 2012-07-17 2022-09-27 Unm Rainforest Innovations Semiconductor product comprising a heteroepitaxial layer grown on a seed area of a nanostructured pedestal

Also Published As

Publication number Publication date
EP0324020A1 (en) 1989-07-19
GB2207281B (en) 1992-02-05
GB8717612D0 (en) 1987-09-03
GB2207281A (en) 1989-01-25
JPH02500153A (en) 1990-01-18

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