WO1990000826A1

WO1990000826A1 - Circuit protection arrangement

Info

Publication number: WO1990000826A1
Application number: PCT/GB1989/000808
Authority: WO
Inventors: David Mansel Williams
Original assignee: Raychem Limited
Priority date: 1988-07-13
Filing date: 1989-07-13
Publication date: 1990-01-25
Also published as: IL90962A0; GB8816631D0

Abstract

A switching arrangement (3), for example for protecting an electrical circuit from a voltage transient, comprises a threshold foldback electrical device (3') for example a spark gap or a chalcogenide glass device, and connected in series therewith, a device (3'') comprising a body of an amorphous, intrinsically semiconducting silicon compound and a pair of n- or p-doped amorphous silicon compound regions located on, and separated by, the intrinsically semiconducting compound. Preferably the device is formed monolithically by sequential deposition of the silicon and other layers.

Description

Circuit Protection Arrangement

This invention relates to electrical circuits that are protected from voltage transients and to devices for protecting circuits from voltage transients.

Voltage transients may be produced in electrical circuits by a variety of methods, for example by lightning or electrostatic discharge. These phenomena may all induce very large currents on cables and struc¬ tures such as aircraft and ships which can penetrate and damage electrical systems, either causing hardware damage such as semiconductor burnout or electronic upset such as transmission loss or loss of stored data.

Electrostatic discharges are extremely fast discharges from a capacitor such as a human body. These discharges, because they can be so local, present a great threat to the individual electronic components. Induced electrical transients caused by lightning represent a threat to electrical/electronic equipment especially in aerospace vehicles. The induςed pulses are described in the SAE AE4L committee report AE4L-81-22, the two basic types being waveform 3 with a frequency of between 1 and 10 MHz, a rise time of 45 nanoseconds and a peak current of 24 amps, and waveform 4A which is a decaying exponential with a rise time of 100 nanoseconds, a width of 2 microseconds, a peak voltage of 300 volts and a peak current of 60 amps.

It has been proposed to protect circuits from such transients by means of a threshold foldback device con¬ nected in parallel with the load. Such devices will change from a high resistance state to a low resistance state on application of a high voltage (the lowest such voltage being referred to as the "threshold voltage") whereupon the voltage across the device will fall to a fraction of the threshold voltage, but will remain in their low resistance state only for as long as a small "holding" current is maintained. Examples of threshold foldback devices include gas discharge tubes (spark gaps), and chalcogenide glass devices for example as described in our European patent applications Nos. 196,891, 261,939, 261,937 and 261,938. Other devices include for example diacs and triacs diodes. Such devices function well at protecting electrical circuits from electrical transients, but often may need to be connected in series with a capacitor in_. order to pre¬ vent the normal d.c. signals latching the device in its low resistance state. The use of such a capacitor, preferably one having a capacitance of at least 2 uF, is proposed in our European application No. 198,624. However, the use of a capacitor in this way has the disadvantage that, when the electrical circuit is sub¬ jected to very large transients, e.g. transients that last for 1 us or longer, the capacitor will become charged and the potential across the capacitor, and hence across the load, will rise. In fact, we have found that when circuits are subjected to some of the threats described above, the voltage across the load found that when circuits are subjected to some of the threats described above, the voltage across the load that is caused by charging of the capacitor may cause damage to the circuit.

According to the present invention there is provided a switching arrangement, for example for protecting an electrical circuit from a voltage transient, which comprises a threshold foldback electrical device and, connected in series therewith, a device comprising a body of an amorphous, intrinsically semiconducting sili¬ con compound and a pair of n- or p-doped amorphous sili¬ con compound regions located on, and separated by, the intrinsically semiconducting silicon compound.

The threshold foldback device used in the arrangement may comprise any of the devices described* above but pre¬ ferably comprises a solid state device e.g. an amorphous chalcogenide device.

The amorphous silicon device used in the arrangement, may be referred to as a "nin" device or a "pip" device depending on whether the doped layer contains an n- or p-dopant. For the sake of brevity the devices are referred to^' herein as "nin" devices whatever dopants they contain. The device will normally employ an insu¬ lating layer of thickness in the range of from 100 to 5000 nm, especially from 500 to 2000 nm. Thus the device will have the characteristics of a parallel plate capacitor, at least ^"at low applied voltages, with a capitance in the range of from 20 pF to 1 nF. In addi¬ tion the nin device should normally exhibit a clamping voltage that is greater, e.g. at least 1.5 times as great as the normal operating voltages of the circuit in order to prevent the normal operating voltage holding the foldback device in it,s. low resistance (or "on") When an electrical circuit that is protected by the arrangement according to the invention is subjected to a transient, the threshold voltage device will change to its low resistance state as the applied voltage across the load exceeds the threshold voltage of the device. At this stage, during which the tran¬ sient voltage rises rapidly, the transient will be shunted across the load and the nin device will conduct current across the load until the transient voltage subsides to a value below the clamping voltage of the nin device. Thus, according to the invention, the maximum voltage across the load during the transient, apart from any very short duration spike experienced before the threshold foldback device has switched, will correspond to the clamping voltage of the nin device. The arrangement according to the invention thus has the advantage that the nin device limits the energy passed through the load during long transients and prevents the normal d.c. signals in the circuit latching the foldback device in its low resistance state (on state) , while the total capacitance of the arrangement is usually determined by the capacitance of the foldback device since, at least for nin devices which clamp at lower voltages, this is normally lower than that of the nin device. Preferably the threshold foldback device has a capacitance of not more than 500 pF, more pre¬ ferably not more than 100 pF and especially not more than 50 pF. The arrangement also has the advantage that the nin's high resistance (or "off") state often has a higher resistance than that of the threshold device alone and in many cases much higher, e.g\ at least ten times that of the foldback device. Thus, for example, while it is often difficult to form a chalco¬ genide glass device having an "off" state resistance greater than 1 Mohm when used alone, the resistance of a combination of such a device with a nin device may well be greater than 10 Mohms, and often greater than 100 Mohms. In contrast, devices such as varistors, which are generally relatively leaky having a low off- state resistance at least when used at voltages near their clamping voltage, can be used only with foldback devices such as spark-gaps having very high off-state resistance. Furthermore, even though chalcogenide glass foldback devices are recognised as very fast switches, usually switching in less than 100 picose¬ conds, we have found no significant reduction in the switching speed when a nin device is included with the chalcogenide glass device.

For transient pulses with no significant low fre¬ quency components the nin device will show no signifi¬ cant impedance and is essentially transparant to the pulse. Thus the arrangement according to the invention may be used to protect circuits (a.c. or d.c). from very fast transients and very slow transients with large low frequency components, without letting signi¬ ficant amounts of energy to the load.

It is believed that the electrical behaviour of the nin device employed in the arrangement according to the invention is due to a mechanism called space charge ' limited conduction in which the device behaves as a resistor at low fields where the effect of the equilibrium carrier predominates, amorphous silicon being highly resistive and the device may have an "off" resistance in the order of 10^1 ohms in the ohmic region of its I-V characteristics. At high fields, however, the n-doped contacts or the p-doped contacts inject either electrons or holes

on the polarity. Holes have a very short lifetime in amorphous silicon and are trapped before they can recombine with the injected electrons, as a result of which the electron and hole space charges only par¬ tially neutralise each other leaving an excess electron concentration which increases with increasing electric field. At this point the conduction is said to have become space-charge limited, and the current increases sharply as the excess electrons accumulate, according to the equation:

Where I and V are the current and voltage, k is a constant, d is the thickness of the amorphous silicon layer and the exponent n reflects the non-linearity of the device. Preferably n has a value of at least 4 and most preferably at least 6 and usually up to 10.

Preferably the amorphous silicon compound forming the middle layer or "i" layer has been formed by reacting amorphous silicon with a passivating agent in order to remove or substantially reduce the number of unpaired electrons occurring therein. Although it is possible in all cases to passivate the silicon layer after deposition e.g. by means of a hydrogen plasma or by ion implantation, it is much preferred to passivate the silicon simultaneously with deposition of the sili¬ con.

The layer will normally be formed by a vapour deposition process, e.g. by evaporation, by chemical vapour deposition, plasma deposition or a sputtering process, in which cases the passivating agent may be present in the deposition atmosphere to react with the silicon being deposited. The passivating agent pre¬ ferably comprises hydrogen or a halogen, more pre¬ ferably hydrogen or fluorine, and especially hydrogen. In the case of plasma deposition, in which silane is employed as the vapour, the hydrogen passivating agent may be formed _in situ by decomposition of the silane. Preferably 1 to 25, more preferably 5 to 15 atomic per¬ cent hydrogen may be incorporated in the silicon based film in order to remove the so-called "dangling bonds", the term "dangling bonds" as used herein simply being intended to mean unpaired electrons in the silicon atom valence orbitals. The degree to which the silicon atom "dangling bonds" are passivated will depend on the deposition conditions including the deposition pressure and material. The number of dangling bonds is reduced from an original value of about 10^0 e ^~l cm^~3 to 10^5 to 101 eV~l cm^~3. The reduction in the dangling bond density due to passivation will relieve mechanical stress in the rigid tetrahedral structure and will sharply decrease the density of localized states thus decreasing the material's room temperature conductivity by many orders of magnitude. Normally the switching material will have resistivity in the range of 10⁹ to 10 -^■-^■ ohm cm.

The silicon/hydrogen compound layer may advan¬ tageously be formed by depositing silicon by plasma deposition from a silane atmosphere. The silane is fed into a vacuum chamber maintained at a pressure of about 0.1 Torr, and passed between a pair of electrodes one of which may be earthed and the other of which self biases to a high negative potential due to the applica¬ tion of a radio frequency (13.56 MHz) signal. The substrate is located on one of these electrodes (usually the earthed electrode) and the material is deposited on the substrate in its amorphous state. Normally the deposition rate is not greater than 1 um/hr, preferably not more than 0.2 um/hr, preferably not more than 0.1 um/hr, and at an elevated tem¬ perature, preferably from 100 to 400°C and especially from 200 to 300°C. If the layer is deposited too rapidly and/or at too low a temperature or too high a pressure, there is a danger that the silicon-hydrogen bonding will be incorrectly configured. Silicon- hydrogen alloys, in contrast to pure amorphous silicon, have much smaller unpaired spin densities and exhibit predominantly band-like conduction rather than variable-range hopping conduction among localized sta- tes. In addition to changing the conductivity of the layer the silicon hydrogen bond formation allows effi¬ cient n or p type doping which is not possible in either evaporated or sputtered pure amorphous silicon.

Alternatively, the materials may be deposited by a reactive sputtering method in which method predomi¬ nantly neutral atomic or molecular species are ejected from a silicon target under the bombardment of inert positive ions e.g. argon ions. The high energy species ejected will travel considerable distances to be depo¬ sited on the substrate held in a medium vacuum e.g. 10^~4 to 10~² mbar. The positive ions required for bombardment may be generated in a glow discharge where the sputtering target serves as the cathode electrode to the glow discharge system.

-. Passivating agent is introduced into the vacuum chamber in addition to argon to enable it to be incor¬ porated into the silicon. The partial pressure of passivating gas will normally be between 2 and 30%, preferably up to 25%. As with plasma deposition, and for the same reason, the material is preferably depo¬ sited at a rate of not more than 1 micrometre per hour, most preferably not more than 0.2 micrometres per hour and especially about 0.1 micrometre per hour and at an elevated temperature, preferably from 100 to 400°C and especially from 200 to 300°C to maintain a low con¬ centration of unpaired electrons.

The n- or p-doped layers, are normally con¬ siderably thinner than the i layer, having a thickness in the range of from 10 to 200 nm, especially from 20 to 100 nm, and most especially about 50 nm and can simply be formed by introducing a small quantity of dopant or precursor thereof into the deposition atmosphere during part only of the deposition process. Thus, for example, a small quantity, e.g. 0.1 to 5 volume percent, of phosphine or arsine (or, for p-type doping, diborane or boron trifluoride) may be incor¬ porated into the silane at the start or at the end of the i-layer material deposition step. The doped layer usually extends over the entire area of the device.

The nin device will normally be provided with a pair of electrodes over the n- or p-doped layers, although it is not always necessary for the nin device to be provided with two electrodes. For example where a composite device including a threshold foldback switching material is produced the foldback switching material may be provided in direct contact with one of the doped layers. In the case of chalcogenide glass foldback devices, this arrangement has the advantage that any diffusion of the silicon-based doped layer into the chalcogenide glass has a smaller effect on the foldback device characteristics. If metal electrodes are employed, preferred electrode metals are refractory metals and include molybdenum, titanium, aluminium, nickel and chromium and alloys thereof. The electrodes may be formed by any appropriate deposition technique. For example at least one electrode may be deposited by a sputtering method onto a substrate e.g. alumina, and the insulating layer deposited on the electrode. The top electrode may also be deposited by a sputtering technique although it is preferred to employ an eva¬ poration method e.g. electron beam evaporation. Whichever method is used deposition rates in the range of from 5 to 20 micrometres per hour, e.g. 8 to 12 micrometres per hour are preferred. A coating of copper may be provided on the refractory metal in order to act as a heat sink and to improve the solderability thereof.

As stated above the insulating layer will normally have a^' thickness in the range of from 100 to 5000 ^"nm, preferably from 500 to 2000 nm. In the region of ^{^}interest the clamping voltage increases roughly in pro¬ portion to the thickness of the insulating layer. The area of the insulating layer or of the electrodes will depend to some extent on the type of electrical circuit that is to be protected and the amount of energy that can be passed through the device will be proportional to the area of the device.

The nin device and the threshold foldback device employed in the arrangement according to the invention may be connected to the threshold foldback device by any conventional means or it may be formed together with the foldback device (in the case of solid state foldback devices) as a unitary structure, e.g. by sequential deposition. Alternatively, or in addition, the arrangement may be employed together with a device disclosed in our co-pending application entitled "Electrical Device" and filed on even date herewith (Agent's ref: RK382). That device, which acts in the manner of a resettable fuse, is one that exhibits a low resistance until it experiences a transient, whereupon its resistance immediately rises several order of magnitude, the device being connected in series with the load. In such a combination the resettable fuse device should be connected between the arrangement according to the present invention and the load. It is possible to form the resettable fuse device according to our copending application and the nin device according to the present invention from the same insulating silicon-passivating agent com-

which the resettable fuse device has been subjected to a "forming" operation in which a large potential difference is applied across the insulating material and in which the nin device includes n- or p- doped layers. Thus, both devices may be formed as a single monolithic device, for example as part of a hybrid circuit, by depositing an appropriate design of electrically conducting tracks on a layer of the insu- lating material, and the resettable fuse device may be "formed" by applying a potential difference to a pair of the tracks e.g. by means of probes.

An arrrangement in accordance with the present invention will now be described by way of example with reference to the accompanying drawings in which:

Figure 1 is a circuit diagram of an electrical circuit employing an arrangement according to - the invention;

Figure 2 is a graphical representation showing the voltage across a typical load with and without a circuit protection arrangement according to the invention and with a conven¬ tional circuit protection arrangement;

Figure 3 is a schematic perspective view of part of an electrical connector that employs a circuit protection device according to the invention; and

Figure 4 is a schematic cross-sectional view of one form of arrangement according to the invention.

Referring initially to figures 1 and 2 of the accompanying drawings, an electrical circuit in its simplest form is shown in figure 1. The circuit has an alternating or direct current source 1, a load 2 con¬ nected to the current source 1 by lines 3 and 4, and, across the load 2, a circuit protection arrangement 3 for protecting the circuit from a voltage transient which comprises threshold foldback device 3' and nin device 3". In operation, if the circuit, for example one of the lines 2 or 3 is subjected to a transient a current will be induced in it which will correspond to a voltage across the load 2 and device 3 the size of which will be determined by the impedance of the load 2 which will typically be at least 50 ohms. A typical voltage caused by a test pulse is shown as line 21 in figure 2 which corresponds to the voltage across the load of an unprotected circuit. As soon as the poten¬ tial across the device 3 rises above the threshold voltage of device 3' the resistance of the device 3' begins to fall from an initial value of about 1 Mohm to about 1 ohm and thereby causes the potential difference across the load to fall to a very low value as shown in figure 2.

Line 22 of figure 2 shows the response of a cir¬ cuit protection arrangement as described in European patent application No. 196,891 in which a threshold foldback device is connected in series with a 0.5 uF capacitor. When the foldback device has changed to its low resistance state or has "fired" the potential across the load is^' about 0 V, but begins to ^'rise as the capacitor charges. The maximum potential difference across the load will depend on the size of the capaci¬ tor and the size and the duration of the pulse, but may exceed that required to damage the load. This poten¬ tial only starts to decrease after the transient has subsided.

Line 23 of figure 3 shows the response of a cir¬ cuit protection arrangement according to the present invention to the same test pulse. When the foldback device 3' has fired, the potential across the load falls to a value that is set by the clamping voltage of the nin device 3", typically about 10 V. Although the potential difference across the load immediately after the foldback device 3' has fired is slightly higher than that experienced with the prior art arrangement, the potential difference remains constant at the clamping voltage of the nin device 3" until the tran- sient has subsided, with the result that the total energy let through to the load by the transient is limited.

Figure 3 is a schematic perspective view of a modified wafer 41 that may be used in the flat mass termination connector described in British patent spe¬ cification No. 1,522,485. The wafer has a number (usually 25 to 50) metallic electrical conductors 42 extending through it which terminate at one end either in the form of pins 43 or complementary tuning fork female contacts, and at the other end in the form of contacts for connection to a flat cable.

The particular means used for connecting the con¬ ductors 42 to the wires or flat cable is not shown but usually comprises one or more solder devices for example as described in U.S. patent specification No. 3,852,517.

In each of the wafers 41 a stepped recess 27 is made that extends across the width of the entire wafer to expose each of the conductors. In one embodiment of this connector, a metal electrode, e.g. aluminium, copper or gold is deposited onto the step 44 of the recess adjacent to the exposed conductors, to form a "ground plane", and a 100 nm thick layer 45 of insula¬ tor is deposited on the lower electrode. Spot electro¬ des 46 are formed on top of the insulating layer 45 as described above optionally with a final thin top layer of gold in order to facilitate wire bonding of gold wires 47 to the conductors 42.

A composite chalcogenide nin protection device 40 is located on the step 44 and connected to the ground plane and the end conductor 42 for passing any tran¬ sient induced in one of the lines of the connector directly to earth. Figure 4 is a schematic cross-sectional view of a monolithic circuit protection device according to the invention with the thickness of some layers therein grossly exaggerated for the sake of clarity. The device comprises a glass or ceramic support 51 onto which a 30 nm nickel layer 52 and a 10 urn copper layer 53 have been deposited by evaporation. On top of the copper layer 53 an n-doped amorphous hydrogenated sili¬ con layer 54, is deposited followed by a 600 nm thick undoped amorphous hydrogenated silicon layer 55, and a further n-doped amorphous hydrogenated silicon layer 56, the n-doped layers 54 and 56 and the "i" layer 55 forming the nin device. The nin device area is slightly smaller than the area of the copper layer 53 so as to leave an area suitable for forming an electri¬ cal connection to the base.

A chalcogenide glass layer 57 of 10 urn thickness is deposited on the n-doped layer 56 followed by a 30 nm molybdenum layer 58, a 10.urn copper .layer 59, a 30 nm nickel layer 60 and a 300 nm gold layer 61. A gold wire bond 62 is formed between the gold layer 61 and an isolated extension 53' of layer 53, and solder bonds are formed directly to the exposed part of layer 53 and to the isolated extension 53' thereof.

Figure 5 shows another monolithic device according to the present invention which comprises a glass base 121 a 1.5 um thick aluminium layer 122 which has been deposited by electron beam evaporation. A 50 nm thick n-doped intrinsically semiconducting amorphous silicon/hydrogen compound layer 123 has been deposited on the aluminium layer followed by a 600 nm thick undoped layer 124 and a second 50 nm thick n-doped layer 125.

After deposition of the n layer 125 an area 126 of a Germanium-Arsenic-selenium glass was deposited by thermal evaporation to a thickness of 8 um, followed by a 30 nm thick layer 127 of nickel and a 10 um thick layer 128 of copper.

The following Examples illustrate the invention.

EXAMPLE 1

A monolithic chalcogenide glass nin device as described in figure 5 was prepared.

The layers 54, 55 and 56 were formed by plasma deposition ^' from a silane-helium atmosphere at a pressure of 0.2 Torr, a substrate temperature of 270°C, an Rf power of 0.2 Wcm^~2 and a deposition rate of 0.1 nm s~l. 1% by volume phosphine (based on the silane) was introduced into the atmosphere in order to form the doped n layers 54 and 56.

The chalcogenide glass was prepared according to Example 7 of European patent application No. 196,891 and was thermally evaporated with no substrate heating. The layers 52, 53, 58 and 60 were all electron beam evaporated, and layer 61 was thermally evaporated from a molybdenum boat.

The device was subjected to a 5.5 microsecond square wave test pulse of 100 V. The device switched at a threshold voltage of 80 V and thereafter the potential across the device remained constant at 9 V until the pulse finished. EXAMPLE 2

A monolithic chalcogenide glass nin devices of similar structure to that described in Example 1 but in which the nickel layer 52 and the nickel and gold layers 60 and 61 were omitted, and a molybdenum layer was included between layers 53 and 54, were prepared by sequential deposition.

The layers- 54, 55 and 56 were formed by plasma deposition as described in Example 1 as was the chalco¬ genide glass layer. The remaining layers were depo¬ sited by electron beam evaporation.

Twenty devices were tested to determine their off-state resistance and their switching voltage. The results are shown in table 1 as are the results for comparative tests performed on 38 devices formed from chalcogenide glass only (prepared as described in Example 7 of European patent application No. 196,891).

TABLE 1

Resistance Range (Mohms)

0.1 0.1-1 1-10 10-100 100 composite devices 10% 5% 10% 5% 70% chalcogenide devices 32% 58% 10%

Switching Voltage Range (V)

80 80-160 160-240 240-320 320-400 composite devices 15% 10% 30% 45% chalcogenide devices 36% 24% 32% 8%

' It can be seen that the majority of composite nin devices exhibit very high off state resistances with 70% over 100 Mohms while the chalcogenide glass devices exhibit much lower and less consistant resistances. In addition, apart from a small percentage of composite devices that exhibited low switching voltages, due to defects in the chalcogenide glass layer, the composite devices exhibited significantly more consistant switching voltages.

Claims

CLAIMS :

1. A switching arrangement which comprises a threshold foldback electrical device and, connected in series therewith, a device comprising a body of an amorphous, intrinsically semiconducting silicon com¬ pound and a pair of n- or p-doped amorphous silicon compound regions located on, and separated by, the intrinsically semiconducting silicon compound.

2. An arrangement as claimed in claim 1, wherein the threshold foldback device comprises a gas discharge tube, a chalcogenide glass device a diac or triac.

3. An arrangement as claimed in claim 1 or claim 2, wherein the intrinsically semiconducting layer has a thickness in the range of from 500 to 2000 nm.

4. An arrangement as claimed in any one of claims 1 to 3, wherein the compound is an amorphous silicon com¬ pound that has been made by reacting amorphous silicon with a passivating agent to remove or reduce the number of unpaired electrons occurring therein.

5. An arrangement as -claimed in claim 4, wherein the passivating agent comprises hydrogen.

6. An arrangement as claimed in any one of claims 1 to 5, wherein the layer has been made by plasma deposi¬ tion.

7. An arrangement as claimed in any one of claims 1 to 5, wherein the dopant is derived from phosphine, arsine, diborane or boron trifluoride.

8. An arrangement as claimed in any one of claims 1 to 7, wherein at least one of the electrodes comprises titanium, molybdenum, chromium or ni_^ckel or an alloy thereof. . c , threshold foldback device is a thin film device and the arrangement has been formed monolithically by sequen¬ tial deposition.

10. An arrangement as claimed in any one of claims 1 to 9, wherein the nin device exhibits electrical beha¬ viour (for positive values of applied voltage) represented by the equation:

I = KVⁿ

where I is the electrical current flowing through the layer;

V is the voltage across the layer; K is a constant; and n is at least 4.

11. An electrical circuit that comprises an electri¬ cal source and a load, the circuit including an arrangement as claimed in any one of claims 1 to 10, across the load.

12. The use of an arrangement as claimed in any one of claims 1 to 10, for protecting an electrical cir¬ cuit.

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