WO1990004853A1 - Tete d'impression - Google Patents

Tete d'impression Download PDF

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Publication number
WO1990004853A1
WO1990004853A1 PCT/GB1989/001273 GB8901273W WO9004853A1 WO 1990004853 A1 WO1990004853 A1 WO 1990004853A1 GB 8901273 W GB8901273 W GB 8901273W WO 9004853 A1 WO9004853 A1 WO 9004853A1
Authority
WO
WIPO (PCT)
Prior art keywords
print head
chip
led
substrate
contact
Prior art date
Application number
PCT/GB1989/001273
Other languages
English (en)
Inventor
George Arthur Abbott Chilton
Richard Arthur Kirk
Peter Brian Hart
Original Assignee
Prp Optoelectronics Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Prp Optoelectronics Limited filed Critical Prp Optoelectronics Limited
Publication of WO1990004853A1 publication Critical patent/WO1990004853A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/435—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material
    • B41J2/447—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material using arrays of radiation sources
    • B41J2/45—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material using arrays of radiation sources using light-emitting diode [LED] or laser arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED

Definitions

  • the present invention relates to a print head and more particularly to a print head having light emitting diodes (LE.D.'s).
  • Previous photo-printing techniques used in laser printers and photocopies have typically employed a light source, such as a laser, to print upon photostatic paper.
  • the light source is scanned across a sheet of paper using a relatively complex optical system of mirrors and lenses.
  • the use of such an optical system limits the size of image that can be printed and print quality is relatively poor as the image consists of toned dots distributed to give shading.
  • higher quality laser printing is expensive.
  • Light emitting diodes can be fabricated at very small sizes, such as lO ⁇ m or less, giving high resolution and so good print quality. Furthermore, scanning is not necessary if a static print head can be fabricated to span a whole sheet of paper, so removing the necessity of a complicated optical scanning system.
  • FIG. 1 illustrates, in cross section, a known print head comprising a substrate 2 having a row 4 of LED chips 6, the chips being disposed in staggered array with each chip disposed at an angle to the direction of row 4.
  • Each chip comprises eight LED's 8 arranged in four rows 10, the rows being disposed so as to present four long rows of parallel leads with 600 LED's per inch in the assembled row of chips.
  • Each led is electrically connected to control chips 12 by wire bonds (not shown).
  • a chip 6 is shown in partial cross-section in Figure 2, wherein a single LED 8 is illustrated.
  • Chip 6 comprises a substrate 20 of a material such as GaAs having n-type doping therein, having on its lower surface a sheet electrode 22 forming a cathode for all LED's bonded to substrate 2 of the print head by a conductive expoxy 54, substrate 2 carrying a metallised region 26 for securing the cathode to a reference potential.
  • the upper surface of chip 6 has formed therein a p-type diffusion region 28 in an n-type substrate 30, to form a p-n junction 32 in which light can be generated.
  • Conductive pad regions 34, overlying insulative regions 36 make contact with diffusion region 28.
  • a wire providing connection 38 is made between pad 34 and an external terminal 40 of chip 12.
  • Light is emitted from LED 6 through a transparent optical window 52. It will be appreciated that for high resolution LED print heads as shown with, 600 or more LED's per inch (25mm), then a similar number of wire connections are required. This is a lengthy and time consuming manual operation.
  • a further disadvantage of the conventional LED configuration illustrated in Figure 2 is that a significant proportion of any light generated by the junction 1 is masked by the contact 5. Light is thus only radiated through a limited window 9 and so effective output light intensity is reduced.
  • the junction 1 is relatively remote from the print head substrate 4 and consequently the substrate 4 heatsink effect is reduced, so limiting the efficiency of the LED.
  • a print head comprising at least one chip mounted upon a print head substrate, the print head substrate having a defined arrangement of contact pads upon its upper surface, the or each chip having a plurality of light emitting diodes (LEDs), each LED comprising a doped junction formed adjacent a lower surface of the chip and being electrically connected to first contact means and to a respective second contact, the second contacts of the LED's being arranged upon a said lower surface of the chip, each second contact including a solder wettable pad, the solder wettable pads of the second contacts forming an array which corresponds with said defined arrangement of contact pads upon the print head substrate, each solder wettable pad being electrically connected to the defined arrangement of contact pads upon the print head substrate by a respective solder bump so that each solder bump provides electrical connection for its respective second contact whereby the solder bumps secure each chip upon the print head substrate and light generated by each LED propagates through the chip to be radiated through an upper surface of the chip.
  • LEDs light emitting diodes
  • the chip is transparent to visible light although the substrate may be etched to prevent catastrophic attenuation of light generated by each LED prior to radiation from the upper surface increased power.
  • the first electrode may be a common cathode for all LED's and possibly ring shaped upon the upper surface of the chip.
  • the doped junction may be a P-N junction and formed in a Gallium Arsenide substrate.
  • FIG. 3 illustrates, in cross-section, an LED configuration according to the present invention
  • Figure 4 illustrates, in plan, a first electrode according to the present invention in common contact ring shape
  • Figure 5 illustrates, in side elevation, a chip according to the present invention.
  • Figure 6 illustrates, in plan view, the chip as illustrated in" Figure 4.
  • a chip substrate 21 is doped to provide doped junctions 23 (only one is illustrated) " whilst a first contact 3 is electrically connected to the chip substrate 21.
  • the chip substrate 21 may be formed of a light transmissive material such as Gallium Phosphide and doped with an n type material such as sulphur to provide the junction 23. However, the chip substrate 21 may be etched above the junction 23 to provide a cavity 30 to allow other materials of a lower light transmissivity to be use.
  • Each junction 23 is electrically connected to a second contact 27 arranged upon a lower surface 24 of the chip 21.
  • Each second contact 27 is electrically connected to a chip solder wettable pad 29 which may be directly attached or connected through a conductive track (not shown) upon the chip 21 to its respective second contact 27.
  • a print head substrate 31 has a defined arrangement of print head solder wettable contact pads 41 and at least one wire contact pad 42.
  • Each chip solder wettable pad 29 of the chip substrate 21 corresponds to a print head solder wettable pad 41 of the print head substrate 31.
  • a solder bump 37 electrically connects chip solder wettable pads 29 and print head solder wettable pads 41 without any connections.
  • Each first contact 33 is connected to each wire contact pad 42 by a wire connection 39.
  • first contact 33 may be common for all LED's in the chip substrate 21 , consequently only one wire connection 39 would be required.
  • a single wire connection 39 has great advantages in cost and fabrication time reduction.
  • removal in the present print head of the necessity of a vast number of wire connections allows a reduction in LED pitch spacing so increasing print head resolution and printed image quality.
  • the LED doped junction 23 may be a PN junction with a N side upper most upon the chip 21.
  • the first contact 33 is a cathode (N contact) whilst the second contact 27 is an anode (P contact).
  • N contact cathode
  • P contact anode
  • the contact 27 can be spread completely over the junction 23. This gives greater electrical contact with the junction 23 and allows the solder wettable pad 29 to be attached directly below the junction 23.
  • solder bump 37 in a molten state, is to align the print head substrate pad 41 with the pad 29 through minimisation of surface tension.
  • the chip substrate 21 has a plurality of LED's with solder wettable pads 29. corresponding with print head solder wettable pads 41 can be located upon each chip substrate 21 and the print head substrate 31 respectively.
  • a first contact 33 and second contacts 27 according to a preferred embodiment of the present print head are illustrated in Figures 3 to 5.
  • a common first (or cathode) contact 33 for all LED's in the chip substrate 21 is illustrated as a ring about the edge of the chip 21.
  • a single wire connection 39 (figure 2) can be made to that ring.
  • the lower surface of the chip 21 is illustrated prior to electrical connection with the print head substrate through solder bumps 37. Solder bumps 37 are arranged in the defined arrangement.
  • solder bump 37 may be integral with either the pad 29 or the pad 41. Furthermore, a proportion of the solder bump 37 may be upon both pad 29 and pad 41.
  • the print head substrate 31 may be a thin film of silicon with conductive tracking or an integrated driver chip arranged to operate each LED.

Abstract

L'invention concerne une tête d'impression comprenant un substrat de tête d'impression ainsi qu'au moins une puce comportant un réseau de diodes électroluminescentes (DEL). Chaque puce à DEL est configurée de sorte que sa jonction dopée se trouve sur une surface inférieure de la puce tandis que de la lumière se dégage d'une surface supérieure de la puce. La jonction est électriquement reliée au substrat de la tête d'impression par une perle de soudure, ce qui permet de réduire le nombre de connexions à fils entre la DEL et le substrat de la tête d'impression, chaque substrat de puce étant positionné avec précision sur le substrat de la tête d'impression.
PCT/GB1989/001273 1988-10-25 1989-10-25 Tete d'impression WO1990004853A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8824914A GB2225869A (en) 1988-10-25 1988-10-25 A print head
GB8824914.9 1988-10-25

Publications (1)

Publication Number Publication Date
WO1990004853A1 true WO1990004853A1 (fr) 1990-05-03

Family

ID=10645723

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB1989/001273 WO1990004853A1 (fr) 1988-10-25 1989-10-25 Tete d'impression

Country Status (2)

Country Link
GB (1) GB2225869A (fr)
WO (1) WO1990004853A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013117760A1 (fr) * 2012-02-10 2013-08-15 University College Cork, National University Of Ireland, Cork Puce de diode électroluminescente

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4039890A (en) * 1974-08-16 1977-08-02 Monsanto Company Integrated semiconductor light-emitting display array
GB2099221A (en) * 1981-05-26 1982-12-01 Purdy Haydn Victor Light emitting diode array devices and image transfer systems

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4039890A (en) * 1974-08-16 1977-08-02 Monsanto Company Integrated semiconductor light-emitting display array
GB2099221A (en) * 1981-05-26 1982-12-01 Purdy Haydn Victor Light emitting diode array devices and image transfer systems

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
IBM Technical Disclosure Bulletin, Vol. 26, No. 2, July 1983, New York (US) P.E. CADE et al.: "Input/Output Device Interconnections", pages 572-57 *
Journal of Applied Physics, Vol. 48, No. 1, January 1977, American Institute of Physics, New York (US) M. KITADA: "Upside-Down Fabricated GaP Monolithic Display", pages 279-281 *
Proceeding of the Society for Information-Display, Vol. 18, No. 2, 1977 Los Angeles (US) M. IUOUE et al.: "A GaP Monolithic Numeric Display with Internal Reflection Facets", pages 195-198 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013117760A1 (fr) * 2012-02-10 2013-08-15 University College Cork, National University Of Ireland, Cork Puce de diode électroluminescente
US9472594B2 (en) 2012-02-10 2016-10-18 Oculus Vr, Llc Light emitting diode chip
US9917136B2 (en) 2012-02-10 2018-03-13 Oculus Vr, Llc Light emitting diode chip
US10121823B2 (en) 2012-02-10 2018-11-06 Facebook Technologies, Llc Light emitting diode chip
EP3528295A1 (fr) * 2012-02-10 2019-08-21 Facebook Technologies, LLC Dispositif d'affichage à puce à diode électroluminescente et procédé de sa fabrication

Also Published As

Publication number Publication date
GB2225869A (en) 1990-06-13
GB8824914D0 (en) 1988-11-30

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