WO1990011615A1

WO1990011615A1 - Trench gate metal oxide semiconductor transistor

Info

Publication number: WO1990011615A1
Application number: PCT/US1990/000237
Authority: WO
Inventors: Allen L. Solomon
Original assignee: Grumman Aerospace Corporation
Priority date: 1989-03-21
Filing date: 1990-01-09
Publication date: 1990-10-04
Also published as: CA2007908A1

Abstract

A process for forming a trench gate metal-oxide semiconductor transistor, and the resulting structure are disclosed. The transistor is formed by forming a trench (31) in the semiconductor substrate (20) which is used to construct the gate region. Regions adjacent the upper surface of the trench are doped to form source and drain regions (21, 23). A layer of insulator (33) is applied along the surface of the trench and a conductive layer (35), forming the gate, is applied on the surface of the trench above the insulating layer. The source and drain (21, 23) regions are therefore separated by the trench (31) and the gate region (35) is separated from the source and drain regions (21, 23) by the insulating layer (33) lining the trench surface.

Description

TRENCH GATE METAL OXIDE SEMICONDUCTOR TRANSISTOR

Background of the invention

The present invention finds application in connection with thin silicon plates or wafers formed to support a multiplicity of monolithically integrated data processor circuits. More particularly, the invention is directed to the production of circuits formed on silicon wafers for interfacing devices such as infrared detector elements to a processing network that amplifies, stores and interprets detected infrared frequency signals.

The infrared spectrum covers a range of wavelengths longer than the visible wavelengths, but shorter than microwave wavelengths. Visible wavelengths are generally regarded as between 0.4 and 0.75 micrometers. The infrared wavelengths extend from 0.75 micrometers to 1 millimeter. The function of infrared detectors is to respond to the energy of a wavelength within some particular portion of the infrared region.

Heated objects generate radiant energy having characteristic wavelengths within the infrared spectrum. Many current infrared image detection systems incorporate arrays with large numbers of discrete, highly sensitive detector elements, the electrical outputs of which are connected to processing circuitry. By analyzing the pattern and sequence of detector element excitation, the processing circuitry can identify and track sources of infrared radiation. Though the theoretical performance of such contemporary systems is satisfactory for many applications, it is difficult to construct structures that adequately interface large numbers of detector elements with associated circuitry in a practical and reliable manner. Consequently, practical applications for contemporary infrared image detector systems have necessitated further advances in the areas of miniaturization of the detector array and accompanying circuitry, of minimization of circuit generated noise that results in lower sensitivity of the detected signal , and of improvements in the reliability and economical production of detector arrays and the accompanying circuitry .

Contemporary arrays of detectors, useful for some applications , may be sized to include 256 detector elements on a side, or a total of 65, 536 detectors, the size of each square detector being approximately 0.009 centimeters on a side, with 0.00116 centimeters spacing between detectors . Such a subarray would therefore be 2.601 centimeters on a side . Interconnection of such a subarray to processing circuitry would require connecting each of the 65, 536 detectors to processing circuitry within a square, a l ittle more than one inch on a side. Each subarray may, in turn , be joined to other subarrays to form an array that connects to 25 , 000 , 000 detectors or more. As would be expected considerable difficulties are presented in electricl ly connecting the detector elements to associated circuitry, and laying out the circuitry in a minimal area . The problems of forming processing circuitry in such a dense environment require minimization of the surface area used for the circuitry.

The outputs of the detector elements typical ly undergo a series of processing steps in order to permit derivation of the informational content of the detector output sign al . The more fundamental processing steps , such as preamplification, tuned band pass filtering , clutter and background rejection, multiplexing and fixed noise pattern suppression, are preferably done at a location adjacent the detector array focal plane . As a consequence of such on-focal plane, or up-front signal processing, reductions in size , power and cost of the main processor may be achieved. Moreover, on-focal plane signal processing helps alleviate performance, reliability and economic problems associated with the construction of millions of closely spaced conductors connecting each detector element to the signal processing network.

Aside from the aforementioned physical limitations on the size of the detector module, limitations on the performance of contemporary detection systems can arise due to the presence of electronic circuit generated noise in particular, from the preamplifier. Such noise components can degrade the minimal level of detectivity available from the detector. A type of noise that is particularly significant where the preamplifier operates at low frequency is commonly called flicker or 1/f noise. Because 1/f noise can be the principal noise component at low frequencies of operation, it is highly desirable that circuits operating within such frequencies be constructed in such a manner as to decrease 1/f noise to an acceptably low level.

U.S. Patent No. 4,633,086, to Parrish, for Input Circuit For Infrared Detector, assigned to the common assignee, describes one technique for biasing the on-focal plane processing circuit to maintain the associated detector in a zero bias condition, thus reducing 1/f noise and enhancing the signal to noise ratio of the circuit.

Reduction of 1/f noise in the preamplifier, where the preamplifier transistor is a field effect device, is conventionally obtained by increasing the area of the channel region under the gate. This large area over the semiconductor substrate surface results in a decrease in circuit component density or decreased circuit component miniaturization. In the present invention, the channel region of a metal-oxide-semiconductor (MOS) field effect transistor is formed in a trench in the semiconductor. The transistor then occupies far less semiconductor substrate surface and so enables a high component density circuit to be obtained. Summary of the Invention

A process for forming a trench gate metal oxide semiconductor transistor, and the resulting structure are disclosed. The transistor gate region is formed in a trench in the semiconductor substrate. Regions adjacent the upper surface of the trench are doped to form source and drain regions. A layer of insulator is applied to the surface of the trench. A conductive layer is applied on the surface of the trench upon the insulating layer to complete the formation of an insulated gate. The source and drain regions are therefore separated by the trench and the gate region is separated from the source and drain regions by the insulating layer lining the trench surface. In the presently preferred embodiment the trench can be formed by reactive ion etching and the insulating layers formed by thermally oxidizing the silicon substrate exposed by the trench. Gate and source regions are formed by diffusing dopants into the substrate adjacent upper surfaces of the trench. The conductive layer can be formed by vapor deposition of a doped polycrystalline silicon layer on the surface of the trench above the insulating layer.

In the presently preferred embodiment the substrate is formed of p-doped silicon, and the gate and drain regions are formed of degenerately n-doped regions. The conductive layer, which forms the transistor gate, may be formed of a metal, or of degenerately doped polysilicon. The insulating layer may be formed to be comprised of silicon dioxide.

In the presently preferred embodiment the trench is formed up to approximately 10 to 20 microns deep, 2 to 3 microns wide and up to 10 to 20 microns wide. The trench may be completely filled with the conductive material, an insulator material, or left open and simply lined with the layer of conductive material.

Brief Description of the Drawings Figure 1 is a cross-sectional view of a contemporary MOS transistor structure; Figure 2 is a cross-sectional view of a transistor formed in accordance with the present invention; and

Figure 3 is a top perspective view of the transistor illustrated at Figure 2. Detailed Description of the Presently Preferred Embodiment The detailed description set forth below in connection with the appended drawings is intended as a description of the presently preferred embodiment of the invention, and is not intended to represent the only form in which the present invention may be constructed or utilized. The description sets forth the functions and sequence of steps for construction of the invention in connection with the illustrated embodiment. It is to be understood, however, that the same or equivalent functions and sequences may be accomplished by different embodiments that are also intended to be encompassed within the spirit and scope of the invention. Furthermore, a similar trench gate embodiment can include a p-MOS transistor, an n or p junction field effect transistor (JFET) as well as the n-MOS transistor described here.

As previously noted large numbers of closely spaced high component density, integrated circuit processor channels may be used in on-focal-plane signal processors. Each detector element in the detector array may be connected to a preamplifier, such as a CMOS preamplifier, in an analog processor circuit. Low preamplifier noise is essential to prevent degradation of detector sensitivity. Since the preamplifiers are operated at low frequency, a principal source of noise is flicker or 1/f noise. The l/f noise is inversely proportional to the area of the channel or gate regions of an MOS transistor, as expressed in the following equation:

C_oxWLf, where v = the characteristic noise in microvolts;

K = a constant; Δf = bandwidth f = the frequency of operation; C = characteristic capacitance of the oxide layer; w = the width of the gate; and

L = the length of the gate. See: R. Gregorian and G.C. Temes, Analog MOS Integrated Circuits For Signal Processing, pp. 98, 99, John Wiley & Sons, N.Y., N.Y. (1986) A large area gate region in a MOS transistor will produce a low 1/f noise component. However, such a structure requires a large amount of semiconductor surface area. This makes it difficult to obtain a high density of such integrated circuit functions. The present invention is directed to a structure and process for enhancing the area of the gate region without enhancing the semiconductor surface area.

The MOS transistor gate region may be regarded as a capacitor, which is formed by a metal oxide sem conductor cross-section. Large area capacitors that preserve semiconductor surface are obtained in bulk silicon by using the walls of trenches, grooves or holes, which are cut in silicon, for example, by plasma or reactive ion etching. In such a manner, gate region area may be enhanced by using the depth of the trench to enlarge the electrode channel area without the need to use a large amount of the semiconductor surface. The present invention recognizes the capacitive characteristics of the MOS transistor gate region and applies particular trench forming techniques to the construction of the MOS transistor. In such a manner the MOS transistor gate channel area or gate channel region, is enhanced, mitigating 1/f noise, without the need to use large amounts of the semiconductor surface. Figure 1 illustrates an n-MOS transistor constructed in accordance with conventional techniques. As shown therein MOS transistor 11 is formed of an n-doped source region 21 and an n-doped drain region 23 formed in p-doped silicon 20. The source and drain regions are bridged by an insulating layer, e.g. insulating layer 25, which may be formed of material such as silicon dioxide ( Si0₂ ) or silicon nitride. A conductive gate 27 is disposed on the upper surface of the insulator 25. The gate 27 is typically formed of metal or doped polysilicon.

In relation to Figure 1 the characteristic 1/f noise is related to the width and length of the gate area intermediate to the source and drain. The length of the gate area, labeled L, is shown at Figure 1. The width of the gate area is orthogonal to the plane of the drawing. By increasing the length of the gate L, 1/f noise is reduced, though the maximum speed at which the circuit will efficiently operate is reduced. The present invention is directed to a construction and technique wherein the gate area is enhanced without the need to appropriate greater surface area of the semiconductor wafer. Figure 2 illustrates one embodiment of the present invention. As with MOS transistor 11 shown at Figure 1, MOS transistor 13 comprises an n-doped source region 21, and an n-doped drain region 23, both formed in p-doped silicon 20. Unlike the construction shown at Figure 1, a trench 31 is formed in the silicon substrate. The trench may be formed by any of a variety of techniques, such aβ reactive ion etching. An insulating layer 33 is disposed on the vertical and bottom surface of the trench 31. In the presently preferred embodiment the insulating layer 33 is a thin film of silicon dioxide formed by thermal oxidation of the silicon. A conductive film 35, which serves as the gate, is then disposed on the upper surface of insulating layer 33. The gate layer 35 may be formed of conductive material, such aβ metal or of degenerately doped semiconductor material, e.g. polysilicon. In alternative structures, the trench can be filled with an insulator material such as Si0₂ or with a conductive material without the need for a conductive film liner.

Electrodes 37, 39 may be formed on the upper exposed surfaces of source 21 and drain 23, respectively. Where the insulating layer 33 extends above the surfaces of source 21 and drain 23, the Si0₂ may be etched by any of a number of contemporary techniques to facilitate the formation of the electrodes. An additional electrode (not shown) may be formed to facilitate contact with the gate layer 35.

In accordance with the construction shown at Figure 2 the gate region intermediate to the source 21 and drain 23 is enlarged by means of a formation of trench 31. In the presently preferred embodiment trench 31 is formed to be up to approximately 10 to 20 microns deep and 2 to 3 microns wide. The length of the trench (orthogonal to the plane of Figure 1) is up to the range of 10 to 20 microns. The particular dimensions may be selected in accordance with the desired noise characteristics and speed of the transistor, and the available surface area.

A perspective view of a MOS transistor formed in accordance with Figure 2 is illustrated at Figure 3. Figure 3 illustrates the arrangement of source, gate, and drain electrodes on the semiconductor substrate surface. A filled trench is depicted.

It is anticipated that the gate would be connected to a dedicated detector element and the drain to a storage capacitor which may be selectively interrogated by the further processing circuitry (not shown). The source may be connected to a low level bias circuit, or alternatively may be sustained at a substantially zero level, as may be desired.

The construction illustrated at Figures 2 and 3, therefore provides advantages of low 1/f noise without the penalty in terms of semiconductor surface area. Though certain penalties may be inherited in terms of the speed of the MOS transistor, in certain applications the speed limitations are not restrictive. On the contrary, 1/f noise reduction is needed in low speed imaging systems, for example, for highest sensitivity.

As discussed above, various modifications and substitutions may be affected to implement the structure and function of the invention, without departing from the spirit and scope of the invention.

Claims

What is Claimed is:

1. A method of forming a trench gate metal-oxide-semiconductor transistor comprising: forming a trench in a semiconductor substrate; doping regions adjacent upper surfaces of the trench; applying a layer of insulator on the surface of the trench; and forming conductive material on the surface of the trench over the insulating layer; wherein the source and drain regions are separated by the trench and wherein the trench walls then form an insulated gate region intermediate to the doped source and drain regions.

2. The process as recited in Claim 1 wherein the trench is formed to be between 10 to 20 microns deep.

3. The process as recited in Claim 1 wherein the trench is formed to be between 2 to 3 microns wide.

4. The process as recited in Claim 1 wherein the trench is formed to be between 10 to 20 microns long.

5. The process as recited in Claim 1 wherein the trench is formed to be approximately 10 microns deep, 2 to 3 microns wide and 20 microns long.

6. The process as recited in Claim 1 wherein a trench is formed by reactive ion etching.

7. The process as recited in Claim 6 wherein the insulating layer is formed by thermally oxidizing the silicon substrate exposed by the trench.

8. The process as recited in Claim 7 wherein the transistor gate and source regions are formed by diffusing dopants in the semiconductor substrate.

9. The process as recited in the Claim 8 wherein the layer of conductive material is formed by a chemical vapor deposition.

10. The process as recited in Claim 1 wherein the trench is filled with an insulator material.

11. The process as recited in Claim 1 wherein the conductive material completely fills the trench within the insulating layer.

12. A trench gate metal-oxide semiconductor transistor comprising: a semiconductor substrate; a trench formed in the semiconductor substrate; dopant regions formed in the semiconductor substrate adjacent upper surfaces of the trench; an insulating layer disposed on the surface of the trench; and a layer of conductive material formed on the insulating layer and extending along the surface of the trench above the insulating layer; wherein the doped regions form the source and drain of the transistor and the conductive material forms the gate of the transistor; and wherein the source and drain are separated by the trench, the trench extending substantially beyond the thickness of the doped regions.

13. The transistor as recited in the Claim 12 wherein the depth of the trench is 5 to 100 times the depth of the doped regions.

14. The transistor as recited in Claim 12 wherein an insulator material fills the trench.

15. The transistor as recited in Claim 12 wherein the conductive material completely fills the trench within the insulating layer.

16. The transistor as recited in Claim 12 wherein the source and drain are separated by the trench and wherein the gate is isolated from the source drain by the insulating layer.