WO1990013890A1 - Digital waveform encoder and generator - Google Patents

Digital waveform encoder and generator Download PDF

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Publication number
WO1990013890A1
WO1990013890A1 PCT/GB1990/000732 GB9000732W WO9013890A1 WO 1990013890 A1 WO1990013890 A1 WO 1990013890A1 GB 9000732 W GB9000732 W GB 9000732W WO 9013890 A1 WO9013890 A1 WO 9013890A1
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WIPO (PCT)
Prior art keywords
signal
waveform
analogue
values
digital
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Application number
PCT/GB1990/000732
Other languages
French (fr)
Inventor
Vernon Thomas Seymour Howell
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Hi-Med Instruments Limited
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Publication of WO1990013890A1 publication Critical patent/WO1990013890A1/en

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    • GPHYSICS
    • G10MUSICAL INSTRUMENTS; ACOUSTICS
    • G10LSPEECH ANALYSIS OR SYNTHESIS; SPEECH RECOGNITION; SPEECH OR VOICE PROCESSING; SPEECH OR AUDIO CODING OR DECODING
    • G10L25/00Speech or voice analysis techniques not restricted to a single one of groups G10L15/00 - G10L21/00

Definitions

  • the present invention relates to a method and apparatus for encoding an electronic waveform as a digital signal, and a method and apparatus for regenerating the waveform from the digital signal.
  • the invention relates to the encoding and generation of audio signals, especially those including speech.
  • analogue to digital converter In a conventional method for encoding an analogue waveform, the waveform is sampled periodically, and each instantaneous sampled value is then quantised as a digital value by means of an analogue to digital converter (ADC).
  • ADC an analogue to digital converter
  • the ADC may be an 8 bit device allowing a resolution of 256 quantised values.
  • the bandwith of the encoder is determined by the rate at which the waveform is sampled, the maximum frequency detectable being half the sampling frequency.
  • Such a method has the disadvantage that the quantity of data in the digital signal is vast. For example, using the aforementioned 8-bit ADC at a sampling frequency of 20KHz for normal speech, 160000 bits of data are encoded per second.
  • the resolution or the sampling frequency, or both can be reduced, but with a corresponding reduction in the quality of the encoded signal.
  • Known systems storing speech in ROM or other computer memory produce unnatural, robot-like speech.
  • the waveform is encoded by extracting values of alternate maxima and minima from the waveform, and measuring timing intervals associated with consecutive minima and maxima.
  • the extracted values and the timing information can be combined and arranged as the digital signal.
  • the waveform is regenerated from the digital signal by joining together segments of a predetermined wavefunction of period determined by the timing information, and of amplitude determined by the values of the maxima and minima.
  • a second aspect of the invention is a generator for generating an analogue signal in the form of a segment of predetermined wavefunction shape, extending from a first digitally encoded amplitude level to a second digitally encoded amplitude level.
  • a generator generates a sequence of digital values representing consecutive points on the predetermined wavefunction, which extends between a maximum level and a zero level.
  • a DAC converts the digital values to a corresponding analogue signal, and another DAC converts the digital values to a complementary analogue signal.
  • the amplitudes of the analogue signals are controlled by the first and second amplitude levels, and the analogue signals are mixed to produce an output signal.
  • Figure 1 is a block diagram of the parts of an apparatus for recording and replaying an analogue waveform
  • Figures 2-5 show examples of waveforms in the record and replay sections of the apparatus.
  • a waveform recording apparatus 10 has an encoding or recording sub-system generally comprising the elements on the left hard side of the block diagram, and a playback or generating sub-system generally comprising the elements on the right hand side of the block diagram. Some elements are common to both sub-systems.
  • the recording sub-system has an analogue A.C. input 12 which feeds in parallel to a maximum or positive peak detector 14, and, via an inverter 16, to a minimum or negative peak detector 18.
  • the peak detectors 14 and IS are similar devices which detect and hold peak values, until they are reset. They are resettable to zero concurrently by means of a reset control line 20.
  • the outputs of the peak detectors 14 and IS are ⁇ connected to respective inputs of a summing amplifier 22, having a sum output 24 connected in turn to the input of an analogue to digital converter (ADC) 23 to provide a digital output 25.
  • ADC analogue to digital converter
  • the input 12 is also connected to a reference detector 26 which detects when the input signal crosses a predetermined reference value.
  • the detector 26 outputs a high pulse whenever the reference value is crossed.
  • the reference value is zero.
  • the reference detector 26 controls the maximum and minimum peak detectors 14 and 18 defect alternate maxima and minima in the input waveform.
  • both detectors 14 and 18 are reset as the waveform crosses the zero value.
  • the maximum value of the waveform until it again crosses the zero value is detected and held by the maximum peak detector 14.
  • This maximum value appears at the input of the summing amplifier 22, and, since the output from the minimum peak detector 18 is still zero, the maximum value appears at the sum output 24.
  • both detectors 14 and 18 are again reset, and the subsequent minimum value is detected and its amplitude appears at the sum output 24.
  • a free running crystal oscillator 30 has an output 32 which is connected via a divide by 100 counter 34 to a record counter 36.
  • the record counter has a reset input 38 which is connected to the reset line 20. In use during recording the record counter counts clock pulses to time relative intervals between the points at which the input waveform crosses the zero value.
  • the digital output 25 from the ADC 23, and the output from the record counter 36 are connected to bidirectional input/output data lines 40a, 40b respectively of a random access memory (RAM) 42.
  • the RAM 42 communicates via a data bus 44 with an EPROM 46 which can store a recorded waveform for playback.
  • SRAM static RAM
  • EPROM 46 The showing of the static RAM (SRAM) 42 and EPROM 46 is schematic. In practice, in a recording apparatus the data will be recorded in RAM 42 and then drawn from RAM into one or more EPROMs. In a pure playback apparatus the EPROM may replace the RAM.
  • the peak amplitude data and the time interval data are stored as a sequential digital signal of pairs of digital words.
  • the first word in the pair corresponds to the peak data, and the second word corresponds to time interval data.
  • the inputs and outputs of the memories include multiplexers for arranging the data as the sequential digital signal.
  • the RAM 42 is accessed by means of a first address counter 43, which has an increment input 45 connected to the centre pole 51 of a record/playback selector switch 53.
  • the record pole 54a of the switch 53 is connected to the reset line 20, whereby in the record mode, the address counter is incremented by reset pulses.
  • the address counter 43 controls the RAM 42 to sequentially store or retrieve data in the RAM 42.
  • the data line 40b from the RAM 42 is also connected to a control input of a variable frequency divider counter 48.
  • the counter 48 has another input which is connected to the output 32 from the oscillator 30, such that the output from the divider counter 48 is equal to the signal from the oscillator G
  • the output from the counter 48 is connected to the input of a second address counter 50.
  • the counter 50 has an overflow output 52 which is connected to the playback pole 54b of the switch 53.
  • timing information is read out from the RAM 42, and a timing period signal of frequency dependent on the timing information is generated by the divider 48.
  • a pulse is sent from the second address counter 50 to increment the first address counter 43, and thereby access the next data in the RAM 42.
  • the output from RAM 42 is applied to the circuitry shown at the right hand end of Figure 1 which operates to generate an analoque signal in the form of a segment of predetermined wavefunction shape extending from one digitally encoded amplitude level read from RAM 42 to the next digitally encoded amplitude level.
  • the data line 40a is also connected in parallel to the data inputs of a first or down amplitude latch 55, and a second or up amplitude latch 56.
  • the overflow output 52 from the second address counter 50 is connected to the input of a flip flop 58, which has complementary outputs 60a and 60b connected to control inputs of the latches 55 and 56, respectively.
  • the flip flop 58 determines which latch 55, 56 accepts the data from the data line 40a.
  • the first latch 55 accepts the data
  • the second latch 56 accepts the data.
  • the output from the first latch 55 is connected to the input of a first or down level reference digital to analogue converter (DAC) 62, and the output from the second latch 56 is connected to the input of a second or up level reference DAC 64.
  • the analogue output form the first DAC 62 is connected through a first buffer amplifier 66 to the reference voltage input of an output third DAC 70, and the analogue output from the second DAC 64 is connected through a second buffer amplifier 68 to the reference voltage input of an output fourth DAC 72.
  • the address counter 50 has an address output bus 74 which is connected in parallel to the inputs of two preprogrammed memories 76 and 78.
  • the data output of the memories 76, 78 are connected to the digital inputs of the third and fourth DACS 70, 72 respectively.
  • Each memory has one hundred locations in which are stored digital values representing points in a half cycle of a cosine function which is offset to vary between the values 255 and 0.
  • the memories 76, 78 are thus termed half-cosine wave count up and down PROMs (programmable read-only memories) respectively.
  • the contents of memory 76 are shown graphically as a line 88, and the contents of memory 78 are shown as a line 86.
  • the wavefunctions defined by the lines 88 and 86 are complementary wavefunctions.
  • the address counter 50 behaves as a variable frequency generator to count sequentially through the one hundred address values at the rate specified by the timing information N.
  • the digital values representing the half cycle complementary cosine functions are passed to the third and fourth DACS, 70 and 72 to generate the half cycle cosine functions as analogue functions. These are used to generate the waveform, as % explained hereinafter, and are termed half-cosine output DACs for the up and down half-cycles respectively.
  • Control logic (not shown) synchronises the flip-flop 58 to the second address counter such that the particular up or down latch 55 or 56, respectively, enabled by the flip-flop 58 when data is read from the RAM 42 the latch associated with the particular half-cosine wave count up and down PROM, 76 or 78, respectively, whose output is zero.
  • the output from the fourth DAC 72 is passed through an inverting amplifier 80, whose output is connected to one input of a summing or combining amplifier 82.
  • the output from the third DAC 70 is connected directly to another input of the summing amplifier 82, whose sum output 84 is the generated analogue waveform.
  • the switch 53 is set to the pole 54a and an analogue input is applied to the input 12.
  • the input waveform may be of the form shown in figure 3.
  • the amplitudes of alternate maximum and minimum peaks in the waveform are extracted from the waveform and appear as digital values at the output from the ADC 23.
  • F the output frequency of the oscillator 30
  • the first peak will be the amplitude yx, with its timing information Tx.
  • the value yx is transferred to the RAM 42 via the ADC 23 at the end of Tx, when the zero crossing detector 26 detects that the waveform crosses zero.
  • the next peak will be the amplitute y ⁇ with its timing information Ta, and the next amplitude 3 with its timing information T3. Only the amplitude of a peak is important, and not its sign, since the peaks are necessarily detected as alternate maxima and minima about the reference value of zero.
  • a reset pulse is generated to store the peak data, and the timing information in the RAM 42, and reset the detectors 14 and 18 and the counter 36, as well as to increment the first address counter 43. Alternate maximum and minimum values of the waveform are thereby stored sequentially in the RAM 42 each in association with the corresponding time value.
  • the switch 53 In the playback, or waveform generation, mode the switch 53 is set to the pole 54b, and the first address counter 43 is initially reset. Timing information data is output from the RAM 42 at the data line 40b concurrently with peak data being output at the data line 40a. Depending on the state of the flip flop 58, the peak data will either be interpreted as a maximum point and stored in the first latch 55, or it will be interpreted as a minimum point and stored in the second latch 56.
  • the digital values in the latches 55, 56 are converted into analogue reference levels by the first and second DACs 62, 64 respectively, and fed to the reference voltage inputs of the third and fourth DACs 70, 72 respectively.
  • the reference voltage inputs control the maximum outputs available from the third and fourth DACs 70, 72, whereby the peak data contained in the latches 55, 56 effectively controls the amplitude of a signal generated by the DACs 70, 72 respectively.
  • the timing information data output from the RAM 42 is input to the variable frequency divider counter 48.
  • the timing information value N introduced hereinbefore is used to generate an output freqency from the divider counter 48 of frequency F/N, or period N/F.
  • the output from the third DAC 70 will be as shown by the line 90, decreasing from the value yx stored in the latch.55 to zero.
  • the output from the fourth DAC 72 will be as shown by the line 92 increasing (negatively in figure 4) from zero to the value yz stored in the latch 56.
  • the output from the fourth DAC 72 is shown inverted in figure 4, because it is inverted by the inverting amplifier 80.
  • the sum signal is formed in the summing amplifier 82, and is itself a half-cycle cosine function as shown by the line 94.
  • a new peak value 3 is I I loaded into the latch 56 as the next (maximum) peak value, and its associated timing information corresponding to T3 is loaded into the time period divider counter 48.
  • the next section of the waveform is interpolated in a similar way to that discussed above.
  • the flip flop 58 is toggled each time new peak data is read from the RAM 42, such that new peak data is loaded alternately into the latches 55, 56.
  • the address counter counts alternately up and down through the one hundred addresses such that the roles of the memories 76, 78 in outputting the increasing and decreasing half-cycle cosine functions are effectively reversed for each new peak value.
  • the amount of digital data is reduced compared with an equivalent method using continuous periodic sampling.
  • the digital signal can be compressed by the order of 30 for speech signals, and 20 for music signals, compared with conventional sampling techniques.
  • the digital data is stored in an integrated circuit memory array (RAM or ROM) since it is feasible to store several minutes of passable audio in an inexpensive chip.
  • the sum output of the generated waveform is smooth since new data for the interpolation parameters is only loaded when the gradient of the waveform is zero.
  • the output waveform can only contain second and higher order discontinuities.
  • a pre-programmed speech generator may have only the playback section.
  • Such a speech generator may for example be used in devices such as intruder alarms, personal alarms, or fire alarms, to emit an intelligible warning or distress message. Where small size is important, the circuit for the speech generator may be contained substantially in a single integrated circuit. The speech generator may also be used in talking toys or novelty items, for example a talking picture.
  • a further application of the invention is in the field of computer speech recognition and comprehension.
  • the present method of encoding an input waveform compresses the amount of information in the input signal to a level easily manageable by a computer, while still preserving the important features of the input signal waveform.
  • the encoding can reduce the input waveform to a sequence of identifiable portions that may be stored or processed by a computer.
  • the generated waveform output is not identical to the analogue waveform input, the differences are sufficiently small that adequate fidelity of the original waveform is maintained. This is especially the case for human speech.
  • the waveform is encoded by extracting only values of alternate maxima and minima which occur above and below, respectively, the zero reference value
  • other maxima and minima may be extracted.
  • the values of intermediate points ys and y could be included in the encoded signal, as well as the values of yx, yz and y_> although at the expense of substantially increased circuit complexity.
  • the timing information corresponds to relative intervals between points at which the waveform crosses the zero reference value
  • the timing information may correspond to the actual positions at which the detected maxima and minima occur.
  • the relative time intervals tx to t- ⁇ , t- ⁇ to ts etc. would be encoded as the timing information (assuming that only maxima and minima separated by zero crossings are encoded, as in fig 3).
  • the time locations of the maxima and minima may also be combined with the time locations of the points at which the waveform crosses the zero reference value, giving a more detailed encoded signal representing the waveform. The method of regenerating the waveform could then use segments of quarter cycle sine waves, thereby generating the original waveform more accurately.
  • the waveform is generated by combining segments of cosine waves, each segment starting and ending at a maximum or minimum
  • the segments could be of half cycle sine waves, beginning at zero and passing through the maximum or minimum and returning to zero.
  • the encoding and generating sections of the apparatus are comprised of dedicated hardware for performing the encoding and generation. It will be appreciated, however, that one or both of these sections can be realised by using a programmed computer.
  • an ADC could be used to convert an input analogue waveform to a periodically sampled digital form, and the signal fed to a programmed computer.
  • the computer would be programmed to detect alternate values of maxima and minima in the signal, and to measure timing intervals associated with consecutive maxima and minima, in accordance with the invention.
  • the resulting data in the computer would be combined and arranged in a suitable format for the enclosed digital signal.
  • a programmed computer could have a digital output port connected to an output DAC.
  • the computer would generate digital values of the wavefunction segments in accordance with the invention, and feed the digital values to the DAC to produce an analogue output waveform.

Abstract

A waveform encoder has an input (12), a clock generator (30, 34) and respective detectors (14, 18, 26) for detecting maxima, minima and zeros in the waveform. During encoding, values of alternate maxima and minima are combined with associated timing information, and stored as a digital signal in a memory (42, 46). The waveform generator includes a variable wavefunction generator (55, 56, 62, 64, 76, 78, 50, 48, 72, 80, 70, 82) for generating segments of a predetermined wavefunction of period determined by the timing information and of amplitude determined by values of consecutive maxima and minima. The wavefunction can be a cosine wave. The output waveform is generated by joining together consecutive segments. The wavefunction segments are produced in the wavefunction generator by output DACs (70, 72) fed from PROMS (78, 76) containing values of sampled points representing the predetermined wavefunction. Reference DACs (64, 66) are fed alternately with amplitude levels between which the segments extend, and the reference DACs control the output levels of the output DACs.

Description

I
DIGITAL WAVEFORM ENCODER AND GENERATOR
FIELD OF THE INVENTION
The present invention relates to a method and apparatus for encoding an electronic waveform as a digital signal, and a method and apparatus for regenerating the waveform from the digital signal.
In particular, the invention relates to the encoding and generation of audio signals, especially those including speech.
BACKGROUND OF THE INVENTION
In a conventional method for encoding an analogue waveform, the waveform is sampled periodically, and each instantaneous sampled value is then quantised as a digital value by means of an analogue to digital converter (ADC). Typically for a medium quality encoder, the ADC may be an 8 bit device allowing a resolution of 256 quantised values. The bandwith of the encoder is determined by the rate at which the waveform is sampled, the maximum frequency detectable being half the sampling frequency. Such a method has the disadvantage that the quantity of data in the digital signal is vast. For example, using the aforementioned 8-bit ADC at a sampling frequency of 20KHz for normal speech, 160000 bits of data are encoded per second.
For this reason, common digital memory devices, such as integrated circuits, are not used to store digital audio data of this type. Storage media having a higher storage density are used instead. X.
To reduce the quantity of encoded data, the resolution or the sampling frequency, or both, can be reduced, but with a corresponding reduction in the quality of the encoded signal. Known systems storing speech in ROM or other computer memory produce unnatural, robot-like speech.
OBJECT OF THE INVENTION
It is an object of the present invention to provide a method of encoding a waveform as a digital signal, that can produce less digital data than the aforementioned method, with an adequate bandwith and resolution in the encoding.
SUMMARY OF THE INVENTION
The invention is defined in the appended claims.
In a first aspect of the present invention, the waveform is encoded by extracting values of alternate maxima and minima from the waveform, and measuring timing intervals associated with consecutive minima and maxima. The extracted values and the timing information can be combined and arranged as the digital signal.
The waveform is regenerated from the digital signal by joining together segments of a predetermined wavefunction of period determined by the timing information, and of amplitude determined by the values of the maxima and minima.
A second aspect of the invention is a generator for generating an analogue signal in the form of a segment of predetermined wavefunction shape, extending from a first digitally encoded amplitude level to a second digitally encoded amplitude level. A generator generates a sequence of digital values representing consecutive points on the predetermined wavefunction, which extends between a maximum level and a zero level. A DAC converts the digital values to a corresponding analogue signal, and another DAC converts the digital values to a complementary analogue signal. The amplitudes of the analogue signals are controlled by the first and second amplitude levels, and the analogue signals are mixed to produce an output signal.
DESCRIPTION OF THE PREFERRED EMBODIMENT
An embodiment of the invention will now be described by way of example, with reference to the accompanying drawings, in which:
Figure 1 is a block diagram of the parts of an apparatus for recording and replaying an analogue waveform; and
Figures 2-5 show examples of waveforms in the record and replay sections of the apparatus.
Referring to figure 1, a waveform recording apparatus 10 has an encoding or recording sub-system generally comprising the elements on the left hard side of the block diagram, and a playback or generating sub-system generally comprising the elements on the right hand side of the block diagram. Some elements are common to both sub-systems. The recording sub-system has an analogue A.C. input 12 which feeds in parallel to a maximum or positive peak detector 14, and, via an inverter 16, to a minimum or negative peak detector 18. The peak detectors 14 and IS are similar devices which detect and hold peak values, until they are reset. They are resettable to zero concurrently by means of a reset control line 20. The outputs of the peak detectors 14 and IS are ~Ϋ connected to respective inputs of a summing amplifier 22, having a sum output 24 connected in turn to the input of an analogue to digital converter (ADC) 23 to provide a digital output 25.
The input 12 is also connected to a reference detector 26 which detects when the input signal crosses a predetermined reference value. The detector 26 outputs a high pulse whenever the reference value is crossed. In the present embodiment adapted for A.C. waveforms, (i.e. with no DC component), the reference value is zero.
In use during recording as explained hereinafter the reference detector 26 controls the maximum and minimum peak detectors 14 and 18 defect alternate maxima and minima in the input waveform. On a positive going part of the input waveform, both detectors 14 and 18 are reset as the waveform crosses the zero value. The maximum value of the waveform until it again crosses the zero value is detected and held by the maximum peak detector 14. This maximum value appears at the input of the summing amplifier 22, and, since the output from the minimum peak detector 18 is still zero, the maximum value appears at the sum output 24. When the waveform drops below zero, both detectors 14 and 18 are again reset, and the subsequent minimum value is detected and its amplitude appears at the sum output 24.
A free running crystal oscillator 30 has an output 32 which is connected via a divide by 100 counter 34 to a record counter 36. The record counter has a reset input 38 which is connected to the reset line 20. In use during recording the record counter counts clock pulses to time relative intervals between the points at which the input waveform crosses the zero value. The digital output 25 from the ADC 23, and the output from the record counter 36 are connected to bidirectional input/output data lines 40a, 40b respectively of a random access memory (RAM) 42. The RAM 42 communicates via a data bus 44 with an EPROM 46 which can store a recorded waveform for playback.
The showing of the static RAM (SRAM) 42 and EPROM 46 is schematic. In practice, in a recording apparatus the data will be recorded in RAM 42 and then drawn from RAM into one or more EPROMs. In a pure playback apparatus the EPROM may replace the RAM.
In the RAM and EPROM memories, the peak amplitude data and the time interval data are stored as a sequential digital signal of pairs of digital words. The first word in the pair corresponds to the peak data, and the second word corresponds to time interval data. The inputs and outputs of the memories include multiplexers for arranging the data as the sequential digital signal.
The RAM 42 is accessed by means of a first address counter 43, which has an increment input 45 connected to the centre pole 51 of a record/playback selector switch 53. The record pole 54a of the switch 53 is connected to the reset line 20, whereby in the record mode, the address counter is incremented by reset pulses. The address counter 43 controls the RAM 42 to sequentially store or retrieve data in the RAM 42.
The data line 40b from the RAM 42 is also connected to a control input of a variable frequency divider counter 48. The counter 48 has another input which is connected to the output 32 from the oscillator 30, such that the output from the divider counter 48 is equal to the signal from the oscillator G
30 divided by a parameter N obtained from the RAM 42.
The output from the counter 48 is connected to the input of a second address counter 50. The counter 50 has an overflow output 52 which is connected to the playback pole 54b of the switch 53. In use during playback as explained hereinafter, timing information is read out from the RAM 42, and a timing period signal of frequency dependent on the timing information is generated by the divider 48. At the end of each timing period, a pulse is sent from the second address counter 50 to increment the first address counter 43, and thereby access the next data in the RAM 42.
The output from RAM 42 is applied to the circuitry shown at the right hand end of Figure 1 which operates to generate an analoque signal in the form of a segment of predetermined wavefunction shape extending from one digitally encoded amplitude level read from RAM 42 to the next digitally encoded amplitude level.
The data line 40a is also connected in parallel to the data inputs of a first or down amplitude latch 55, and a second or up amplitude latch 56. The overflow output 52 from the second address counter 50 is connected to the input of a flip flop 58, which has complementary outputs 60a and 60b connected to control inputs of the latches 55 and 56, respectively. In use, during playback, when data is read out from the RAM 42, the flip flop 58 determines which latch 55, 56 accepts the data from the data line 40a. When the output 60a is high and output 60b is low, the first latch 55 accepts the data, and when the output 60a is low and the output 60b is high, the second latch 56 accepts the data. The output from the first latch 55 is connected to the input of a first or down level reference digital to analogue converter (DAC) 62, and the output from the second latch 56 is connected to the input of a second or up level reference DAC 64. The analogue output form the first DAC 62 is connected through a first buffer amplifier 66 to the reference voltage input of an output third DAC 70, and the analogue output from the second DAC 64 is connected through a second buffer amplifier 68 to the reference voltage input of an output fourth DAC 72.
The address counter 50 has an address output bus 74 which is connected in parallel to the inputs of two preprogrammed memories 76 and 78. The data output of the memories 76, 78 are connected to the digital inputs of the third and fourth DACS 70, 72 respectively. Each memory has one hundred locations in which are stored digital values representing points in a half cycle of a cosine function which is offset to vary between the values 255 and 0. The memories 76, 78 are thus termed half-cosine wave count up and down PROMs (programmable read-only memories) respectively.
Referring to figure 2, the contents of memory 76 are shown graphically as a line 88, and the contents of memory 78 are shown as a line 86. The wavefunctions defined by the lines 88 and 86 are complementary wavefunctions. Under the control of the variable frequency divider counter 48, the address counter 50 behaves as a variable frequency generator to count sequentially through the one hundred address values at the rate specified by the timing information N. In so doing, the digital values representing the half cycle complementary cosine functions are passed to the third and fourth DACS, 70 and 72 to generate the half cycle cosine functions as analogue functions. These are used to generate the waveform, as % explained hereinafter, and are termed half-cosine output DACs for the up and down half-cycles respectively.
Control logic (not shown) synchronises the flip-flop 58 to the second address counter such that the particular up or down latch 55 or 56, respectively, enabled by the flip-flop 58 when data is read from the RAM 42 the latch associated with the particular half-cosine wave count up and down PROM, 76 or 78, respectively, whose output is zero.
The output from the fourth DAC 72 is passed through an inverting amplifier 80, whose output is connected to one input of a summing or combining amplifier 82. The output from the third DAC 70 is connected directly to another input of the summing amplifier 82, whose sum output 84 is the generated analogue waveform.
In use, in the recording, or waveform encoding, mode, the switch 53 is set to the pole 54a and an analogue input is applied to the input 12. For example, the input waveform may be of the form shown in figure 3. As explained hereinbefore, the amplitudes of alternate maximum and minimum peaks in the waveform are extracted from the waveform and appear as digital values at the output from the ADC 23. Each peak value has an associated, time count in clock pulses which appears at the output from the record counter 38. If the output frequency of the oscillator 30 is F, the associated time count will be N where T=100N, T being the timed interval for the peak. F
Referring to figure 3, with an input waveform as shown, the first peak will be the amplitude yx, with its timing information Tx. The value yx, is transferred to the RAM 42 via the ADC 23 at the end of Tx, when the zero crossing detector 26 detects that the waveform crosses zero. The next peak will be the amplitute y~~ with its timing information Ta, and the next amplitude 3 with its timing information T3. Only the amplitude of a peak is important, and not its sign, since the peaks are necessarily detected as alternate maxima and minima about the reference value of zero.
Referring to figures 1 and 3, each time the waveform crosses zero, a reset pulse is generated to store the peak data, and the timing information in the RAM 42, and reset the detectors 14 and 18 and the counter 36, as well as to increment the first address counter 43. Alternate maximum and minimum values of the waveform are thereby stored sequentially in the RAM 42 each in association with the corresponding time value.
In the playback, or waveform generation, mode the switch 53 is set to the pole 54b, and the first address counter 43 is initially reset. Timing information data is output from the RAM 42 at the data line 40b concurrently with peak data being output at the data line 40a. Depending on the state of the flip flop 58, the peak data will either be interpreted as a maximum point and stored in the first latch 55, or it will be interpreted as a minimum point and stored in the second latch 56. The digital values in the latches 55, 56 are converted into analogue reference levels by the first and second DACs 62, 64 respectively, and fed to the reference voltage inputs of the third and fourth DACs 70, 72 respectively. The reference voltage inputs control the maximum outputs available from the third and fourth DACs 70, 72, whereby the peak data contained in the latches 55, 56 effectively controls the amplitude of a signal generated by the DACs 70, 72 respectively. \ The timing information data output from the RAM 42 is input to the variable frequency divider counter 48. The timing information value N introduced hereinbefore is used to generate an output freqency from the divider counter 48 of frequency F/N, or period N/F. The time taken for one hundred output pulses to be generated will be 100 N/F = T, the interval timed for the peak. Therefore, the second address counter 50 counts through the one hundred addresses for the memories 76 and 78 at a rate determined by the timing information, such that the time taken to count through the addresses is equal to a the interval of the duration of the associated peak in the original waveform.
Referring to the figures, and considering regeneration of the waveform in figure 3 between the points yx and y__, as the second address counter 50 counts through the one hundred addresses in the time period T_s, the outputs from the memories 76 and 78 follow the lines 88 and 86, respectively, in figure 2.
Referring especially to figure 4, as the values of the digital output from the memory 78 decrease in the shape of a half cycle cosine function, the output from the third DAC 70 will be as shown by the line 90, decreasing from the value yx stored in the latch.55 to zero. Similarly, the output from the fourth DAC 72 will be as shown by the line 92 increasing (negatively in figure 4) from zero to the value yz stored in the latch 56. The output from the fourth DAC 72 is shown inverted in figure 4, because it is inverted by the inverting amplifier 80.
The sum signal is formed in the summing amplifier 82, and is itself a half-cycle cosine function as shown by the line 94. Once the point γ-~ has been reached, a new peak value 3 is I I loaded into the latch 56 as the next (maximum) peak value, and its associated timing information corresponding to T3 is loaded into the time period divider counter 48. The next section of the waveform is interpolated in a similar way to that discussed above.
The flip flop 58 is toggled each time new peak data is read from the RAM 42, such that new peak data is loaded alternately into the latches 55, 56. The address counter counts alternately up and down through the one hundred addresses such that the roles of the memories 76, 78 in outputting the increasing and decreasing half-cycle cosine functions are effectively reversed for each new peak value.
It will be appreciated that with the method for encoding the waveform as a digital signal described above, the amount of digital data is reduced compared with an equivalent method using continuous periodic sampling. Typically, the digital signal can be compressed by the order of 30 for speech signals, and 20 for music signals, compared with conventional sampling techniques. In the preferred embodiment the digital data is stored in an integrated circuit memory array (RAM or ROM) since it is feasible to store several minutes of passable audio in an inexpensive chip.
It will also be appreciated that the reference voltages supplied to the third and fourth DACs 70, 72 respectively, are only altered when the output from the respective DAC is zero. This avoids any glitches which would otherwise be present in the output waveform.
It will be appreciated further that the sum output of the generated waveform is smooth since new data for the interpolation parameters is only loaded when the gradient of the waveform is zero. The output waveform can only contain second and higher order discontinuities.
Although the embodiment described above has both a recording, or encoding section and a playback, or regenerating section, other embodiments may have only one section. For example, a pre-programmed speech generator may have only the playback section.
Such a speech generator may for example be used in devices such as intruder alarms, personal alarms, or fire alarms, to emit an intelligible warning or distress message. Where small size is important, the circuit for the speech generator may be contained substantially in a single integrated circuit. The speech generator may also be used in talking toys or novelty items, for example a talking picture.
A further application of the invention is in the field of computer speech recognition and comprehension. The present method of encoding an input waveform compresses the amount of information in the input signal to a level easily manageable by a computer, while still preserving the important features of the input signal waveform. The encoding can reduce the input waveform to a sequence of identifiable portions that may be stored or processed by a computer.
Although in the method described above, the generated waveform output is not identical to the analogue waveform input, the differences are sufficiently small that adequate fidelity of the original waveform is maintained. This is especially the case for human speech.
Although in the preferred embodiment, the waveform is encoded by extracting only values of alternate maxima and minima which occur above and below, respectively, the zero reference value, in an alternative embodiment, other maxima and minima may be extracted. For example, referring to a sample waveform shown in figure 5, the values of intermediate points ys and y could be included in the encoded signal, as well as the values of yx, yz and y_> although at the expense of substantially increased circuit complexity.
Similarly, although in the preferred embodiment, the timing information corresponds to relative intervals between points at which the waveform crosses the zero reference value, in an alternative embodiment, the timing information may correspond to the actual positions at which the detected maxima and minima occur. Referring again to figure 5, the relative time intervals tx to t-~ , t-~ to ts etc. would be encoded as the timing information (assuming that only maxima and minima separated by zero crossings are encoded, as in fig 3). In another embodiment, the time locations of the maxima and minima may also be combined with the time locations of the points at which the waveform crosses the zero reference value, giving a more detailed encoded signal representing the waveform. The method of regenerating the waveform could then use segments of quarter cycle sine waves, thereby generating the original waveform more accurately.
Although in the preferred embodiment, the waveform is generated by combining segments of cosine waves, each segment starting and ending at a maximum or minimum, in an alternative embodiment, the segments could be of half cycle sine waves, beginning at zero and passing through the maximum or minimum and returning to zero. In the embodiment described above, the encoding and generating sections of the apparatus are comprised of dedicated hardware for performing the encoding and generation. It will be appreciated, however, that one or both of these sections can be realised by using a programmed computer.
For example, in the encoding section, an ADC could be used to convert an input analogue waveform to a periodically sampled digital form, and the signal fed to a programmed computer. The computer would be programmed to detect alternate values of maxima and minima in the signal, and to measure timing intervals associated with consecutive maxima and minima, in accordance with the invention.
The resulting data in the computer would be combined and arranged in a suitable format for the enclosed digital signal.
In the generating section, a programmed computer could have a digital output port connected to an output DAC. The computer would generate digital values of the wavefunction segments in accordance with the invention, and feed the digital values to the DAC to produce an analogue output waveform.
It will be appreciated that if the waveform is itself a digital signal, the input ADC and the output DAC would be omitted, and the encoding and generating sections incorporated in software programming of the computer.

Claims

1. A method of encoding an electronic waveform as a digital signal, wherein values of alternate maxima and minima in the waveform are extracted from the waveform and combined with associated timing information, and . arranged as the digital signal.
2. A method according to claim 1, wherein the values of the extracted maxima and minima are above and below, respectively, a predetermined reference value.
3. A method according to claim 2, wherein the predetermined reference value is zero.
4. A method according to claim 2, wherein the timing information corresponds to the intervals between the times at which the waveform crosses the predetermined reference value.
5. A method according to claim 1, wherein the timing information corresponds to the intervals between the times at which the maxima and minima are detected.
6. A method according to claim 1, wherein the timing information corresponds to the intervals between the times at which the maxima and minima are detected and the times at which the waveform crosses the predetermined reference value.
7. A method according to claim 1, wherein the electronic waveform is an audio signal. \ (a
8. A method of generating an electronic waveform from an encoded digital signal, the digital signal containing values of alternate maxima and minima in the waveform and associated timing information, the waveform being generated by joining together segments of a predetermined wavefunction of period determined by the timing information, and of amplitude determined by the values of the maxima and minima.
9. A method according to claim 8, wherein the predetermined wavefunction is a cosine wave.
10. A method according to claim 8, wherein the peak to peak amplitude of the wavefunction is equal to the difference between the values of consecutive maxima and minima.
11. A method according to claim 8, wherein the amplitude of the wavefunction is equal to the value of a maximum or minimum.
12. A method according to claim 8, wherein the timing information corresponds to an interval between consecutive maxima and minima, the period of the predetermined wavefunction being twice the interval, and each segment being a half cycle of the wavefunction.
13. A method according to claim 8, wherein the segment is a quarter cycle of the wavefunction.
14. A method according to claim 8, wherein each segment starts and ends with zero slope.
15. A method according to claim 8, wherein the electronic waveform is an audio signal.
16. Apparatus for encoding an electronic waveform as a digital signal, comprising: detector means for detecting alternate maxima and minima values in the waveform; timing means for timing intervals associated with consecutive maxima and minima; and means for arranging the outputs from the detectors and the timing means as the digital signal.
17. Apparatus according to claim 16, whererin the detector means comprises a resettable first detector for sensing and holding a maximum value of the waveform, a resettable second detector for sensing and holding a minimum value of the waveform, and means for controlling the detectors to sense alternate maxima and minima in the waveform.
18. Apparatus according to claim 17, wherein the controlling means comprise a third detector for sensing when the waveform crosses a predetermined reference value.
19. Apparatus according to claim 18, wherein the timing means times intervals between points at which the waveform crosses the reference value.
20. Apparatus according to claim 16, wherein the electronic waveform is an analogue signal, further comprising an analogue to digital converter for translating values of maxima and minima into digital form.
21. Apparatus according to claim 16, further comprising memory means for storing the digital signal. I *.
22. Apparatus for generating an electronic waveform from an encoded digital signal, the digital signal containing values of alternate maxima and minima in the waveform and associated timing information, comprising: means for generating a segment of a predetermined wavefunction, of period determined by the timing information, and of amplitude determined by the values of the maxima and minima; and means for joining together segments generated consecutively to produce the electronic waveform.
23. Apparatus according to claim 22, wherein the generating means includes a preprogrammed digital memory containing sample values of the wavefunction, an address counter for accessing the memory, and a clock generator for generating a clock pulse signal at rate determined by the timing information, the output from the clock generator being connected to step the address counter to sequentially access values of the wavefunction, further comprising means for controlling the amplitude of the wavefunction depending on the values of maxima and minima.
24. Apparatus according to claim 23, wherein the electronic waveform is an analogue signal, the waveform being generated by an. output digital to analogue converter, characterised in that the means for controlling the amplitude of the wavefunction comprising a reference digital to analogue converter for generating an analogue voltage representing a maximum or a minimum, the voltage being connected to the reference input of the output digital to analogue converter to control its output amplitude.
25. Apparatus according to claim 24, further comprising a second preprogrammed memory containing in reverse order the sampled valves of the wavefunction, the first and second memories being accessed in parallel by the address counter, a second output digital to analogue converter, and a second reference digital to analogue converter therefore, and means for subtracting the output of the second output digital to analogue converter from that of the first output digital to analogue converter to obtain the generated waveform.
26. A system for recording an electronic waveform as a digital signal, and for regenerating a waveform encoded as a digital signal, the system including a recording sub-system and a generating sub-system, characterised in that the recording sub-system comprises: detector means for sensing alternate maxima and minima values in the waveform; timing means coupled to the detector means, for measuring timing intervals associated with consecutive maxima and minima in the waveform; and means coupled to the detector means and to the timing means, for arranging the outputs from the detector means and from the timing means as the digital signal; and the generating sub-system comprises: means for generating a segment of a predetermined wavefunction, of period determined by the timing information in the digital signal, and of amplitude determined by the values of the maxima and minima information in the digital signal; and means for joining together segments generated consecutively to produce the generated waveform. P-JD
27. Apparatus according to claim 26, characterised in that the system further comprises a digital memory means for storing the digital signal from the recording sub-system, means for selectively retrieving the stored signal from the memory means, and means for sending the retrieved signal to the generating sub-system.
28. A method of encoding an electronic waveform as a digital signal, comprising the steps of: extracting from the waveform values of alternate maxima and minima in the waveform; measuring timing intervals associated with consecutive maxima and minima in the waveform; and arranging the measured timing intervals and the extracted values as the digital signal.
29. A method according to claim 30, wherein the electronic waveform is an analogue signal, wherein the method includes the step of converting values in the waveform to digital form.
30. A method of generating an electronic waveform from an encoded digital signal, the digital signal containing values of alternate maxima and minima in the waveform and associated timing information, comprising the steps of: generating a segment of a predetermined wavefunction of period determined by the timing information, and of amplitude determined by values of the maxima and minima; and joining together segments generated consecutively to produce the waveform.
31. A system for recording an electronic audio signal as a digital signal, characterised in that the recording system comprises: input means for inputting the electronic audio signal;
Figure imgf000023_0001
detector means coupled to the input means for sensing alternate maximum and minimum values in the audio signal; and timing means coupled to the detector means for measuring timing intervals associated with consecutive maxima and minima in the audio signal.
32. A system for regenerating an audio signal digitally encoded as values of alternate maxima and minima in the audio signal and associated timing information, comprising: means for generating a segment of a predetermined wavefunction, the segment having a period determined by the timing information in the digital signal, and an amplitude determined by the values of the maxima and minima information in the digital signal; and means for joining together segments generated consecutively to produce the generated waveform.
33. A system according to claim 33, characterised in that the segment generating means comprises means for generating a half-cycle of a cosine wave.
34. A system for storing identifiable portions of an electronic audio waveform, comprising: detector means for sensing alternate maximum and minimum values in the audio waveform; timing means for measuring timing intervals associated with consecutive maxima and minima in the audio waveform; and memory means for storing the maxima and minima values and the associated timing intervals.
35. A method of storing identifiable portions of an electronic audio waveform, comprising the steps of: detecting alternate maximum and minimum values in the audio waveform; ~^J~- measuring timing intervals associated with consecutive maxima and minima values, and storing the detected maxima and minima values and the associated timing intervals.
36. Apparatus for generating an analogue signal in the form of a segment of predetermined wavefunction shape extending from a first digitally encoded amplitude level to a second digitally encoded amplitude level, comprising: first converter means for converting the first digitally encoded amplitude level to a corresponding analogue first reference signal; second converter means for converting the second digitally encoded amplitude level to a corresponding analogue second reference signal; means for generating a sequence of digital values representing consecutive points on the predetermined wavefunction, the wavefunction extending between a maximum level and zero level; means for converting the sequence of digital values to a corresponding third analogue signal; means for converting the sequence of digital values to a fourth analogue signal complementary to the third analogue signal; first amplitude control means for controlling the amplitude of the third analogue signal in response to the level of the first reference signal; second amplitude control means for controlling the amplitude of the fourth analogue signal in response to the level of the second reference signal; and combining means for combining the third and fourth analogue signals to produce the generated analogue signal. ~ S
37. Apparatus according to claim 36, wherein the generating means comprises a digital memory containing the digital values stored sequentially, and means for addressing the memory to read out the sequence of digital values.
38. Apparatus according to claim 36, wherein the first amplitude control means is incorporated in the third converter, the analogue first reference signal being fed to a reference voltage input of the third converter, and wherein the second amplitude control means is incorporated in the fourth converter, the analogue second reference signal being fed to a reference voltage input of the fourth converter.
39. Apparatus according to claim 36, wherein the digitally encoded first and second amplitude levels correspond to levels of opposite polarity, the apparatus further comprising an analogue inverter coupled between the output of one of the third and fourth converters, and the combining means.
40. A method of generating an analogue signal in the form of a segment of predetermined wavefunction shape extending from a first digitally encoded amplitude level to a second digitally encoded amplitude level, comprising: converting the first digitally encoded amplitude level to a corresponding analogue first reference signal; converting the second digitally encoded amplitude level to a corresponding analogue second reference signal; generating a sequence of digital values representing consecutive points on the predetermined wavefunction, the wavefunction extending between a maximum level and a zero level; converting the sequence of digital values to a corresponding third analogue signal; converting the sequence of digital values to a fourth An- analogue signal complementary to the third analogue signal; controlling the amplitude of the third analogue signal in response to the first reference signal; controlling the amplitude of the fourth analogue signal in response to the second reference signal; combining the third and fourth analogue signals to produce the generated analogue signal.
41. Apparatus according to claim 22, wherein the wave function segment generating means comprises a generator for generating an analogue signal in the form of a segment of predetermined wavefunction shape extending from a first digitally encoded amplitude level to a second digitally encoded amplitude level, comprising: first converter means for converting the first digitally encoded amplitude level to a corresponding analogue first reference signal; first converter means for converting the second digitally encoded amplitude level to a corresponding analogue second reference signal; means for generating a sequence of digital values representing consecutive points on the predetermined wavefunction, the wavefunction extending between a maximum level and zero level; means for converting the sequence of digital values to a corresponding third analogue signal; means for converting the sequence of digital values to a fourth analogue signal complementary to the third analogue signal; first amplitude control means for controlling the amplitude of the third analogue signal in response to the level of the first reference signal; second amplitude control means for controlling the _ amplitude of the fourth analogue signal in response to the level of the second reference signal; and combining means for combining the third and fourth analogue signals to produce the generated analogue signal.
42. A method according to claim 8, wherein the segment of the predetermined wavefunction is generated as an analogue signal extending from a first digitally encoded amplitude level, the generating method comprising the steps of: converting the first digitally encoded amplitude level to a corresponding analogue first reference signal; converting the second digitally encoded amplitude level to a corresponding analogue second reference signal; generating a sequence of digital values representing consecutive points on the predetermined wavefunction, the wavefunction extending between a maximum level and a zero level; converting the sequence of digital values to a corresponding third analogue signal; converting the sequence of digital values to a fourth analogue signal complementary to the third analogue signal; controlling the amplitude of the third analogue signal in response to the first reference signal; controlling the amplitude of the fourth analogue signal in response to the second reference signal; combining the third and fourth analogue signals to produce the generated analogue signal.
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US11172312B2 (en) 2013-05-23 2021-11-09 Knowles Electronics, Llc Acoustic activity detecting microphone
US10313796B2 (en) 2013-05-23 2019-06-04 Knowles Electronics, Llc VAD detection microphone and method of operating the same
US10332544B2 (en) 2013-05-23 2019-06-25 Knowles Electronics, Llc Microphone and corresponding digital interface
CN106104686A (en) * 2013-11-08 2016-11-09 美商楼氏电子有限公司 Mike and corresponding digital interface
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US10469967B2 (en) 2015-01-07 2019-11-05 Knowler Electronics, LLC Utilizing digital microphones for low power keyword detection and noise suppression
WO2020076713A1 (en) * 2018-10-09 2020-04-16 Brian Kaczynski Fundamental frequency detection using peak detectors with frequency-controlled decay time
US11289062B2 (en) 2018-10-09 2022-03-29 Second Sound, LLC Fundamental frequency detection using peak detectors with frequency-controlled decay time

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