WO1991000565A2 - Power conservation in microprocessor controlled devices - Google Patents

Power conservation in microprocessor controlled devices Download PDF

Info

Publication number
WO1991000565A2
WO1991000565A2 PCT/US1990/003466 US9003466W WO9100565A2 WO 1991000565 A2 WO1991000565 A2 WO 1991000565A2 US 9003466 W US9003466 W US 9003466W WO 9100565 A2 WO9100565 A2 WO 9100565A2
Authority
WO
WIPO (PCT)
Prior art keywords
processor
multiprocessor system
processors
power supply
task
Prior art date
Application number
PCT/US1990/003466
Other languages
French (fr)
Other versions
WO1991000565A3 (en
Inventor
Richard A. Perry
Vernon L. Stant
Original Assignee
Hand Held Products, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hand Held Products, Inc. filed Critical Hand Held Products, Inc.
Publication of WO1991000565A2 publication Critical patent/WO1991000565A2/en
Publication of WO1991000565A3 publication Critical patent/WO1991000565A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3293—Power saving characterised by the action undertaken by switching to a less power-consuming processor, e.g. sub-CPU
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • This invention relates to microprocessor controlled devices, and more particularly to a method and apparatus for conserving power in microprocessor controlled devices.
  • battery powered microprocessor controlled devices have i acome increasingly popular.
  • a battery powered microprocessor controlled device is a portable bar code reader of the type employed by overnight delivery services, supermarkets and others to scan and store bar code data.
  • a major limitation of battery powered microprocessor controlled devices is the battery life. Such devices are not useful in a practical sense if the battery life is too short. Of course, battery life may be extended by improving the batteries themselves or by providing more batteries in the device. However, such improvements often increase the cost, size and/or weight of the device.
  • Battery life may also be extended by improving the microprocessor control system so that it consumes less power during device operation.
  • U.S. Patent No. 4,673,805 to Shepard et al. entitled Narrow-Bodied, Single- And Twin-Windowed Portable Scanning Head For Reading Bar Code Symbols discloses a system in which a trigger signal or keyboard entry activates a microprocessor in a scanner, which in turn activates a laser for bar code scanning. After a scan or data entry the microprocessor is deactivated. Unfortunately, for sophisticated battery powered devices, the microprocessor cannot be deactivated because there are certain "background" tasks, for example maintaining correct time of day, which must always be performed. A similar system is described in U.S. Patent No.
  • U.S. Patent No. 4,677,433 to Catlin et al. entitled Two-Speed Clock Scheme For Co-Processors discloses a system including two processors one of which is a high speed microprocessor, the other of which is a low speed numeric data processor. The system runs at low speed when both processors must be used and runs at high speed when only the microprocessor needs to be used. A source control provides a high or low speed clock via a clocking generator which is coupled to both processors. There is no suggestion to use such a system for power conservation. It is also known in the art to operate a microprocessor at two speeds to conserve power. For example, U.S. Patent No.
  • a microprocessor controlled device which employ, two microprocessors.
  • One of the microprocessors is ⁇ . low power low performance low speed processor for performing background tasks.
  • the other microprocessor is a high power high performance processor that may run at one of several high speeds for performing computationally intensive foreground tasks.
  • the low speed microprocessor includes means for activating the high speed processor when a high performance task is to be performed.
  • the low performance processor always remains activated, so that background tasks such as timekeeping may be performed. Power is thereby conserved, without the need to totally deactivate the system.
  • the low speed processor may operate with a low level (e.g. low voltage) power supply while the high speed processor requires a high level (e.g. high voltage) power supply. Accordingly, when activating the high performance processor the low performance processor also controls the power supply to provide high power level (e.g. high voltage) to the high speed processor.
  • a low level e.g. low voltage
  • high level e.g. high voltage
  • the use of multiple power supply levels which are a function of the task to be performed further extends battery life.
  • the high speed processor may run at variable clock speeds, with power consumption of the processor increasing with increasing speed.
  • the high speed processor executes a plurality of software subroutines for performing a plurality of tasks.
  • the high speed processor selects its own clock speed based upon the task to be performed. This may be accomplished, according to the invention, by including a clock speed in each subroutine, preferably at the beginning of the subroutine.
  • the high speed processor executes a software subroutine at the clock speed associated with that subroutine. This clock speed may be set to be the lowest possible clock speed consistent with the task to be performed.
  • battery life may be extended by providing a high performance processor which is activated by a low performance processor depending upon the task to be performed; by controlling the power supply to provide high power only when the high performance processor is active; and by providing self control of the high performance processor speed.
  • each of the above described features may be employed separately or in connection with other features in order to extend battery life.
  • the above described combination of features provides a system which is uniquely capable of performing computationally intensive foreground tasks and simple background tasks with minimal power drain. It will also be recognized that advantages other than power conservation may be obtained according to the present invention.
  • each task is performed at its lowest required speed, thereby preventing overload, permitting the use of lower capacity peripherals and enhancing system efficiency.
  • Figure 1 is a block diagram of a battery powered microprocessor controlled device according to the present invention.
  • FIG. 2A-2C is a flowchart illustrating certain operations employed in the present invention.
  • microprocessor controlled device 1 includes a low performance microprocessor 10 and high performance microprocessor 20.
  • low performance microprocessor 10 may be a MC68HC04P4 Microcomputer Unit distributed by Motorola (Phoenix, Arizona) , which is an 8 bit microprocessor containing a central processing unit, on-chip clock, read only memory, random access memory, input and output buffers and a timer.
  • This microcomputer is a low performance low power microprocessor which operates at a clock rate of 32 KHz and average current consumption of 10-20 ⁇ A.
  • the low performance microprocessor 10 may be employed to refresh the display in the device, maintain the time of day, control the device power supply, control the keyboard, and activate a high performance microprocessor as will be described in detail below.
  • High performance microprocessor 20 may be an RTX 2000 Real Time Microcontroller distributed by Harris Corporation (Melbourne, Florida ) .
  • the RTX 2000 is a high performance 16 bit microcontroller with on chip timers, an interrupt controller .nd single cycle multiplier.
  • the RTX 2000 employs single cycle instruction execution and may directly execute software written in FORTH, a high level language.
  • the RTX 2000 may operate at variable clock speeds ranging from 0 up to 10 MHz, with power consumption being directly proportional to clock speed. For example, at a 1 MHz clock speed current consumption i*-? approximately 3.5 A while at 10 MHz, current consu. ption is approximately 35 mA.
  • the RTX 2000 may be employed according to the invention for performing numerically intensive foreground tasks, such as bar code decoding and processing.
  • system 1 also includes an Application Specific Integrated Circuit (ASIC) 13 which, as is well known to those having skill in the art, is a customized integrated circuit which integrates many functions on a single chip.
  • ASIC 13 may include a display control 13a which is connected to display 14, a keyboard control 13b which is connected to keyboard IS, a Universal Asynchronous Receiver/Transmitter (UART) 13c, digital to analog converters 13d, and analog to digital converters 13e.
  • a horn control 13f which controls horn 16 may also be included as may be a bar code reader control 13g which controls the operation of bar code scanner 17.
  • a variable speed clock control 13h is also included in ASIC 13. It will be understood by those having skill in the art that the individual functions included in ASIC 13 also be provided using discrete components.
  • Low performance microprocessor 10 high performance microprocessor 20 and ASIC 13 may be interconnected for data transmission via a bus 18, as is well known to those having skill in the art.
  • memory 23 which may include read/write memory and random access memory.
  • an on key 11 which is part of keyboard 15 and a reed switch 12 which is the trigger for controlling data transfer to or from a charging and communications unit (not shown) .
  • Low performance microprocessor 10 also controls an adjustable switching regulator 19.
  • the adjustable switching regulator 19 may be an MAX631 Fixed/Adjustable Output Step Up Switching Regulator distributed by Maxim (Sunnyvale, California) , which is a high efficiency step up DC-DC converter for use in low power high efficiency switching regulator applications.
  • a battery supply 21, for example two nickel cadmium or lithium batteries may be connected to the adjustable switching regulator 19.
  • a low power detector 22 may also be connected between the battery 21 and low performance microprocessor 10.
  • a backup capacitor 24 may also be connected between switching regulator 19, memory 23, high performance microprocessor 20 and low performance microprocessor 10 for providing short term backup power, for example when battery 21 is replaced.
  • the adjustable switching regulator 19 provides power for memory 23, high performance microprocessor 20, low performance microprocessor 10 and ASIC 13. It should be noted that low performance microprocessor 10, ASIC 13 and memory 23 require a minimum of 2V power supply for operation, while high performance microprocessor 20 requires a minimum of 5V power supply. According to the invention, the low performance microprocessor controls adjustable switching regulator 19 to boost the 2.4V battery voltage to 5V when the high performance microprocessor 20 is activated by the low performance processor. It should also be noted that low performance microprocessor 10, ASIC 13 and memory 23 may be run directly from the 2.4V supplied by two nickel cadmium or lithium batteries, without requiring an intervening switching regulator, to thereby provide maximum transfer efficiency from battery 21 at low voltage levels. The switching regulator 19 may be activated only when high performance microprocessor 20 is activated. As may be seen from the block diagram of
  • low performance microprocessor may perform timekeeping and other background tasks and may continuously monitor for activation of the on key 11 or reed switch 12 or the need to perform another foreground task.
  • low performance microprocessor 10 may activate high performance microprocessor 20. It may also be seen that low performance microprocessor 10 and high performance microprocessor 20 may control the speed of variable speed clock 13h which governs the speed of high performance microprocessor 20.
  • FIG. 2 the sequence of operat ons for controlling microprocessor controlled device 1 according to the present invention will now be described. It will be recognized by those having skill in the art that the sequence of operations described in Figure 2 may be performed by low performance microprocessor 10 and high performance microprocessor 20 under control of a stored program which may reside in on-processor memory and/or in memory 23.
  • processor 10 when battery power is first applied to device 1 (Block 31) , processor 10 runs with a 2V power supply and a clock speed of 32 khz as long as power is available from the battery (Block 32) .
  • processor 10 continually scans the on key 11 and the reed switch 12 and maintains time. Other background processing tasks may be performed as necessary.
  • microprocessor 10 checks whether the battery level is below a critical level (Block 35) . This test may be performed using low power detector 22. This test is performed to see whether there is sufficient battery power to activate high performance microprocessor 20. For a 2.4V system comprising two nickel cadmium batteries the test of Block 35 may be whether the battery voltage is 2.1V or less. If the battery voltage is below the critical level then at Block 36 processor 10 will not activate processor 20 until the batteries are replaced or recharged (Block 37) . Processor 10 will, however, continue to perform background processing (Block 33) .
  • processor 10 activates the high voltage power supply using adjustable switching regulator 19, and activates processor 20 which runs at low system clock speed, for example 200 KHz (Block 38) .
  • High performance processor 20 runs at low clock speed until it has been determined that a higher clock speed is required to process a specific foreground task.
  • a second test of battery voltage is performed by processor 20. For a typical two nickel cadmium battery pack this level might be 2.4V. This test is performed to see if there is enough power to run the high speed processor 20 at high speeds. If the voltage is near the critical level (Block 40) then processor 20 places a message on display 14 and then deactivates itself (Block 41) . Then, after a predetermined timeout period (for example ten seconds) has elapsed, processor 10 turns off the high voltage power supply which turns off the •- " _splay 14.
  • a predetermined timeout period for example ten seconds
  • processor 20 runs the main application program and timeoi ;est (Block 46) in a continuous loop unless an interrupt is received.
  • a test is made c 3lock 46 to determine whether a predetermined tim (for example ten seconds) has been exceeded. If not, processing continues. If the predetermined time has been exceeded, processor 10 deactivates processor 20 (Block 47) .
  • a predetermined tim for example ten seconds
  • each interrupt or other task to be performed is performed by a software subroutine.
  • a clock speed code which indicates the appropriate clock speed for performing the task (Block 48) .
  • This clock speed code is examined and an appropriate control code is t en sent from processor 20 to the variable speed system clock 13h in ASIC 13 (Block 49) .
  • the variable speed clock then changes the speed of high performance microprocessor 20 (Block 50) .
  • three clock speeds may be employed, for example 200 KHz, 1.6 MHz and 10 MHz.
  • a control code associated with each subroutine determines the appropriate clock speed.
  • a large number of clock speeds may be employed, so that in effect a continuously variable clock speed is provided.
  • the processor 20 executes the software at the preselected speed (Block 51) .
  • processor 20 sends a control code to the variable speed clock to slow down to the slow speed.
  • the timeout clock is reset (Block 53) and processing resumes at the point in the supervisory software loop where the interrupt occurred (Block 54) .

Abstract

Power may be conserved and battery life may be extended in a microprocessor controlled device by providing two microprocessors, one of which is a low power, low performance, low speed processor for performing background tasks, the other of which is a high power, high performance, high speed processor for performing computationally intensive foreground tasks. The low speed processor activates the high speed processor when a high performance task is to be performed. When activating the high performance processor, the low performance processor also controls the device's power supply to provide high voltage to the high speed processor. The high speed processor may run at variable clock speeds, with power consumption of the processor increasing with increasing speed. The high speed processor selects its own clock speed based upon the task to be performed, by including a clock speed in each software subroutine which controls a task. The software subroutine associated with a task is thereby executed at its associated clock speed, which may be chosen to be the lowest possible clock speed consistent with the task to be performed.

Description

POWER CONSERVATION IN MICROPROCESSOR CONTROLLED DEVICES
Field Of The Invention
This invention relates to microprocessor controlled devices, and more particularly to a method and apparatus for conserving power in microprocessor controlled devices.
Background Of The nvention With the advent of low cost, high density integrated circuits, battery powered microprocessor controlled devices have i acome increasingly popular. One example of a battery powered microprocessor controlled device is a portable bar code reader of the type employed by overnight delivery services, supermarkets and others to scan and store bar code data. A major limitation of battery powered microprocessor controlled devices is the battery life. Such devices are not useful in a practical sense if the battery life is too short. Of course, battery life may be extended by improving the batteries themselves or by providing more batteries in the device. However, such improvements often increase the cost, size and/or weight of the device.
Battery life may also be extended by improving the microprocessor control system so that it consumes less power during device operation. For example, U.S. Patent No. 4,673,805 to Shepard et al. entitled Narrow-Bodied, Single- And Twin-Windowed Portable Scanning Head For Reading Bar Code Symbols discloses a system in which a trigger signal or keyboard entry activates a microprocessor in a scanner, which in turn activates a laser for bar code scanning. After a scan or data entry the microprocessor is deactivated. Unfortunately, for sophisticated battery powered devices, the microprocessor cannot be deactivated because there are certain "background" tasks, for example maintaining correct time of day, which must always be performed. A similar system is described in U.S. Patent No. 4,203,153 to Boyd entitled Circuit For Reducing Power Consumption In Battery Operated Microprocessor Based Systems in which a microprocessor is powered up only during programmed task performance. A timer, which may be fixed or programmable, reactivates the microprocessor after a predetermined timing interval. As stated above, sophisticated systems cannot permit the microprocessor to be deactivated.
It is known in the art to employ systems with two processors having different characteristics. For example, U.S. Patent No. 4,677,433 to Catlin et al. entitled Two-Speed Clock Scheme For Co-Processors discloses a system including two processors one of which is a high speed microprocessor, the other of which is a low speed numeric data processor. The system runs at low speed when both processors must be used and runs at high speed when only the microprocessor needs to be used. A source control provides a high or low speed clock via a clocking generator which is coupled to both processors. There is no suggestion to use such a system for power conservation. It is also known in the art to operate a microprocessor at two speeds to conserve power. For example, U.S. Patent No. 4,254,475 to Cooney et al. entitled Microprocessor Having Dual Frequency Clock discloses a power conservation system in which a microprocessor operates at low speed until a sensor is activated or a predetermined time duration has passed. When either of these events occur, the high speed clock is activated. Similarly, a μPD7507/08 Four Bit Single Chip CMOS Microprocessor distributed by NEC Electronics, Inc. (Mountain View, California) may be controlled to run at a plurality of clock speeds by a plurality of clock sources. Summary Of The Invention It is therefore an object of the invention to provide a method and apparatus for conserving power in microprocessor controlled devices.
It is another object of the present invention to provide a method and apparatus for extending battery life in battery powered microprocessor controlled devices.
It is yet another object of the present invention to provide a method and apparatus which allows background processing in a microprocessor controlled device without a large power drain.
It is still another object of the.present invention to allow high perfoi .ance foreground and low performance background processing in a microprocessor controlled device without a large power drain.
These and other objects are provided according to the invention by a microprocessor controlled device which employ, two microprocessors. One of the microprocessors is ε. low power low performance low speed processor for performing background tasks. The other microprocessor is a high power high performance processor that may run at one of several high speeds for performing computationally intensive foreground tasks. According to the invention, the low speed microprocessor includes means for activating the high speed processor when a high performance task is to be performed. The low performance processor always remains activated, so that background tasks such as timekeeping may be performed. Power is thereby conserved, without the need to totally deactivate the system.
According to another aspect of the invention the low speed processor may operate with a low level (e.g. low voltage) power supply while the high speed processor requires a high level (e.g. high voltage) power supply. Accordingly, when activating the high performance processor the low performance processor also controls the power supply to provide high power level (e.g. high voltage) to the high speed processor. The use of multiple power supply levels which are a function of the task to be performed further extends battery life.
According to yet another aspect of the present invention the high speed processor may run at variable clock speeds, with power consumption of the processor increasing with increasing speed. The high speed processor executes a plurality of software subroutines for performing a plurality of tasks. According to the invention, the high speed processor selects its own clock speed based upon the task to be performed. This may be accomplished, according to the invention, by including a clock speed in each subroutine, preferably at the beginning of the subroutine. The high speed processor executes a software subroutine at the clock speed associated with that subroutine. This clock speed may be set to be the lowest possible clock speed consistent with the task to be performed.
As described above, battery life may be extended by providing a high performance processor which is activated by a low performance processor depending upon the task to be performed; by controlling the power supply to provide high power only when the high performance processor is active; and by providing self control of the high performance processor speed. It will be recognized by those having skill in the art that each of the above described features may be employed separately or in connection with other features in order to extend battery life. It will also be recognized that the above described combination of features provides a system which is uniquely capable of performing computationally intensive foreground tasks and simple background tasks with minimal power drain. It will also be recognized that advantages other than power conservation may be obtained according to the present invention. For example, use of a high performance processor only for computationally intensive tasks may reduce computer overhead and enhance the data processing efficiency of the overall system, because high performance processors are often not well suited for performing simple tasks. Moreover, the performance of all tasks at high speed may require high capacity peripheral devices which are only active for a small percentage of the device operation time. According to the invention, each task is performed at its lowest required speed, thereby preventing overload, permitting the use of lower capacity peripherals and enhancing system efficiency.
Brief Description Of The Drawings Figure 1 is a block diagram of a battery powered microprocessor controlled device according to the present invention.
Figure 2A-2C is a flowchart illustrating certain operations employed in the present invention.
Detailed Description Of The Invention The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which a preferred embodiment of the invention is shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiment set forth herein; rather, this embodiment is provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout. Referring now to Figure 1 a block diagram of a microprocessor controlled device according to the present invention is shown. According to the invention, microprocessor controlled device 1 includes a low performance microprocessor 10 and high performance microprocessor 20. In one embodiment, low performance microprocessor 10 may be a MC68HC04P4 Microcomputer Unit distributed by Motorola (Phoenix, Arizona) , which is an 8 bit microprocessor containing a central processing unit, on-chip clock, read only memory, random access memory, input and output buffers and a timer. This microcomputer is a low performance low power microprocessor which operates at a clock rate of 32 KHz and average current consumption of 10-20 μA. The low performance microprocessor 10 may be employed to refresh the display in the device, maintain the time of day, control the device power supply, control the keyboard, and activate a high performance microprocessor as will be described in detail below.
High performance microprocessor 20 may be an RTX 2000 Real Time Microcontroller distributed by Harris Corporation (Melbourne, Florida ) . The RTX 2000 is a high performance 16 bit microcontroller with on chip timers, an interrupt controller .nd single cycle multiplier. The RTX 2000 employs single cycle instruction execution and may directly execute software written in FORTH, a high level language. The RTX 2000 may operate at variable clock speeds ranging from 0 up to 10 MHz, with power consumption being directly proportional to clock speed. For example, at a 1 MHz clock speed current consumption i*-? approximately 3.5 A while at 10 MHz, current consu. ption is approximately 35 mA. The RTX 2000 may be employed according to the invention for performing numerically intensive foreground tasks, such as bar code decoding and processing.
Still referring to Figure 1, system 1 also includes an Application Specific Integrated Circuit (ASIC) 13 which, as is well known to those having skill in the art, is a customized integrated circuit which integrates many functions on a single chip. ASIC 13 may include a display control 13a which is connected to display 14, a keyboard control 13b which is connected to keyboard IS, a Universal Asynchronous Receiver/Transmitter (UART) 13c, digital to analog converters 13d, and analog to digital converters 13e. A horn control 13f which controls horn 16 may also be included as may be a bar code reader control 13g which controls the operation of bar code scanner 17. According to the invention a variable speed clock control 13h is also included in ASIC 13. It will be understood by those having skill in the art that the individual functions included in ASIC 13 also be provided using discrete components.
Low performance microprocessor 10, high performance microprocessor 20 and ASIC 13 may be interconnected for data transmission via a bus 18, as is well known to those having skill in the art. Also connected to high performance microprocessor 20 is memory 23 which may include read/write memory and random access memory. Also connected to low performance microprocessor 10 is an on key 11 which is part of keyboard 15 and a reed switch 12 which is the trigger for controlling data transfer to or from a charging and communications unit (not shown) . Low performance microprocessor 10 also controls an adjustable switching regulator 19. The adjustable switching regulator 19 may be an MAX631 Fixed/Adjustable Output Step Up Switching Regulator distributed by Maxim (Sunnyvale, California) , which is a high efficiency step up DC-DC converter for use in low power high efficiency switching regulator applications. A battery supply 21, for example two nickel cadmium or lithium batteries may be connected to the adjustable switching regulator 19. A low power detector 22 may also be connected between the battery 21 and low performance microprocessor 10. A backup capacitor 24 may also be connected between switching regulator 19, memory 23, high performance microprocessor 20 and low performance microprocessor 10 for providing short term backup power, for example when battery 21 is replaced.
The adjustable switching regulator 19 provides power for memory 23, high performance microprocessor 20, low performance microprocessor 10 and ASIC 13. It should be noted that low performance microprocessor 10, ASIC 13 and memory 23 require a minimum of 2V power supply for operation, while high performance microprocessor 20 requires a minimum of 5V power supply. According to the invention, the low performance microprocessor controls adjustable switching regulator 19 to boost the 2.4V battery voltage to 5V when the high performance microprocessor 20 is activated by the low performance processor. It should also be noted that low performance microprocessor 10, ASIC 13 and memory 23 may be run directly from the 2.4V supplied by two nickel cadmium or lithium batteries, without requiring an intervening switching regulator, to thereby provide maximum transfer efficiency from battery 21 at low voltage levels. The switching regulator 19 may be activated only when high performance microprocessor 20 is activated. As may be seen from the block diagram of
Figure 1, low performance microprocessor may perform timekeeping and other background tasks and may continuously monitor for activation of the on key 11 or reed switch 12 or the need to perform another foreground task. When an appropriate foreground task is required, low performance microprocessor 10 may activate high performance microprocessor 20. It may also be seen that low performance microprocessor 10 and high performance microprocessor 20 may control the speed of variable speed clock 13h which governs the speed of high performance microprocessor 20.
Referring now to Figure 2 the sequence of operat ons for controlling microprocessor controlled device 1 according to the present invention will now be described. It will be recognized by those having skill in the art that the sequence of operations described in Figure 2 may be performed by low performance microprocessor 10 and high performance microprocessor 20 under control of a stored program which may reside in on-processor memory and/or in memory 23. Referring now to Figure 2A, when battery power is first applied to device 1 (Block 31) , processor 10 runs with a 2V power supply and a clock speed of 32 khz as long as power is available from the battery (Block 32) . At Block 33 processor 10 continually scans the on key 11 and the reed switch 12 and maintains time. Other background processing tasks may be performed as necessary.
When the on key 11 or reed switch 12 has been activated (Block 34) , microprocessor 10 checks whether the battery level is below a critical level (Block 35) . This test may be performed using low power detector 22. This test is performed to see whether there is sufficient battery power to activate high performance microprocessor 20. For a 2.4V system comprising two nickel cadmium batteries the test of Block 35 may be whether the battery voltage is 2.1V or less. If the battery voltage is below the critical level then at Block 36 processor 10 will not activate processor 20 until the batteries are replaced or recharged (Block 37) . Processor 10 will, however, continue to perform background processing (Block 33) .
If the battery level is above the critical level of Block 35, processor 10 activates the high voltage power supply using adjustable switching regulator 19, and activates processor 20 which runs at low system clock speed, for example 200 KHz (Block 38) . High performance processor 20 runs at low clock speed until it has been determined that a higher clock speed is required to process a specific foreground task.
At Block 39 a second test of battery voltage is performed by processor 20. For a typical two nickel cadmium battery pack this level might be 2.4V. This test is performed to see if there is enough power to run the high speed processor 20 at high speeds. If the voltage is near the critical level (Block 40) then processor 20 places a message on display 14 and then deactivates itself (Block 41) . Then, after a predetermined timeout period (for example ten seconds) has elapsed, processor 10 turns off the high voltage power supply which turns off the •-" _splay 14.
Referring now to Figure 2B, processing continues at block 43 in which processor 20 runs the main application program and timeoi ;est (Block 46) in a continuous loop unless an interrupt is received. A test is made c 3lock 46 to determine whether a predetermined tim (for example ten seconds) has been exceeded. If not, processing continues. If the predetermined time has been exceeded, processor 10 deactivates processor 20 (Block 47) .
Referring now to Figure 2C, when an interrupt is received (Block 45) , indicating that a foreground task is to be performed, the application software selects the appropriε clock speed for the interrupt routine about to be executed (Block 48) . According to the invention, each interrupt or other task to be performed is performed by a software subroutine. Associated with each software subroutine, preferably at the beginning thereof, is a clock speed code which indicates the appropriate clock speed for performing the task (Block 48) . This clock speed code is examined and an appropriate control code is t en sent from processor 20 to the variable speed system clock 13h in ASIC 13 (Block 49) . The variable speed clock then changes the speed of high performance microprocessor 20 (Block 50) . In one embodiment, three clock speeds may be employed, for example 200 KHz, 1.6 MHz and 10 MHz. A control code associated with each subroutine determines the appropriate clock speed. In another embodiment, a large number of clock speeds may be employed, so that in effect a continuously variable clock speed is provided. The processor 20 executes the software at the preselected speed (Block 51) . Referring to Block 52, when execution of the software routine is complete, processor 20 sends a control code to the variable speed clock to slow down to the slow speed. The timeout clock is reset (Block 53) and processing resumes at the point in the supervisory software loop where the interrupt occurred (Block 54) .
The above description illustrates that battery power may be conserved and system efficiency enhanced according to the invention, by providing a low power low performance processor 10 which is continuously on for processing background tasks. High performance processor 20 is only activated when a foreground task needs to be performed. Similarly, the adjustable switching regulator 19 is maintained at low voltage when the low performance processor 10 is activated and is only switched to high voltage when the high performance processor 20 is active. Finally, when the high performance processor 20 is active the software routine for the foreground processing task controls the clock speed of the task so that processing may be accomplished as quickly as necessary with minimal power consumption. It has been found that when employing the present invention a hand held bar code scanner may typically be used for the duration of an eight hour shift without requiring replacement or recharging of its batteries. A similar hand held bar code scanner which does not employ the present invention may only operate for 2 or 3 hours of use.
In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, tae scope of the invention being set forth in the following claims.

Claims

THAT WHICH IS CLAIMED IS
1. A multiprocessor system comprising: a first processor operating at a first speed for performing first tasks; and a second processor operating at a second speed which is greater than said first speed, said first processor including means for activating said second processor for performing second tasks at said second speed.
2. The multiprocessor system of Claim 1 wherein said first processor consumes a first amount of power and wherein said second processor consumes a second amount of power which is greater than said first amount of power, said means for activating said second processor thereby minimizing power consumption in said multiprocessor system.
3. The multiprocessor system of Claim 1 further including means for supplying power to said first and second processors.
4. The multiprocessor system of Claim 3 wherein said power supplying means includes a battery.
5. The multiprocessor system of Claim 1 wherein said multiprocessor system is portable.
6. The multiprocessor system of Claim 1 wherein said multiprocessor system is a portable bar code reader.
7. The multiprocessor system of Claim 1 wherein said first tasks comprise background tasks and wherein said second tasks comprise foreground tasks.
8. The multiprocessor system of Claim 7 wherein said background tasks ccr rise computationally simple tasks and nerein said foreground tasks comprise computationally intensive tasks.
9. The multiprocessor system of Claim 1 wherein said first processor includes means for determining that a second task is to be performed; said means for activating said se ond processor comprising means for activating -aid second processor in response to said determining means.
10. The multiprocessor system of Claim 1 wherein said first processor continues to operate at said first speed for performing said first tasks when said second processor operates at said second speed for performing said second tasks.
11. The multiprocessor system of Claim 3 wherein said power supplying means comprises an adjustable power supplying means.
12. The multiprocessor system of Claim 11 wherein said first processor operates at a first power supply voltage and wherein said second processor operates at a second power supply voltage greater than said first power supply voltage, and wherein said multiprocessor system further comprises power supply control means, connected to said means for activating said second processor, for causing said power supply to provide said second power supply voltage to said first and second processors when said second processor is active.
13. The multiprocessor system of Claim 12 wherein said power supply means includes a battery for supplying said first power supply voltage and a switching regulator connected to said battery for supplying said second power supply voltage.
14. The multiprocessor system of Claim 6 further comprising: a scanner connected to at least one of said first and second processors for reading and decoding bar codes under control of at least one of said first and second processors.
15. The multiprocessor system of Claim 6 further comprising: a keyboard connected to at least one of said first and second processors for accepting user inputs under control of at least one of said first and second processors.
16. The multiprocessor system of Claim 6 further comprising: a display connected to at least one of said first and sec. d processors for displaying user information under control of at least one of said first and second processors.
17. The multiprocessor system of Claim 6 further comprising: a scanner connected to at least one of said first and second proc-ssors for reading and decoding bar codes under control of at least one of said first and second processors; a keyboard connected to at least one of said first and second processors for accepting user inputs under control of at least one of said first and second processors; and a display connected to at least one of said first and second processors for displaying user information under control of at least one of said first and second processors.
18. The multiprocessor system of Claims 1 or 12 wherein -aid second speed comprises a plurality of second speeds greater than said first speed, and wherein said multiprocessor system further comprises: a variable speed clock, connected to said second processor, for operate, j said second processor at said pit. "ality of second speeds; and me is for controlling said variable speed clock to operate at said one of said second speeds.
19. The multiprocessor system of Claim 18 further comprising: a plurality of stored program routines for controlling said second processor to perform said second tasks, each of said routines having one of said plurality of second speeds associated therewith; and means for selecting one of said stored program routines to be performed; said means for^ controlling said variable speed clock being responsive to said means for selecting to thereby control said variable speed clock to operate at said one of said second speeds associated with the selected one of said stored program routines.
20. The multiprocessor system of Claim 19 wherein said one of said plurality of second speeds associated with a respective one of said plurality of routines comprises the lowest speed with which the associated one of said plurality of tasks may be performed.
21. A multiprocessor system comprising: a first processor operating at a first power supply level for performing a first task; a second processor operating at a second power supply level for performing a second task; power supplying means for selectively providing one of said first and second power supply levels to said first and second processors; and means for causing said power supplying means to provide said second power supply level to said first and second processors when said second task is performed.
22. The multiprocesscr system of Claim 21 wherein said first and second power supply levels comprise first and second power supply voltages, respectively.
23. The multiprocessor system of Claim 21 wherein said means for causing is included in said first processor.
24. The multiprocessor system of Claim 21 wherein said second power supply level is greater than said first power supply level.
25. The multiprocessor system of Claim 21 wherein said power s1 -lying means includes a battery.
26. The multiprocessor system of Claim 21 wherein said power supply means includes a battery for supplying said first power supply voltage and a switching regulator connected to said battery for supplying said second power supply voltage.
27. The multiprocessor system of Claim 21 wherein said multiprocessor system is portable.
28. The multiprocessor system of Claim 21 wherein said multiprocessor system is a portable bar code reader.
29. The multiprocessor system of Claim 21 wherein said first processor further comprises means for determining that said second task is to be performed; said determining means being connected to said means for causing to thereby activate said second processor when said second task is to be performed.
30. The multiprocessor system of Claim 21 further comprising: a scanner connected to at least one of said first and second processors for reading and decoding bar codes under control of at least one of said first and second processors.
31. The multiprocessor system of Claim 21 further comprising: a keyboard connected to at least one of said first and second processors for accepting user inputs under control of at least one of said first and second processors.
32. The multiprocessor system of Claim 21 further comprising: a display connected to at least one of said first and second processors for displaying user information under control of at least one of said first and second processors.
33. The multiprocessor system of Claim 21 further comprising: a scanner connected to at least one of said first and second processors for reading and decoding bar codes under control of at least one of said first and second processors; a keyboard connected to at least one of said first and second processors for accepting user inputs under control of at least one of said first and second processors; and a display connected to at least one of said first and second processors for displaying user information under control of at least one of said first and second processors.
34. The multiprocessor system of Claim 21 wherein said second speed comprises a plurality of second speeds greater than said first speed, wherein said second task comprises a plurality of second tasks, and wherein said multiprocessor system further comprises: a variable speed clock, connected to said second processor, for operating said second processor at said pli rality of second speeds; and means for controlling said variable speed clock to operate at one of said second speeds.
35. The multiprocessor system of Claim 34 further comprising: a plurality of stored program routines for controlling said second processor to perform said second tasks, each of said routines having one of said plurality of second speeds associated therewith; and means for selecting one of said stored program routines to be performed; said means for controlling said variable speed clock being responsive to said means for selecting to thereby control said variable speed clock to operate at said one of said second speeds associated with the selected one of said stored program routines.
36. The multiprocessor system of Claim 23 wherein said one of said plurality of second speeds associated with a respective one of said routines comprises the lowest speed with which the associated one of said plurality of tasks may be performed.
37. The multiprocessor system of Claim 21 wherein said first task comprises a background task and wherein said second task comprises a foreground task.
38. The multiprocessor system of Claim 37 wherein said background task is a computationally simple task and wherein said foreground task is a computationally intensive task.
39. The multiprocessor system of Claim 21 wherein said first processor continues to operate at said second power supply level for performing said first task while said second processor operates at said second power supply level for performing said second task.
40. A data proc _sing system comprising: a first stored program processor; a variable speed clock, connected to said first processor, for operating said first processor at a plurality of speeds; a plurality of stored program routines for controlling said first processor to perform a plurality of tasks, each of said routines having one of said plurality of speeds associated therewith; means for selecting one of said stored program routines to be performed; and means for controlling said variable speed clock to COerate said first processor at said one of said plurality of speeds associated with the selected one of said stored program routines.
41. The data processing system of Claim 40 wherein said one of said plurality of speeds associated with a respective one of said routines comprises the lowest speed with which the associated one of said plurality of tasks may be performed.
42. The data processing system of Claim 40 further comprising means for supplying power to said first processor.
43. The data processing system of Claim 40 further comprising battery powered means for supplying power to said first processor.
44. The data processing system of Claim 40 wherein said data processing system is portable.
45. The data processing system of Claim 40 wherein said data processing system is a portable bar code reader.
46. The data processing system of Claim 40 further comprising: a scanner connected to said first processor for reading and decoding bar codes under control of said first processor.
47. The data processing system of Claim 40 further comprising: a keyboard connected to said first processor for accepting user inputs under control of said first processor.
48. The data processing system of Claim 40 further comprising: a display connected to said first processor for displaying user information under control of said first processor.
49. The data processing system of Claim 40 further comprising: a scanner connected to said first processor for reading and decoding bar codes under control of said first processor; a keyboard connected to said first processor for accepting user inputs under control of said first processor; and a display connected to said first processor for displaying user information under control of said first processor.
50. The data processing system of Claim 40 further comprising a second processor, said second processor including means for activating said first processor for performing said plurality of tasks.
51. The data processing system of Claim 50 wherein said second processor operates at a second r.peed and wherein said plurality of speeds are greater than said second speed.
52. The data processing system of Claim 51 wherein said second processor consumes a second amount of power and wherein said first processor consumes a first amount of power which is directly proportional to the selected one of said plurality of speeds.
53. The data processing system of Claim 50 wherein said second processor operates at a second power supply voltage and said first processor- operates at a first power supply voltage; said data processing system further comprising an adjustable power supply for supplying said first and second power supply voltages to said first and second processors; said data processing system further comprising power supply control means, connected to said means for activating said first processor, for causing said power supply to provide said first power supply voltage to said first and second processors while said first processor is active.
54. The multiprocessor system of Claim 53 wherein said power supply means includes a battery for supplying said first power supply voltage and a switching regulator connected to said battery for supplying said second power supply voltage.
55. A multiprocessor system comprising: a first processor operating at a first speed at a first power supply voltage; a second processor operating at a selected one of a plurality of second speeds, at a second power supply voltage which is greater then said first power supply voltage; a power supplying means for selectively providing one of said first and second power supply levels to said first and second processors; means in said first processor for performing background tasks; means in said first processor for determining that a foreground task is to be performed; means, responsive to said determining means, for causing said power supply to provide said second power supply voltage to said first and second processors; means, responsive to said determining means, for activating said second processor to perform a foreground task; a plurality of stored program routines for controlling ε id second processor to perform foreground tasks, each of said routines having one of said plurality of second speeds associated therewith; means for selecting one of said stored program routines to be performed; and means for operating said second processor at said one of said plurality of speeds associated with the selected one of said stored program routines, whereby power consumption in said multiprocessor system is minimized.
56. The multiprocessor system of Claim 55 wherein said power supplying means includes a battery.
57. The multiprocessor system of Claim 55 wherein raid multiprocessor system is a portable multiprot .ssor system.
58. The multiprocessor system of Claim 55 wherein said multiprocessor system is a portable bar code reader.
59. The multiprocessor system of Claim 55 further comprising:
& scanner connected to at least one of said first and second pro; essors for reading and decoding bar ccies under control of at least one of said first and second processors.
60. The multiprocessor system of Claim 55 further comprising: a keyboard connected to at least one of said first and second processors for accepting user inputs under control of at least one of said first and second processors.
61. The multiprocessor of Claim 55 further comprising: a display connected to at least one of said first and second processors for displaying user information under control of at least one of said first and second processors.
62. The multiprocessor system of Claim 55 further comprising: a scanner connected to at least one of said first and second processors for reading and decoding bar codes under control of at least one of said first and second processors; a keyboard connected to at least one of said first and second processors for accepting user inputs under control of at least one of said, first and second processors; and a display connected to at least one of said first and second processors for displaying user information under control of at least one of said first and second processors.
63. The multiprocessor system of Claim 55 wherein said one of said plurality of second speeds associated with a respective one of said routines comprises the lowest speed with which the associate "1 one of said foreground tasks may be performed.
64. A method for controlling a multiprocessor system including a first processor operating at a first speed and a second processor operating at a second speed which is greater than said first speed, said method comprising the steps of: operating said first processor at said first speed; determining whether a task is to be performed at said second speed; and activating said secord processor if a task is to be performed at said seccnd speed.
65. The method of Claim 64 wherein sa:d multiprocessor system is a portable battery powe.2d multiprocessor system including an adjustable po*.er supplying means for supplying first and second power supply voltages to sa„d first and second processors, said first processor operating at said first voltage and sa'd second processor operating at said second voltage which is greater than said first voltage; and wherein said activating step is preceded by the step of: causing said power supplying means to provide said second voltage if a task is to be performed at said second speed.
66. The method of Claim wherein said causing step is preceded by the step of determining whether sufficient battery power is available to oper te said power supplying means at said second power supply voltage if a task is to be performed at said second speed.
67. The method of Claims 64 or 65 wherein said second speed comprises a plurality of second speeds, and wherein said activating step is followed by the step of: operating said second processor at one of said plurality of second speeds for performing the task.
68. The method of Claim 67 wherein the step of operating said second processor at one of said plurality of second speeds for performing the task comprises the steps of: identifying the task to be performed at said second speed; activating a software routine for performing the identified task; identifying one of said plurality of second speeds associated with the activated software routine; and operating said second processor at the identified one of said plurality of second speeds for performing the task.
69. The method of Claim 67 wherein the step of operating said second processor at one of said plurality of second speeds for performing the task is followed by the step of operating said second processor at a slow one of said plurality of second speeds after said task is performed.
70. The method of Claim 64 wherein said activating step is followed by the step of continuing to operate said first processor at said first speed.
71. A method for controlling a stored program processor, said stored program processor operating under control of a plurality of stored program routines for performing a plurality of tasks, said stored program processor being capable of operating at one of a plurality of speeds, said method comprising the steps of: selecting one of said plurality of stored program routines to be executed; identifying one of said plurality of speeds associated with the selected one of said plurality of stored program routines to be executed; causing said stored program processor to operate at the identified one of said plurality of speeds; and executing the selected one of said plurality of stored program routines.
72. The method of Claim 71 wherein said executing step is followed by the step of causing said stored program processor to operate at a slow one of said plurality of speeds after th<__ selected one of said plurality of stored program routines is executed.
73. A method for controlling a multiprocessor system including a first processor operating at a first speed at a first power supply voltage, and a second processor operating at one of a plurality of second speeds at a second power supply voltage which is greater than said first power supply voltage, and a power supplying means for selectively providing one of said first and second power supply voltages to said first and second processors, said method comprising the steps of: operating said first processor at said first speed; determining whether a task is to be performed by said second processor; causing said power supplying means to provide said second voltage if a task is to be performed by said second processor; activating said second processor if a task is to be performed by said second processor; identifying the task to be performed by said second processor; activating a software routine for performing the identified task; identifying one of said plurality of second speeds associated with the activated software routine; and operating said second processor at the identified one of said plurality of second speeds for performing the task.
74. The method of Claim 73 wherein said causing step is proceeded by the step of determining whether sufficient battery power is available to operate said power supplying means at said second power supply voltage if a task is to be performed by said second processor.
75. The method of Claim 73 wherein the step of operating said second processor is followed by the step of operating said second processor at a slow one of said plurality of second speeds after said task is performed.
PCT/US1990/003466 1989-06-23 1990-06-20 Power conservation in microprocessor controlled devices WO1991000565A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/370,648 US5142684A (en) 1989-06-23 1989-06-23 Power conservation in microprocessor controlled devices
US370,648 1995-09-21

Publications (2)

Publication Number Publication Date
WO1991000565A2 true WO1991000565A2 (en) 1991-01-10
WO1991000565A3 WO1991000565A3 (en) 1991-09-05

Family

ID=23460560

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1990/003466 WO1991000565A2 (en) 1989-06-23 1990-06-20 Power conservation in microprocessor controlled devices

Country Status (2)

Country Link
US (1) US5142684A (en)
WO (1) WO1991000565A2 (en)

Cited By (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0499178A1 (en) * 1991-02-08 1992-08-19 Nec Corporation System clock switching mechanism for microprocessor
EP0794481A2 (en) * 1996-03-06 1997-09-10 Mitsubishi Denki Kabushiki Kaisha Multitask processing system with variable clock rate for power saving
EP1459170A1 (en) * 2001-12-13 2004-09-22 Intel Corporation Computing system capable of reducing power consumption by distributing execution of instruction across multiple processors and method therefore
US11445232B2 (en) 2019-05-01 2022-09-13 Magic Leap, Inc. Content provisioning system and method
US11510027B2 (en) 2018-07-03 2022-11-22 Magic Leap, Inc. Systems and methods for virtual and augmented reality
US11514673B2 (en) 2019-07-26 2022-11-29 Magic Leap, Inc. Systems and methods for augmented reality
US11521296B2 (en) 2018-11-16 2022-12-06 Magic Leap, Inc. Image size triggered clarification to maintain image sharpness
US11579441B2 (en) 2018-07-02 2023-02-14 Magic Leap, Inc. Pixel intensity modulation using modifying gain values
US11598651B2 (en) 2018-07-24 2023-03-07 Magic Leap, Inc. Temperature dependent calibration of movement detection devices
US11609645B2 (en) 2018-08-03 2023-03-21 Magic Leap, Inc. Unfused pose-based drift correction of a fused pose of a totem in a user interaction system
US11624929B2 (en) 2018-07-24 2023-04-11 Magic Leap, Inc. Viewing device with dust seal integration
US11630507B2 (en) 2018-08-02 2023-04-18 Magic Leap, Inc. Viewing system with interpupillary distance compensation based on head motion
US11737832B2 (en) 2019-11-15 2023-08-29 Magic Leap, Inc. Viewing system for use in a surgical environment
US11756335B2 (en) 2015-02-26 2023-09-12 Magic Leap, Inc. Apparatus for a near-eye display
US11762623B2 (en) 2019-03-12 2023-09-19 Magic Leap, Inc. Registration of local content between first and second augmented reality viewers
US11762222B2 (en) 2017-12-20 2023-09-19 Magic Leap, Inc. Insert for augmented reality viewing device
US11776509B2 (en) 2018-03-15 2023-10-03 Magic Leap, Inc. Image correction due to deformation of components of a viewing device
US11790554B2 (en) 2016-12-29 2023-10-17 Magic Leap, Inc. Systems and methods for augmented reality
US11856479B2 (en) 2018-07-03 2023-12-26 Magic Leap, Inc. Systems and methods for virtual and augmented reality along a route with markers
US11874468B2 (en) 2016-12-30 2024-01-16 Magic Leap, Inc. Polychromatic light out-coupling apparatus, near-eye displays comprising the same, and method of out-coupling polychromatic light
US11885871B2 (en) 2018-05-31 2024-01-30 Magic Leap, Inc. Radar head pose localization
US11927759B2 (en) 2017-07-26 2024-03-12 Magic Leap, Inc. Exit pupil expander
US11953653B2 (en) 2017-12-10 2024-04-09 Magic Leap, Inc. Anti-reflective coatings on optical waveguides
US11960661B2 (en) 2023-02-07 2024-04-16 Magic Leap, Inc. Unfused pose-based drift correction of a fused pose of a totem in a user interaction system

Families Citing this family (183)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5222239A (en) * 1989-07-28 1993-06-22 Prof. Michael H. Davis Process and apparatus for reducing power usage microprocessor devices operating from stored energy sources
US5218704A (en) * 1989-10-30 1993-06-08 Texas Instruments Real-time power conservation for portable computers
US6158012A (en) * 1989-10-30 2000-12-05 Texas Instruments Incorporated Real-time power conservation and thermal management for computers
US5201059A (en) * 1989-11-13 1993-04-06 Chips And Technologies, Inc. Method for reducing power consumption includes comparing variance in number of time microprocessor tried to react input in predefined period to predefined variance
US5355501A (en) * 1990-03-09 1994-10-11 Novell, Inc. Idle detection system
EP0448350B1 (en) 1990-03-23 1996-12-27 Matsushita Electric Industrial Co., Ltd. Hand held data processing apparatus having reduced power consumption
US6795929B2 (en) * 1990-03-23 2004-09-21 Matsushita Electric Industrial Co., Ltd. Data processing apparatus
DE69127873T2 (en) * 1990-08-20 1998-04-16 Advanced Micro Devices Inc Memory access control
JPH04155417A (en) * 1990-10-19 1992-05-28 Toshiba Corp Device for extending function
US5560017A (en) * 1990-11-09 1996-09-24 Wang Laboratories, Inc. System with clock frequency controller responsive to interrupt independent of software routine and software loop repeatedly executing instruction to slow down system clock
US5239652A (en) * 1991-02-04 1993-08-24 Apple Computer, Inc. Arrangement for reducing computer power consumption by turning off the microprocessor when inactive
US5410711A (en) * 1991-02-14 1995-04-25 Dell Usa, L.P. Portable computer with BIOS-independent power management
US5566340A (en) * 1991-02-14 1996-10-15 Dell Usa L.P. Portable computer system with adaptive power control parameters
JPH04333119A (en) * 1991-05-09 1992-11-20 Matsushita Electric Ind Co Ltd Information processor
US5303171A (en) * 1992-04-03 1994-04-12 Zenith Data Systems Corporation System suspend on lid close and system resume on lid open
US5652890A (en) * 1991-05-17 1997-07-29 Vantus Technologies, Inc. Interrupt for a protected mode microprocessor which facilitates transparent entry to and exit from suspend mode
US5551033A (en) 1991-05-17 1996-08-27 Zenith Data Systems Corporation Apparatus for maintaining one interrupt mask register in conformity with another in a manner invisible to an executing program
US5394527A (en) * 1991-05-17 1995-02-28 Zenith Data Systems Corporation Method and apparatus facilitating use of a hard disk drive in a computer system having suspend/resume capability
WO1993012480A1 (en) 1991-12-17 1993-06-24 Compaq Computer Corporation Apparatus for reducing computer system power consumption
US5367638A (en) * 1991-12-23 1994-11-22 U.S. Philips Corporation Digital data processing circuit with control of data flow by control of the supply voltage
ES2206454T3 (en) * 1992-03-12 2004-05-16 Ipm International Sa METHOD AND DEVICE THAT ALLOWS THE REDUCTION OF POWER CONSUMPTION IN A PUBLIC TELEPHONE.
US6343363B1 (en) 1994-09-22 2002-01-29 National Semiconductor Corporation Method of invoking a low power mode in a computer system using a halt instruction
JP3058986B2 (en) * 1992-04-02 2000-07-04 ダイヤセミコンシステムズ株式会社 Computer system power saving controller
US6193422B1 (en) 1992-04-03 2001-02-27 Nec Corporation Implementation of idle mode in a suspend/resume microprocessor system
US5423045A (en) * 1992-04-15 1995-06-06 International Business Machines Corporation System for distributed power management in portable computers
WO1993025955A1 (en) * 1992-06-12 1993-12-23 Norand Corporation Portable data processor which selectively activates and deactivates internal modular units and application processor to conserve power
US5287292A (en) * 1992-10-16 1994-02-15 Picopower Technology, Inc. Heat regulator for integrated circuits
US5477476A (en) * 1993-07-14 1995-12-19 Bayview Technology Group, Inc. Power-conservation system for computer peripherals
US5587675A (en) * 1993-08-12 1996-12-24 At&T Global Information Solutions Company Multiclock controller
US6865684B2 (en) * 1993-12-13 2005-03-08 Hewlett-Packard Development Company, L.P. Utilization-based power management of a clocked device
US5535401A (en) * 1994-04-05 1996-07-09 International Business Machines Corporation Method and system of power and thermal management for a data processing system using object-oriented program design
US5532524A (en) * 1994-05-11 1996-07-02 Apple Computer, Inc. Distributed power regulation in a portable computer to optimize heat dissipation and maximize battery run-time for various power modes
TW282525B (en) * 1994-06-17 1996-08-01 Intel Corp
US7167993B1 (en) 1994-06-20 2007-01-23 Thomas C Douglass Thermal and power management for computer systems
US5752011A (en) 1994-06-20 1998-05-12 Thomas; C. Douglas Method and system for controlling a processor's clock frequency in accordance with the processor's temperature
US5490059A (en) * 1994-09-02 1996-02-06 Advanced Micro Devices, Inc. Heuristic clock speed optimizing mechanism and computer system employing the same
US5630142A (en) * 1994-09-07 1997-05-13 International Business Machines Corporation Multifunction power switch and feedback led for suspend systems
US6311287B1 (en) * 1994-10-11 2001-10-30 Compaq Computer Corporation Variable frequency clock control for microprocessor-based computer systems
US5659761A (en) * 1994-10-18 1997-08-19 Hand Held Products Data recognition apparatus and portable data reader having power management system
US5734585A (en) * 1994-11-07 1998-03-31 Norand Corporation Method and apparatus for sequencing power delivery in mixed supply computer systems
EP0727728A1 (en) * 1995-02-15 1996-08-21 International Business Machines Corporation Computer system power management
US5623647A (en) * 1995-03-07 1997-04-22 Intel Corporation Application specific clock throttling
US5838929A (en) * 1995-06-01 1998-11-17 Ast Research, Inc. Upgrade CPU module with integral power supply
US5752044A (en) * 1995-06-07 1998-05-12 International Business Machines Corporation Computer system having multi-level suspend timers to suspend from operation in attended and unattended modes
US5983357A (en) * 1995-07-28 1999-11-09 Compaq Computer Corporation Computer power management
US5996083A (en) * 1995-08-11 1999-11-30 Hewlett-Packard Company Microprocessor having software controllable power consumption
US5684392A (en) * 1995-10-03 1997-11-04 International Business Machines Corporation System for extending operating time of a battery-operated electronic device
US5822596A (en) * 1995-11-06 1998-10-13 International Business Machines Corporation Controlling power up using clock gating
US5746697A (en) * 1996-02-09 1998-05-05 Nellcor Puritan Bennett Incorporated Medical diagnostic apparatus with sleep mode
US5703790A (en) * 1996-02-27 1997-12-30 Hughes Electronics Series connection of multiple digital devices to a single power source
JP2933523B2 (en) * 1996-03-13 1999-08-16 日本電気エンジニアリング株式会社 Data transceiver
US5954819A (en) * 1996-05-17 1999-09-21 National Semiconductor Corporation Power conservation method and apparatus activated by detecting programmable signals indicative of system inactivity and excluding prefetched signals
US5923887A (en) * 1996-05-20 1999-07-13 Advanced Micro Devices, Inc. Interrupt request that defines resource usage
US5774704A (en) * 1996-07-29 1998-06-30 Silicon Graphics, Inc. Apparatus and method for dynamic central processing unit clock adjustment
US5828868A (en) * 1996-11-13 1998-10-27 Intel Corporation Processor having execution core sections operating at different clock rates
US6631454B1 (en) 1996-11-13 2003-10-07 Intel Corporation Processor and data cache with data storage unit and tag hit/miss logic operated at a first and second clock frequencies
US6256745B1 (en) 1998-06-05 2001-07-03 Intel Corporation Processor having execution core sections operating at different clock rates
US6604200B2 (en) * 1997-04-22 2003-08-05 Intel Corporation System and method for managing processing
JP3961619B2 (en) * 1997-06-03 2007-08-22 株式会社東芝 Computer system and processing speed control method thereof
US6411156B1 (en) 1997-06-20 2002-06-25 Intel Corporation Employing transistor body bias in controlling chip parameters
US6928559B1 (en) 1997-06-27 2005-08-09 Broadcom Corporation Battery powered device with dynamic power and performance management
US6954804B2 (en) * 1998-03-26 2005-10-11 Micro, Inc. Controller for portable electronic devices
US6675233B1 (en) 1998-03-26 2004-01-06 O2 Micro International Limited Audio controller for portable electronic devices
US6895448B2 (en) 1998-03-26 2005-05-17 O2 Micro, Inc. Low-power audio CD player for portable computers
US6105141A (en) * 1998-06-04 2000-08-15 Apple Computer, Inc. Method and apparatus for power management of an external cache of a computer system
US6141762A (en) * 1998-08-03 2000-10-31 Nicol; Christopher J. Power reduction in a multiprocessor digital signal processor based on processor load
US6240521B1 (en) * 1998-09-10 2001-05-29 International Business Machines Corp. Sleep mode transition between processors sharing an instruction set and an address space
US6298448B1 (en) 1998-12-21 2001-10-02 Siemens Information And Communication Networks, Inc. Apparatus and method for automatic CPU speed control based on application-specific criteria
US6484265B2 (en) * 1998-12-30 2002-11-19 Intel Corporation Software control of transistor body bias in controlling chip parameters
US6345362B1 (en) 1999-04-06 2002-02-05 International Business Machines Corporation Managing Vt for reduced power using a status table
US6477654B1 (en) 1999-04-06 2002-11-05 International Business Machines Corporation Managing VT for reduced power using power setting commands in the instruction stream
US6735708B2 (en) * 1999-10-08 2004-05-11 Dell Usa, L.P. Apparatus and method for a combination personal digital assistant and network portable device
US6501999B1 (en) 1999-12-22 2002-12-31 Intel Corporation Multi-processor mobile computer system having one processor integrated with a chipset
US6665802B1 (en) 2000-02-29 2003-12-16 Infineon Technologies North America Corp. Power management and control for a microcontroller
KR20010087876A (en) * 2000-03-09 2001-09-26 구자홍 CPU clock control method
US6721893B1 (en) 2000-06-12 2004-04-13 Advanced Micro Devices, Inc. System for suspending operation of a switching regulator circuit in a power supply if the temperature of the switching regulator is too high
US6968469B1 (en) 2000-06-16 2005-11-22 Transmeta Corporation System and method for preserving internal processor context when the processor is powered down and restoring the internal processor context when processor is restored
US6748545B1 (en) * 2000-07-24 2004-06-08 Advanced Micro Devices, Inc. System and method for selecting between a voltage specified by a processor and an alternate voltage to be supplied to the processor
US6450958B1 (en) * 2000-09-13 2002-09-17 Koninklikje Philips Electronics N.V. Portable ultrasound system with efficient shutdown and startup
US6527719B1 (en) 2000-09-13 2003-03-04 Koninklijke Philips Electronics N.V. Ultrasonic diagnostic imaging system with reduced power consumption and heat generation
US6440073B1 (en) * 2000-09-13 2002-08-27 Koninklijke Philips Electronics N.V. Ultrasonic diagnostic imaging system with automatic restart and response
US7260731B1 (en) 2000-10-23 2007-08-21 Transmeta Corporation Saving power when in or transitioning to a static mode of a processor
ATE492840T1 (en) * 2000-10-31 2011-01-15 Millennial Net Inc NETWORKED PROCESSING SYSTEM WITH OPTIMIZED PERFORMANCE EFFICIENCY
US7540424B2 (en) 2000-11-24 2009-06-02 Metrologic Instruments, Inc. Compact bar code symbol reading system employing a complex of coplanar illumination and imaging stations for omni-directional imaging of objects within a 3D imaging volume
US7594609B2 (en) 2003-11-13 2009-09-29 Metrologic Instruments, Inc. Automatic digital video image capture and processing system supporting image-processing based code symbol reading during a pass-through mode of system operation at a retail point of sale (POS) station
US7490774B2 (en) 2003-11-13 2009-02-17 Metrologic Instruments, Inc. Hand-supportable imaging based bar code symbol reader employing automatic light exposure measurement and illumination control subsystem integrated therein
US7464877B2 (en) 2003-11-13 2008-12-16 Metrologic Instruments, Inc. Digital imaging-based bar code symbol reading system employing image cropping pattern generator and automatic cropped image processor
US7128266B2 (en) 2003-11-13 2006-10-31 Metrologic Instruments. Inc. Hand-supportable digital imaging-based bar code symbol reader supporting narrow-area and wide-area modes of illumination and image capture
US7708205B2 (en) 2003-11-13 2010-05-04 Metrologic Instruments, Inc. Digital image capture and processing system employing multi-layer software-based system architecture permitting modification and/or extension of system features and functions by way of third party code plug-ins
US7607581B2 (en) 2003-11-13 2009-10-27 Metrologic Instruments, Inc. Digital imaging-based code symbol reading system permitting modification of system features and functionalities
US8042740B2 (en) 2000-11-24 2011-10-25 Metrologic Instruments, Inc. Method of reading bar code symbols on objects at a point-of-sale station by passing said objects through a complex of stationary coplanar illumination and imaging planes projected into a 3D imaging volume
US6836850B2 (en) * 2000-11-30 2004-12-28 Intel Corporation Portable system arrangements having dual high-level-/low-level processor modes
US7522966B2 (en) * 2000-12-01 2009-04-21 O2Micro International Limited Low power digital audio decoding/playing system for computing devices
US7522964B2 (en) 2000-12-01 2009-04-21 O2Micro International Limited Low power digital audio decoding/playing system for computing devices
US7522965B2 (en) 2000-12-01 2009-04-21 O2Micro International Limited Low power digital audio decoding/playing system for computing devices
US7890741B2 (en) * 2000-12-01 2011-02-15 O2Micro International Limited Low power digital audio decoding/playing system for computing devices
US7526349B2 (en) * 2000-12-01 2009-04-28 O2Micro International Limited Low power digital audio decoding/playing system for computing devices
US7818443B2 (en) * 2000-12-01 2010-10-19 O2Micro International Ltd. Low power digital audio decoding/playing system for computing devices
JP2002196845A (en) * 2000-12-27 2002-07-12 Matsushita Electric Ind Co Ltd Method for controlling microcomputer
US7725748B1 (en) 2000-12-29 2010-05-25 Intel Corporation Low power subsystem for portable computers
US6986066B2 (en) 2001-01-05 2006-01-10 International Business Machines Corporation Computer system having low energy consumption
US20020108064A1 (en) * 2001-02-07 2002-08-08 Patrick Nunally System and method for optimizing power/performance in network-centric microprocessor-controlled devices
US6895520B1 (en) 2001-03-02 2005-05-17 Advanced Micro Devices, Inc. Performance and power optimization via block oriented performance measurement and control
US20030153353A1 (en) * 2001-03-16 2003-08-14 Cupps Bryan T. Novel personal electronics device with simultaneous multi-processor operation
US7184003B2 (en) * 2001-03-16 2007-02-27 Dualcor Technologies, Inc. Personal electronics device with display switching
US7231531B2 (en) * 2001-03-16 2007-06-12 Dualcor Technologies, Inc. Personal electronics device with a dual core processor
US20030100340A1 (en) * 2001-03-16 2003-05-29 Cupps Bryan T. Novel personal electronics device with thermal management
US20030153354A1 (en) * 2001-03-16 2003-08-14 Cupps Bryan T. Novel personal electronics device with keypad application
US20030159026A1 (en) * 2001-03-16 2003-08-21 Cupps Bryan T. Novel personal electronics device with appliance drive features
US20030163601A1 (en) * 2001-03-16 2003-08-28 Cupps Bryan T. Novel personal electronics device with common application platform
US20020173344A1 (en) * 2001-03-16 2002-11-21 Cupps Bryan T. Novel personal electronics device
US7216242B2 (en) 2001-03-16 2007-05-08 Dualcor Technologies, Inc. Personal electronics device with appliance drive features
US20020166075A1 (en) * 2001-05-04 2002-11-07 Sanjay Agarwal Low power interface between a control processor and a digital signal processing coprocessor
US6920573B2 (en) * 2001-05-23 2005-07-19 Smartpower Corporation Energy-conserving apparatus and operating system having multiple operating functions stored in keep-alive memory
DE10127423B4 (en) * 2001-06-06 2005-10-06 Infineon Technologies Ag Electronic circuit with power control
WO2003014902A1 (en) * 2001-08-10 2003-02-20 Shakti Systems, Inc. Distributed power supply architecture
US6820018B2 (en) * 2001-08-27 2004-11-16 Mitsumi Electric Co., Ltd. Power control circuit
KR100883067B1 (en) * 2001-09-14 2009-02-10 엘지전자 주식회사 Method for controling a device performance for each application programs, and software drive system
BR0213139A (en) * 2001-10-04 2004-08-10 Elan Pharm Inc Compound, method of treating or preventing disease and preparing a compound, use of a compound and pharmaceutical composition
US7111179B1 (en) 2001-10-11 2006-09-19 In-Hand Electronics, Inc. Method and apparatus for optimizing performance and battery life of electronic devices based on system and application parameters
WO2003041249A1 (en) * 2001-11-05 2003-05-15 Shakti Systems, Inc. Dc-dc converter with resonant gate drive
US6791298B2 (en) * 2001-11-05 2004-09-14 Shakti Systems, Inc. Monolithic battery charging device
FR2833448B1 (en) * 2001-12-06 2004-02-27 Cit Alcatel OPTIMIZATION OF THE CONSUMPTION OF A MULTIMEDIA AUXILIARY CHIP IN A MOBILE RADIO COMMUNICATION TERMINAL
US7076674B2 (en) * 2001-12-19 2006-07-11 Hewlett-Packard Development Company L.P. Portable computer having dual clock mode
JP3685401B2 (en) * 2001-12-26 2005-08-17 インターナショナル・ビジネス・マシーンズ・コーポレーション CPU control method, computer apparatus and CPU using the same, and program
WO2003083693A1 (en) * 2002-04-03 2003-10-09 Fujitsu Limited Task scheduler in distributed processing system
EP1351117A1 (en) * 2002-04-03 2003-10-08 Hewlett-Packard Company Data processing system and method
AU2003281382A1 (en) * 2002-05-28 2004-01-23 Sendo International Limited A processor system and method for controlling signal timing therein
US7254812B1 (en) * 2002-05-31 2007-08-07 Advanced Micro Devices, Inc. Multi-processor task scheduling
US7100060B2 (en) * 2002-06-26 2006-08-29 Intel Corporation Techniques for utilization of asymmetric secondary processing resources
US6924667B2 (en) 2002-07-19 2005-08-02 O2Micro International Limited Level shifting and level-shifting amplifier circuits
US7162279B2 (en) * 2002-12-20 2007-01-09 Intel Corporation Portable communication device having dynamic power management control and method therefor
KR20040084832A (en) * 2003-03-26 2004-10-06 마츠시타 덴끼 산교 가부시키가이샤 Information processing apparatus, electronic device, method for controlling a clock of the information processing apparatus, program for controlling a clock, and program product for the same
US20050046400A1 (en) * 2003-05-21 2005-03-03 Efraim Rotem Controlling operation of a voltage supply according to the activity of a multi-core integrated circuit component or of multiple IC components
JP4196333B2 (en) * 2003-05-27 2008-12-17 日本電気株式会社 Parallel processing system and parallel processing program
US20050002050A1 (en) * 2003-07-01 2005-01-06 Kabushiki Kaisha Toshiba Image processing apparatus
JP4062441B2 (en) * 2003-07-18 2008-03-19 日本電気株式会社 Parallel processing system and parallel processing program
JP3958720B2 (en) * 2003-07-22 2007-08-15 沖電気工業株式会社 Clock control circuit and clock control method
JP2005078518A (en) * 2003-09-02 2005-03-24 Renesas Technology Corp Microcontroller unit and compiler thereof
US7841533B2 (en) 2003-11-13 2010-11-30 Metrologic Instruments, Inc. Method of capturing and processing digital images of an object within the field of view (FOV) of a hand-supportable digitial image capture and processing system
JP4059838B2 (en) * 2003-11-14 2008-03-12 ソニー株式会社 Battery pack, battery protection processing device, and control method for battery protection processing device
EP1692622B1 (en) * 2003-12-02 2008-05-21 Research In Motion Limited Inter-processor parameter management in a multiple-processor wireless mobile communication device operating on a processor specific communication network
US20050132239A1 (en) * 2003-12-16 2005-06-16 Athas William C. Almost-symmetric multiprocessor that supports high-performance and energy-efficient execution
JP4171910B2 (en) * 2004-03-17 2008-10-29 日本電気株式会社 Parallel processing system and parallel processing program
US7809932B1 (en) * 2004-03-22 2010-10-05 Altera Corporation Methods and apparatus for adapting pipeline stage latency based on instruction type
US7152171B2 (en) * 2004-04-28 2006-12-19 Microsoft Corporation Task-oriented processing as an auxiliary to primary computing environments
US20060064606A1 (en) * 2004-09-21 2006-03-23 International Business Machines Corporation A method and apparatus for controlling power consumption in an integrated circuit
KR101128251B1 (en) * 2004-10-11 2012-03-26 엘지전자 주식회사 Apparatus and method for controling power saving by devices of executed program
US7472301B2 (en) * 2005-05-27 2008-12-30 Codman Neuro Sciences Sárl Circuitry for optimization of power consumption in a system employing multiple electronic components, one of which is always powered on
AU2015205867A1 (en) * 2005-05-27 2015-09-17 Codman Neuro Sciences Sarl Circuitry for optimization of power consumption in a system employing multiple electronic components, one of which is always powered on
KR101177125B1 (en) * 2005-06-11 2012-08-24 엘지전자 주식회사 Method and apparatus for implementing hybrid power management mode in a multi-core processor
JP4483720B2 (en) * 2005-06-23 2010-06-16 株式会社デンソー Electronic control unit
US20060294401A1 (en) * 2005-06-24 2006-12-28 Dell Products L.P. Power management of multiple processors
US7461275B2 (en) * 2005-09-30 2008-12-02 Intel Corporation Dynamic core swapping
US7539888B2 (en) * 2006-03-31 2009-05-26 Freescale Semiconductor, Inc. Message buffer for a receiver apparatus on a communications bus
CN100525231C (en) * 2006-09-06 2009-08-05 中国移动通信集团公司 Energy-saving information household appliance network and energy-saving control method
US7844838B2 (en) * 2006-10-30 2010-11-30 Hewlett-Packard Development Company, L.P. Inter-die power manager and power management method
US7962775B1 (en) * 2007-01-10 2011-06-14 Marvell International Ltd. Methods and apparatus for power mode control for PDA with separate communications and applications processors
US7831850B2 (en) * 2007-03-29 2010-11-09 Microsoft Corporation Hybrid operating systems for battery powered computing systems
US7856562B2 (en) * 2007-05-02 2010-12-21 Advanced Micro Devices, Inc. Selective deactivation of processor cores in multiple processor core systems
US8627116B2 (en) * 2007-08-07 2014-01-07 Maxim Integrated Products, Inc. Power conservation in an intrusion detection system
TWI358635B (en) * 2008-02-26 2012-02-21 Mstar Semiconductor Inc Power managing method for a multi-microprocessor s
USD654499S1 (en) 2009-06-09 2012-02-21 Data Ltd., Inc. Tablet computer
USD635568S1 (en) 2009-06-09 2011-04-05 Data Ltd., Inc. Tablet computer
US8862786B2 (en) * 2009-08-31 2014-10-14 International Business Machines Corporation Program execution with improved power efficiency
USD638834S1 (en) 2009-10-05 2011-05-31 Data Ltd., Inc. Tablet computer
US8972702B2 (en) * 2009-11-30 2015-03-03 Intenational Business Machines Corporation Systems and methods for power management in a high performance computing (HPC) cluster
WO2011117669A1 (en) * 2010-03-22 2011-09-29 Freescale Semiconductor, Inc. Integrated circuit device, signal processing system, electronic device and method therefor
US8489904B2 (en) * 2010-03-25 2013-07-16 International Business Machines Corporation Allocating computing system power levels responsive to service level agreements
US8484495B2 (en) * 2010-03-25 2013-07-09 International Business Machines Corporation Power management in a multi-processor computer system
US8700934B2 (en) * 2010-07-27 2014-04-15 Blackberry Limited System and method for dynamically configuring processing speeds in a wireless mobile telecommunications device
US8756442B2 (en) 2010-12-16 2014-06-17 Advanced Micro Devices, Inc. System for processor power limit management
JP5636276B2 (en) * 2010-12-27 2014-12-03 ルネサスエレクトロニクス株式会社 Semiconductor device
USD690296S1 (en) 2011-02-01 2013-09-24 Data Ltd., Inc. Tablet computer
KR101744356B1 (en) * 2011-03-17 2017-06-08 삼성전자주식회사 Device and method for reducing current consuming in wireless terminal
KR101797523B1 (en) * 2011-05-23 2017-11-15 삼성전자 주식회사 The display apparatus and control method thereof
KR102006470B1 (en) 2011-12-28 2019-08-02 삼성전자 주식회사 Method and apparatus for multi-tasking in a user device
US9223383B2 (en) 2012-12-21 2015-12-29 Advanced Micro Devices, Inc. Guardband reduction for multi-core data processor
US9360918B2 (en) 2012-12-21 2016-06-07 Advanced Micro Devices, Inc. Power control for multi-core data processor
US9377843B2 (en) * 2013-05-07 2016-06-28 Broadcom Corporation Systems and methods for managing current consumption by an electronic device
US20150247933A1 (en) * 2013-06-27 2015-09-03 Galaxray, LLC Spectrometric personal radiation detector - radioisotope identifier
US9554239B2 (en) 2015-04-21 2017-01-24 Apple Inc. Opportunistic offloading of tasks between nearby computing devices
US10372479B2 (en) * 2017-08-09 2019-08-06 International Business Machines Corporation Scheduling framework for tightly coupled jobs

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4101072A (en) * 1976-10-21 1978-07-18 The Singer Company Data-gathering device for scanning data having a variable amplitude modulation and signal to noise ratio
GB2134676A (en) * 1983-01-24 1984-08-15 Sharp Kk Control of multi-processor system
WO1985002275A1 (en) * 1983-11-07 1985-05-23 Motorola, Inc. Synthesized clock microcomputer with power saving
DE3433970A1 (en) * 1983-11-10 1986-03-27 Udo Eckhardt Portable data acquisition device with reader
EP0178642A2 (en) * 1984-10-18 1986-04-23 Unisys Corporation Power control network for multiple digital modules

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4123794A (en) * 1974-02-15 1978-10-31 Tokyo Shibaura Electric Co., Limited Multi-computer system
US3941989A (en) * 1974-12-13 1976-03-02 Mos Technology, Inc. Reducing power consumption in calculators
DE2555963C2 (en) * 1975-12-12 1982-10-28 Ibm Deutschland Gmbh, 7000 Stuttgart Function modification facility
US4143417A (en) * 1976-10-21 1979-03-06 The Singer Company Portable data-gathering apparatus formed by modular components having operate-standby modes
DE2911909C2 (en) * 1978-03-29 1984-03-15 British Broadcasting Corp., London Digital data processing device
US4203153A (en) * 1978-04-12 1980-05-13 Diebold, Incorporated Circuit for reducing power consumption in battery operated microprocessor based systems
US4366540A (en) * 1978-10-23 1982-12-28 International Business Machines Corporation Cycle control for a microprocessor with multi-speed control stores
US4254475A (en) * 1979-03-12 1981-03-03 Raytheon Company Microprocessor having dual frequency clock
DE2911998C2 (en) * 1979-03-27 1985-11-07 Robert Bosch Gmbh, 7000 Stuttgart Power supply for a microprocessor that controls electrical devices, in particular a motor vehicle
US4317181A (en) * 1979-12-26 1982-02-23 Texas Instruments Incorporated Four mode microcomputer power save operation
US4673805A (en) * 1982-01-25 1987-06-16 Symbol Technologies, Inc. Narrow-bodied, single- and twin-windowed portable scanning head for reading bar code symbols
DE3302940A1 (en) * 1983-01-28 1984-08-02 Siemens AG, 1000 Berlin und 8000 München PROGRAMMABLE CONTROL WITH WORD AND BIT PROCESSOR
US4677433A (en) * 1983-02-16 1987-06-30 Daisy Systems Corporation Two-speed clock scheme for co-processors
US4893271A (en) * 1983-11-07 1990-01-09 Motorola, Inc. Synthesized clock microcomputer with power saving
US4819164A (en) * 1983-12-12 1989-04-04 Texas Instruments Incorporated Variable frequency microprocessor clock generator
US4631702A (en) * 1984-02-28 1986-12-23 Canadian Patents and Deveopment Limited--Societe Canadienne des Brevets et d'Exploitation Limitee Computer speed control
US4670837A (en) * 1984-06-25 1987-06-02 American Telephone And Telegraph Company Electrical system having variable-frequency clock
US4696019A (en) * 1984-09-19 1987-09-22 United Technologies Corporation Multi-channel clock synchronizer
US4851987A (en) * 1986-01-17 1989-07-25 International Business Machines Corporation System for reducing processor power consumption by stopping processor clock supply if a desired event does not occur
JPS63131616A (en) * 1986-11-20 1988-06-03 Mitsubishi Electric Corp Programmable clock frequency divider
US4916441A (en) * 1988-09-19 1990-04-10 Clinicom Incorporated Portable handheld terminal

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4101072A (en) * 1976-10-21 1978-07-18 The Singer Company Data-gathering device for scanning data having a variable amplitude modulation and signal to noise ratio
GB2134676A (en) * 1983-01-24 1984-08-15 Sharp Kk Control of multi-processor system
WO1985002275A1 (en) * 1983-11-07 1985-05-23 Motorola, Inc. Synthesized clock microcomputer with power saving
DE3433970A1 (en) * 1983-11-10 1986-03-27 Udo Eckhardt Portable data acquisition device with reader
EP0178642A2 (en) * 1984-10-18 1986-04-23 Unisys Corporation Power control network for multiple digital modules

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Electro/81 Conference Record, vol. 6, 7-9 April 1981, (New York, NY, US), B. Huston: "Watch chip for an MPU -- real-time clock peripheral", pages 1-8 *
IBM Technical Disclosure Bulletin, vol. 29, no. 6, November 1986, (New York, NY, US), "Method for warning users of a low battery condition on a battery-powered computer", pages 2641-2643 *

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0499178A1 (en) * 1991-02-08 1992-08-19 Nec Corporation System clock switching mechanism for microprocessor
EP0794481A2 (en) * 1996-03-06 1997-09-10 Mitsubishi Denki Kabushiki Kaisha Multitask processing system with variable clock rate for power saving
EP0794481A3 (en) * 1996-03-06 1999-04-07 Mitsubishi Denki Kabushiki Kaisha Multitask processing system with variable clock rate for power saving
EP1459170A1 (en) * 2001-12-13 2004-09-22 Intel Corporation Computing system capable of reducing power consumption by distributing execution of instruction across multiple processors and method therefore
US11756335B2 (en) 2015-02-26 2023-09-12 Magic Leap, Inc. Apparatus for a near-eye display
US11790554B2 (en) 2016-12-29 2023-10-17 Magic Leap, Inc. Systems and methods for augmented reality
US11874468B2 (en) 2016-12-30 2024-01-16 Magic Leap, Inc. Polychromatic light out-coupling apparatus, near-eye displays comprising the same, and method of out-coupling polychromatic light
US11927759B2 (en) 2017-07-26 2024-03-12 Magic Leap, Inc. Exit pupil expander
US11953653B2 (en) 2017-12-10 2024-04-09 Magic Leap, Inc. Anti-reflective coatings on optical waveguides
US11762222B2 (en) 2017-12-20 2023-09-19 Magic Leap, Inc. Insert for augmented reality viewing device
US11908434B2 (en) 2018-03-15 2024-02-20 Magic Leap, Inc. Image correction due to deformation of components of a viewing device
US11776509B2 (en) 2018-03-15 2023-10-03 Magic Leap, Inc. Image correction due to deformation of components of a viewing device
US11885871B2 (en) 2018-05-31 2024-01-30 Magic Leap, Inc. Radar head pose localization
US11579441B2 (en) 2018-07-02 2023-02-14 Magic Leap, Inc. Pixel intensity modulation using modifying gain values
US11510027B2 (en) 2018-07-03 2022-11-22 Magic Leap, Inc. Systems and methods for virtual and augmented reality
US11856479B2 (en) 2018-07-03 2023-12-26 Magic Leap, Inc. Systems and methods for virtual and augmented reality along a route with markers
US11598651B2 (en) 2018-07-24 2023-03-07 Magic Leap, Inc. Temperature dependent calibration of movement detection devices
US11624929B2 (en) 2018-07-24 2023-04-11 Magic Leap, Inc. Viewing device with dust seal integration
US11630507B2 (en) 2018-08-02 2023-04-18 Magic Leap, Inc. Viewing system with interpupillary distance compensation based on head motion
US11609645B2 (en) 2018-08-03 2023-03-21 Magic Leap, Inc. Unfused pose-based drift correction of a fused pose of a totem in a user interaction system
US11521296B2 (en) 2018-11-16 2022-12-06 Magic Leap, Inc. Image size triggered clarification to maintain image sharpness
US11762623B2 (en) 2019-03-12 2023-09-19 Magic Leap, Inc. Registration of local content between first and second augmented reality viewers
US11445232B2 (en) 2019-05-01 2022-09-13 Magic Leap, Inc. Content provisioning system and method
US11514673B2 (en) 2019-07-26 2022-11-29 Magic Leap, Inc. Systems and methods for augmented reality
US11737832B2 (en) 2019-11-15 2023-08-29 Magic Leap, Inc. Viewing system for use in a surgical environment
US11960661B2 (en) 2023-02-07 2024-04-16 Magic Leap, Inc. Unfused pose-based drift correction of a fused pose of a totem in a user interaction system

Also Published As

Publication number Publication date
WO1991000565A3 (en) 1991-09-05
US5142684A (en) 1992-08-25

Similar Documents

Publication Publication Date Title
US5142684A (en) Power conservation in microprocessor controlled devices
US5870613A (en) Power mangement system for a computer
US5450003A (en) Power-supply control system for a portable data processor and method for driving the same
US5163153A (en) Low-power, standby mode computer
EP0819999B1 (en) Dynamic hibernation time in a computer system
US5241680A (en) Low-power, standby mode computer
US5598567A (en) Apparatus for controlling power supply in a computer system by introducing delays before activation and deactivation of power
US5898880A (en) Power saving apparatus for hard disk drive and method of controlling the same
US5230074A (en) Battery operated computer power management system
CA2187501C (en) Process and apparatus for generating power management events in a computer system
EP1988443B1 (en) Suspend induced by AC power disturbance
US6467042B1 (en) Method and/or apparatus for lowering power consumption in a peripheral device
WO1995012158A1 (en) Timer-controlled computer system shutdown and startup
US5148380A (en) Method and apparatus for conserving power in a data processing system
JPH04333119A (en) Information processor
US7228445B2 (en) Clock frequency control method and electronic apparatus
US5758103A (en) Circuit for replacing a peripheral device of a computer system and method therefor
US20230188139A1 (en) Ultra-low power adaptively reconfigurable system
US6477655B1 (en) System and method to set PME—status bit and wake up the system, and selectively load device driver by searching who set the bit without requiring clock
WO1997034218A1 (en) Method and apparatus for power management using power control
US20030041234A1 (en) Reset function incorporated microcomputer
KR950009649A (en) Floppy disk controller to detect changes in floppy disk driver status in standby mode
US5325039A (en) Method and apparatus for controlling power supply
JPH10143274A (en) Clock controller for cpu
KR102536104B1 (en) Computer energy saving system based on power usage pattern identification

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): JP

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH DE DK ES FR GB IT LU NL SE

AK Designated states

Kind code of ref document: A3

Designated state(s): JP

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): AT BE CH DE DK ES FR GB IT LU NL SE