WO1991002258A1 - Method and package for integrated circuit identification and testing - Google Patents

Method and package for integrated circuit identification and testing Download PDF

Info

Publication number
WO1991002258A1
WO1991002258A1 PCT/US1990/004296 US9004296W WO9102258A1 WO 1991002258 A1 WO1991002258 A1 WO 1991002258A1 US 9004296 W US9004296 W US 9004296W WO 9102258 A1 WO9102258 A1 WO 9102258A1
Authority
WO
WIPO (PCT)
Prior art keywords
rom
electronic device
output
substitutesheet
testing
Prior art date
Application number
PCT/US1990/004296
Other languages
French (fr)
Inventor
Richard A. Meany
Raymond J. Speer
Original Assignee
Analog Devices, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Analog Devices, Inc. filed Critical Analog Devices, Inc.
Publication of WO1991002258A1 publication Critical patent/WO1991002258A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/006—Identification
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns

Definitions

  • the present invention relates generally to the field of integrated circuit testing in general and, for a specific example, to the field of testing the temperature coefficients of integrated circuit voltage references.
  • test results are used to separate good devices from bad devices, to establish component grading, and to establish a test record for devices required to carry such a pedigree ( e . g . , for certain military, space and atomic energy applications)
  • SUBSTITUTESHEET As an example, consider a typical voltage reference product (e.g., for a digital-to-analog converter) whose temperature coefficient must be determined during the test process.
  • One prior art method for testing electronic devices such as voltage references is to test a number of such references in sequence, in an assembly line-fashion.
  • the references are arranged on or supplied via an apparatus which sequentially moves each of the references near an automatic tester which tests the references one at a time, performing all necessary tests on one reference before advancing to test the next reference.
  • the measurements may be stored in the tester or in a computer, where they may be filed under the sequential number of the reference. For instance, the first reference tested is assigned the identification number 1, the second reference tested is assigned the identification number 2, and so forth, for all of the references.
  • the output voltage of each reference is measured at a number of different temperatures, and these temperatures are also stored.
  • the temperature coefficients for the references can then be calculated. This temperature coefficient is then compared to a specified value, to determine whether the reference has passed the test, or to a group of values, to grade the voltage reference by quality.
  • Another prior art method for testing electronic devices for temperature coefficient is to arrange all of the DUTs on a large board. The board with the DUTs is then placed into an environmental chamber, where the testing takes place. The main problem with this method is that it is expensive to use and maintain an environmental chamber to perform the testing.
  • test jig is brought to a selected test temperature, check each DUT at that, temperature, in sequence, recording the test data for each DUT as it is measured. Then, the jig temperature is changed to the next test temperature and all the DUT's are tested as before, at this new temperature. The assumption is made that the DUT's remained in the same sequence, so the second round of test data will be recorded for, the correct DUT's. This sequence is repeated as many times as there are test temperatures. On ⁇ e the data is all available, the temperature coefficients are calculated.
  • a solution to these problems is one that allows the tester to individually recognize each DUT.
  • Each DUT is given a unique identification number and the test dats can be indexed according to the DUT.
  • There have been several methods utilized in the past for associating the identification number with the DUT such as affixing or printing a bar code on the underside of the DUT package and mounting in the test jig an optical reader for reading the bar code.
  • the problem with such methods is that they add considerable expense.
  • a bar code identification system requires either manual labor or additional apparatus for attaching or printing a bar code on the DUT, and equipment (i.e., an optical scanning head) to read the code.
  • SUBSTITUTESHEET Another object of the invention is to provide a method for identifying integrated circuit devices which are to be tested at varying temperatures, to allow flexibility in test sequencing.
  • Still another object of the invention is to provide an integrated circuit structure with means facilitating identification of a DUT during the testing process.
  • ROM read-only memory
  • This code identifies the reference device in which it is housed.
  • the device identification code is written to the ROM when the device wafer is initially probed, immediately after manufacture. Therefore, when a tester tests the DUT, it reads the ROM and indexes the voltage measurement with the identification code. The measurements are therefore all correlated with each other and with the DUT.
  • the ROM is programmable once only. That is, a laser beam programs the ROM cells by cutting selected thin film
  • This ROM is therefore a so-called WORM (write once read many) device, a specific specie of programmable ROM (or PROM).
  • FIG. 1 is a top view of a diagrammatic illustration of an integrated circuit device package having an identification ROM, according to the present invention
  • FIG. 2 is a block diagram of a first exemplary embodiment of a ROM according to the present invention, utilizing a serial interface for reading the ROM output;
  • FIG. 3 is a schematic circuit diagram of one cell of the exemplary ROM of FIG. 2;
  • FIG. 4 is a schematic circuit diagram of a second exemplary embodiment of an identification ROM utilizing a parallel interface.
  • the present invention utilizes, in an integrated circuit device, a memory device which can store an
  • SUBSTITUTESHEET identification code which can be read by a tester.
  • the identification code is used to identify the electronic device during the testing process.
  • the identification code is used to identify a voltage reference circuit which supplies a reference voltage.
  • the identification code is, in a preferred embodiment, stored in a ROM.
  • FIG. 1 illustrates the concept of the present invention.
  • the ROM 10 is housed on the same integrated circuit substrate 12 as the DUT (device under test) 14, which may, for example, be a voltage reference. However, in a multi-chip package, the ROM and DUT may be on different substrates.
  • the ROM 10 may be accessed via dedicated conductors 16 or via a bus 18 associated with the DUT.
  • FIG. 2 shows a first embodiment of the ROM 10, wherein, for purposes of convenience only, and not to limit the scope of the present invention, the ROM is depicted .as utilizing a serial output interface.
  • FIG. 2 A block diagram of an exemplary 16-bit ROM 10 is shown in FIG. 2.
  • the ROM 10 contains a number of SPROM (Static Programmable Read Only Memory) cells 22(A-P) .
  • SPROM Static Programmable Read Only Memory
  • Each SPROM cell provides a 1-bit output which represents one digit of the binary word identifying the device. Therefore, in an embodiment in which the identification code is a 16-bit word, there are 16 SPROMs which constitute the ROM.
  • Each SPROM has two
  • SUBSTITUTESHEET inputs labeled 24(A-P) and 26(A-P), connected to appropriate leads of, for example, bus 28.
  • the SPROM outputs are all connected to a common parallel bus 30.
  • a Johnson counter can select appropriate leads in bus 28 to address the SPROMs for reading, in a manner which will be familiar to digital circuit designers.
  • the Johnson counter (and other bus logic, as well as the bus) may already be present in the DUT for other purposes, so the only added hardware may be the SPROMs.
  • another form of bus it may readily be substituted for the exemplary Johnson bus.
  • FIG. 3 illustrates an exemplary embodiment for a representative SPROM cell 22.
  • a SPROM cell is utilized in the present invention because of its ability to be fully testable and to be programmed by laser cutting a resistive link.
  • Those of ordinary skill in the art should realize that, of course, other memory circuits can be utilized in the present invention without departing from its spirit. Maximum benefit will be obtained from use of a non-volatile ROM technology, such as the one described herein, since a device under test may lose power between successive tests.
  • Another example of an appropriate technology is the use of fusible-link ROM, wherein the links may be electrically blown open, instead of the laser-cut thin-film resistors.
  • the inputs 24 and 26 of the SPROM are to be connected to appropriate leads of the Johnson bus 28 of FIG. 2.
  • Inputs 24 and 26 are connected to a NAND gate 44.
  • the output of the NAND gate 44 is applied to the gate of a p-channel MOSFET 46 and to the input of an inverter 48.
  • a voltage source VDD is applied at terminal 50, to the drain of the MOSFET 46.
  • the source of the MOSFET 46 is attached to the output connection 52 of the SPROM.
  • the output of the inverter 48 is connected to the gate of an n-channel MOSFET 54.
  • the source of the MOSFET 54 is connected to digital ground 56.
  • MOSFET 54 The drain of MOSFET 54 is serially connected to one lead of a resistor link 58, the other lead of which is connected to the source of MOSFET 46 and the SPROM output 52.
  • This circuit is a ratioed logic circuit where the n-channel FET is "strong” (i.e., drives more current than the p-channel FET) and the p-channel FET is "weak” (i.e., drives less current than the n-channel FET). Because the MOSFETs are ratioed, they will always remain in the same state (i.e., they are both either ON or both OFF) .
  • each SPROM must be tested. The following procedure tests the integrity of the resistor links and the entire
  • SUBSTITUTESHEET SPROM circuit Before the ROM is programmed the output of the SPROMS is read. The SPROM outputs should all be “0". Thus, bus 30 should initially be at "0". If the resistor link 54 is cut or there is a malfunction in gate 44, inverter 48 or MOSFET 54, then that SPROM output will be a "1", the die is bad and it is not used. The final step in the testing of a good ROM is to program the ROM and read the data back to ensure that it is correct.
  • the following description illustrates the operation of a typical SPROM cell.
  • the inputs 24 and 26 to the NAND gate 44 are both set to a “1", making the output of the NAND gate a “0".
  • the "0" output of the NAND gate is supplied to inverter 48. This signal is inverted to a "1", which is applied to the gate of MOSFET 54, turning it on.
  • the "0" output of the NAND gate is also applied to the gate of MOSFET 46. Because of the ratioed logic, since MOSFET 54 is on, MOSFET 46 is also turned on. Current is driven through both MOSFETs.
  • resistor link 54 If the resistor link 54 has not been cut, then current is driven through the resistor and due to the fact that the n-channel MOSFET 54 is strong and p-channel MOSFET 46 is weak, the former will pull down the SPROM output 52, producing a "0" output. If the resistor link 54 were cut or there was a malfunction in gate 44, inverter 48 or MOSFET 54, then the weak p-channel would pull the output high and the SPROM output would be a "1".
  • the SPROMs are programmed by cutting the resistor link in each SPROM which is to be set to a "1".
  • the resistor link is a thin-filra resistance.
  • the links to be cut are severed by a laser beam at the time of initial wafer probing, to program each good die with die and wafer identification numbers. However, if the desired output of a SPROM is a "0" then the resistor link is not cut.
  • the SPROM output 52 corresponds to one digit of the binary word, which is the identification code.
  • the SPROMs 22(A-P) in FIG. 2 are numbered so that each SPROM output corresponds to a particular digit in the binary word. For example, in FIG. 2, the output of SPROM 22A corresponds to the first digit in the binary word, the output of SPROM 22B corresponds to the second digit in the binary word, and so forth.
  • FIG. 2 is an embodiment of a serial interface.
  • the Johnson Bus 28 is a twenty-bit-wide bus. By tapping different connections of this bus, each cell can be enabled in sequence, forming a serial data stream at the output 32.
  • the 16 SPROMs are enabled one at a time when both of the inputs 24 and 26 of a particular SPROM are "1".
  • the n-channel MOSFET 54 pulls down the output 52 producing a "0".
  • the p-channel MOSFET 46 pulls the output 52 high, producing a "1".
  • FIG. 4 is an alternative embodiment of the present invention, utilizing a parallel output interface.
  • the ROM elements also use ratioed logic, a weak p-channel MOSFET 82 and a strong n-channel MOSFET 86.
  • a 9-bit parallel output bus 88 is used, so the ROM data is multiplexed into two read operations, one providing 9 bits and the other providing 5 bits.
  • the status of the control signals 72 and 74 applied to the inputs of NAND gate 76 determine which word is read. There are only 15 bits used in this embodiment. Each bit value is established by the state of an associated resistor link 84 As in the serial interface embodiment, if the resistor link is cut, then the output is pulled up, but if the resistor is not cut, then the output is pulled down.
  • An automatic tester (not shown) is used to measure the parameters of interest. Assume the DUT is a voltage reference whose temperature coefficient is to be measured, as above. The voltage of each reference is measured at multiple temperatures and each reference's temperature coefficient is then calculated. The procedure for testing the positive temperature coefficient of a voltage reference is as follows. The reference voltage is measured at 25°C, Vref(25). The reference voltage is then measured at
  • the negative temperature coefficient (TCneg) can also be calculated by measuring the reference voltage at -55°C, Vref(-55), and then using the following formula:
  • the negative and positive temperature coefficients may be compared to a specified predetermined acceptable temperature coefficient to determine whether or not the reference passes this test. Alternately, the data may simply be recorded to provide a test record for each DUT. DUT's can be tested or retested in random order and the temperatures may be randomly sequenced.
  • the ROM enables the automatic tester to quickly and accurately identify the DUT being tested, at the time each measurement is made. Each time the tester measures the voltage of a reference, it also reads the ROM and determines the identification code for the
  • SUBSTITUTESHEET reference under test It can then store all of the information and measurements on a computer disk, or in the tester itself, indexing the test data with the DUT identification code.
  • the recorded information can be a simple pass/fail result or it can be actual numeric test measurement data.

Abstract

In an integrated circuit package, a ROM is provided for identifying the device for testing purposes. The ROM is programmed, for example, by cutting resistor links. The resistor links set the output of the PROM. This output is a binary word which is read by the tester at the same time that the tester performs measurements on the reference device. With this information the tester can then perform various calculations.

Description

METHOD AND PACKAGE FOR INTEGRATED CIRCUIT IDENTIFICATION AND TESTING
BACKGROUND OF THE INVENT ION
1 . Field of the Invention
The present invention relates generally to the field of integrated circuit testing in general and, for a specific example, to the field of testing the temperature coefficients of integrated circuit voltage references.
2. Background Description
When manufacturing integrated circuits, various needs exist for testing the devices being fabricated. Such devices often must be tested not only to determine whether they are operative, but also to determine their actual specifications. The test results are used to separate good devices from bad devices, to establish component grading, and to establish a test record for devices required to carry such a pedigree ( e . g . , for certain military, space and atomic energy applications)
SUBSTITUTESHEET As an example, consider a typical voltage reference product (e.g., for a digital-to-analog converter) whose temperature coefficient must be determined during the test process. One prior art method for testing electronic devices such as voltage references is to test a number of such references in sequence, in an assembly line-fashion. The references are arranged on or supplied via an apparatus which sequentially moves each of the references near an automatic tester which tests the references one at a time, performing all necessary tests on one reference before advancing to test the next reference. The measurements may be stored in the tester or in a computer, where they may be filed under the sequential number of the reference. For instance, the first reference tested is assigned the identification number 1, the second reference tested is assigned the identification number 2, and so forth, for all of the references. In calculating temperature coefficients, the output voltage of each reference is measured at a number of different temperatures, and these temperatures are also stored. The temperature coefficients for the references can then be calculated. This temperature coefficient is then compared to a specified value, to determine whether the reference has passed the test, or to a group of values, to grade the voltage reference by quality.
SUBSTITUTESHEET The problem with this method of testing is that it is very slow. The device under test (DUT) must be brought to each test temperature, in sequence, and allowed to stabilize before each measurement is made. Additionally, the test jig itself must be allowed to stabilize at each test temperature, and it may exhibit considerable thermal inertia.
Another prior art method for testing electronic devices for temperature coefficient is to arrange all of the DUTs on a large board. The board with the DUTs is then placed into an environmental chamber, where the testing takes place. The main problem with this method is that it is expensive to use and maintain an environmental chamber to perform the testing.
Yet, another approach is to bring the test jig to a selected test temperature, check each DUT at that, temperature, in sequence, recording the test data for each DUT as it is measured. Then, the jig temperature is changed to the next test temperature and all the DUT's are tested as before, at this new temperature. The assumption is made that the DUT's remained in the same sequence, so the second round of test data will be recorded for, the correct DUT's. This sequence is repeated as many times as there are test temperatures. Onςe the data is all available, the temperature coefficients are calculated.
SUBSTITUTESHEET If the references do not remain in sequence when they are being tested, then the test data is meaningless. In practice it is very difficult to maintain the references in sequence. For example, device handlers may become jammed and DUT's may be damaged or otherwise may have to be removed from the sequence. This will necessitate that the tests be conducted again, from the start.
A solution to these problems is one that allows the tester to individually recognize each DUT. Each DUT is given a unique identification number and the test dats can be indexed according to the DUT. There have been several methods utilized in the past for associating the identification number with the DUT, such as affixing or printing a bar code on the underside of the DUT package and mounting in the test jig an optical reader for reading the bar code. The problem with such methods is that they add considerable expense. For example, a bar code identification system requires either manual labor or additional apparatus for attaching or printing a bar code on the DUT, and equipment (i.e., an optical scanning head) to read the code.
It is tMerefore an object of the present invention to provide an improved and inexpensive method for identifying integrated circuit devices which are to be tested.
SUBSTITUTESHEET Another object of the invention is to provide a method for identifying integrated circuit devices which are to be tested at varying temperatures, to allow flexibility in test sequencing.
Still another object of the invention is to provide an integrated circuit structure with means facilitating identification of a DUT during the testing process.
SUMMARY OF THE INVENTION
The foregoing and other objects and advantages of the invention are achieved by providing in an integrated circuit to be tested a ROM (i.e., read-only memory) which stores a unique identification code for each device. This code identifies the reference device in which it is housed. The device identification code is written to the ROM when the device wafer is initially probed, immediately after manufacture. Therefore, when a tester tests the DUT, it reads the ROM and indexes the voltage measurement with the identification code. The measurements are therefore all correlated with each other and with the DUT.
In the exemplary embodiment discussed below, the ROM is programmable once only. That is, a laser beam programs the ROM cells by cutting selected thin film
SUBSTITUTESHEET resistor links. This ROM is therefore a so-called WORM (write once read many) device, a specific specie of programmable ROM (or PROM).
The invention will be more fully understood from the detailed description below, which should be read in conjunction with the accompanying drawing.
BRIEF DESCRIPTION OF THE DRAWING
In the drawing;
FIG. 1 is a top view of a diagrammatic illustration of an integrated circuit device package having an identification ROM, according to the present invention;
FIG. 2 is a block diagram of a first exemplary embodiment of a ROM according to the present invention, utilizing a serial interface for reading the ROM output;
FIG. 3 is a schematic circuit diagram of one cell of the exemplary ROM of FIG. 2;
FIG. 4 is a schematic circuit diagram of a second exemplary embodiment of an identification ROM utilizing a parallel interface.
DETAILED DESCRIPTION
The present invention utilizes, in an integrated circuit device, a memory device which can store an
SUBSTITUTESHEET identification code which can be read by a tester. The identification code is used to identify the electronic device during the testing process. In a typical application, the identification code is used to identify a voltage reference circuit which supplies a reference voltage. The identification code is, in a preferred embodiment, stored in a ROM.
FIG. 1 illustrates the concept of the present invention. In a preferred embodiment, the ROM 10 is housed on the same integrated circuit substrate 12 as the DUT (device under test) 14, which may, for example, be a voltage reference. However, in a multi-chip package, the ROM and DUT may be on different substrates. The ROM 10 may be accessed via dedicated conductors 16 or via a bus 18 associated with the DUT.
FIG. 2 shows a first embodiment of the ROM 10, wherein, for purposes of convenience only, and not to limit the scope of the present invention, the ROM is depicted .as utilizing a serial output interface.
A block diagram of an exemplary 16-bit ROM 10 is shown in FIG. 2. The ROM 10 contains a number of SPROM (Static Programmable Read Only Memory) cells 22(A-P) . Each SPROM cell provides a 1-bit output which represents one digit of the binary word identifying the device. Therefore, in an embodiment in which the identification code is a 16-bit word, there are 16 SPROMs which constitute the ROM. Each SPROM has two
SUBSTITUTESHEET inputs, labeled 24(A-P) and 26(A-P), connected to appropriate leads of, for example, bus 28. The SPROM outputs are all connected to a common parallel bus 30. A Johnson counter, not shown, can select appropriate leads in bus 28 to address the SPROMs for reading, in a manner which will be familiar to digital circuit designers. Advantageously, the Johnson counter (and other bus logic, as well as the bus) may already be present in the DUT for other purposes, so the only added hardware may be the SPROMs. Thus, if another form of bus is present, it may readily be substituted for the exemplary Johnson bus.
FIG. 3 illustrates an exemplary embodiment for a representative SPROM cell 22. A SPROM cell is utilized in the present invention because of its ability to be fully testable and to be programmed by laser cutting a resistive link. Those of ordinary skill in the art should realize that, of course, other memory circuits can be utilized in the present invention without departing from its spirit. Maximum benefit will be obtained from use of a non-volatile ROM technology, such as the one described herein, since a device under test may lose power between successive tests. Another example of an appropriate technology is the use of fusible-link ROM, wherein the links may be electrically blown open, instead of the laser-cut thin-film resistors.
SUBSTITUTESHEET The inputs 24 and 26 of the SPROM are to be connected to appropriate leads of the Johnson bus 28 of FIG. 2. Inputs 24 and 26 are connected to a NAND gate 44. The output of the NAND gate 44 is applied to the gate of a p-channel MOSFET 46 and to the input of an inverter 48. A voltage source VDD is applied at terminal 50, to the drain of the MOSFET 46. The source of the MOSFET 46 is attached to the output connection 52 of the SPROM. The output of the inverter 48 is connected to the gate of an n-channel MOSFET 54. The source of the MOSFET 54 is connected to digital ground 56. The drain of MOSFET 54 is serially connected to one lead of a resistor link 58, the other lead of which is connected to the source of MOSFET 46 and the SPROM output 52. This circuit is a ratioed logic circuit where the n-channel FET is "strong" (i.e., drives more current than the p-channel FET) and the p-channel FET is "weak" (i.e., drives less current than the n-channel FET). Because the MOSFETs are ratioed, they will always remain in the same state (i.e., they are both either ON or both OFF) .
Four operating events must now be considered: initial testing of the SPROM, programming the SPROM, reading the ROM, and performing tests using the ROM.
Before the ROM can be considered useful, each SPROM must be tested. The following procedure tests the integrity of the resistor links and the entire
SUBSTITUTESHEET SPROM circuit. Before the ROM is programmed the output of the SPROMS is read. The SPROM outputs should all be "0". Thus, bus 30 should initially be at "0". If the resistor link 54 is cut or there is a malfunction in gate 44, inverter 48 or MOSFET 54, then that SPROM output will be a "1", the die is bad and it is not used. The final step in the testing of a good ROM is to program the ROM and read the data back to ensure that it is correct.
The following description illustrates the operation of a typical SPROM cell. The inputs 24 and 26 to the NAND gate 44 are both set to a "1", making the output of the NAND gate a "0". The "0" output of the NAND gate is supplied to inverter 48. This signal is inverted to a "1", which is applied to the gate of MOSFET 54, turning it on. The "0" output of the NAND gate is also applied to the gate of MOSFET 46. Because of the ratioed logic, since MOSFET 54 is on, MOSFET 46 is also turned on. Current is driven through both MOSFETs. If the resistor link 54 has not been cut, then current is driven through the resistor and due to the fact that the n-channel MOSFET 54 is strong and p-channel MOSFET 46 is weak, the former will pull down the SPROM output 52, producing a "0" output. If the resistor link 54 were cut or there was a malfunction in gate 44, inverter 48 or MOSFET 54, then the weak p-channel would pull the output high and the SPROM output would be a "1".
SUBSTITUTESHEET The SPROMs are programmed by cutting the resistor link in each SPROM which is to be set to a "1". In a preferred embodiment, the resistor link is a thin-filra resistance. The links to be cut are severed by a laser beam at the time of initial wafer probing, to program each good die with die and wafer identification numbers. However, if the desired output of a SPROM is a "0" then the resistor link is not cut.
The SPROM output 52 corresponds to one digit of the binary word, which is the identification code. The SPROMs 22(A-P) in FIG. 2 are numbered so that each SPROM output corresponds to a particular digit in the binary word. For example, in FIG. 2, the output of SPROM 22A corresponds to the first digit in the binary word, the output of SPROM 22B corresponds to the second digit in the binary word, and so forth.
The present invention may utilize either a serial or parallel output interface. FIG. 2 is an embodiment of a serial interface. The Johnson Bus 28 is a twenty-bit-wide bus. By tapping different connections of this bus, each cell can be enabled in sequence, forming a serial data stream at the output 32. The 16 SPROMs are enabled one at a time when both of the inputs 24 and 26 of a particular SPROM are "1". When the resistor link is not cut, the n-channel MOSFET 54 pulls down the output 52 producing a "0". When the resistor link has been cut, the p-channel MOSFET 46 pulls the output 52 high, producing a "1".
SUBSTITUTESHEET FIG. 4 is an alternative embodiment of the present invention, utilizing a parallel output interface. The ROM elements also use ratioed logic, a weak p-channel MOSFET 82 and a strong n-channel MOSFET 86. In this embodiment, a 9-bit parallel output bus 88 is used, so the ROM data is multiplexed into two read operations, one providing 9 bits and the other providing 5 bits. The status of the control signals 72 and 74 applied to the inputs of NAND gate 76 determine which word is read. There are only 15 bits used in this embodiment. Each bit value is established by the state of an associated resistor link 84 As in the serial interface embodiment, if the resistor link is cut, then the output is pulled up, but if the resistor is not cut, then the output is pulled down.
Having fully described the components and operation of the ROM, the method of utilizing the ROM in testing can be discussed. An automatic tester (not shown) is used to measure the parameters of interest. Assume the DUT is a voltage reference whose temperature coefficient is to be measured, as above. The voltage of each reference is measured at multiple temperatures and each reference's temperature coefficient is then calculated. The procedure for testing the positive temperature coefficient of a voltage reference is as follows. The reference voltage is measured at 25°C, Vref(25). The reference voltage is then measured at
SUBSTITUTESHEET 125°C, Vref(125). The positive temperature coefficient (TCpos) is calculated using the following formula:
TCpos = (Vref(125)-Vref(25))/(125-25) [Volts/degree C]
The negative temperature coefficient (TCneg) can also be calculated by measuring the reference voltage at -55°C, Vref(-55), and then using the following formula:
TCneg = (Vref(25)-Vref(-55))/(125+55) [Volts/degree C]
The negative and positive temperature coefficients may be compared to a specified predetermined acceptable temperature coefficient to determine whether or not the reference passes this test. Alternately, the data may simply be recorded to provide a test record for each DUT. DUT's can be tested or retested in random order and the temperatures may be randomly sequenced.
The ROM enables the automatic tester to quickly and accurately identify the DUT being tested, at the time each measurement is made. Each time the tester measures the voltage of a reference, it also reads the ROM and determines the identification code for the
SUBSTITUTESHEET reference under test. It can then store all of the information and measurements on a computer disk, or in the tester itself, indexing the test data with the DUT identification code. The recorded information can be a simple pass/fail result or it can be actual numeric test measurement data.
Having thus described one particular embodiment of the invention, various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements as are made obvious by this disclosure are intended to be part of this description though not expressly stated herein, and are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only and is not intended as limiting. The invention is limited only as defined in the following claims and the equivalents thereto.

Claims

1. In the testing of electronic devices, the method which comprises: packaging with the electronic device a read-only memory (ROM); programming the ROM with a device-unique identification code of a predetermined number of bits, said code being used to. identify unambiguously said electronic device; when measuring a selected characteristic of the electronic device, reading from said ROM the identification code; and associating the measurement of the selected characteristic with the identified code.
2. The method of claim 1 wherein the ROM and the electronic device are formed on the same substrate.
.
3. The method of claim 1 wherein the ROM and the electronic device are on different substrates.
4. The method of claim 1 wherein the step of programming the ROM permanently alters the ROM
SUBSTITUTESHEET •16-
5. The method of claim 4 wherein the ROM includes a thin-film resistor link for each bit to be programmed and the step of programming the ROM includes the operation of cutting the selected resistor link for each bit to be set to a predetermined state.
6. The method of claim 1 wherein the step of measuring a selected characteristic of the device is performed by using an automatic tester.
7. The method of claim 6 wherein the automatic tester includes means for calculating the temperature coefficient of each electronic device.
8. In a package containing an electronic device, the improvement comprising electrically readable means for uniquely identifying the electronic device.
9. The apparatus of claim 8 wherein the means for uniquely identifying the electronic device is a non-volatile ROM which can be programmed once with a digital code.
10. The apparatus of claim 9 wherein the ROM can be programmed to contain said digital code by cutting links in the ROM.
SUBSTITUTESHEET
11. The apparatus of claim 9 or 10 wherein the ROM is connected to be read via an output bus which is employed for other purposes by the electronic device.
SUBSTITUTESHEET
PCT/US1990/004296 1989-08-01 1990-08-01 Method and package for integrated circuit identification and testing WO1991002258A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US388,247 1989-08-01
US07/388,247 US5289113A (en) 1989-08-01 1989-08-01 PROM for integrated circuit identification and testing

Publications (1)

Publication Number Publication Date
WO1991002258A1 true WO1991002258A1 (en) 1991-02-21

Family

ID=23533300

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1990/004296 WO1991002258A1 (en) 1989-08-01 1990-08-01 Method and package for integrated circuit identification and testing

Country Status (4)

Country Link
US (1) US5289113A (en)
EP (1) EP0485480A1 (en)
JP (1) JPH05501153A (en)
WO (1) WO1991002258A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0831401A1 (en) * 1996-09-20 1998-03-25 Nec Corporation Semiconductor integrated circuit device containing means for storing chip specific information
WO2000051379A1 (en) * 1999-02-25 2000-08-31 Ericsson, Inc. Manufacturing method for wireless communications devices employing potentially different versions of integrated circuits
WO2023107622A1 (en) 2021-12-10 2023-06-15 Illumina, Inc. Parallel sample and index sequencing

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5440230A (en) * 1993-04-02 1995-08-08 Heflinger; Bruce L. Combinatorial signature for component identification
KR960014952A (en) * 1994-10-14 1996-05-22 가즈오 가네코 Burn-in and test method of semiconductor wafer and burn-in board used for it
US5742526A (en) * 1996-01-03 1998-04-21 Micron Technology, Inc. Apparatus and method for identifying an integrated device
US5872449A (en) * 1996-01-26 1999-02-16 Lsi Logic Corporation Semiconductor package qualification chip
US5927512A (en) 1997-01-17 1999-07-27 Micron Technology, Inc. Method for sorting integrated circuit devices
US6100486A (en) 1998-08-13 2000-08-08 Micron Technology, Inc. Method for sorting integrated circuit devices
US5844803A (en) * 1997-02-17 1998-12-01 Micron Technology, Inc. Method of sorting a group of integrated circuit devices for those devices requiring special testing
US5915231A (en) * 1997-02-26 1999-06-22 Micron Technology, Inc. Method in an integrated circuit (IC) manufacturing process for identifying and redirecting IC's mis-processed during their manufacture
US5856923A (en) * 1997-03-24 1999-01-05 Micron Technology, Inc. Method for continuous, non lot-based integrated circuit manufacturing
US7120513B1 (en) * 1997-06-06 2006-10-10 Micron Technology, Inc. Method for using data regarding manufacturing procedures integrated circuits (ICS) have undergone, such as repairs, to select procedures the ICS will undergo, such as additional repairs
US5907492A (en) 1997-06-06 1999-05-25 Micron Technology, Inc. Method for using data regarding manufacturing procedures integrated circuits (IC's) have undergone, such as repairs, to select procedures the IC's will undergo, such as additional repairs
US6216239B1 (en) * 1997-09-15 2001-04-10 Integrated Device Technology, Inc. Testing method and apparatus for identifying disturbed cells within a memory cell array
US6049624A (en) 1998-02-20 2000-04-11 Micron Technology, Inc. Non-lot based method for assembling integrated circuit devices
US6313658B1 (en) 1998-05-22 2001-11-06 Micron Technology, Inc. Device and method for isolating a short-circuited integrated circuit (IC) from other IC's on a semiconductor wafer
JP2001208795A (en) * 2000-01-28 2001-08-03 Ando Electric Co Ltd Carrier discrimination system, carrier discrimination method, and recording medium
DE10034878C2 (en) * 2000-07-18 2003-12-04 Infineon Technologies Ag Method for checking a component and component with test memory
US6524881B1 (en) * 2000-08-25 2003-02-25 Micron Technology, Inc. Method and apparatus for marking a bare semiconductor die
US6795743B1 (en) * 2000-09-18 2004-09-21 Dell Products L.P. Apparatus and method for electronically encoding an article with work-in-progress information
US6820179B2 (en) * 2000-12-04 2004-11-16 Hitachi Hokkai Semiconductor, Ltd. Semiconductor device and data processing system
US6792365B2 (en) * 2001-08-10 2004-09-14 Micron Technology, Inc. Sequential unique marking
US6694272B1 (en) * 2001-11-08 2004-02-17 Galaxy Power, Inc. Microcontroller controlled voltage reference
US7169685B2 (en) * 2002-02-25 2007-01-30 Micron Technology, Inc. Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach adhesive
KR20050032613A (en) 2002-08-30 2005-04-07 코닌클리즈케 필립스 일렉트로닉스 엔.브이. Integrated circuit with embedded identification code
US7609562B2 (en) * 2007-01-31 2009-10-27 Intel Corporation Configurable device ID in non-volatile memory
JP2020038116A (en) * 2018-09-04 2020-03-12 株式会社アドバンテスト Automatic handling of test target device for different foam factors in test cell
US20220270699A1 (en) * 2021-02-23 2022-08-25 Changxin Memory Technologies, Inc. Method and apparatus for batch testing device, related computer device and medium

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4380070A (en) * 1979-11-20 1983-04-12 Lockheed Corporation Automatic circuit identifier
EP0173103A2 (en) * 1984-08-30 1986-03-05 Casio Computer Company Limited IC Card and an identification system thereof
GB2214673A (en) * 1988-01-29 1989-09-06 Texas Instruments Ltd Electronic control device for producing a particular code group of digits when energised.

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7005372A (en) * 1970-04-15 1971-10-19
US4150331A (en) * 1977-07-29 1979-04-17 Burroughs Corporation Signature encoding for integrated circuits
US4183460A (en) * 1977-12-23 1980-01-15 Burroughs Corporation In-situ test and diagnostic circuitry and method for CML chips
US4768195A (en) * 1985-07-03 1988-08-30 Stoner Donald W Chip tester
US4760330A (en) * 1986-06-06 1988-07-26 Northern Telecom Limited Test system with shared test instruments
US4942358A (en) * 1988-11-02 1990-07-17 Motorola, Inc. Integrated circuit option identification circuit and method
US5003251A (en) * 1989-09-12 1991-03-26 Grumman Aerospace Corporation Bar code reader for printed circuit board

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4380070A (en) * 1979-11-20 1983-04-12 Lockheed Corporation Automatic circuit identifier
EP0173103A2 (en) * 1984-08-30 1986-03-05 Casio Computer Company Limited IC Card and an identification system thereof
GB2214673A (en) * 1988-01-29 1989-09-06 Texas Instruments Ltd Electronic control device for producing a particular code group of digits when energised.

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0831401A1 (en) * 1996-09-20 1998-03-25 Nec Corporation Semiconductor integrated circuit device containing means for storing chip specific information
US5872738A (en) * 1996-09-20 1999-02-16 Nec Corporation Semiconductor integrated circuit device for enabling easy confirmation of discrete information
WO2000051379A1 (en) * 1999-02-25 2000-08-31 Ericsson, Inc. Manufacturing method for wireless communications devices employing potentially different versions of integrated circuits
US6253076B1 (en) 1999-02-25 2001-06-26 Ericsson Inc. Manufacturing method for wireless communications devices employing potentially different versions of integrated circuits
WO2023107622A1 (en) 2021-12-10 2023-06-15 Illumina, Inc. Parallel sample and index sequencing

Also Published As

Publication number Publication date
EP0485480A1 (en) 1992-05-20
US5289113A (en) 1994-02-22
JPH05501153A (en) 1993-03-04

Similar Documents

Publication Publication Date Title
US5289113A (en) PROM for integrated circuit identification and testing
US6894526B2 (en) Apparatus for determining burn-in reliability from wafer level burn-in
EP0017808B1 (en) Method involving testing an electrically alterable microelectronic memory circuit
US5790771A (en) Apparatus and method for configuring a reconfigurable electronic system having defective resources
US5416409A (en) Apparatus and method for testing circuit board interconnect integrity
US6587980B2 (en) Intelligent binning for electrically repairable semiconductor chips
US6829737B1 (en) Method and system for storing device test information on a semiconductor device using on-device logic for determination of test results
US5895443A (en) Testable non-volatile memory device
US5764650A (en) Intelligent binning for electrically repairable semiconductor chips
WO1998006103A1 (en) System for optimizing memory repair time using test data
US5043657A (en) Marking techniques for identifying integrated circuit parts at the time of testing
KR100272712B1 (en) Semiconductor device on semiconductor wafer having simple wiring for test and capable of being tested in a short time
US5619463A (en) Integrated circuit device and test method therefor
JP2765771B2 (en) Test method for semiconductor memory device
US6429677B1 (en) Method and apparatus for characterization of gate dielectrics
US6209110B1 (en) Circuitry, apparatus and method for embedding a test status outcome within a circuit being tested
US6181615B1 (en) Circuitry, apparatus and method for embedding quantifiable test results within a circuit being tested
JPH0252446A (en) Testing apparatus for integrated circuit
JP2583057B2 (en) IC test system
RU2149417C1 (en) Method for grading batch of integral memory circuits with respect to their radiation stability
JPH1114709A (en) Test method of integrated circuit device
Bowles et al. Application specific Tester-On-a-Resident-Chip (TORCH {trademark})-innovation in the area of semiconductor testing
US20030115502A1 (en) Method of restoring encapsulated integrated circuit devices
JPS6117302B2 (en)

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FR GB IT LU NL SE

WWE Wipo information: entry into national phase

Ref document number: 1990912308

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 1990912308

Country of ref document: EP

WWW Wipo information: withdrawn in national office

Ref document number: 1990912308

Country of ref document: EP